9 #include "sys/syscall.h"
40 static void trace_input_func
PARAMS ((char *name
,
45 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
47 static void trace_output_func
PARAMS ((enum op_types result
));
49 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
51 static int init_text_p
= 0;
52 static asection
*text
;
53 static bfd_vma text_start
;
54 static bfd_vma text_end
;
57 #ifndef SIZE_INSTRUCTION
58 #define SIZE_INSTRUCTION 8
62 #define SIZE_OPERANDS 18
66 #define SIZE_VALUES 13
70 #define SIZE_LOCATION 20
77 #ifndef SIZE_LINE_NUMBER
78 #define SIZE_LINE_NUMBER 4
82 trace_input_func (name
, in1
, in2
, in3
)
97 const char *functionname
;
98 unsigned int linenumber
;
101 if ((d10v_debug
& DEBUG_TRACE
) == 0)
104 switch (State
.ins_type
)
107 case INS_UNKNOWN
: type
= " ?"; break;
108 case INS_LEFT
: type
= " L"; break;
109 case INS_RIGHT
: type
= " R"; break;
110 case INS_LEFT_PARALLEL
: type
= "*L"; break;
111 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
112 case INS_LONG
: type
= " B"; break;
115 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
116 (*d10v_callback
->printf_filtered
) (d10v_callback
,
118 SIZE_PC
, (unsigned)PC
,
120 SIZE_INSTRUCTION
, name
);
127 for (s
= exec_bfd
->sections
; s
; s
= s
->next
)
128 if (strcmp (bfd_get_section_name (exec_bfd
, s
), ".text") == 0)
131 text_start
= bfd_get_section_vma (exec_bfd
, s
);
132 text_end
= text_start
+ bfd_section_size (exec_bfd
, s
);
138 byte_pc
= (bfd_vma
)PC
<< 2;
139 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
141 filename
= (const char *)0;
142 functionname
= (const char *)0;
144 if (bfd_find_nearest_line (exec_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
145 &filename
, &functionname
, &linenumber
))
150 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
155 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
156 p
+= SIZE_LINE_NUMBER
+2;
161 sprintf (p
, "%s ", functionname
);
166 char *q
= (char *) strrchr (filename
, '/');
167 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
176 (*d10v_callback
->printf_filtered
) (d10v_callback
,
177 "0x%.*x %s: %-*.*s %-*s ",
178 SIZE_PC
, (unsigned)PC
,
180 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
181 SIZE_INSTRUCTION
, name
);
189 for (i
= 0; i
< 3; i
++)
202 sprintf (p
, "%sr%d", comma
, OP
[i
]);
210 sprintf (p
, "%scr%d", comma
, OP
[i
]);
216 case OP_ACCUM_OUTPUT
:
217 case OP_ACCUM_REVERSE
:
218 sprintf (p
, "%sa%d", comma
, OP
[i
]);
224 sprintf (p
, "%s%d", comma
, OP
[i
]);
230 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
236 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
242 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
248 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
254 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
260 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
266 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
272 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
280 sprintf (p
, "%sf0", comma
);
283 sprintf (p
, "%sf1", comma
);
286 sprintf (p
, "%sc", comma
);
294 if ((d10v_debug
& DEBUG_VALUES
) == 0)
298 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
303 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
306 for (i
= 0; i
< 3; i
++)
312 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
318 case OP_ACCUM_OUTPUT
:
320 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
328 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
329 (uint16
)State
.regs
[OP
[i
]]);
333 tmp
= (long)((((uint32
) State
.regs
[OP
[i
]]) << 16) | ((uint32
) State
.regs
[OP
[i
]+1]));
334 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
339 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
340 (uint16
)State
.cregs
[OP
[i
]]);
344 case OP_ACCUM_REVERSE
:
345 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
346 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
347 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
351 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
356 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
357 (uint16
)SEXT4(OP
[i
]));
361 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
362 (uint16
)SEXT8(OP
[i
]));
366 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
367 (uint16
)SEXT3(OP
[i
]));
372 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
376 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
380 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
386 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
388 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
389 (uint16
)State
.regs
[OP
[++i
]]);
393 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
394 (uint16
)State
.regs
[2]);
398 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
399 (uint16
)State
.regs
[3]);
407 trace_output_func (result
)
408 enum op_types result
;
410 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
422 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
423 (uint16
)State
.regs
[OP
[0]],
424 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
429 tmp
= (long)((((uint32
) State
.regs
[OP
[0]]) << 16) | ((uint32
) State
.regs
[OP
[0]+1]));
430 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-10, "", tmp
,
431 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
436 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
437 (uint16
)State
.cregs
[OP
[0]],
438 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
442 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES
-6, "",
443 (uint16
)State
.cregs
[OP
[1]],
444 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
448 case OP_ACCUM_OUTPUT
:
449 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
450 ((int)(State
.a
[OP
[0]] >> 32) & 0xff),
451 ((unsigned long)State
.a
[OP
[0]]) & 0xffffffff,
452 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
455 case OP_ACCUM_REVERSE
:
456 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s0x%.2x%.8lx F0=%d F1=%d C=%d\n", SIZE_VALUES
-12, "",
457 ((int)(State
.a
[OP
[1]] >> 32) & 0xff),
458 ((unsigned long)State
.a
[OP
[1]]) & 0xffffffff,
459 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
464 (*d10v_callback
->printf_filtered
) (d10v_callback
, " :: %*s F0=%d F1=%d C=%d\n", SIZE_VALUES
, "",
465 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
472 #define trace_input(NAME, IN1, IN2, IN3)
473 #define trace_output(RESULT)
480 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
482 if ((int16
)(State
.regs
[OP
[0]]) < 0)
484 State
.regs
[OP
[0]] = -(int16
)(State
.regs
[OP
[0]]);
489 trace_output (OP_REG
);
498 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
500 State
.a
[OP
[0]] = SEXT40(State
.a
[OP
[0]]);
502 if (State
.a
[OP
[0]] < 0 )
504 tmp
= -State
.a
[OP
[0]];
508 State
.a
[OP
[0]] = MAX32
;
509 else if (tmp
< MIN32
)
510 State
.a
[OP
[0]] = MIN32
;
512 State
.a
[OP
[0]] = tmp
& MASK40
;
515 State
.a
[OP
[0]] = tmp
& MASK40
;
520 trace_output (OP_ACCUM
);
527 uint16 tmp
= State
.regs
[OP
[0]];
528 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
529 State
.regs
[OP
[0]] += State
.regs
[OP
[1]];
530 if ( tmp
> State
.regs
[OP
[0]])
534 trace_output (OP_REG
);
542 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
544 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
548 State
.a
[OP
[0]] = MAX32
;
549 else if ( tmp
< MIN32
)
550 State
.a
[OP
[0]] = MIN32
;
552 State
.a
[OP
[0]] = tmp
& MASK40
;
555 State
.a
[OP
[0]] = tmp
& MASK40
;
556 trace_output (OP_ACCUM
);
564 tmp
= SEXT40(State
.a
[OP
[0]]) + SEXT40(State
.a
[OP
[1]]);
566 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
570 State
.a
[OP
[0]] = MAX32
;
571 else if ( tmp
< MIN32
)
572 State
.a
[OP
[0]] = MIN32
;
574 State
.a
[OP
[0]] = tmp
& MASK40
;
577 State
.a
[OP
[0]] = tmp
& MASK40
;
578 trace_output (OP_ACCUM
);
586 uint32 tmp1
= (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1];
587 uint32 tmp2
= (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
589 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
591 if ( (tmp
< tmp1
) || (tmp
< tmp2
) )
595 State
.regs
[OP
[0]] = tmp
>> 16;
596 State
.regs
[OP
[0]+1] = tmp
& 0xFFFF;
597 trace_output (OP_DREG
);
604 uint16 tmp
= State
.regs
[OP
[0]];
605 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] + OP
[2];
607 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
608 if ( tmp
> State
.regs
[OP
[0]])
612 trace_output (OP_REG
);
620 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
622 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
623 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
624 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
625 trace_output (OP_DREG
);
633 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
635 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
636 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
637 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
638 trace_output (OP_DREG
);
648 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
649 tmp
= SEXT40(State
.a
[OP
[2]]) + SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
652 State
.regs
[OP
[0]] = 0x7fff;
653 State
.regs
[OP
[0]+1] = 0xffff;
656 else if (tmp
< MIN32
)
658 State
.regs
[OP
[0]] = 0x8000;
659 State
.regs
[OP
[0]+1] = 0;
664 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
665 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
668 trace_output (OP_DREG
);
678 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
679 tmp
= SEXT40(State
.a
[OP
[1]]) + SEXT40(State
.a
[OP
[2]]);
682 State
.regs
[OP
[0]] = 0x7fff;
683 State
.regs
[OP
[0]+1] = 0xffff;
686 else if (tmp
< MIN32
)
688 State
.regs
[OP
[0]] = 0x8000;
689 State
.regs
[OP
[0]+1] = 0;
694 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
695 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
698 trace_output (OP_DREG
);
705 uint tmp
= State
.regs
[OP
[0]];
708 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
709 State
.regs
[OP
[0]] += OP
[1];
710 if (tmp
> State
.regs
[OP
[0]])
714 trace_output (OP_REG
);
721 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
722 State
.regs
[OP
[0]] &= State
.regs
[OP
[1]];
723 trace_output (OP_REG
);
730 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
731 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & OP
[2];
732 trace_output (OP_REG
);
739 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
740 State
.regs
[OP
[0]] &= ~(0x8000 >> OP
[1]);
741 trace_output (OP_REG
);
748 trace_input ("bl.s", OP_CONSTANT8
, OP_R2
, OP_R3
);
749 State
.regs
[13] = PC
+1;
751 trace_output (OP_VOID
);
758 trace_input ("bl.l", OP_CONSTANT16
, OP_R2
, OP_R3
);
759 State
.regs
[13] = PC
+1;
761 trace_output (OP_VOID
);
768 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
769 State
.regs
[OP
[0]] ^= 0x8000 >> OP
[1];
770 trace_output (OP_REG
);
777 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
779 trace_output (OP_VOID
);
786 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
788 trace_output (OP_VOID
);
795 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
798 trace_output (OP_FLAG
);
805 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
808 trace_output (OP_FLAG
);
815 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
818 trace_output (OP_FLAG
);
825 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
828 trace_output (OP_FLAG
);
835 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
836 State
.regs
[OP
[0]] |= 0x8000 >> OP
[1];
837 trace_output (OP_REG
);
844 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
846 State
.F0
= (State
.regs
[OP
[0]] & (0x8000 >> OP
[1])) ? 1 : 0;
847 trace_output (OP_FLAG
);
854 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
856 trace_output (OP_ACCUM
);
863 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
865 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(State
.regs
[OP
[1]])) ? 1 : 0;
866 trace_output (OP_FLAG
);
873 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
875 State
.F0
= (SEXT40(State
.a
[OP
[0]]) < SEXT40(State
.a
[OP
[1]])) ? 1 : 0;
876 trace_output (OP_FLAG
);
883 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
885 State
.F0
= (State
.regs
[OP
[0]] == State
.regs
[OP
[1]]) ? 1 : 0;
886 trace_output (OP_FLAG
);
893 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
895 State
.F0
= (State
.a
[OP
[0]] == State
.a
[OP
[1]]) ? 1 : 0;
896 trace_output (OP_FLAG
);
903 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
905 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)SEXT4(OP
[1])) ? 1 : 0;
906 trace_output (OP_FLAG
);
913 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
915 State
.F0
= (State
.regs
[OP
[0]] == (reg_t
)OP
[1]) ? 1 : 0;
916 trace_output (OP_FLAG
);
923 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
925 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)SEXT4(OP
[1])) ? 1 : 0;
926 trace_output (OP_FLAG
);
933 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
935 State
.F0
= ((int16
)(State
.regs
[OP
[0]]) < (int16
)(OP
[1])) ? 1 : 0;
936 trace_output (OP_FLAG
);
943 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
945 State
.F0
= (State
.regs
[OP
[0]] < State
.regs
[OP
[1]]) ? 1 : 0;
946 trace_output (OP_FLAG
);
953 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
955 State
.F0
= (State
.regs
[OP
[0]] < (reg_t
)OP
[1]) ? 1 : 0;
956 trace_output (OP_FLAG
);
965 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
979 trace_output (OP_FLAG
);
986 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
987 State
.exception
= SIGTRAP
;
994 uint16 foo
, tmp
, tmpf
;
996 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
997 foo
= (State
.regs
[OP
[0]] << 1) | (State
.regs
[OP
[0]+1] >> 15);
998 tmp
= (int16
)foo
- (int16
)(State
.regs
[OP
[1]]);
999 tmpf
= (foo
>= State
.regs
[OP
[1]]) ? 1 : 0;
1000 State
.regs
[OP
[0]] = (tmpf
== 1) ? tmp
: foo
;
1001 State
.regs
[OP
[0]+1] = (State
.regs
[OP
[0]+1] << 1) | tmpf
;
1002 trace_output (OP_DREG
);
1009 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1010 State
.exe
= (State
.F0
== 0);
1011 trace_output (OP_FLAG
);
1018 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1019 State
.exe
= (State
.F0
!= 0);
1020 trace_output (OP_FLAG
);
1027 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1028 State
.exe
= (State
.F1
== 0);
1029 trace_output (OP_FLAG
);
1036 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1037 State
.exe
= (State
.F1
!= 0);
1038 trace_output (OP_FLAG
);
1045 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1046 State
.exe
= (State
.F0
== 0) & (State
.F1
== 0);
1047 trace_output (OP_FLAG
);
1054 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1055 State
.exe
= (State
.F0
== 0) & (State
.F1
!= 0);
1056 trace_output (OP_FLAG
);
1063 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1064 State
.exe
= (State
.F0
!= 0) & (State
.F1
== 0);
1065 trace_output (OP_FLAG
);
1072 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1073 State
.exe
= (State
.F0
!= 0) & (State
.F1
!= 0);
1074 trace_output (OP_FLAG
);
1084 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1085 if (((int16
)State
.regs
[OP
[1]]) >= 0)
1086 tmp
= (State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1];
1088 tmp
= ~((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
1095 State
.regs
[OP
[0]] = i
-1;
1096 trace_output (OP_REG
);
1101 State
.regs
[OP
[0]] = 16;
1102 trace_output (OP_REG
);
1112 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1113 if (SEXT40(State
.a
[OP
[1]]) >= 0)
1114 tmp
= State
.a
[OP
[1]];
1116 tmp
= ~(State
.a
[OP
[1]]);
1118 foo
= 0x4000000000LL
;
1123 State
.regs
[OP
[0]] = i
-9;
1124 trace_output (OP_REG
);
1129 State
.regs
[OP
[0]] = 16;
1130 trace_output (OP_REG
);
1137 trace_input ("jl", OP_REG
, OP_R2
, OP_R3
);
1138 State
.regs
[13] = PC
+1;
1139 PC
= State
.regs
[OP
[0]];
1140 trace_output (OP_VOID
);
1147 trace_input ("jmp", OP_REG
,
1148 (OP
[0] == 13) ? OP_R2
: OP_VOID
,
1149 (OP
[0] == 13) ? OP_R3
: OP_VOID
);
1151 PC
= State
.regs
[OP
[0]];
1152 trace_output (OP_VOID
);
1159 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1160 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1161 trace_output (OP_REG
);
1168 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1169 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1170 INC_ADDR(State
.regs
[OP
[1]],-2);
1171 trace_output (OP_REG
);
1178 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1179 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1180 INC_ADDR(State
.regs
[OP
[1]],2);
1181 trace_output (OP_REG
);
1188 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1189 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1190 trace_output (OP_REG
);
1197 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1198 State
.regs
[OP
[0]] = RW (OP
[1] + State
.regs
[OP
[2]]);
1199 State
.regs
[OP
[0]+1] = RW (OP
[1] + State
.regs
[OP
[2]] + 2);
1200 trace_output (OP_DREG
);
1207 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1208 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1209 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1210 INC_ADDR(State
.regs
[OP
[1]],-4);
1211 trace_output (OP_DREG
);
1218 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1219 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1220 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1221 INC_ADDR(State
.regs
[OP
[1]],4);
1222 trace_output (OP_REG
);
1229 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1230 State
.regs
[OP
[0]] = RW (State
.regs
[OP
[1]]);
1231 State
.regs
[OP
[0]+1] = RW (State
.regs
[OP
[1]]+2);
1232 trace_output (OP_REG
);
1239 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1240 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1241 SEXT8 (State
.regs
[OP
[0]]);
1242 trace_output (OP_REG
);
1249 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1250 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1251 SEXT8 (State
.regs
[OP
[0]]);
1252 trace_output (OP_REG
);
1259 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1260 State
.regs
[OP
[0]] = SEXT4(OP
[1]);
1261 trace_output (OP_REG
);
1268 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1269 State
.regs
[OP
[0]] = OP
[1];
1270 trace_output (OP_REG
);
1277 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1278 State
.regs
[OP
[0]] = RB (OP
[1] + State
.regs
[OP
[2]]);
1279 trace_output (OP_REG
);
1286 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1287 State
.regs
[OP
[0]] = RB (State
.regs
[OP
[1]]);
1288 trace_output (OP_REG
);
1297 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1298 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1301 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1303 if (State
.ST
&& tmp
> MAX32
)
1306 tmp
+= SEXT40(State
.a
[OP
[0]]);
1310 State
.a
[OP
[0]] = MAX32
;
1311 else if (tmp
< MIN32
)
1312 State
.a
[OP
[0]] = MIN32
;
1314 State
.a
[OP
[0]] = tmp
& MASK40
;
1317 State
.a
[OP
[0]] = tmp
& MASK40
;
1318 trace_output (OP_ACCUM
);
1327 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1328 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1330 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1332 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1333 trace_output (OP_ACCUM
);
1342 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1343 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1345 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1346 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) + tmp
) & MASK40
;
1347 trace_output (OP_ACCUM
);
1354 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1355 State
.F1
= State
.F0
;
1356 if ((int16
)State
.regs
[OP
[1]] > (int16
)State
.regs
[OP
[0]])
1358 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1363 trace_output (OP_REG
);
1372 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1373 State
.F1
= State
.F0
;
1374 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1375 if (tmp
> SEXT40(State
.a
[OP
[0]]))
1377 State
.a
[OP
[0]] = tmp
& MASK40
;
1382 trace_output (OP_ACCUM
);
1389 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1390 State
.F1
= State
.F0
;
1391 if (SEXT40(State
.a
[OP
[1]]) > SEXT40(State
.a
[OP
[0]]))
1393 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1398 trace_output (OP_ACCUM
);
1406 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1407 State
.F1
= State
.F0
;
1408 if ((int16
)State
.regs
[OP
[1]] < (int16
)State
.regs
[OP
[0]])
1410 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1415 trace_output (OP_REG
);
1424 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1425 State
.F1
= State
.F0
;
1426 tmp
= SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1];
1427 if (tmp
< SEXT40(State
.a
[OP
[0]]))
1429 State
.a
[OP
[0]] = tmp
& MASK40
;
1434 trace_output (OP_ACCUM
);
1441 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1442 State
.F1
= State
.F0
;
1443 if (SEXT40(State
.a
[OP
[1]]) < SEXT40(State
.a
[OP
[0]]))
1445 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1450 trace_output (OP_ACCUM
);
1459 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1460 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1463 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1465 if (State
.ST
&& tmp
> MAX32
)
1468 tmp
= SEXT40(State
.a
[OP
[0]]) - tmp
;
1472 State
.a
[OP
[0]] = MAX32
;
1473 else if (tmp
< MIN32
)
1474 State
.a
[OP
[0]] = MIN32
;
1476 State
.a
[OP
[0]] = tmp
& MASK40
;
1479 State
.a
[OP
[0]] = tmp
& MASK40
;
1480 trace_output (OP_ACCUM
);
1489 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1490 tmp
= SEXT40 ((int16
)State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1492 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1494 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1495 trace_output (OP_ACCUM
);
1504 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1505 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1507 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1509 State
.a
[OP
[0]] = (SEXT40 (State
.a
[OP
[0]]) - tmp
) & MASK40
;
1510 trace_output (OP_ACCUM
);
1517 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1518 State
.regs
[OP
[0]] *= State
.regs
[OP
[1]];
1519 trace_output (OP_REG
);
1528 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1529 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * (int16
)(State
.regs
[OP
[2]]));
1532 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1534 if (State
.ST
&& tmp
> MAX32
)
1535 State
.a
[OP
[0]] = MAX32
;
1537 State
.a
[OP
[0]] = tmp
& MASK40
;
1538 trace_output (OP_ACCUM
);
1547 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1548 tmp
= SEXT40 ((int16
)(State
.regs
[OP
[1]]) * State
.regs
[OP
[2]]);
1553 State
.a
[OP
[0]] = tmp
& MASK40
;
1554 trace_output (OP_ACCUM
);
1563 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1564 tmp
= SEXT40 (State
.regs
[OP
[1]] * State
.regs
[OP
[2]]);
1569 State
.a
[OP
[0]] = tmp
& MASK40
;
1570 trace_output (OP_ACCUM
);
1577 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1578 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1579 trace_output (OP_REG
);
1586 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1587 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1588 State
.regs
[OP
[0]+1] = State
.regs
[OP
[1]+1];
1589 trace_output (OP_DREG
);
1596 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1597 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1598 State
.regs
[OP
[0]+1] = State
.a
[OP
[1]] & 0xffff;
1599 trace_output (OP_DREG
);
1606 trace_input ("mv2wtac", OP_ACCUM_OUTPUT
, OP_DREG
, OP_VOID
);
1607 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | State
.regs
[OP
[0]+1]) & MASK40
;
1608 trace_output (OP_ACCUM
);
1615 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1616 State
.a
[OP
[0]] = State
.a
[OP
[1]];
1617 trace_output (OP_ACCUM
);
1624 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1625 State
.regs
[OP
[0]] = SEXT8 (State
.regs
[OP
[1]] & 0xff);
1626 trace_output (OP_REG
);
1633 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1635 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1636 trace_output (OP_REG
);
1643 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1645 State
.regs
[OP
[0]] = State
.regs
[OP
[1]];
1646 trace_output (OP_REG
);
1653 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1654 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 32) & 0xff;
1655 trace_output (OP_ACCUM
);
1662 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1663 State
.regs
[OP
[0]] = (State
.a
[OP
[1]] >> 16) & 0xffff;
1664 trace_output (OP_REG
);
1671 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1672 State
.regs
[OP
[0]] = State
.a
[OP
[1]] & 0xffff;
1673 trace_output (OP_REG
);
1680 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
1683 /* PSW is treated specially */
1685 if (State
.SM
) PSW
|= 0x8000;
1686 if (State
.EA
) PSW
|= 0x2000;
1687 if (State
.DB
) PSW
|= 0x1000;
1688 if (State
.IE
) PSW
|= 0x400;
1689 if (State
.RP
) PSW
|= 0x200;
1690 if (State
.MD
) PSW
|= 0x100;
1691 if (State
.FX
) PSW
|= 0x80;
1692 if (State
.ST
) PSW
|= 0x40;
1693 if (State
.F0
) PSW
|= 8;
1694 if (State
.F1
) PSW
|= 4;
1695 if (State
.C
) PSW
|= 1;
1697 State
.regs
[OP
[0]] = State
.cregs
[OP
[1]];
1698 trace_output (OP_REG
);
1705 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
1706 State
.a
[OP
[1]] &= MASK32
;
1707 State
.a
[OP
[1]] |= (int64
)(State
.regs
[OP
[0]] & 0xff) << 32;
1708 trace_output (OP_ACCUM_REVERSE
);
1717 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
1718 tmp
= State
.a
[OP
[1]] & 0xffff;
1719 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]]) << 16 | tmp
) & MASK40
;
1720 trace_output (OP_ACCUM_REVERSE
);
1727 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
1728 State
.a
[OP
[1]] = (SEXT16 (State
.regs
[OP
[0]])) & MASK40
;
1729 trace_output (OP_ACCUM_REVERSE
);
1736 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
1737 State
.cregs
[OP
[1]] = State
.regs
[OP
[0]];
1740 /* PSW is treated specially */
1741 State
.SM
= (PSW
& 0x8000) ? 1 : 0;
1742 State
.EA
= (PSW
& 0x2000) ? 1 : 0;
1743 State
.DB
= (PSW
& 0x1000) ? 1 : 0;
1744 State
.IE
= (PSW
& 0x400) ? 1 : 0;
1745 State
.RP
= (PSW
& 0x200) ? 1 : 0;
1746 State
.MD
= (PSW
& 0x100) ? 1 : 0;
1747 State
.FX
= (PSW
& 0x80) ? 1 : 0;
1748 State
.ST
= (PSW
& 0x40) ? 1 : 0;
1749 State
.F0
= (PSW
& 8) ? 1 : 0;
1750 State
.F1
= (PSW
& 4) ? 1 : 0;
1752 if (State
.ST
&& !State
.FX
)
1754 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1755 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
1757 State
.exception
= SIGILL
;
1760 trace_output (OP_CR_REVERSE
);
1767 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1768 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] & 0xff;
1769 trace_output (OP_REG
);
1776 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
1777 State
.regs
[OP
[0]] = 0 - State
.regs
[OP
[0]];
1778 trace_output (OP_REG
);
1787 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
1788 tmp
= -SEXT40(State
.a
[OP
[0]]);
1792 State
.a
[OP
[0]] = MAX32
;
1793 else if (tmp
< MIN32
)
1794 State
.a
[OP
[0]] = MIN32
;
1796 State
.a
[OP
[0]] = tmp
& MASK40
;
1799 State
.a
[OP
[0]] = tmp
& MASK40
;
1800 trace_output (OP_ACCUM
);
1808 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
1809 trace_output (OP_VOID
);
1811 if (State
.ins_type
== INS_LEFT
|| State
.ins_type
== INS_LEFT_PARALLEL
)
1821 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
1822 State
.regs
[OP
[0]] = ~(State
.regs
[OP
[0]]);
1823 trace_output (OP_REG
);
1830 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
1831 State
.regs
[OP
[0]] |= State
.regs
[OP
[1]];
1832 trace_output (OP_REG
);
1839 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
1840 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] | OP
[2];
1841 trace_output (OP_REG
);
1849 int shift
= SEXT3 (OP
[2]);
1851 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1854 (*d10v_callback
->printf_filtered
) (d10v_callback
,
1855 "ERROR at PC 0x%x: instruction only valid for A0\n",
1857 State
.exception
= SIGILL
;
1860 State
.F1
= State
.F0
;
1862 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) << shift
;
1864 tmp
= ((State
.a
[0] << 16) | (State
.a
[1] & 0xffff)) >> -shift
;
1865 tmp
= ( SEXT60(tmp
) + 0x8000 ) >> 16;
1868 State
.regs
[OP
[0]] = 0x7fff;
1869 State
.regs
[OP
[0]+1] = 0xffff;
1872 else if (tmp
< MIN32
)
1874 State
.regs
[OP
[0]] = 0x8000;
1875 State
.regs
[OP
[0]+1] = 0;
1880 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1881 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
1884 trace_output (OP_DREG
);
1892 int shift
= SEXT3 (OP
[2]);
1894 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
1895 State
.F1
= State
.F0
;
1897 tmp
= SEXT44 (State
.a
[1]) << shift
;
1899 tmp
= SEXT44 (State
.a
[1]) >> -shift
;
1904 State
.regs
[OP
[0]] = 0x7fff;
1907 else if (tmp
< 0xfff80000000LL
)
1909 State
.regs
[OP
[0]] = 0x8000;
1914 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
1917 trace_output (OP_REG
);
1924 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1927 RPT_C
= State
.regs
[OP
[0]];
1931 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
1932 State
.exception
= SIGILL
;
1936 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
1937 State
.exception
= SIGILL
;
1939 trace_output (OP_VOID
);
1946 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
1953 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
1954 State
.exception
= SIGILL
;
1958 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
1959 State
.exception
= SIGILL
;
1961 trace_output (OP_VOID
);
1968 d10v_callback
->printf_filtered(d10v_callback
, "ERROR: rtd - NOT IMPLEMENTED\n");
1969 State
.exception
= SIGILL
;
1976 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
1979 trace_output (OP_VOID
);
1988 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1989 tmp
= SEXT40(State
.a
[OP
[0]]) + (SEXT40(State
.a
[OP
[1]]) >> 16);
1993 State
.a
[OP
[0]] = MAX32
;
1994 else if (tmp
< MIN32
)
1995 State
.a
[OP
[0]] = MIN32
;
1997 State
.a
[OP
[0]] = tmp
& MASK40
;
2000 State
.a
[OP
[0]] = tmp
& MASK40
;
2001 trace_output (OP_ACCUM
);
2008 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2009 State
.regs
[OP
[0]] = (State
.F0
== 0) ? 1 : 0;
2010 trace_output (OP_REG
);
2017 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2018 State
.regs
[OP
[0]] = (State
.F0
== 1) ? 1 : 0;
2019 trace_output (OP_REG
);
2026 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2028 trace_output (OP_VOID
);
2035 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2036 State
.regs
[OP
[0]] <<= (State
.regs
[OP
[1]] & 0xf);
2037 trace_output (OP_REG
);
2045 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2046 if ((State
.regs
[OP
[1]] & 31) <= 16)
2047 tmp
= SEXT40 (State
.a
[OP
[0]]) << (State
.regs
[OP
[1]] & 31);
2050 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2051 State
.exception
= SIGILL
;
2058 State
.a
[OP
[0]] = MAX32
;
2059 else if (tmp
< 0xffffff80000000LL
)
2060 State
.a
[OP
[0]] = MIN32
;
2062 State
.a
[OP
[0]] = tmp
& MASK40
;
2065 State
.a
[OP
[0]] = tmp
& MASK40
;
2066 trace_output (OP_ACCUM
);
2073 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2074 State
.regs
[OP
[0]] <<= OP
[1];
2075 trace_output (OP_REG
);
2087 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2088 tmp
= SEXT40(State
.a
[OP
[0]]) << OP
[1];
2093 State
.a
[OP
[0]] = MAX32
;
2094 else if (tmp
< 0xffffff80000000LL
)
2095 State
.a
[OP
[0]] = MIN32
;
2097 State
.a
[OP
[0]] = tmp
& MASK40
;
2100 State
.a
[OP
[0]] = tmp
& MASK40
;
2101 trace_output (OP_ACCUM
);
2110 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2111 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] << 1) | State
.F0
;
2112 trace_output (OP_REG
);
2119 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2120 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> (State
.regs
[OP
[1]] & 0xf);
2121 trace_output (OP_REG
);
2128 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2129 if ((State
.regs
[OP
[1]] & 31) <= 16)
2130 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2133 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2134 State
.exception
= SIGILL
;
2138 trace_output (OP_ACCUM
);
2145 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2146 State
.regs
[OP
[0]] = ((int16
)(State
.regs
[OP
[0]])) >> OP
[1];
2147 trace_output (OP_REG
);
2157 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2158 State
.a
[OP
[0]] >>= OP
[1];
2159 trace_output (OP_ACCUM
);
2166 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2167 State
.regs
[OP
[0]] >>= (State
.regs
[OP
[1]] & 0xf);
2168 trace_output (OP_REG
);
2175 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2176 if ((State
.regs
[OP
[1]] & 31) <= 16)
2177 State
.a
[OP
[0]] >>= (State
.regs
[OP
[1]] & 31);
2180 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", State
.regs
[OP
[1]] & 31);
2181 State
.exception
= SIGILL
;
2185 trace_output (OP_ACCUM
);
2192 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2193 State
.regs
[OP
[0]] >>= OP
[1];
2194 trace_output (OP_REG
);
2204 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2205 State
.a
[OP
[0]] >>= OP
[1];
2206 trace_output (OP_ACCUM
);
2215 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2216 tmp
= State
.F0
<< 15;
2217 State
.regs
[OP
[0]] = (State
.regs
[OP
[0]] >> 1) | tmp
;
2218 trace_output (OP_REG
);
2225 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2226 SW (OP
[1] + State
.regs
[OP
[2]], State
.regs
[OP
[0]]);
2227 trace_output (OP_VOID
);
2234 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2235 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2236 trace_output (OP_VOID
);
2243 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2246 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2247 State
.exception
= SIGILL
;
2250 State
.regs
[OP
[1]] -= 2;
2251 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2252 trace_output (OP_VOID
);
2259 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2260 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2261 INC_ADDR (State
.regs
[OP
[1]],2);
2262 trace_output (OP_VOID
);
2269 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2270 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2271 INC_ADDR (State
.regs
[OP
[1]],-2);
2272 trace_output (OP_VOID
);
2279 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2280 SW (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2281 SW (State
.regs
[OP
[2]]+OP
[1]+2, State
.regs
[OP
[0]+1]);
2282 trace_output (OP_VOID
);
2289 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2290 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2291 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2292 trace_output (OP_VOID
);
2299 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2302 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2303 State
.exception
= SIGILL
;
2306 State
.regs
[OP
[1]] -= 4;
2307 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2308 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2309 trace_output (OP_VOID
);
2316 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2317 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2318 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2319 INC_ADDR (State
.regs
[OP
[1]],4);
2320 trace_output (OP_VOID
);
2327 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2328 SW (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2329 SW (State
.regs
[OP
[1]]+2, State
.regs
[OP
[0]+1]);
2330 INC_ADDR (State
.regs
[OP
[1]],-4);
2331 trace_output (OP_VOID
);
2338 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2339 SB (State
.regs
[OP
[2]]+OP
[1], State
.regs
[OP
[0]]);
2340 trace_output (OP_VOID
);
2347 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2348 SB (State
.regs
[OP
[1]], State
.regs
[OP
[0]]);
2349 trace_output (OP_VOID
);
2356 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2357 State
.exception
= SIG_D10V_STOP
;
2358 trace_output (OP_VOID
);
2367 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
2368 tmp
= (int16
)State
.regs
[OP
[0]]- (int16
)State
.regs
[OP
[1]];
2369 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2370 State
.regs
[OP
[0]] = tmp
& 0xffff;
2371 trace_output (OP_REG
);
2380 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
2381 tmp
= SEXT40(State
.a
[OP
[0]]) - (SEXT16 (State
.regs
[OP
[1]]) << 16 | State
.regs
[OP
[1]+1]);
2385 State
.a
[OP
[0]] = MAX32
;
2386 else if ( tmp
< MIN32
)
2387 State
.a
[OP
[0]] = MIN32
;
2389 State
.a
[OP
[0]] = tmp
& MASK40
;
2392 State
.a
[OP
[0]] = tmp
& MASK40
;
2394 trace_output (OP_ACCUM
);
2404 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2405 tmp
= SEXT40(State
.a
[OP
[0]]) - SEXT40(State
.a
[OP
[1]]);
2409 State
.a
[OP
[0]] = MAX32
;
2410 else if ( tmp
< MIN32
)
2411 State
.a
[OP
[0]] = MIN32
;
2413 State
.a
[OP
[0]] = tmp
& MASK40
;
2416 State
.a
[OP
[0]] = tmp
& MASK40
;
2418 trace_output (OP_ACCUM
);
2428 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
2429 a
= (int32
)((State
.regs
[OP
[0]] << 16) | State
.regs
[OP
[0]+1]);
2430 b
= (int32
)((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]);
2432 State
.C
= (tmp
& 0xffffffff00000000LL
) ? 1 : 0;
2433 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2434 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2435 trace_output (OP_DREG
);
2444 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2445 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40 (State
.a
[OP
[2]]);
2446 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2447 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2448 trace_output (OP_DREG
);
2457 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2458 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2459 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2460 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2461 trace_output (OP_DREG
);
2470 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
2471 State
.F1
= State
.F0
;
2472 tmp
= SEXT40 ((State
.regs
[OP
[1]] << 16) | State
.regs
[OP
[1]+1]) - SEXT40(State
.a
[OP
[2]]);
2475 State
.regs
[OP
[0]] = 0x7fff;
2476 State
.regs
[OP
[0]+1] = 0xffff;
2479 else if (tmp
< MIN32
)
2481 State
.regs
[OP
[0]] = 0x8000;
2482 State
.regs
[OP
[0]+1] = 0;
2487 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2488 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2491 trace_output (OP_DREG
);
2500 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
2501 State
.F1
= State
.F0
;
2502 tmp
= SEXT40(State
.a
[OP
[1]]) - SEXT40(State
.a
[OP
[2]]);
2505 State
.regs
[OP
[0]] = 0x7fff;
2506 State
.regs
[OP
[0]+1] = 0xffff;
2509 else if (tmp
< MIN32
)
2511 State
.regs
[OP
[0]] = 0x8000;
2512 State
.regs
[OP
[0]+1] = 0;
2517 State
.regs
[OP
[0]] = (tmp
>> 16) & 0xffff;
2518 State
.regs
[OP
[0]+1] = tmp
& 0xffff;
2521 trace_output (OP_DREG
);
2532 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2533 tmp
= (int16
)State
.regs
[OP
[0]] - OP
[1];
2534 State
.C
= (tmp
& 0xffff0000) ? 1 : 0;
2535 State
.regs
[OP
[0]] = tmp
& 0xffff;
2536 trace_output (OP_REG
);
2543 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
2544 trace_output (OP_VOID
);
2550 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown trap code %d\n", OP
[0]);
2551 State
.exception
= SIGILL
;
2553 /* Use any other traps for batch debugging. */
2556 static int first_time
= 1;
2561 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
2562 for (i
= 0; i
< 16; i
++)
2563 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
2564 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
2567 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
2569 for (i
= 0; i
< 16; i
++)
2570 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) State
.regs
[i
]);
2572 for (i
= 0; i
< 2; i
++)
2573 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
2574 ((int)(State
.a
[OP
[i
]] >> 32) & 0xff),
2575 ((unsigned long)State
.a
[OP
[i
]]) & 0xffffffff);
2577 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
2578 State
.F0
!= 0, State
.F1
!= 0, State
.C
!= 0);
2583 /* Trap 0 is used for simulating low-level I/O */
2585 int save_errno
= errno
;
2588 /* Registers passed to trap 0 */
2590 #define FUNC State.regs[6] /* function number */
2591 #define PARM1 State.regs[2] /* optional parm 1 */
2592 #define PARM2 State.regs[3] /* optional parm 2 */
2593 #define PARM3 State.regs[4] /* optional parm 3 */
2594 #define PARM4 State.regs[5] /* optional parm 3 */
2596 /* Registers set by trap 0 */
2598 #define RETVAL State.regs[2] /* return value */
2599 #define RETVAL_HIGH State.regs[2] /* return value */
2600 #define RETVAL_LOW State.regs[3] /* return value */
2601 #define RETERR State.regs[4] /* return error code */
2603 /* Turn a pointer in a register into a pointer into real memory. */
2605 #define MEMPTR(x) ((char *)((x) + State.imem))
2609 #if !defined(__GO32__) && !defined(_WIN32)
2614 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2615 (char **)MEMPTR (PARM3
));
2618 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2626 RETVAL
= pipe (host_fd
);
2627 SW (buf
, host_fd
[0]);
2628 buf
+= sizeof(uint16
);
2629 SW (buf
, host_fd
[1]);
2636 RETVAL
= wait (&status
);
2642 RETVAL
= d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
2647 RETVAL
= (int)d10v_callback
->write_stdout (d10v_callback
,
2648 MEMPTR (PARM2
), PARM3
);
2650 RETVAL
= (int)d10v_callback
->write (d10v_callback
, PARM1
,
2651 MEMPTR (PARM2
), PARM3
);
2655 unsigned long ret
= d10v_callback
->lseek (d10v_callback
, PARM1
,
2656 (((unsigned long)PARM2
) << 16) || (unsigned long)PARM3
,
2658 RETVAL_HIGH
= ret
>> 16;
2659 RETVAL_LOW
= ret
& 0xffff;
2663 RETVAL
= d10v_callback
->close (d10v_callback
, PARM1
);
2666 RETVAL
= d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
);
2669 State
.exception
= SIG_D10V_EXIT
;
2673 /* stat system call */
2675 struct stat host_stat
;
2678 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2682 /* The hard-coded offsets and sizes were determined by using
2683 * the D10V compiler on a test program that used struct stat.
2685 SW (buf
, host_stat
.st_dev
);
2686 SW (buf
+2, host_stat
.st_ino
);
2687 SW (buf
+4, host_stat
.st_mode
);
2688 SW (buf
+6, host_stat
.st_nlink
);
2689 SW (buf
+8, host_stat
.st_uid
);
2690 SW (buf
+10, host_stat
.st_gid
);
2691 SW (buf
+12, host_stat
.st_rdev
);
2692 SLW (buf
+16, host_stat
.st_size
);
2693 SLW (buf
+20, host_stat
.st_atime
);
2694 SLW (buf
+28, host_stat
.st_mtime
);
2695 SLW (buf
+36, host_stat
.st_ctime
);
2700 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2703 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2706 /* Cast the second argument to void *, to avoid type mismatch
2707 if a prototype is present. */
2708 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
2713 RETERR
= d10v_callback
->get_errno(d10v_callback
);
2718 /* Trap 1 prints a string */
2720 char *fstr
= State
.regs
[2] + State
.imem
;
2721 fputs (fstr
, stdout
);
2726 /* Trap 2 calls printf */
2728 char *fstr
= State
.regs
[2] + State
.imem
;
2729 (*d10v_callback
->printf_filtered
) (d10v_callback
, fstr
,
2730 (int16
)State
.regs
[3],
2731 (int16
)State
.regs
[4],
2732 (int16
)State
.regs
[5]);
2737 /* Trap 3 writes a character */
2738 putchar (State
.regs
[2]);
2748 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2749 State
.F1
= State
.F0
;
2750 State
.F0
= (State
.regs
[OP
[0]] & OP
[1]) ? 1 : 0;
2751 trace_output (OP_FLAG
);
2758 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2759 State
.F1
= State
.F0
;
2760 State
.F0
= (~(State
.regs
[OP
[0]]) & OP
[1]) ? 1 : 0;
2761 trace_output (OP_FLAG
);
2768 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
2770 trace_output (OP_VOID
);
2777 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
2778 State
.regs
[OP
[0]] ^= State
.regs
[OP
[1]];
2779 trace_output (OP_REG
);
2786 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2787 State
.regs
[OP
[0]] = State
.regs
[OP
[1]] ^ OP
[2];
2788 trace_output (OP_REG
);