13 #include "targ-vals.h"
15 extern char *strrchr ();
48 PSW_MASK
= (PSW_SM_BIT
59 /* The following bits in the PSW _can't_ be set by instructions such
61 PSW_HW_MASK
= (PSW_MASK
| PSW_DM_BIT
)
65 move_to_cr (int cr
, reg_t mask
, reg_t val
, int psw_hw_p
)
67 /* A MASK bit is set when the corresponding bit in the CR should
69 /* This assumes that (VAL & MASK) == 0 */
77 if ((mask
& PSW_SM_BIT
) == 0)
79 int new_psw_sm
= (val
& PSW_SM_BIT
) != 0;
81 SET_HELD_SP (PSW_SM
, GPR (SP_IDX
));
82 if (PSW_SM
!= new_psw_sm
)
84 SET_GPR (SP_IDX
, HELD_SP (new_psw_sm
));
86 if ((mask
& (PSW_ST_BIT
| PSW_FX_BIT
)) == 0)
88 if (val
& PSW_ST_BIT
&& !(val
& PSW_FX_BIT
))
90 (*d10v_callback
->printf_filtered
)
92 "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
94 State
.exception
= SIGILL
;
97 /* keep an up-to-date psw around for tracing */
98 State
.trace
.psw
= (State
.trace
.psw
& mask
) | val
;
102 /* Just like PSW, mask things like DM out. */
115 /* only issue an update if the register is being changed */
116 if ((State
.cregs
[cr
] & ~mask
) != val
)
117 SLOT_PEND_MASK (State
.cregs
[cr
], mask
, val
);
121 /* Modify registers according to an AE - address exception. */
123 address_exception (void)
127 SET_HW_PSW ((PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
128 JMP (AE_VECTOR_START
);
132 static void trace_input_func
PARAMS ((char *name
,
137 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (name, in1, in2, in3); } while (0)
139 #ifndef SIZE_INSTRUCTION
140 #define SIZE_INSTRUCTION 8
143 #ifndef SIZE_OPERANDS
144 #define SIZE_OPERANDS 18
148 #define SIZE_VALUES 13
151 #ifndef SIZE_LOCATION
152 #define SIZE_LOCATION 20
159 #ifndef SIZE_LINE_NUMBER
160 #define SIZE_LINE_NUMBER 4
164 trace_input_func (name
, in1
, in2
, in3
)
177 const char *filename
;
178 const char *functionname
;
179 unsigned int linenumber
;
182 if ((d10v_debug
& DEBUG_TRACE
) == 0)
185 switch (State
.ins_type
)
188 case INS_UNKNOWN
: type
= " ?"; break;
189 case INS_LEFT
: type
= " L"; break;
190 case INS_RIGHT
: type
= " R"; break;
191 case INS_LEFT_PARALLEL
: type
= "*L"; break;
192 case INS_RIGHT_PARALLEL
: type
= "*R"; break;
193 case INS_LEFT_COND_TEST
: type
= "?L"; break;
194 case INS_RIGHT_COND_TEST
: type
= "?R"; break;
195 case INS_LEFT_COND_EXE
: type
= "&L"; break;
196 case INS_RIGHT_COND_EXE
: type
= "&R"; break;
197 case INS_LONG
: type
= " B"; break;
200 if ((d10v_debug
& DEBUG_LINE_NUMBER
) == 0)
201 (*d10v_callback
->printf_filtered
) (d10v_callback
,
203 SIZE_PC
, (unsigned)PC
,
205 SIZE_INSTRUCTION
, name
);
210 byte_pc
= decode_pc ();
211 if (text
&& byte_pc
>= text_start
&& byte_pc
< text_end
)
213 filename
= (const char *)0;
214 functionname
= (const char *)0;
216 if (bfd_find_nearest_line (prog_bfd
, text
, (struct symbol_cache_entry
**)0, byte_pc
- text_start
,
217 &filename
, &functionname
, &linenumber
))
222 sprintf (p
, "#%-*d ", SIZE_LINE_NUMBER
, linenumber
);
227 sprintf (p
, "%-*s ", SIZE_LINE_NUMBER
+1, "---");
228 p
+= SIZE_LINE_NUMBER
+2;
233 sprintf (p
, "%s ", functionname
);
238 char *q
= strrchr (filename
, '/');
239 sprintf (p
, "%s ", (q
) ? q
+1 : filename
);
248 (*d10v_callback
->printf_filtered
) (d10v_callback
,
249 "0x%.*x %s: %-*.*s %-*s ",
250 SIZE_PC
, (unsigned)PC
,
252 SIZE_LOCATION
, SIZE_LOCATION
, buf
,
253 SIZE_INSTRUCTION
, name
);
261 for (i
= 0; i
< 3; i
++)
275 sprintf (p
, "%sr%d", comma
, OP
[i
]);
283 sprintf (p
, "%scr%d", comma
, OP
[i
]);
289 case OP_ACCUM_OUTPUT
:
290 case OP_ACCUM_REVERSE
:
291 sprintf (p
, "%sa%d", comma
, OP
[i
]);
297 sprintf (p
, "%s%d", comma
, OP
[i
]);
303 sprintf (p
, "%s%d", comma
, SEXT8(OP
[i
]));
309 sprintf (p
, "%s%d", comma
, SEXT4(OP
[i
]));
315 sprintf (p
, "%s%d", comma
, SEXT3(OP
[i
]));
321 sprintf (p
, "%s@r%d", comma
, OP
[i
]);
327 sprintf (p
, "%s@(%d,r%d)", comma
, (int16
)OP
[i
], OP
[i
+1]);
333 sprintf (p
, "%s@%d", comma
, OP
[i
]);
339 sprintf (p
, "%s@r%d+", comma
, OP
[i
]);
345 sprintf (p
, "%s@r%d-", comma
, OP
[i
]);
351 sprintf (p
, "%s@-r%d", comma
, OP
[i
]);
359 sprintf (p
, "%sf0", comma
);
362 sprintf (p
, "%sf1", comma
);
365 sprintf (p
, "%sc", comma
);
373 if ((d10v_debug
& DEBUG_VALUES
) == 0)
377 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%s", buf
);
382 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%-*s", SIZE_OPERANDS
, buf
);
385 for (i
= 0; i
< 3; i
++)
391 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "");
397 case OP_ACCUM_OUTPUT
:
399 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s", SIZE_VALUES
, "---");
407 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
408 (uint16
) GPR (OP
[i
]));
412 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "", (uint16
) OP
[i
]);
416 tmp
= (long)((((uint32
) GPR (OP
[i
])) << 16) | ((uint32
) GPR (OP
[i
] + 1)));
417 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.8lx", SIZE_VALUES
-10, "", tmp
);
422 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
423 (uint16
) CREG (OP
[i
]));
427 case OP_ACCUM_REVERSE
:
428 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.2x%.8lx", SIZE_VALUES
-12, "",
429 ((int)(ACC (OP
[i
]) >> 32) & 0xff),
430 ((unsigned long) ACC (OP
[i
])) & 0xffffffff);
434 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
439 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
440 (uint16
)SEXT4(OP
[i
]));
444 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
445 (uint16
)SEXT8(OP
[i
]));
449 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
450 (uint16
)SEXT3(OP
[i
]));
455 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF0 = %d", SIZE_VALUES
-6, "",
459 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sF1 = %d", SIZE_VALUES
-6, "",
463 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*sC = %d", SIZE_VALUES
-5, "",
469 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
471 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
472 (uint16
)GPR (OP
[i
+ 1]));
477 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
482 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
487 (*d10v_callback
->printf_filtered
) (d10v_callback
, "%*s0x%.4x", SIZE_VALUES
-6, "",
495 (*d10v_callback
->flush_stdout
) (d10v_callback
);
499 do_trace_output_flush (void)
501 (*d10v_callback
->flush_stdout
) (d10v_callback
);
505 do_trace_output_finish (void)
507 (*d10v_callback
->printf_filtered
) (d10v_callback
,
508 " F0=%d F1=%d C=%d\n",
509 (State
.trace
.psw
& PSW_F0_BIT
) != 0,
510 (State
.trace
.psw
& PSW_F1_BIT
) != 0,
511 (State
.trace
.psw
& PSW_C_BIT
) != 0);
512 (*d10v_callback
->flush_stdout
) (d10v_callback
);
516 trace_output_40 (uint64 val
)
518 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
520 (*d10v_callback
->printf_filtered
) (d10v_callback
,
521 " :: %*s0x%.2x%.8lx",
524 ((int)(val
>> 32) & 0xff),
525 ((unsigned long) val
) & 0xffffffff);
526 do_trace_output_finish ();
531 trace_output_32 (uint32 val
)
533 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
535 (*d10v_callback
->printf_filtered
) (d10v_callback
,
540 do_trace_output_finish ();
545 trace_output_16 (uint16 val
)
547 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
549 (*d10v_callback
->printf_filtered
) (d10v_callback
,
554 do_trace_output_finish ();
561 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
563 (*d10v_callback
->printf_filtered
) (d10v_callback
, "\n");
564 do_trace_output_flush ();
571 if ((d10v_debug
& (DEBUG_TRACE
| DEBUG_VALUES
)) == (DEBUG_TRACE
| DEBUG_VALUES
))
573 (*d10v_callback
->printf_filtered
) (d10v_callback
,
577 do_trace_output_finish ();
585 #define trace_input(NAME, IN1, IN2, IN3)
586 #define trace_output(RESULT)
594 trace_input ("abs", OP_REG
, OP_VOID
, OP_VOID
);
604 SET_GPR (OP
[0], tmp
);
605 trace_output_16 (tmp
);
613 trace_input ("abs", OP_ACCUM
, OP_VOID
, OP_VOID
);
616 tmp
= SEXT40 (ACC (OP
[0]));
622 if (tmp
> SEXT40(MAX32
))
624 else if (tmp
< SEXT40(MIN32
))
627 tmp
= (tmp
& MASK40
);
630 tmp
= (tmp
& MASK40
);
635 tmp
= (tmp
& MASK40
);
638 SET_ACC (OP
[0], tmp
);
639 trace_output_40 (tmp
);
646 uint16 a
= GPR (OP
[0]);
647 uint16 b
= GPR (OP
[1]);
648 uint16 tmp
= (a
+ b
);
649 trace_input ("add", OP_REG
, OP_REG
, OP_VOID
);
651 SET_GPR (OP
[0], tmp
);
652 trace_output_16 (tmp
);
660 tmp
= SEXT40(ACC (OP
[0])) + (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
662 trace_input ("add", OP_ACCUM
, OP_REG
, OP_VOID
);
665 if (tmp
> SEXT40(MAX32
))
667 else if (tmp
< SEXT40(MIN32
))
670 tmp
= (tmp
& MASK40
);
673 tmp
= (tmp
& MASK40
);
674 SET_ACC (OP
[0], tmp
);
675 trace_output_40 (tmp
);
683 tmp
= SEXT40(ACC (OP
[0])) + SEXT40(ACC (OP
[1]));
685 trace_input ("add", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
688 if (tmp
> SEXT40(MAX32
))
690 else if (tmp
< SEXT40(MIN32
))
693 tmp
= (tmp
& MASK40
);
696 tmp
= (tmp
& MASK40
);
697 SET_ACC (OP
[0], tmp
);
698 trace_output_40 (tmp
);
706 uint32 a
= (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1);
707 uint32 b
= (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
708 trace_input ("add2w", OP_DREG
, OP_DREG
, OP_VOID
);
711 SET_GPR (OP
[0] + 0, (tmp
>> 16));
712 SET_GPR (OP
[0] + 1, (tmp
& 0xFFFF));
713 trace_output_32 (tmp
);
720 uint16 a
= GPR (OP
[1]);
722 uint16 tmp
= (a
+ b
);
723 trace_input ("add3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
725 SET_GPR (OP
[0], tmp
);
726 trace_output_16 (tmp
);
734 tmp
= SEXT40(ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
736 trace_input ("addac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
737 SET_GPR (OP
[0] + 0, ((tmp
>> 16) & 0xffff));
738 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
739 trace_output_32 (tmp
);
747 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
749 trace_input ("addac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
750 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
751 SET_GPR (OP
[0] + 1, tmp
& 0xffff);
752 trace_output_32 (tmp
);
762 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
763 tmp
= SEXT40 (ACC (OP
[2])) + SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
764 if (tmp
> SEXT40(MAX32
))
769 else if (tmp
< SEXT40(MIN32
))
778 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
779 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
780 trace_output_32 (tmp
);
790 trace_input ("addac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
791 tmp
= SEXT40(ACC (OP
[1])) + SEXT40(ACC (OP
[2]));
792 if (tmp
> SEXT40(MAX32
))
797 else if (tmp
< SEXT40(MIN32
))
806 SET_GPR (OP
[0] + 0, (tmp
>> 16) & 0xffff);
807 SET_GPR (OP
[0] + 1, (tmp
& 0xffff));
808 trace_output_32 (tmp
);
815 uint16 a
= GPR (OP
[0]);
822 trace_input ("addi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
824 SET_GPR (OP
[0], tmp
);
825 trace_output_16 (tmp
);
832 uint16 tmp
= GPR (OP
[0]) & GPR (OP
[1]);
833 trace_input ("and", OP_REG
, OP_REG
, OP_VOID
);
834 SET_GPR (OP
[0], tmp
);
835 trace_output_16 (tmp
);
842 uint16 tmp
= GPR (OP
[1]) & OP
[2];
843 trace_input ("and3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
844 SET_GPR (OP
[0], tmp
);
845 trace_output_16 (tmp
);
853 trace_input ("bclri", OP_REG
, OP_CONSTANT16
, OP_VOID
);
854 tmp
= (GPR (OP
[0]) &~(0x8000 >> OP
[1]));
855 SET_GPR (OP
[0], tmp
);
856 trace_output_16 (tmp
);
863 trace_input ("bl.s", OP_CONSTANT8
, OP_R0
, OP_R1
);
864 SET_GPR (13, PC
+ 1);
865 JMP( PC
+ SEXT8 (OP
[0]));
866 trace_output_void ();
873 trace_input ("bl.l", OP_CONSTANT16
, OP_R0
, OP_R1
);
874 SET_GPR (13, (PC
+ 1));
876 trace_output_void ();
884 trace_input ("bnoti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
885 tmp
= (GPR (OP
[0]) ^ (0x8000 >> OP
[1]));
886 SET_GPR (OP
[0], tmp
);
887 trace_output_16 (tmp
);
894 trace_input ("bra.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
895 JMP (PC
+ SEXT8 (OP
[0]));
896 trace_output_void ();
903 trace_input ("bra.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
905 trace_output_void ();
912 trace_input ("brf0f.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
914 JMP (PC
+ SEXT8 (OP
[0]));
915 trace_output_flag ();
922 trace_input ("brf0f.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
925 trace_output_flag ();
932 trace_input ("brf0t.s", OP_CONSTANT8
, OP_VOID
, OP_VOID
);
934 JMP (PC
+ SEXT8 (OP
[0]));
935 trace_output_flag ();
942 trace_input ("brf0t.l", OP_CONSTANT16
, OP_VOID
, OP_VOID
);
945 trace_output_flag ();
953 trace_input ("bseti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
954 tmp
= (GPR (OP
[0]) | (0x8000 >> OP
[1]));
955 SET_GPR (OP
[0], tmp
);
956 trace_output_16 (tmp
);
963 trace_input ("btsti", OP_REG
, OP_CONSTANT16
, OP_VOID
);
965 SET_PSW_F0 ((GPR (OP
[0]) & (0x8000 >> OP
[1])) ? 1 : 0);
966 trace_output_flag ();
973 trace_input ("clrac", OP_ACCUM_OUTPUT
, OP_VOID
, OP_VOID
);
982 trace_input ("cmp", OP_REG
, OP_REG
, OP_VOID
);
984 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(GPR (OP
[1]))) ? 1 : 0);
985 trace_output_flag ();
992 trace_input ("cmp", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
994 SET_PSW_F0 ((SEXT40(ACC (OP
[0])) < SEXT40(ACC (OP
[1]))) ? 1 : 0);
995 trace_output_flag ();
1002 trace_input ("cmpeq", OP_REG
, OP_REG
, OP_VOID
);
1003 SET_PSW_F1 (PSW_F0
);
1004 SET_PSW_F0 ((GPR (OP
[0]) == GPR (OP
[1])) ? 1 : 0);
1005 trace_output_flag ();
1012 trace_input ("cmpeq", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1013 SET_PSW_F1 (PSW_F0
);
1014 SET_PSW_F0 (((ACC (OP
[0]) & MASK40
) == (ACC (OP
[1]) & MASK40
)) ? 1 : 0);
1015 trace_output_flag ();
1022 trace_input ("cmpeqi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1023 SET_PSW_F1 (PSW_F0
);
1024 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
) SEXT4 (OP
[1])) ? 1 : 0);
1025 trace_output_flag ();
1032 trace_input ("cmpeqi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1033 SET_PSW_F1 (PSW_F0
);
1034 SET_PSW_F0 ((GPR (OP
[0]) == (reg_t
)OP
[1]) ? 1 : 0);
1035 trace_output_flag ();
1042 trace_input ("cmpi.s", OP_REG
, OP_CONSTANT4
, OP_VOID
);
1043 SET_PSW_F1 (PSW_F0
);
1044 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)SEXT4(OP
[1])) ? 1 : 0);
1045 trace_output_flag ();
1052 trace_input ("cmpi.l", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1053 SET_PSW_F1 (PSW_F0
);
1054 SET_PSW_F0 (((int16
)(GPR (OP
[0])) < (int16
)(OP
[1])) ? 1 : 0);
1055 trace_output_flag ();
1062 trace_input ("cmpu", OP_REG
, OP_REG
, OP_VOID
);
1063 SET_PSW_F1 (PSW_F0
);
1064 SET_PSW_F0 ((GPR (OP
[0]) < GPR (OP
[1])) ? 1 : 0);
1065 trace_output_flag ();
1072 trace_input ("cmpui", OP_REG
, OP_CONSTANT16
, OP_VOID
);
1073 SET_PSW_F1 (PSW_F0
);
1074 SET_PSW_F0 ((GPR (OP
[0]) < (reg_t
)OP
[1]) ? 1 : 0);
1075 trace_output_flag ();
1084 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1088 else if (OP
[1] == 1)
1097 trace_output_flag ();
1106 trace_input ("cpfg", OP_FLAG_OUTPUT
, OP_FLAG
, OP_VOID
);
1110 else if (OP
[1] == 1)
1119 trace_output_flag ();
1126 /* d10v_callback->printf_filtered(d10v_callback, "***** DBT ***** PC=%x\n",PC); */
1128 /* GDB uses the instruction pair ``dbt || nop'' as a break-point.
1129 The conditional below is for either of the instruction pairs
1130 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases
1131 where the dbt instruction should be interpreted.
1133 The module `sim-break' provides a more effective mechanism for
1134 detecting GDB planted breakpoints. The code below may,
1135 eventually, be changed to use that mechanism. */
1137 if (State
.ins_type
== INS_LEFT
1138 || State
.ins_type
== INS_RIGHT
)
1140 trace_input ("dbt", OP_VOID
, OP_VOID
, OP_VOID
);
1143 SET_HW_PSW (PSW_DM_BIT
| (PSW
& (PSW_F0_BIT
| PSW_F1_BIT
| PSW_C_BIT
)));
1144 JMP (DBT_VECTOR_START
);
1145 trace_output_void ();
1149 State
.exception
= SIGTRAP
;
1157 uint16 foo
, tmp
, tmpf
;
1161 trace_input ("divs", OP_DREG
, OP_REG
, OP_VOID
);
1162 foo
= (GPR (OP
[0]) << 1) | (GPR (OP
[0] + 1) >> 15);
1163 tmp
= (int16
)foo
- (int16
)(GPR (OP
[1]));
1164 tmpf
= (foo
>= GPR (OP
[1])) ? 1 : 0;
1165 hi
= ((tmpf
== 1) ? tmp
: foo
);
1166 lo
= ((GPR (OP
[0] + 1) << 1) | tmpf
);
1167 SET_GPR (OP
[0] + 0, hi
);
1168 SET_GPR (OP
[0] + 1, lo
);
1169 trace_output_32 (((uint32
) hi
<< 16) | lo
);
1176 trace_input ("exef0f", OP_VOID
, OP_VOID
, OP_VOID
);
1177 State
.exe
= (PSW_F0
== 0);
1178 trace_output_flag ();
1185 trace_input ("exef0t", OP_VOID
, OP_VOID
, OP_VOID
);
1186 State
.exe
= (PSW_F0
!= 0);
1187 trace_output_flag ();
1194 trace_input ("exef1f", OP_VOID
, OP_VOID
, OP_VOID
);
1195 State
.exe
= (PSW_F1
== 0);
1196 trace_output_flag ();
1203 trace_input ("exef1t", OP_VOID
, OP_VOID
, OP_VOID
);
1204 State
.exe
= (PSW_F1
!= 0);
1205 trace_output_flag ();
1212 trace_input ("exefaf", OP_VOID
, OP_VOID
, OP_VOID
);
1213 State
.exe
= (PSW_F0
== 0) & (PSW_F1
== 0);
1214 trace_output_flag ();
1221 trace_input ("exefat", OP_VOID
, OP_VOID
, OP_VOID
);
1222 State
.exe
= (PSW_F0
== 0) & (PSW_F1
!= 0);
1223 trace_output_flag ();
1230 trace_input ("exetaf", OP_VOID
, OP_VOID
, OP_VOID
);
1231 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
== 0);
1232 trace_output_flag ();
1239 trace_input ("exetat", OP_VOID
, OP_VOID
, OP_VOID
);
1240 State
.exe
= (PSW_F0
!= 0) & (PSW_F1
!= 0);
1241 trace_output_flag ();
1251 trace_input ("exp", OP_REG_OUTPUT
, OP_DREG
, OP_VOID
);
1252 if (((int16
)GPR (OP
[1])) >= 0)
1253 tmp
= (GPR (OP
[1]) << 16) | GPR (OP
[1] + 1);
1255 tmp
= ~((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
1262 SET_GPR (OP
[0], (i
- 1));
1263 trace_output_16 (i
- 1);
1268 SET_GPR (OP
[0], 16);
1269 trace_output_16 (16);
1279 trace_input ("exp", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1280 tmp
= SEXT40(ACC (OP
[1]));
1282 tmp
= ~tmp
& MASK40
;
1284 foo
= 0x4000000000LL
;
1289 SET_GPR (OP
[0], i
- 9);
1290 trace_output_16 (i
- 9);
1295 SET_GPR (OP
[0], 16);
1296 trace_output_16 (16);
1303 trace_input ("jl", OP_REG
, OP_R0
, OP_R1
);
1304 SET_GPR (13, PC
+ 1);
1306 trace_output_void ();
1313 trace_input ("jmp", OP_REG
,
1314 (OP
[0] == 13) ? OP_R0
: OP_VOID
,
1315 (OP
[0] == 13) ? OP_R1
: OP_VOID
);
1318 trace_output_void ();
1326 uint16 addr
= OP
[1] + GPR (OP
[2]);
1327 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1330 address_exception ();
1331 trace_output_void ();
1335 SET_GPR (OP
[0], tmp
);
1336 trace_output_16 (tmp
);
1344 uint16 addr
= GPR (OP
[1]);
1345 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1348 address_exception ();
1349 trace_output_void ();
1353 SET_GPR (OP
[0], tmp
);
1355 INC_ADDR (OP
[1], -2);
1356 trace_output_16 (tmp
);
1364 uint16 addr
= GPR (OP
[1]);
1365 trace_input ("ld", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1368 address_exception ();
1369 trace_output_void ();
1373 SET_GPR (OP
[0], tmp
);
1375 INC_ADDR (OP
[1], 2);
1376 trace_output_16 (tmp
);
1384 uint16 addr
= GPR (OP
[1]);
1385 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1388 address_exception ();
1389 trace_output_void ();
1393 SET_GPR (OP
[0], tmp
);
1394 trace_output_16 (tmp
);
1402 uint16 addr
= OP
[1];
1403 trace_input ("ld", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1406 address_exception ();
1407 trace_output_void ();
1411 SET_GPR (OP
[0], tmp
);
1412 trace_output_16 (tmp
);
1420 uint16 addr
= OP
[1] + GPR (OP
[2]);
1421 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1424 address_exception ();
1425 trace_output_void ();
1429 SET_GPR32 (OP
[0], tmp
);
1430 trace_output_32 (tmp
);
1437 uint16 addr
= GPR (OP
[1]);
1439 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTDEC
, OP_VOID
);
1442 address_exception ();
1443 trace_output_void ();
1447 SET_GPR32 (OP
[0], tmp
);
1448 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1449 INC_ADDR (OP
[1], -4);
1450 trace_output_32 (tmp
);
1458 uint16 addr
= GPR (OP
[1]);
1459 trace_input ("ld2w", OP_REG_OUTPUT
, OP_POSTINC
, OP_VOID
);
1462 address_exception ();
1463 trace_output_void ();
1467 SET_GPR32 (OP
[0], tmp
);
1468 if (OP
[0] != OP
[1] && ((OP
[0] + 1) != OP
[1]))
1469 INC_ADDR (OP
[1], 4);
1470 trace_output_32 (tmp
);
1477 uint16 addr
= GPR (OP
[1]);
1479 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1482 address_exception ();
1483 trace_output_void ();
1487 SET_GPR32 (OP
[0], tmp
);
1488 trace_output_32 (tmp
);
1496 uint16 addr
= OP
[1];
1497 trace_input ("ld2w", OP_REG_OUTPUT
, OP_MEMREF3
, OP_VOID
);
1500 address_exception ();
1501 trace_output_void ();
1505 SET_GPR32 (OP
[0], tmp
);
1506 trace_output_32 (tmp
);
1514 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1515 tmp
= SEXT8 (RB (OP
[1] + GPR (OP
[2])));
1516 SET_GPR (OP
[0], tmp
);
1517 trace_output_16 (tmp
);
1525 trace_input ("ldb", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1526 tmp
= SEXT8 (RB (GPR (OP
[1])));
1527 SET_GPR (OP
[0], tmp
);
1528 trace_output_16 (tmp
);
1536 trace_input ("ldi.s", OP_REG_OUTPUT
, OP_CONSTANT4
, OP_VOID
);
1537 tmp
= SEXT4 (OP
[1]);
1538 SET_GPR (OP
[0], tmp
);
1539 trace_output_16 (tmp
);
1547 trace_input ("ldi.l", OP_REG_OUTPUT
, OP_CONSTANT16
, OP_VOID
);
1549 SET_GPR (OP
[0], tmp
);
1550 trace_output_16 (tmp
);
1558 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF2
, OP_VOID
);
1559 tmp
= RB (OP
[1] + GPR (OP
[2]));
1560 SET_GPR (OP
[0], tmp
);
1561 trace_output_16 (tmp
);
1569 trace_input ("ldub", OP_REG_OUTPUT
, OP_MEMREF
, OP_VOID
);
1570 tmp
= RB (GPR (OP
[1]));
1571 SET_GPR (OP
[0], tmp
);
1572 trace_output_16 (tmp
);
1581 trace_input ("mac", OP_ACCUM
, OP_REG
, OP_REG
);
1582 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1585 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1587 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1590 tmp
+= SEXT40 (ACC (OP
[0]));
1593 if (tmp
> SEXT40(MAX32
))
1595 else if (tmp
< SEXT40(MIN32
))
1598 tmp
= (tmp
& MASK40
);
1601 tmp
= (tmp
& MASK40
);
1602 SET_ACC (OP
[0], tmp
);
1603 trace_output_40 (tmp
);
1612 trace_input ("macsu", OP_ACCUM
, OP_REG
, OP_REG
);
1613 tmp
= SEXT40 ((int16
) GPR (OP
[1]) * GPR (OP
[2]));
1615 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1616 tmp
= ((SEXT40 (ACC (OP
[0])) + tmp
) & MASK40
);
1617 SET_ACC (OP
[0], tmp
);
1618 trace_output_40 (tmp
);
1629 trace_input ("macu", OP_ACCUM
, OP_REG
, OP_REG
);
1630 src1
= (uint16
) GPR (OP
[1]);
1631 src2
= (uint16
) GPR (OP
[2]);
1635 tmp
= ((ACC (OP
[0]) + tmp
) & MASK40
);
1636 SET_ACC (OP
[0], tmp
);
1637 trace_output_40 (tmp
);
1645 trace_input ("max", OP_REG
, OP_REG
, OP_VOID
);
1646 SET_PSW_F1 (PSW_F0
);
1647 if ((int16
) GPR (OP
[1]) > (int16
)GPR (OP
[0]))
1657 SET_GPR (OP
[0], tmp
);
1658 trace_output_16 (tmp
);
1667 trace_input ("max", OP_ACCUM
, OP_DREG
, OP_VOID
);
1668 SET_PSW_F1 (PSW_F0
);
1669 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1670 if (tmp
> SEXT40 (ACC (OP
[0])))
1672 tmp
= (tmp
& MASK40
);
1680 SET_ACC (OP
[0], tmp
);
1681 trace_output_40 (tmp
);
1689 trace_input ("max", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1690 SET_PSW_F1 (PSW_F0
);
1691 if (SEXT40 (ACC (OP
[1])) > SEXT40 (ACC (OP
[0])))
1701 SET_ACC (OP
[0], tmp
);
1702 trace_output_40 (tmp
);
1711 trace_input ("min", OP_REG
, OP_REG
, OP_VOID
);
1712 SET_PSW_F1 (PSW_F0
);
1713 if ((int16
)GPR (OP
[1]) < (int16
)GPR (OP
[0]))
1723 SET_GPR (OP
[0], tmp
);
1724 trace_output_16 (tmp
);
1733 trace_input ("min", OP_ACCUM
, OP_DREG
, OP_VOID
);
1734 SET_PSW_F1 (PSW_F0
);
1735 tmp
= SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1);
1736 if (tmp
< SEXT40(ACC (OP
[0])))
1738 tmp
= (tmp
& MASK40
);
1746 SET_ACC (OP
[0], tmp
);
1747 trace_output_40 (tmp
);
1755 trace_input ("min", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
1756 SET_PSW_F1 (PSW_F0
);
1757 if (SEXT40(ACC (OP
[1])) < SEXT40(ACC (OP
[0])))
1767 SET_ACC (OP
[0], tmp
);
1768 trace_output_40 (tmp
);
1777 trace_input ("msb", OP_ACCUM
, OP_REG
, OP_REG
);
1778 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1781 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1783 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1786 tmp
= SEXT40(ACC (OP
[0])) - tmp
;
1789 if (tmp
> SEXT40(MAX32
))
1791 else if (tmp
< SEXT40(MIN32
))
1794 tmp
= (tmp
& MASK40
);
1798 tmp
= (tmp
& MASK40
);
1800 SET_ACC (OP
[0], tmp
);
1801 trace_output_40 (tmp
);
1810 trace_input ("msbsu", OP_ACCUM
, OP_REG
, OP_REG
);
1811 tmp
= SEXT40 ((int16
)GPR (OP
[1]) * GPR (OP
[2]));
1813 tmp
= SEXT40( (tmp
<< 1) & MASK40
);
1814 tmp
= ((SEXT40 (ACC (OP
[0])) - tmp
) & MASK40
);
1815 SET_ACC (OP
[0], tmp
);
1816 trace_output_40 (tmp
);
1827 trace_input ("msbu", OP_ACCUM
, OP_REG
, OP_REG
);
1828 src1
= (uint16
) GPR (OP
[1]);
1829 src2
= (uint16
) GPR (OP
[2]);
1833 tmp
= ((ACC (OP
[0]) - tmp
) & MASK40
);
1834 SET_ACC (OP
[0], tmp
);
1835 trace_output_40 (tmp
);
1843 trace_input ("mul", OP_REG
, OP_REG
, OP_VOID
);
1844 tmp
= GPR (OP
[0]) * GPR (OP
[1]);
1845 SET_GPR (OP
[0], tmp
);
1846 trace_output_16 (tmp
);
1855 trace_input ("mulx", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1856 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * (int16
)(GPR (OP
[2])));
1859 tmp
= SEXT40 ((tmp
<< 1) & MASK40
);
1861 if (PSW_ST
&& tmp
> SEXT40(MAX32
))
1864 tmp
= (tmp
& MASK40
);
1865 SET_ACC (OP
[0], tmp
);
1866 trace_output_40 (tmp
);
1875 trace_input ("mulxsu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1876 tmp
= SEXT40 ((int16
)(GPR (OP
[1])) * GPR (OP
[2]));
1880 tmp
= (tmp
& MASK40
);
1881 SET_ACC (OP
[0], tmp
);
1882 trace_output_40 (tmp
);
1893 trace_input ("mulxu", OP_ACCUM_OUTPUT
, OP_REG
, OP_REG
);
1894 src1
= (uint16
) GPR (OP
[1]);
1895 src2
= (uint16
) GPR (OP
[2]);
1899 tmp
= (tmp
& MASK40
);
1900 SET_ACC (OP
[0], tmp
);
1901 trace_output_40 (tmp
);
1909 trace_input ("mv", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1911 SET_GPR (OP
[0], tmp
);
1912 trace_output_16 (tmp
);
1920 trace_input ("mv2w", OP_DREG_OUTPUT
, OP_DREG
, OP_VOID
);
1921 tmp
= GPR32 (OP
[1]);
1922 SET_GPR32 (OP
[0], tmp
);
1923 trace_output_32 (tmp
);
1931 trace_input ("mv2wfac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_VOID
);
1933 SET_GPR32 (OP
[0], tmp
);
1934 trace_output_32 (tmp
);
1942 trace_input ("mv2wtac", OP_DREG
, OP_ACCUM_OUTPUT
, OP_VOID
);
1943 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | GPR (OP
[0] + 1)) & MASK40
);
1944 SET_ACC (OP
[1], tmp
);
1945 trace_output_40 (tmp
);
1953 trace_input ("mvac", OP_ACCUM_OUTPUT
, OP_ACCUM
, OP_VOID
);
1955 SET_ACC (OP
[0], tmp
);
1956 trace_output_40 (tmp
);
1964 trace_input ("mvb", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1965 tmp
= SEXT8 (GPR (OP
[1]) & 0xff);
1966 SET_GPR (OP
[0], tmp
);
1967 trace_output_16 (tmp
);
1975 trace_input ("mf0f", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1979 SET_GPR (OP
[0], tmp
);
1983 trace_output_16 (tmp
);
1991 trace_input ("mf0t", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
1995 SET_GPR (OP
[0], tmp
);
1999 trace_output_16 (tmp
);
2007 trace_input ("mvfacg", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2008 tmp
= ((ACC (OP
[1]) >> 32) & 0xff);
2009 SET_GPR (OP
[0], tmp
);
2010 trace_output_16 (tmp
);
2018 trace_input ("mvfachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2019 tmp
= (ACC (OP
[1]) >> 16);
2020 SET_GPR (OP
[0], tmp
);
2021 trace_output_16 (tmp
);
2029 trace_input ("mvfaclo", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2031 SET_GPR (OP
[0], tmp
);
2032 trace_output_16 (tmp
);
2040 trace_input ("mvfc", OP_REG_OUTPUT
, OP_CR
, OP_VOID
);
2042 SET_GPR (OP
[0], tmp
);
2043 trace_output_16 (tmp
);
2051 trace_input ("mvtacg", OP_REG
, OP_ACCUM
, OP_VOID
);
2052 tmp
= ((ACC (OP
[1]) & MASK32
)
2053 | ((int64
)(GPR (OP
[0]) & 0xff) << 32));
2054 SET_ACC (OP
[1], tmp
);
2055 trace_output_40 (tmp
);
2063 trace_input ("mvtachi", OP_REG
, OP_ACCUM
, OP_VOID
);
2064 tmp
= ACC (OP
[1]) & 0xffff;
2065 tmp
= ((SEXT16 (GPR (OP
[0])) << 16 | tmp
) & MASK40
);
2066 SET_ACC (OP
[1], tmp
);
2067 trace_output_40 (tmp
);
2075 trace_input ("mvtaclo", OP_REG
, OP_ACCUM
, OP_VOID
);
2076 tmp
= ((SEXT16 (GPR (OP
[0]))) & MASK40
);
2077 SET_ACC (OP
[1], tmp
);
2078 trace_output_40 (tmp
);
2086 trace_input ("mvtc", OP_REG
, OP_CR_OUTPUT
, OP_VOID
);
2088 tmp
= SET_CREG (OP
[1], tmp
);
2089 trace_output_16 (tmp
);
2097 trace_input ("mvub", OP_REG_OUTPUT
, OP_REG
, OP_VOID
);
2098 tmp
= (GPR (OP
[1]) & 0xff);
2099 SET_GPR (OP
[0], tmp
);
2100 trace_output_16 (tmp
);
2108 trace_input ("neg", OP_REG
, OP_VOID
, OP_VOID
);
2109 tmp
= - GPR (OP
[0]);
2110 SET_GPR (OP
[0], tmp
);
2111 trace_output_16 (tmp
);
2120 trace_input ("neg", OP_ACCUM
, OP_VOID
, OP_VOID
);
2121 tmp
= -SEXT40(ACC (OP
[0]));
2124 if (tmp
> SEXT40(MAX32
))
2126 else if (tmp
< SEXT40(MIN32
))
2129 tmp
= (tmp
& MASK40
);
2132 tmp
= (tmp
& MASK40
);
2133 SET_ACC (OP
[0], tmp
);
2134 trace_output_40 (tmp
);
2142 trace_input ("nop", OP_VOID
, OP_VOID
, OP_VOID
);
2144 ins_type_counters
[ (int)State
.ins_type
]--; /* don't count nops as normal instructions */
2145 switch (State
.ins_type
)
2148 ins_type_counters
[ (int)INS_UNKNOWN
]++;
2151 case INS_LEFT_PARALLEL
:
2152 /* Don't count a parallel op that includes a NOP as a true parallel op */
2153 ins_type_counters
[ (int)INS_RIGHT_PARALLEL
]--;
2154 ins_type_counters
[ (int)INS_RIGHT
]++;
2155 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2159 case INS_LEFT_COND_EXE
:
2160 ins_type_counters
[ (int)INS_LEFT_NOPS
]++;
2163 case INS_RIGHT_PARALLEL
:
2164 /* Don't count a parallel op that includes a NOP as a true parallel op */
2165 ins_type_counters
[ (int)INS_LEFT_PARALLEL
]--;
2166 ins_type_counters
[ (int)INS_LEFT
]++;
2167 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2171 case INS_RIGHT_COND_EXE
:
2172 ins_type_counters
[ (int)INS_RIGHT_NOPS
]++;
2176 trace_output_void ();
2184 trace_input ("not", OP_REG
, OP_VOID
, OP_VOID
);
2186 SET_GPR (OP
[0], tmp
);
2187 trace_output_16 (tmp
);
2195 trace_input ("or", OP_REG
, OP_REG
, OP_VOID
);
2196 tmp
= (GPR (OP
[0]) | GPR (OP
[1]));
2197 SET_GPR (OP
[0], tmp
);
2198 trace_output_16 (tmp
);
2206 trace_input ("or3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
2207 tmp
= (GPR (OP
[1]) | OP
[2]);
2208 SET_GPR (OP
[0], tmp
);
2209 trace_output_16 (tmp
);
2217 int shift
= SEXT3 (OP
[2]);
2219 trace_input ("rac", OP_DREG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2222 (*d10v_callback
->printf_filtered
) (d10v_callback
,
2223 "ERROR at PC 0x%x: instruction only valid for A0\n",
2225 State
.exception
= SIGILL
;
2228 SET_PSW_F1 (PSW_F0
);
2229 tmp
= SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff));
2235 tmp
>>= 16; /* look at bits 0:43 */
2236 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2241 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2250 SET_GPR32 (OP
[0], tmp
);
2251 trace_output_32 (tmp
);
2259 int shift
= SEXT3 (OP
[2]);
2261 trace_input ("rachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_CONSTANT3
);
2262 SET_PSW_F1 (PSW_F0
);
2264 tmp
= SEXT40 (ACC (OP
[1])) << shift
;
2266 tmp
= SEXT40 (ACC (OP
[1])) >> -shift
;
2269 if (tmp
> SEXT44 (SIGNED64 (0x0007fffffff)))
2274 else if (tmp
< SEXT44 (SIGNED64 (0xfff80000000)))
2284 SET_GPR (OP
[0], tmp
);
2285 trace_output_16 (tmp
);
2292 trace_input ("rep", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2294 SET_RPT_E (PC
+ OP
[1]);
2295 SET_RPT_C (GPR (OP
[0]));
2297 if (GPR (OP
[0]) == 0)
2299 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep with count=0 is illegal.\n");
2300 State
.exception
= SIGILL
;
2304 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: rep must include at least 4 instructions.\n");
2305 State
.exception
= SIGILL
;
2307 trace_output_void ();
2314 trace_input ("repi", OP_CONSTANT16
, OP_CONSTANT16
, OP_VOID
);
2316 SET_RPT_E (PC
+ OP
[1]);
2321 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi with count=0 is illegal.\n");
2322 State
.exception
= SIGILL
;
2326 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: repi must include at least 4 instructions.\n");
2327 State
.exception
= SIGILL
;
2329 trace_output_void ();
2336 trace_input ("rtd", OP_VOID
, OP_VOID
, OP_VOID
);
2337 SET_CREG (PSW_CR
, DPSW
);
2339 trace_output_void ();
2346 trace_input ("rte", OP_VOID
, OP_VOID
, OP_VOID
);
2347 SET_CREG (PSW_CR
, BPSW
);
2349 trace_output_void ();
2357 trace_input ("sac", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2359 tmp
= SEXT40(ACC (OP
[1]));
2361 SET_PSW_F1 (PSW_F0
);
2363 if (tmp
> SEXT40(MAX32
))
2368 else if (tmp
< SEXT40(MIN32
))
2375 tmp
= (tmp
& MASK32
);
2379 SET_GPR32 (OP
[0], tmp
);
2381 trace_output_40 (tmp
);
2390 trace_input ("sachi", OP_REG_OUTPUT
, OP_ACCUM
, OP_VOID
);
2392 tmp
= SEXT40(ACC (OP
[1]));
2394 SET_PSW_F1 (PSW_F0
);
2396 if (tmp
> SEXT40(MAX32
))
2401 else if (tmp
< SEXT40(MIN32
))
2412 SET_GPR (OP
[0], tmp
);
2414 trace_output_16 (OP
[0]);
2423 trace_input ("sadd", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
2424 tmp
= SEXT40(ACC (OP
[0])) + (SEXT40(ACC (OP
[1])) >> 16);
2427 if (tmp
> SEXT40(MAX32
))
2429 else if (tmp
< SEXT40(MIN32
))
2432 tmp
= (tmp
& MASK40
);
2435 tmp
= (tmp
& MASK40
);
2436 SET_ACC (OP
[0], tmp
);
2437 trace_output_40 (tmp
);
2445 trace_input ("setf0f", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2446 tmp
= ((PSW_F0
== 0) ? 1 : 0);
2447 SET_GPR (OP
[0], tmp
);
2448 trace_output_16 (tmp
);
2456 trace_input ("setf0t", OP_REG_OUTPUT
, OP_VOID
, OP_VOID
);
2457 tmp
= ((PSW_F0
== 1) ? 1 : 0);
2458 SET_GPR (OP
[0], tmp
);
2459 trace_output_16 (tmp
);
2469 trace_input ("slae", OP_ACCUM
, OP_REG
, OP_VOID
);
2471 reg
= SEXT16 (GPR (OP
[1]));
2473 if (reg
>= 17 || reg
<= -17)
2475 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", reg
);
2476 State
.exception
= SIGILL
;
2480 tmp
= SEXT40 (ACC (OP
[0]));
2482 if (PSW_ST
&& (tmp
< SEXT40 (MIN32
) || tmp
> SEXT40 (MAX32
)))
2484 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp
>> 32) & 0xff), ((unsigned long) tmp
) & 0xffffffff);
2485 State
.exception
= SIGILL
;
2489 if (reg
>= 0 && reg
<= 16)
2491 tmp
= SEXT56 ((SEXT56 (tmp
)) << (GPR (OP
[1])));
2494 if (tmp
> SEXT40(MAX32
))
2496 else if (tmp
< SEXT40(MIN32
))
2499 tmp
= (tmp
& MASK40
);
2502 tmp
= (tmp
& MASK40
);
2506 tmp
= (SEXT40 (ACC (OP
[0]))) >> (-GPR (OP
[1]));
2509 SET_ACC(OP
[0], tmp
);
2511 trace_output_40(tmp
);
2518 trace_input ("sleep", OP_VOID
, OP_VOID
, OP_VOID
);
2520 trace_output_void ();
2528 trace_input ("sll", OP_REG
, OP_REG
, OP_VOID
);
2529 tmp
= (GPR (OP
[0]) << (GPR (OP
[1]) & 0xf));
2530 SET_GPR (OP
[0], tmp
);
2531 trace_output_16 (tmp
);
2539 trace_input ("sll", OP_ACCUM
, OP_REG
, OP_VOID
);
2540 if ((GPR (OP
[1]) & 31) <= 16)
2541 tmp
= SEXT40 (ACC (OP
[0])) << (GPR (OP
[1]) & 31);
2544 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2545 State
.exception
= SIGILL
;
2551 if (tmp
> SEXT40(MAX32
))
2553 else if (tmp
< SEXT40(MIN32
))
2556 tmp
= (tmp
& MASK40
);
2559 tmp
= (tmp
& MASK40
);
2560 SET_ACC (OP
[0], tmp
);
2561 trace_output_40 (tmp
);
2569 trace_input ("slli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2570 tmp
= (GPR (OP
[0]) << OP
[1]);
2571 SET_GPR (OP
[0], tmp
);
2572 trace_output_16 (tmp
);
2584 trace_input ("slli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2585 tmp
= SEXT40(ACC (OP
[0])) << OP
[1];
2589 if (tmp
> SEXT40(MAX32
))
2591 else if (tmp
< SEXT40(MIN32
))
2594 tmp
= (tmp
& MASK40
);
2597 tmp
= (tmp
& MASK40
);
2598 SET_ACC (OP
[0], tmp
);
2599 trace_output_40 (tmp
);
2607 trace_input ("slx", OP_REG
, OP_FLAG
, OP_VOID
);
2608 tmp
= ((GPR (OP
[0]) << 1) | PSW_F0
);
2609 SET_GPR (OP
[0], tmp
);
2610 trace_output_16 (tmp
);
2618 trace_input ("sra", OP_REG
, OP_REG
, OP_VOID
);
2619 tmp
= (((int16
)(GPR (OP
[0]))) >> (GPR (OP
[1]) & 0xf));
2620 SET_GPR (OP
[0], tmp
);
2621 trace_output_16 (tmp
);
2628 trace_input ("sra", OP_ACCUM
, OP_REG
, OP_VOID
);
2629 if ((GPR (OP
[1]) & 31) <= 16)
2631 int64 tmp
= ((SEXT40(ACC (OP
[0])) >> (GPR (OP
[1]) & 31)) & MASK40
);
2632 SET_ACC (OP
[0], tmp
);
2633 trace_output_40 (tmp
);
2637 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2638 State
.exception
= SIGILL
;
2648 trace_input ("srai", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2649 tmp
= (((int16
)(GPR (OP
[0]))) >> OP
[1]);
2650 SET_GPR (OP
[0], tmp
);
2651 trace_output_16 (tmp
);
2662 trace_input ("srai", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2663 tmp
= ((SEXT40(ACC (OP
[0])) >> OP
[1]) & MASK40
);
2664 SET_ACC (OP
[0], tmp
);
2665 trace_output_40 (tmp
);
2673 trace_input ("srl", OP_REG
, OP_REG
, OP_VOID
);
2674 tmp
= (GPR (OP
[0]) >> (GPR (OP
[1]) & 0xf));
2675 SET_GPR (OP
[0], tmp
);
2676 trace_output_16 (tmp
);
2683 trace_input ("srl", OP_ACCUM
, OP_REG
, OP_VOID
);
2684 if ((GPR (OP
[1]) & 31) <= 16)
2686 int64 tmp
= ((uint64
)((ACC (OP
[0]) & MASK40
) >> (GPR (OP
[1]) & 31)));
2687 SET_ACC (OP
[0], tmp
);
2688 trace_output_40 (tmp
);
2692 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: shift value %d too large.\n", GPR (OP
[1]) & 31);
2693 State
.exception
= SIGILL
;
2704 trace_input ("srli", OP_REG
, OP_CONSTANT16
, OP_VOID
);
2705 tmp
= (GPR (OP
[0]) >> OP
[1]);
2706 SET_GPR (OP
[0], tmp
);
2707 trace_output_16 (tmp
);
2718 trace_input ("srli", OP_ACCUM
, OP_CONSTANT16
, OP_VOID
);
2719 tmp
= ((uint64
)(ACC (OP
[0]) & MASK40
) >> OP
[1]);
2720 SET_ACC (OP
[0], tmp
);
2721 trace_output_40 (tmp
);
2729 trace_input ("srx", OP_REG
, OP_FLAG
, OP_VOID
);
2731 tmp
= ((GPR (OP
[0]) >> 1) | tmp
);
2732 SET_GPR (OP
[0], tmp
);
2733 trace_output_16 (tmp
);
2740 uint16 addr
= OP
[1] + GPR (OP
[2]);
2741 trace_input ("st", OP_REG
, OP_MEMREF2
, OP_VOID
);
2744 address_exception ();
2745 trace_output_void ();
2748 SW (addr
, GPR (OP
[0]));
2749 trace_output_void ();
2756 uint16 addr
= GPR (OP
[1]);
2757 trace_input ("st", OP_REG
, OP_MEMREF
, OP_VOID
);
2760 address_exception ();
2761 trace_output_void ();
2764 SW (addr
, GPR (OP
[0]));
2765 trace_output_void ();
2773 uint16 addr
= GPR (OP
[1]) - 2;
2774 trace_input ("st", OP_REG
, OP_PREDEC
, OP_VOID
);
2777 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2778 State
.exception
= SIGILL
;
2783 address_exception ();
2784 trace_output_void ();
2787 SW (addr
, GPR (OP
[0]));
2788 SET_GPR (OP
[1], addr
);
2789 trace_output_void ();
2796 uint16 addr
= GPR (OP
[1]);
2797 trace_input ("st", OP_REG
, OP_POSTINC
, OP_VOID
);
2800 address_exception ();
2801 trace_output_void ();
2804 SW (addr
, GPR (OP
[0]));
2805 INC_ADDR (OP
[1], 2);
2806 trace_output_void ();
2813 uint16 addr
= GPR (OP
[1]);
2814 trace_input ("st", OP_REG
, OP_POSTDEC
, OP_VOID
);
2817 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2818 State
.exception
= SIGILL
;
2823 address_exception ();
2824 trace_output_void ();
2827 SW (addr
, GPR (OP
[0]));
2828 INC_ADDR (OP
[1], -2);
2829 trace_output_void ();
2836 uint16 addr
= OP
[1];
2837 trace_input ("st", OP_REG
, OP_MEMREF3
, OP_VOID
);
2840 address_exception ();
2841 trace_output_void ();
2844 SW (addr
, GPR (OP
[0]));
2845 trace_output_void ();
2852 uint16 addr
= GPR (OP
[2])+ OP
[1];
2853 trace_input ("st2w", OP_DREG
, OP_MEMREF2
, OP_VOID
);
2856 address_exception ();
2857 trace_output_void ();
2860 SW (addr
+ 0, GPR (OP
[0] + 0));
2861 SW (addr
+ 2, GPR (OP
[0] + 1));
2862 trace_output_void ();
2869 uint16 addr
= GPR (OP
[1]);
2870 trace_input ("st2w", OP_DREG
, OP_MEMREF
, OP_VOID
);
2873 address_exception ();
2874 trace_output_void ();
2877 SW (addr
+ 0, GPR (OP
[0] + 0));
2878 SW (addr
+ 2, GPR (OP
[0] + 1));
2879 trace_output_void ();
2886 uint16 addr
= GPR (OP
[1]) - 4;
2887 trace_input ("st2w", OP_DREG
, OP_PREDEC
, OP_VOID
);
2890 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot pre-decrement any registers but r15 (SP).\n");
2891 State
.exception
= SIGILL
;
2896 address_exception ();
2897 trace_output_void ();
2900 SW (addr
+ 0, GPR (OP
[0] + 0));
2901 SW (addr
+ 2, GPR (OP
[0] + 1));
2902 SET_GPR (OP
[1], addr
);
2903 trace_output_void ();
2910 uint16 addr
= GPR (OP
[1]);
2911 trace_input ("st2w", OP_DREG
, OP_POSTINC
, OP_VOID
);
2914 address_exception ();
2915 trace_output_void ();
2918 SW (addr
+ 0, GPR (OP
[0] + 0));
2919 SW (addr
+ 2, GPR (OP
[0] + 1));
2920 INC_ADDR (OP
[1], 4);
2921 trace_output_void ();
2928 uint16 addr
= GPR (OP
[1]);
2929 trace_input ("st2w", OP_DREG
, OP_POSTDEC
, OP_VOID
);
2932 (*d10v_callback
->printf_filtered
) (d10v_callback
, "ERROR: cannot post-decrement register r15 (SP).\n");
2933 State
.exception
= SIGILL
;
2938 address_exception ();
2939 trace_output_void ();
2942 SW (addr
+ 0, GPR (OP
[0] + 0));
2943 SW (addr
+ 2, GPR (OP
[0] + 1));
2944 INC_ADDR (OP
[1], -4);
2945 trace_output_void ();
2952 uint16 addr
= OP
[1];
2953 trace_input ("st2w", OP_DREG
, OP_MEMREF3
, OP_VOID
);
2956 address_exception ();
2957 trace_output_void ();
2960 SW (addr
+ 0, GPR (OP
[0] + 0));
2961 SW (addr
+ 2, GPR (OP
[0] + 1));
2962 trace_output_void ();
2969 trace_input ("stb", OP_REG
, OP_MEMREF2
, OP_VOID
);
2970 SB (GPR (OP
[2]) + OP
[1], GPR (OP
[0]));
2971 trace_output_void ();
2978 trace_input ("stb", OP_REG
, OP_MEMREF
, OP_VOID
);
2979 SB (GPR (OP
[1]), GPR (OP
[0]));
2980 trace_output_void ();
2987 trace_input ("stop", OP_VOID
, OP_VOID
, OP_VOID
);
2988 State
.exception
= SIG_D10V_STOP
;
2989 trace_output_void ();
2996 uint16 a
= GPR (OP
[0]);
2997 uint16 b
= GPR (OP
[1]);
2998 uint16 tmp
= (a
- b
);
2999 trace_input ("sub", OP_REG
, OP_REG
, OP_VOID
);
3000 /* see ../common/sim-alu.h for a more extensive discussion on how to
3001 compute the carry/overflow bits. */
3003 SET_GPR (OP
[0], tmp
);
3004 trace_output_16 (tmp
);
3013 trace_input ("sub", OP_ACCUM
, OP_DREG
, OP_VOID
);
3014 tmp
= SEXT40(ACC (OP
[0])) - (SEXT16 (GPR (OP
[1])) << 16 | GPR (OP
[1] + 1));
3017 if (tmp
> SEXT40(MAX32
))
3019 else if (tmp
< SEXT40(MIN32
))
3022 tmp
= (tmp
& MASK40
);
3025 tmp
= (tmp
& MASK40
);
3026 SET_ACC (OP
[0], tmp
);
3028 trace_output_40 (tmp
);
3038 trace_input ("sub", OP_ACCUM
, OP_ACCUM
, OP_VOID
);
3039 tmp
= SEXT40(ACC (OP
[0])) - SEXT40(ACC (OP
[1]));
3042 if (tmp
> SEXT40(MAX32
))
3044 else if (tmp
< SEXT40(MIN32
))
3047 tmp
= (tmp
& MASK40
);
3050 tmp
= (tmp
& MASK40
);
3051 SET_ACC (OP
[0], tmp
);
3053 trace_output_40 (tmp
);
3062 trace_input ("sub2w", OP_DREG
, OP_DREG
, OP_VOID
);
3063 a
= (uint32
)((GPR (OP
[0]) << 16) | GPR (OP
[0] + 1));
3064 b
= (uint32
)((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1));
3065 /* see ../common/sim-alu.h for a more extensive discussion on how to
3066 compute the carry/overflow bits */
3069 SET_GPR32 (OP
[0], tmp
);
3070 trace_output_32 (tmp
);
3079 trace_input ("subac3", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3080 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40 (ACC (OP
[2]));
3081 SET_GPR32 (OP
[0], tmp
);
3082 trace_output_32 (tmp
);
3091 trace_input ("subac3", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3092 tmp
= SEXT40 (ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3093 SET_GPR32 (OP
[0], tmp
);
3094 trace_output_32 (tmp
);
3103 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_DREG
, OP_ACCUM
);
3104 SET_PSW_F1 (PSW_F0
);
3105 tmp
= SEXT40 ((GPR (OP
[1]) << 16) | GPR (OP
[1] + 1)) - SEXT40(ACC (OP
[2]));
3106 if (tmp
> SEXT40(MAX32
))
3111 else if (tmp
< SEXT40(MIN32
))
3120 SET_GPR32 (OP
[0], tmp
);
3121 trace_output_32 (tmp
);
3130 trace_input ("subac3s", OP_DREG_OUTPUT
, OP_ACCUM
, OP_ACCUM
);
3131 SET_PSW_F1 (PSW_F0
);
3132 tmp
= SEXT40(ACC (OP
[1])) - SEXT40(ACC (OP
[2]));
3133 if (tmp
> SEXT40(MAX32
))
3138 else if (tmp
< SEXT40(MIN32
))
3147 SET_GPR32 (OP
[0], tmp
);
3148 trace_output_32 (tmp
);
3159 trace_input ("subi", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3160 /* see ../common/sim-alu.h for a more extensive discussion on how to
3161 compute the carry/overflow bits. */
3162 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
3163 tmp
= ((unsigned)(unsigned16
) GPR (OP
[0])
3164 + (unsigned)(unsigned16
) ( - OP
[1]));
3165 SET_PSW_C (tmp
>= (1 << 16));
3166 SET_GPR (OP
[0], tmp
);
3167 trace_output_16 (tmp
);
3174 trace_input ("trap", OP_CONSTANT4
, OP_VOID
, OP_VOID
);
3175 trace_output_void ();
3180 #if (DEBUG & DEBUG_TRAP) == 0
3182 uint16 vec
= OP
[0] + TRAP_VECTOR_START
;
3185 SET_PSW (PSW
& PSW_SM_BIT
);
3189 #else /* if debugging use trap to print registers */
3192 static int first_time
= 1;
3197 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap # PC ");
3198 for (i
= 0; i
< 16; i
++)
3199 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %sr%d", (i
> 9) ? "" : " ", i
);
3200 (*d10v_callback
->printf_filtered
) (d10v_callback
, " a0 a1 f0 f1 c\n");
3203 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Trap %2d 0x%.4x:", (int)OP
[0], (int)PC
);
3205 for (i
= 0; i
< 16; i
++)
3206 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.4x", (int) GPR (i
));
3208 for (i
= 0; i
< 2; i
++)
3209 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %.2x%.8lx",
3210 ((int)(ACC (i
) >> 32) & 0xff),
3211 ((unsigned long) ACC (i
)) & 0xffffffff);
3213 (*d10v_callback
->printf_filtered
) (d10v_callback
, " %d %d %d\n",
3214 PSW_F0
!= 0, PSW_F1
!= 0, PSW_C
!= 0);
3215 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3219 case 15: /* new system call trap */
3220 /* Trap 15 is used for simulating low-level I/O */
3222 unsigned32 result
= 0;
3225 /* Registers passed to trap 0 */
3227 #define FUNC GPR (4) /* function number */
3228 #define PARM1 GPR (0) /* optional parm 1 */
3229 #define PARM2 GPR (1) /* optional parm 2 */
3230 #define PARM3 GPR (2) /* optional parm 3 */
3231 #define PARM4 GPR (3) /* optional parm 3 */
3233 /* Registers set by trap 0 */
3235 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0)
3236 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0)
3237 #define RETERR(X) SET_GPR (4, (X)) /* return error code */
3239 /* Turn a pointer in a register into a pointer into real memory. */
3241 #define MEMPTR(x) ((char *)(dmem_addr(x)))
3245 #if !defined(__GO32__) && !defined(_WIN32)
3246 case TARGET_SYS_fork
:
3247 trace_input ("<fork>", OP_VOID
, OP_VOID
, OP_VOID
);
3249 trace_output_16 (result
);
3253 case TARGET_SYS_getpid
:
3254 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3256 trace_output_16 (result
);
3259 case TARGET_SYS_kill
:
3260 trace_input ("<kill>", OP_R0
, OP_R1
, OP_VOID
);
3261 if (PARM1
== getpid ())
3263 trace_output_void ();
3264 State
.exception
= PARM2
;
3272 case 1: os_sig
= SIGHUP
; break;
3275 case 2: os_sig
= SIGINT
; break;
3278 case 3: os_sig
= SIGQUIT
; break;
3281 case 4: os_sig
= SIGILL
; break;
3284 case 5: os_sig
= SIGTRAP
; break;
3287 case 6: os_sig
= SIGABRT
; break;
3288 #elif defined(SIGIOT)
3289 case 6: os_sig
= SIGIOT
; break;
3292 case 7: os_sig
= SIGEMT
; break;
3295 case 8: os_sig
= SIGFPE
; break;
3298 case 9: os_sig
= SIGKILL
; break;
3301 case 10: os_sig
= SIGBUS
; break;
3304 case 11: os_sig
= SIGSEGV
; break;
3307 case 12: os_sig
= SIGSYS
; break;
3310 case 13: os_sig
= SIGPIPE
; break;
3313 case 14: os_sig
= SIGALRM
; break;
3316 case 15: os_sig
= SIGTERM
; break;
3319 case 16: os_sig
= SIGURG
; break;
3322 case 17: os_sig
= SIGSTOP
; break;
3325 case 18: os_sig
= SIGTSTP
; break;
3328 case 19: os_sig
= SIGCONT
; break;
3331 case 20: os_sig
= SIGCHLD
; break;
3332 #elif defined(SIGCLD)
3333 case 20: os_sig
= SIGCLD
; break;
3336 case 21: os_sig
= SIGTTIN
; break;
3339 case 22: os_sig
= SIGTTOU
; break;
3342 case 23: os_sig
= SIGIO
; break;
3343 #elif defined (SIGPOLL)
3344 case 23: os_sig
= SIGPOLL
; break;
3347 case 24: os_sig
= SIGXCPU
; break;
3350 case 25: os_sig
= SIGXFSZ
; break;
3353 case 26: os_sig
= SIGVTALRM
; break;
3356 case 27: os_sig
= SIGPROF
; break;
3359 case 28: os_sig
= SIGWINCH
; break;
3362 case 29: os_sig
= SIGLOST
; break;
3365 case 30: os_sig
= SIGUSR1
; break;
3368 case 31: os_sig
= SIGUSR2
; break;
3374 trace_output_void ();
3375 (*d10v_callback
->printf_filtered
) (d10v_callback
, "Unknown signal %d\n", PARM2
);
3376 (*d10v_callback
->flush_stdout
) (d10v_callback
);
3377 State
.exception
= SIGILL
;
3381 RETVAL (kill (PARM1
, PARM2
));
3382 trace_output_16 (result
);
3387 case TARGET_SYS_execve
:
3388 trace_input ("<execve>", OP_R0
, OP_R1
, OP_R2
);
3389 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
3390 (char **)MEMPTR (PARM3
)));
3391 trace_output_16 (result
);
3394 #ifdef TARGET_SYS_execv
3395 case TARGET_SYS_execv
:
3396 trace_input ("<execv>", OP_R0
, OP_R1
, OP_VOID
);
3397 RETVAL (execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
));
3398 trace_output_16 (result
);
3402 case TARGET_SYS_pipe
:
3407 trace_input ("<pipe>", OP_R0
, OP_VOID
, OP_VOID
);
3409 RETVAL (pipe (host_fd
));
3410 SW (buf
, host_fd
[0]);
3411 buf
+= sizeof(uint16
);
3412 SW (buf
, host_fd
[1]);
3413 trace_output_16 (result
);
3418 #ifdef TARGET_SYS_wait
3419 case TARGET_SYS_wait
:
3422 trace_input ("<wait>", OP_R0
, OP_VOID
, OP_VOID
);
3423 RETVAL (wait (&status
));
3426 trace_output_16 (result
);
3432 case TARGET_SYS_getpid
:
3433 trace_input ("<getpid>", OP_VOID
, OP_VOID
, OP_VOID
);
3435 trace_output_16 (result
);
3438 case TARGET_SYS_kill
:
3439 trace_input ("<kill>", OP_REG
, OP_REG
, OP_VOID
);
3440 trace_output_void ();
3441 State
.exception
= PARM2
;
3445 case TARGET_SYS_read
:
3446 trace_input ("<read>", OP_R0
, OP_R1
, OP_R2
);
3447 RETVAL (d10v_callback
->read (d10v_callback
, PARM1
, MEMPTR (PARM2
),
3449 trace_output_16 (result
);
3452 case TARGET_SYS_write
:
3453 trace_input ("<write>", OP_R0
, OP_R1
, OP_R2
);
3455 RETVAL ((int)d10v_callback
->write_stdout (d10v_callback
,
3456 MEMPTR (PARM2
), PARM3
));
3458 RETVAL ((int)d10v_callback
->write (d10v_callback
, PARM1
,
3459 MEMPTR (PARM2
), PARM3
));
3460 trace_output_16 (result
);
3463 case TARGET_SYS_lseek
:
3464 trace_input ("<lseek>", OP_R0
, OP_R1
, OP_R2
);
3465 RETVAL32 (d10v_callback
->lseek (d10v_callback
, PARM1
,
3466 ((((unsigned long) PARM2
) << 16)
3467 || (unsigned long) PARM3
),
3469 trace_output_32 (result
);
3472 case TARGET_SYS_close
:
3473 trace_input ("<close>", OP_R0
, OP_VOID
, OP_VOID
);
3474 RETVAL (d10v_callback
->close (d10v_callback
, PARM1
));
3475 trace_output_16 (result
);
3478 case TARGET_SYS_open
:
3479 trace_input ("<open>", OP_R0
, OP_R1
, OP_R2
);
3480 RETVAL (d10v_callback
->open (d10v_callback
, MEMPTR (PARM1
), PARM2
));
3481 trace_output_16 (result
);
3484 case TARGET_SYS_exit
:
3485 trace_input ("<exit>", OP_R0
, OP_VOID
, OP_VOID
);
3486 State
.exception
= SIG_D10V_EXIT
;
3487 trace_output_void ();
3490 #ifdef TARGET_SYS_stat
3491 case TARGET_SYS_stat
:
3492 trace_input ("<stat>", OP_R0
, OP_R1
, OP_VOID
);
3493 /* stat system call */
3495 struct stat host_stat
;
3498 RETVAL (stat (MEMPTR (PARM1
), &host_stat
));
3502 /* The hard-coded offsets and sizes were determined by using
3503 * the D10V compiler on a test program that used struct stat.
3505 SW (buf
, host_stat
.st_dev
);
3506 SW (buf
+2, host_stat
.st_ino
);
3507 SW (buf
+4, host_stat
.st_mode
);
3508 SW (buf
+6, host_stat
.st_nlink
);
3509 SW (buf
+8, host_stat
.st_uid
);
3510 SW (buf
+10, host_stat
.st_gid
);
3511 SW (buf
+12, host_stat
.st_rdev
);
3512 SLW (buf
+16, host_stat
.st_size
);
3513 SLW (buf
+20, host_stat
.st_atime
);
3514 SLW (buf
+28, host_stat
.st_mtime
);
3515 SLW (buf
+36, host_stat
.st_ctime
);
3517 trace_output_16 (result
);
3521 case TARGET_SYS_chown
:
3522 trace_input ("<chown>", OP_R0
, OP_R1
, OP_R2
);
3523 RETVAL (chown (MEMPTR (PARM1
), PARM2
, PARM3
));
3524 trace_output_16 (result
);
3527 case TARGET_SYS_chmod
:
3528 trace_input ("<chmod>", OP_R0
, OP_R1
, OP_R2
);
3529 RETVAL (chmod (MEMPTR (PARM1
), PARM2
));
3530 trace_output_16 (result
);
3534 #ifdef TARGET_SYS_utime
3535 case TARGET_SYS_utime
:
3536 trace_input ("<utime>", OP_R0
, OP_R1
, OP_R2
);
3537 /* Cast the second argument to void *, to avoid type mismatch
3538 if a prototype is present. */
3539 RETVAL (utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
)));
3540 trace_output_16 (result
);
3546 #ifdef TARGET_SYS_time
3547 case TARGET_SYS_time
:
3548 trace_input ("<time>", OP_R0
, OP_R1
, OP_R2
);
3549 RETVAL32 (time (PARM1
? MEMPTR (PARM1
) : NULL
));
3550 trace_output_32 (result
);
3556 d10v_callback
->error (d10v_callback
, "Unknown syscall %d", FUNC
);
3558 if ((uint16
) result
== (uint16
) -1)
3559 RETERR (d10v_callback
->get_errno(d10v_callback
));
3571 trace_input ("tst0i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3572 SET_PSW_F1 (PSW_F0
);;
3573 SET_PSW_F0 ((GPR (OP
[0]) & OP
[1]) ? 1 : 0);
3574 trace_output_flag ();
3581 trace_input ("tst1i", OP_REG
, OP_CONSTANT16
, OP_VOID
);
3582 SET_PSW_F1 (PSW_F0
);
3583 SET_PSW_F0 ((~(GPR (OP
[0])) & OP
[1]) ? 1 : 0);
3584 trace_output_flag ();
3591 trace_input ("wait", OP_VOID
, OP_VOID
, OP_VOID
);
3593 trace_output_void ();
3601 trace_input ("xor", OP_REG
, OP_REG
, OP_VOID
);
3602 tmp
= (GPR (OP
[0]) ^ GPR (OP
[1]));
3603 SET_GPR (OP
[0], tmp
);
3604 trace_output_16 (tmp
);
3612 trace_input ("xor3", OP_REG_OUTPUT
, OP_REG
, OP_CONSTANT16
);
3613 tmp
= (GPR (OP
[1]) ^ OP
[2]);
3614 SET_GPR (OP
[0], tmp
);
3615 trace_output_16 (tmp
);