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29 #ifndef __EXETRACE_HH__
30 #define __EXETRACE_HH__
36 #include "inst_seq.hh" // for InstSeqNum
38 #include "exec_context.hh"
39 #include "static_inst.hh"
47 static const FlagVec ALL = ULL(0x1);
48 static const FlagVec FULL = ULL(0x2);
49 static const FlagVec SYMBOLS = ULL(0x4);
50 static const FlagVec EXTENDED = ULL(0x8);
51 static const FlagVec BRANCH_TAKEN = ULL(0x10);
52 static const FlagVec BRANCH_NOTTAKEN = ULL(0x20);
53 static const FlagVec CALLPAL = ULL(0x40);
54 static const FlagVec SPECULATIVE = ULL(0x100);
55 static const FlagVec OMIT_COUNT = ULL(0x200);
56 static const FlagVec INCLUDE_THREAD_NUM = ULL(0x400);
59 class InstRecord : public Record
63 // The following fields are initialized by the constructor and
64 // thus guaranteed to be valid.
66 // need to make this ref-counted so it doesn't go away before we
68 StaticInstPtr<TheISA> staticInst;
73 // The remaining fields are only valid for particular instruction
74 // types (e.g, addresses for memory ops) or when particular
75 // options are enabled (e.g., tracing full register contents).
76 // Each data field has an associated valid flag to indicate
77 // whether the data field is valid.
87 DataInt8 = 1, // set to equal number of bytes
107 InstRecord(Tick _cycle, BaseCPU *_cpu, StaticInstPtr<TheISA> _staticInst,
108 Addr _pc, bool spec, unsigned _thread)
109 : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
110 misspeculating(spec), thread(_thread)
112 data_status = DataInvalid;
116 fetch_seq_valid = false;
117 cp_seq_valid = false;
120 virtual ~InstRecord() { }
122 virtual void dump(std::ostream &outs);
124 void setAddr(Addr a) { addr = a; addr_valid = true; }
126 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
127 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
128 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
129 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
131 void setData(int64_t d) { setData((uint64_t)d); }
132 void setData(int32_t d) { setData((uint32_t)d); }
133 void setData(int16_t d) { setData((uint16_t)d); }
134 void setData(int8_t d) { setData((uint8_t)d); }
136 void setData(double d) { data.as_double = d; data_status = DataDouble; }
138 void setFetchSeq(InstSeqNum seq)
139 { fetch_seq = seq; fetch_seq_valid = true; }
141 void setCPSeq(InstSeqNum seq)
142 { cp_seq = seq; cp_seq_valid = true; }
144 void setRegs(const IntRegFile ®s);
146 void finalize() { theLog.append(this); }
148 enum InstExecFlagBits {
161 static std::vector<bool> flags;
163 static void setParams();
165 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
170 InstRecord::setRegs(const IntRegFile ®s)
173 iregs = new iRegFile;
175 memcpy(&iregs->regs, regs, sizeof(IntRegFile));
181 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
182 const StaticInstPtr<TheISA> staticInst,
183 Addr pc, int thread = 0)
185 if (DTRACE(InstExec) &&
186 (InstRecord::traceMisspec() || !xc->misspeculating())) {
187 return new InstRecord(cycle, cpu, staticInst, pc,
188 xc->misspeculating(), thread);
197 #endif // __EXETRACE_HH__