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2001-11-14 Dave Brolley <brolley@redhat.com>
[binutils-gdb.git] / sim / fr30 / sem-switch.c
1 /* Simulator instruction semantics for fr30bf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #ifdef DEFINE_LABELS
26
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
30
31 static struct {
32 int index;
33 void *label;
34 } labels[] = {
35 { FR30BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { FR30BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { FR30BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { FR30BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { FR30BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { FR30BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { FR30BF_INSN_ADD, && case_sem_INSN_ADD },
42 { FR30BF_INSN_ADDI, && case_sem_INSN_ADDI },
43 { FR30BF_INSN_ADD2, && case_sem_INSN_ADD2 },
44 { FR30BF_INSN_ADDC, && case_sem_INSN_ADDC },
45 { FR30BF_INSN_ADDN, && case_sem_INSN_ADDN },
46 { FR30BF_INSN_ADDNI, && case_sem_INSN_ADDNI },
47 { FR30BF_INSN_ADDN2, && case_sem_INSN_ADDN2 },
48 { FR30BF_INSN_SUB, && case_sem_INSN_SUB },
49 { FR30BF_INSN_SUBC, && case_sem_INSN_SUBC },
50 { FR30BF_INSN_SUBN, && case_sem_INSN_SUBN },
51 { FR30BF_INSN_CMP, && case_sem_INSN_CMP },
52 { FR30BF_INSN_CMPI, && case_sem_INSN_CMPI },
53 { FR30BF_INSN_CMP2, && case_sem_INSN_CMP2 },
54 { FR30BF_INSN_AND, && case_sem_INSN_AND },
55 { FR30BF_INSN_OR, && case_sem_INSN_OR },
56 { FR30BF_INSN_EOR, && case_sem_INSN_EOR },
57 { FR30BF_INSN_ANDM, && case_sem_INSN_ANDM },
58 { FR30BF_INSN_ANDH, && case_sem_INSN_ANDH },
59 { FR30BF_INSN_ANDB, && case_sem_INSN_ANDB },
60 { FR30BF_INSN_ORM, && case_sem_INSN_ORM },
61 { FR30BF_INSN_ORH, && case_sem_INSN_ORH },
62 { FR30BF_INSN_ORB, && case_sem_INSN_ORB },
63 { FR30BF_INSN_EORM, && case_sem_INSN_EORM },
64 { FR30BF_INSN_EORH, && case_sem_INSN_EORH },
65 { FR30BF_INSN_EORB, && case_sem_INSN_EORB },
66 { FR30BF_INSN_BANDL, && case_sem_INSN_BANDL },
67 { FR30BF_INSN_BORL, && case_sem_INSN_BORL },
68 { FR30BF_INSN_BEORL, && case_sem_INSN_BEORL },
69 { FR30BF_INSN_BANDH, && case_sem_INSN_BANDH },
70 { FR30BF_INSN_BORH, && case_sem_INSN_BORH },
71 { FR30BF_INSN_BEORH, && case_sem_INSN_BEORH },
72 { FR30BF_INSN_BTSTL, && case_sem_INSN_BTSTL },
73 { FR30BF_INSN_BTSTH, && case_sem_INSN_BTSTH },
74 { FR30BF_INSN_MUL, && case_sem_INSN_MUL },
75 { FR30BF_INSN_MULU, && case_sem_INSN_MULU },
76 { FR30BF_INSN_MULH, && case_sem_INSN_MULH },
77 { FR30BF_INSN_MULUH, && case_sem_INSN_MULUH },
78 { FR30BF_INSN_DIV0S, && case_sem_INSN_DIV0S },
79 { FR30BF_INSN_DIV0U, && case_sem_INSN_DIV0U },
80 { FR30BF_INSN_DIV1, && case_sem_INSN_DIV1 },
81 { FR30BF_INSN_DIV2, && case_sem_INSN_DIV2 },
82 { FR30BF_INSN_DIV3, && case_sem_INSN_DIV3 },
83 { FR30BF_INSN_DIV4S, && case_sem_INSN_DIV4S },
84 { FR30BF_INSN_LSL, && case_sem_INSN_LSL },
85 { FR30BF_INSN_LSLI, && case_sem_INSN_LSLI },
86 { FR30BF_INSN_LSL2, && case_sem_INSN_LSL2 },
87 { FR30BF_INSN_LSR, && case_sem_INSN_LSR },
88 { FR30BF_INSN_LSRI, && case_sem_INSN_LSRI },
89 { FR30BF_INSN_LSR2, && case_sem_INSN_LSR2 },
90 { FR30BF_INSN_ASR, && case_sem_INSN_ASR },
91 { FR30BF_INSN_ASRI, && case_sem_INSN_ASRI },
92 { FR30BF_INSN_ASR2, && case_sem_INSN_ASR2 },
93 { FR30BF_INSN_LDI8, && case_sem_INSN_LDI8 },
94 { FR30BF_INSN_LDI20, && case_sem_INSN_LDI20 },
95 { FR30BF_INSN_LDI32, && case_sem_INSN_LDI32 },
96 { FR30BF_INSN_LD, && case_sem_INSN_LD },
97 { FR30BF_INSN_LDUH, && case_sem_INSN_LDUH },
98 { FR30BF_INSN_LDUB, && case_sem_INSN_LDUB },
99 { FR30BF_INSN_LDR13, && case_sem_INSN_LDR13 },
100 { FR30BF_INSN_LDR13UH, && case_sem_INSN_LDR13UH },
101 { FR30BF_INSN_LDR13UB, && case_sem_INSN_LDR13UB },
102 { FR30BF_INSN_LDR14, && case_sem_INSN_LDR14 },
103 { FR30BF_INSN_LDR14UH, && case_sem_INSN_LDR14UH },
104 { FR30BF_INSN_LDR14UB, && case_sem_INSN_LDR14UB },
105 { FR30BF_INSN_LDR15, && case_sem_INSN_LDR15 },
106 { FR30BF_INSN_LDR15GR, && case_sem_INSN_LDR15GR },
107 { FR30BF_INSN_LDR15DR, && case_sem_INSN_LDR15DR },
108 { FR30BF_INSN_LDR15PS, && case_sem_INSN_LDR15PS },
109 { FR30BF_INSN_ST, && case_sem_INSN_ST },
110 { FR30BF_INSN_STH, && case_sem_INSN_STH },
111 { FR30BF_INSN_STB, && case_sem_INSN_STB },
112 { FR30BF_INSN_STR13, && case_sem_INSN_STR13 },
113 { FR30BF_INSN_STR13H, && case_sem_INSN_STR13H },
114 { FR30BF_INSN_STR13B, && case_sem_INSN_STR13B },
115 { FR30BF_INSN_STR14, && case_sem_INSN_STR14 },
116 { FR30BF_INSN_STR14H, && case_sem_INSN_STR14H },
117 { FR30BF_INSN_STR14B, && case_sem_INSN_STR14B },
118 { FR30BF_INSN_STR15, && case_sem_INSN_STR15 },
119 { FR30BF_INSN_STR15GR, && case_sem_INSN_STR15GR },
120 { FR30BF_INSN_STR15DR, && case_sem_INSN_STR15DR },
121 { FR30BF_INSN_STR15PS, && case_sem_INSN_STR15PS },
122 { FR30BF_INSN_MOV, && case_sem_INSN_MOV },
123 { FR30BF_INSN_MOVDR, && case_sem_INSN_MOVDR },
124 { FR30BF_INSN_MOVPS, && case_sem_INSN_MOVPS },
125 { FR30BF_INSN_MOV2DR, && case_sem_INSN_MOV2DR },
126 { FR30BF_INSN_MOV2PS, && case_sem_INSN_MOV2PS },
127 { FR30BF_INSN_JMP, && case_sem_INSN_JMP },
128 { FR30BF_INSN_JMPD, && case_sem_INSN_JMPD },
129 { FR30BF_INSN_CALLR, && case_sem_INSN_CALLR },
130 { FR30BF_INSN_CALLRD, && case_sem_INSN_CALLRD },
131 { FR30BF_INSN_CALL, && case_sem_INSN_CALL },
132 { FR30BF_INSN_CALLD, && case_sem_INSN_CALLD },
133 { FR30BF_INSN_RET, && case_sem_INSN_RET },
134 { FR30BF_INSN_RET_D, && case_sem_INSN_RET_D },
135 { FR30BF_INSN_INT, && case_sem_INSN_INT },
136 { FR30BF_INSN_INTE, && case_sem_INSN_INTE },
137 { FR30BF_INSN_RETI, && case_sem_INSN_RETI },
138 { FR30BF_INSN_BRAD, && case_sem_INSN_BRAD },
139 { FR30BF_INSN_BRA, && case_sem_INSN_BRA },
140 { FR30BF_INSN_BNOD, && case_sem_INSN_BNOD },
141 { FR30BF_INSN_BNO, && case_sem_INSN_BNO },
142 { FR30BF_INSN_BEQD, && case_sem_INSN_BEQD },
143 { FR30BF_INSN_BEQ, && case_sem_INSN_BEQ },
144 { FR30BF_INSN_BNED, && case_sem_INSN_BNED },
145 { FR30BF_INSN_BNE, && case_sem_INSN_BNE },
146 { FR30BF_INSN_BCD, && case_sem_INSN_BCD },
147 { FR30BF_INSN_BC, && case_sem_INSN_BC },
148 { FR30BF_INSN_BNCD, && case_sem_INSN_BNCD },
149 { FR30BF_INSN_BNC, && case_sem_INSN_BNC },
150 { FR30BF_INSN_BND, && case_sem_INSN_BND },
151 { FR30BF_INSN_BN, && case_sem_INSN_BN },
152 { FR30BF_INSN_BPD, && case_sem_INSN_BPD },
153 { FR30BF_INSN_BP, && case_sem_INSN_BP },
154 { FR30BF_INSN_BVD, && case_sem_INSN_BVD },
155 { FR30BF_INSN_BV, && case_sem_INSN_BV },
156 { FR30BF_INSN_BNVD, && case_sem_INSN_BNVD },
157 { FR30BF_INSN_BNV, && case_sem_INSN_BNV },
158 { FR30BF_INSN_BLTD, && case_sem_INSN_BLTD },
159 { FR30BF_INSN_BLT, && case_sem_INSN_BLT },
160 { FR30BF_INSN_BGED, && case_sem_INSN_BGED },
161 { FR30BF_INSN_BGE, && case_sem_INSN_BGE },
162 { FR30BF_INSN_BLED, && case_sem_INSN_BLED },
163 { FR30BF_INSN_BLE, && case_sem_INSN_BLE },
164 { FR30BF_INSN_BGTD, && case_sem_INSN_BGTD },
165 { FR30BF_INSN_BGT, && case_sem_INSN_BGT },
166 { FR30BF_INSN_BLSD, && case_sem_INSN_BLSD },
167 { FR30BF_INSN_BLS, && case_sem_INSN_BLS },
168 { FR30BF_INSN_BHID, && case_sem_INSN_BHID },
169 { FR30BF_INSN_BHI, && case_sem_INSN_BHI },
170 { FR30BF_INSN_DMOVR13, && case_sem_INSN_DMOVR13 },
171 { FR30BF_INSN_DMOVR13H, && case_sem_INSN_DMOVR13H },
172 { FR30BF_INSN_DMOVR13B, && case_sem_INSN_DMOVR13B },
173 { FR30BF_INSN_DMOVR13PI, && case_sem_INSN_DMOVR13PI },
174 { FR30BF_INSN_DMOVR13PIH, && case_sem_INSN_DMOVR13PIH },
175 { FR30BF_INSN_DMOVR13PIB, && case_sem_INSN_DMOVR13PIB },
176 { FR30BF_INSN_DMOVR15PI, && case_sem_INSN_DMOVR15PI },
177 { FR30BF_INSN_DMOV2R13, && case_sem_INSN_DMOV2R13 },
178 { FR30BF_INSN_DMOV2R13H, && case_sem_INSN_DMOV2R13H },
179 { FR30BF_INSN_DMOV2R13B, && case_sem_INSN_DMOV2R13B },
180 { FR30BF_INSN_DMOV2R13PI, && case_sem_INSN_DMOV2R13PI },
181 { FR30BF_INSN_DMOV2R13PIH, && case_sem_INSN_DMOV2R13PIH },
182 { FR30BF_INSN_DMOV2R13PIB, && case_sem_INSN_DMOV2R13PIB },
183 { FR30BF_INSN_DMOV2R15PD, && case_sem_INSN_DMOV2R15PD },
184 { FR30BF_INSN_LDRES, && case_sem_INSN_LDRES },
185 { FR30BF_INSN_STRES, && case_sem_INSN_STRES },
186 { FR30BF_INSN_COPOP, && case_sem_INSN_COPOP },
187 { FR30BF_INSN_COPLD, && case_sem_INSN_COPLD },
188 { FR30BF_INSN_COPST, && case_sem_INSN_COPST },
189 { FR30BF_INSN_COPSV, && case_sem_INSN_COPSV },
190 { FR30BF_INSN_NOP, && case_sem_INSN_NOP },
191 { FR30BF_INSN_ANDCCR, && case_sem_INSN_ANDCCR },
192 { FR30BF_INSN_ORCCR, && case_sem_INSN_ORCCR },
193 { FR30BF_INSN_STILM, && case_sem_INSN_STILM },
194 { FR30BF_INSN_ADDSP, && case_sem_INSN_ADDSP },
195 { FR30BF_INSN_EXTSB, && case_sem_INSN_EXTSB },
196 { FR30BF_INSN_EXTUB, && case_sem_INSN_EXTUB },
197 { FR30BF_INSN_EXTSH, && case_sem_INSN_EXTSH },
198 { FR30BF_INSN_EXTUH, && case_sem_INSN_EXTUH },
199 { FR30BF_INSN_LDM0, && case_sem_INSN_LDM0 },
200 { FR30BF_INSN_LDM1, && case_sem_INSN_LDM1 },
201 { FR30BF_INSN_STM0, && case_sem_INSN_STM0 },
202 { FR30BF_INSN_STM1, && case_sem_INSN_STM1 },
203 { FR30BF_INSN_ENTER, && case_sem_INSN_ENTER },
204 { FR30BF_INSN_LEAVE, && case_sem_INSN_LEAVE },
205 { FR30BF_INSN_XCHB, && case_sem_INSN_XCHB },
206 { 0, 0 }
207 };
208 int i;
209
210 for (i = 0; labels[i].label != 0; ++i)
211 {
212 #if FAST_P
213 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
214 #else
215 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
216 #endif
217 }
218
219 #undef DEFINE_LABELS
220 #endif /* DEFINE_LABELS */
221
222 #ifdef DEFINE_SWITCH
223
224 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
225 off frills like tracing and profiling. */
226 /* FIXME: A better way would be to have TRACE_RESULT check for something
227 that can cause it to be optimized out. Another way would be to emit
228 special handlers into the instruction "stream". */
229
230 #if FAST_P
231 #undef TRACE_RESULT
232 #define TRACE_RESULT(cpu, abuf, name, type, val)
233 #endif
234
235 #undef GET_ATTR
236 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
237 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
238 #else
239 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr)
240 #endif
241
242 {
243
244 #if WITH_SCACHE_PBB
245
246 /* Branch to next handler without going around main loop. */
247 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
248 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
249
250 #else /* ! WITH_SCACHE_PBB */
251
252 #define NEXT(vpc) BREAK (sem)
253 #ifdef __GNUC__
254 #if FAST_P
255 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
256 #else
257 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
258 #endif
259 #else
260 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
261 #endif
262
263 #endif /* ! WITH_SCACHE_PBB */
264
265 {
266
267 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
268 {
269 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
270 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
271 #define FLD(f) abuf->fields.fmt_empty.f
272 int UNUSED written = 0;
273 IADDR UNUSED pc = abuf->addr;
274 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
275
276 {
277 /* Update the recorded pc in the cpu state struct.
278 Only necessary for WITH_SCACHE case, but to avoid the
279 conditional compilation .... */
280 SET_H_PC (pc);
281 /* Virtual insns have zero size. Overwrite vpc with address of next insn
282 using the default-insn-bitsize spec. When executing insns in parallel
283 we may want to queue the fault and continue execution. */
284 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
285 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc);
286 }
287
288 #undef FLD
289 }
290 NEXT (vpc);
291
292 CASE (sem, INSN_X_AFTER) : /* --after-- */
293 {
294 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
295 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
296 #define FLD(f) abuf->fields.fmt_empty.f
297 int UNUSED written = 0;
298 IADDR UNUSED pc = abuf->addr;
299 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
300
301 {
302 #if WITH_SCACHE_PBB_FR30BF
303 fr30bf_pbb_after (current_cpu, sem_arg);
304 #endif
305 }
306
307 #undef FLD
308 }
309 NEXT (vpc);
310
311 CASE (sem, INSN_X_BEFORE) : /* --before-- */
312 {
313 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
314 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
315 #define FLD(f) abuf->fields.fmt_empty.f
316 int UNUSED written = 0;
317 IADDR UNUSED pc = abuf->addr;
318 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
319
320 {
321 #if WITH_SCACHE_PBB_FR30BF
322 fr30bf_pbb_before (current_cpu, sem_arg);
323 #endif
324 }
325
326 #undef FLD
327 }
328 NEXT (vpc);
329
330 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
331 {
332 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
333 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
334 #define FLD(f) abuf->fields.fmt_empty.f
335 int UNUSED written = 0;
336 IADDR UNUSED pc = abuf->addr;
337 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
338
339 {
340 #if WITH_SCACHE_PBB_FR30BF
341 #ifdef DEFINE_SWITCH
342 vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
343 pbb_br_type, pbb_br_npc);
344 BREAK (sem);
345 #else
346 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
347 vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
348 CPU_PBB_BR_TYPE (current_cpu),
349 CPU_PBB_BR_NPC (current_cpu));
350 #endif
351 #endif
352 }
353
354 #undef FLD
355 }
356 NEXT (vpc);
357
358 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
359 {
360 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
361 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
362 #define FLD(f) abuf->fields.fmt_empty.f
363 int UNUSED written = 0;
364 IADDR UNUSED pc = abuf->addr;
365 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
366
367 {
368 #if WITH_SCACHE_PBB_FR30BF
369 vpc = fr30bf_pbb_chain (current_cpu, sem_arg);
370 #ifdef DEFINE_SWITCH
371 BREAK (sem);
372 #endif
373 #endif
374 }
375
376 #undef FLD
377 }
378 NEXT (vpc);
379
380 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
381 {
382 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
383 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
384 #define FLD(f) abuf->fields.fmt_empty.f
385 int UNUSED written = 0;
386 IADDR UNUSED pc = abuf->addr;
387 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
388
389 {
390 #if WITH_SCACHE_PBB_FR30BF
391 #if defined DEFINE_SWITCH || defined FAST_P
392 /* In the switch case FAST_P is a constant, allowing several optimizations
393 in any called inline functions. */
394 vpc = fr30bf_pbb_begin (current_cpu, FAST_P);
395 #else
396 #if 0 /* cgen engine can't handle dynamic fast/full switching yet. */
397 vpc = fr30bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
398 #else
399 vpc = fr30bf_pbb_begin (current_cpu, 0);
400 #endif
401 #endif
402 #endif
403 }
404
405 #undef FLD
406 }
407 NEXT (vpc);
408
409 CASE (sem, INSN_ADD) : /* add $Rj,$Ri */
410 {
411 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
412 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
413 #define FLD(f) abuf->fields.sfmt_add.f
414 int UNUSED written = 0;
415 IADDR UNUSED pc = abuf->addr;
416 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
417
418 {
419 {
420 BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
421 CPU (h_vbit) = opval;
422 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
423 }
424 {
425 BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
426 CPU (h_cbit) = opval;
427 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
428 }
429 {
430 SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
431 * FLD (i_Ri) = opval;
432 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
433 }
434 {
435 {
436 BI opval = EQSI (* FLD (i_Ri), 0);
437 CPU (h_zbit) = opval;
438 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
439 }
440 {
441 BI opval = LTSI (* FLD (i_Ri), 0);
442 CPU (h_nbit) = opval;
443 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
444 }
445 }
446 }
447
448 #undef FLD
449 }
450 NEXT (vpc);
451
452 CASE (sem, INSN_ADDI) : /* add $u4,$Ri */
453 {
454 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
455 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
456 #define FLD(f) abuf->fields.sfmt_addi.f
457 int UNUSED written = 0;
458 IADDR UNUSED pc = abuf->addr;
459 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
460
461 {
462 {
463 BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0);
464 CPU (h_vbit) = opval;
465 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
466 }
467 {
468 BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_u4), 0);
469 CPU (h_cbit) = opval;
470 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
471 }
472 {
473 SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
474 * FLD (i_Ri) = opval;
475 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
476 }
477 {
478 {
479 BI opval = EQSI (* FLD (i_Ri), 0);
480 CPU (h_zbit) = opval;
481 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
482 }
483 {
484 BI opval = LTSI (* FLD (i_Ri), 0);
485 CPU (h_nbit) = opval;
486 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
487 }
488 }
489 }
490
491 #undef FLD
492 }
493 NEXT (vpc);
494
495 CASE (sem, INSN_ADD2) : /* add2 $m4,$Ri */
496 {
497 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
498 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
499 #define FLD(f) abuf->fields.sfmt_add2.f
500 int UNUSED written = 0;
501 IADDR UNUSED pc = abuf->addr;
502 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
503
504 {
505 {
506 BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0);
507 CPU (h_vbit) = opval;
508 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
509 }
510 {
511 BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_m4), 0);
512 CPU (h_cbit) = opval;
513 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
514 }
515 {
516 SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
517 * FLD (i_Ri) = opval;
518 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
519 }
520 {
521 {
522 BI opval = EQSI (* FLD (i_Ri), 0);
523 CPU (h_zbit) = opval;
524 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
525 }
526 {
527 BI opval = LTSI (* FLD (i_Ri), 0);
528 CPU (h_nbit) = opval;
529 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
530 }
531 }
532 }
533
534 #undef FLD
535 }
536 NEXT (vpc);
537
538 CASE (sem, INSN_ADDC) : /* addc $Rj,$Ri */
539 {
540 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
541 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
542 #define FLD(f) abuf->fields.sfmt_add.f
543 int UNUSED written = 0;
544 IADDR UNUSED pc = abuf->addr;
545 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
546
547 {
548 SI tmp_tmp;
549 tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
550 {
551 BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
552 CPU (h_vbit) = opval;
553 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
554 }
555 {
556 BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
557 CPU (h_cbit) = opval;
558 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
559 }
560 {
561 SI opval = tmp_tmp;
562 * FLD (i_Ri) = opval;
563 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
564 }
565 {
566 {
567 BI opval = EQSI (* FLD (i_Ri), 0);
568 CPU (h_zbit) = opval;
569 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
570 }
571 {
572 BI opval = LTSI (* FLD (i_Ri), 0);
573 CPU (h_nbit) = opval;
574 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
575 }
576 }
577 }
578
579 #undef FLD
580 }
581 NEXT (vpc);
582
583 CASE (sem, INSN_ADDN) : /* addn $Rj,$Ri */
584 {
585 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
586 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
587 #define FLD(f) abuf->fields.sfmt_add.f
588 int UNUSED written = 0;
589 IADDR UNUSED pc = abuf->addr;
590 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
591
592 {
593 SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
594 * FLD (i_Ri) = opval;
595 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
596 }
597
598 #undef FLD
599 }
600 NEXT (vpc);
601
602 CASE (sem, INSN_ADDNI) : /* addn $u4,$Ri */
603 {
604 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
605 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
606 #define FLD(f) abuf->fields.sfmt_addi.f
607 int UNUSED written = 0;
608 IADDR UNUSED pc = abuf->addr;
609 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
610
611 {
612 SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
613 * FLD (i_Ri) = opval;
614 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
615 }
616
617 #undef FLD
618 }
619 NEXT (vpc);
620
621 CASE (sem, INSN_ADDN2) : /* addn2 $m4,$Ri */
622 {
623 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
624 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
625 #define FLD(f) abuf->fields.sfmt_add2.f
626 int UNUSED written = 0;
627 IADDR UNUSED pc = abuf->addr;
628 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
629
630 {
631 SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
632 * FLD (i_Ri) = opval;
633 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
634 }
635
636 #undef FLD
637 }
638 NEXT (vpc);
639
640 CASE (sem, INSN_SUB) : /* sub $Rj,$Ri */
641 {
642 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
643 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
644 #define FLD(f) abuf->fields.sfmt_add.f
645 int UNUSED written = 0;
646 IADDR UNUSED pc = abuf->addr;
647 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
648
649 {
650 {
651 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
652 CPU (h_vbit) = opval;
653 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
654 }
655 {
656 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
657 CPU (h_cbit) = opval;
658 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
659 }
660 {
661 SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
662 * FLD (i_Ri) = opval;
663 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
664 }
665 {
666 {
667 BI opval = EQSI (* FLD (i_Ri), 0);
668 CPU (h_zbit) = opval;
669 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
670 }
671 {
672 BI opval = LTSI (* FLD (i_Ri), 0);
673 CPU (h_nbit) = opval;
674 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
675 }
676 }
677 }
678
679 #undef FLD
680 }
681 NEXT (vpc);
682
683 CASE (sem, INSN_SUBC) : /* subc $Rj,$Ri */
684 {
685 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
686 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
687 #define FLD(f) abuf->fields.sfmt_add.f
688 int UNUSED written = 0;
689 IADDR UNUSED pc = abuf->addr;
690 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
691
692 {
693 SI tmp_tmp;
694 tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
695 {
696 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
697 CPU (h_vbit) = opval;
698 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
699 }
700 {
701 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
702 CPU (h_cbit) = opval;
703 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
704 }
705 {
706 SI opval = tmp_tmp;
707 * FLD (i_Ri) = opval;
708 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
709 }
710 {
711 {
712 BI opval = EQSI (* FLD (i_Ri), 0);
713 CPU (h_zbit) = opval;
714 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
715 }
716 {
717 BI opval = LTSI (* FLD (i_Ri), 0);
718 CPU (h_nbit) = opval;
719 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
720 }
721 }
722 }
723
724 #undef FLD
725 }
726 NEXT (vpc);
727
728 CASE (sem, INSN_SUBN) : /* subn $Rj,$Ri */
729 {
730 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
731 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
732 #define FLD(f) abuf->fields.sfmt_add.f
733 int UNUSED written = 0;
734 IADDR UNUSED pc = abuf->addr;
735 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
736
737 {
738 SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
739 * FLD (i_Ri) = opval;
740 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
741 }
742
743 #undef FLD
744 }
745 NEXT (vpc);
746
747 CASE (sem, INSN_CMP) : /* cmp $Rj,$Ri */
748 {
749 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
750 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
751 #define FLD(f) abuf->fields.sfmt_str13.f
752 int UNUSED written = 0;
753 IADDR UNUSED pc = abuf->addr;
754 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
755
756 {
757 SI tmp_tmp1;
758 {
759 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
760 CPU (h_vbit) = opval;
761 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
762 }
763 {
764 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
765 CPU (h_cbit) = opval;
766 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
767 }
768 tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
769 {
770 {
771 BI opval = EQSI (tmp_tmp1, 0);
772 CPU (h_zbit) = opval;
773 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
774 }
775 {
776 BI opval = LTSI (tmp_tmp1, 0);
777 CPU (h_nbit) = opval;
778 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
779 }
780 }
781 }
782
783 #undef FLD
784 }
785 NEXT (vpc);
786
787 CASE (sem, INSN_CMPI) : /* cmp $u4,$Ri */
788 {
789 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
790 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
791 #define FLD(f) abuf->fields.sfmt_addi.f
792 int UNUSED written = 0;
793 IADDR UNUSED pc = abuf->addr;
794 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
795
796 {
797 SI tmp_tmp1;
798 {
799 BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0);
800 CPU (h_vbit) = opval;
801 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
802 }
803 {
804 BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_u4), 0);
805 CPU (h_cbit) = opval;
806 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
807 }
808 tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4));
809 {
810 {
811 BI opval = EQSI (tmp_tmp1, 0);
812 CPU (h_zbit) = opval;
813 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
814 }
815 {
816 BI opval = LTSI (tmp_tmp1, 0);
817 CPU (h_nbit) = opval;
818 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
819 }
820 }
821 }
822
823 #undef FLD
824 }
825 NEXT (vpc);
826
827 CASE (sem, INSN_CMP2) : /* cmp2 $m4,$Ri */
828 {
829 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
830 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
831 #define FLD(f) abuf->fields.sfmt_add2.f
832 int UNUSED written = 0;
833 IADDR UNUSED pc = abuf->addr;
834 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
835
836 {
837 SI tmp_tmp1;
838 {
839 BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0);
840 CPU (h_vbit) = opval;
841 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
842 }
843 {
844 BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_m4), 0);
845 CPU (h_cbit) = opval;
846 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
847 }
848 tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4));
849 {
850 {
851 BI opval = EQSI (tmp_tmp1, 0);
852 CPU (h_zbit) = opval;
853 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
854 }
855 {
856 BI opval = LTSI (tmp_tmp1, 0);
857 CPU (h_nbit) = opval;
858 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
859 }
860 }
861 }
862
863 #undef FLD
864 }
865 NEXT (vpc);
866
867 CASE (sem, INSN_AND) : /* and $Rj,$Ri */
868 {
869 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
870 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
871 #define FLD(f) abuf->fields.sfmt_add.f
872 int UNUSED written = 0;
873 IADDR UNUSED pc = abuf->addr;
874 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
875
876 {
877 {
878 SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj));
879 * FLD (i_Ri) = opval;
880 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
881 }
882 {
883 {
884 BI opval = EQSI (* FLD (i_Ri), 0);
885 CPU (h_zbit) = opval;
886 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
887 }
888 {
889 BI opval = LTSI (* FLD (i_Ri), 0);
890 CPU (h_nbit) = opval;
891 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
892 }
893 }
894 }
895
896 #undef FLD
897 }
898 NEXT (vpc);
899
900 CASE (sem, INSN_OR) : /* or $Rj,$Ri */
901 {
902 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
903 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
904 #define FLD(f) abuf->fields.sfmt_add.f
905 int UNUSED written = 0;
906 IADDR UNUSED pc = abuf->addr;
907 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
908
909 {
910 {
911 SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj));
912 * FLD (i_Ri) = opval;
913 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
914 }
915 {
916 {
917 BI opval = EQSI (* FLD (i_Ri), 0);
918 CPU (h_zbit) = opval;
919 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
920 }
921 {
922 BI opval = LTSI (* FLD (i_Ri), 0);
923 CPU (h_nbit) = opval;
924 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
925 }
926 }
927 }
928
929 #undef FLD
930 }
931 NEXT (vpc);
932
933 CASE (sem, INSN_EOR) : /* eor $Rj,$Ri */
934 {
935 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
936 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
937 #define FLD(f) abuf->fields.sfmt_add.f
938 int UNUSED written = 0;
939 IADDR UNUSED pc = abuf->addr;
940 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
941
942 {
943 {
944 SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj));
945 * FLD (i_Ri) = opval;
946 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
947 }
948 {
949 {
950 BI opval = EQSI (* FLD (i_Ri), 0);
951 CPU (h_zbit) = opval;
952 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
953 }
954 {
955 BI opval = LTSI (* FLD (i_Ri), 0);
956 CPU (h_nbit) = opval;
957 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
958 }
959 }
960 }
961
962 #undef FLD
963 }
964 NEXT (vpc);
965
966 CASE (sem, INSN_ANDM) : /* and $Rj,@$Ri */
967 {
968 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
969 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
970 #define FLD(f) abuf->fields.sfmt_str13.f
971 int UNUSED written = 0;
972 IADDR UNUSED pc = abuf->addr;
973 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
974
975 {
976 SI tmp_tmp;
977 tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
978 {
979 {
980 BI opval = EQSI (tmp_tmp, 0);
981 CPU (h_zbit) = opval;
982 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
983 }
984 {
985 BI opval = LTSI (tmp_tmp, 0);
986 CPU (h_nbit) = opval;
987 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
988 }
989 }
990 {
991 SI opval = tmp_tmp;
992 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
993 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
994 }
995 }
996
997 #undef FLD
998 }
999 NEXT (vpc);
1000
1001 CASE (sem, INSN_ANDH) : /* andh $Rj,@$Ri */
1002 {
1003 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1004 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1005 #define FLD(f) abuf->fields.sfmt_str13.f
1006 int UNUSED written = 0;
1007 IADDR UNUSED pc = abuf->addr;
1008 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1009
1010 {
1011 HI tmp_tmp;
1012 tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1013 {
1014 {
1015 BI opval = EQHI (tmp_tmp, 0);
1016 CPU (h_zbit) = opval;
1017 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1018 }
1019 {
1020 BI opval = LTHI (tmp_tmp, 0);
1021 CPU (h_nbit) = opval;
1022 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1023 }
1024 }
1025 {
1026 HI opval = tmp_tmp;
1027 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1028 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1029 }
1030 }
1031
1032 #undef FLD
1033 }
1034 NEXT (vpc);
1035
1036 CASE (sem, INSN_ANDB) : /* andb $Rj,@$Ri */
1037 {
1038 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1039 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1040 #define FLD(f) abuf->fields.sfmt_str13.f
1041 int UNUSED written = 0;
1042 IADDR UNUSED pc = abuf->addr;
1043 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1044
1045 {
1046 QI tmp_tmp;
1047 tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1048 {
1049 {
1050 BI opval = EQQI (tmp_tmp, 0);
1051 CPU (h_zbit) = opval;
1052 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1053 }
1054 {
1055 BI opval = LTQI (tmp_tmp, 0);
1056 CPU (h_nbit) = opval;
1057 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1058 }
1059 }
1060 {
1061 QI opval = tmp_tmp;
1062 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1063 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1064 }
1065 }
1066
1067 #undef FLD
1068 }
1069 NEXT (vpc);
1070
1071 CASE (sem, INSN_ORM) : /* or $Rj,@$Ri */
1072 {
1073 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1074 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1075 #define FLD(f) abuf->fields.sfmt_str13.f
1076 int UNUSED written = 0;
1077 IADDR UNUSED pc = abuf->addr;
1078 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1079
1080 {
1081 SI tmp_tmp;
1082 tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1083 {
1084 {
1085 BI opval = EQSI (tmp_tmp, 0);
1086 CPU (h_zbit) = opval;
1087 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1088 }
1089 {
1090 BI opval = LTSI (tmp_tmp, 0);
1091 CPU (h_nbit) = opval;
1092 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1093 }
1094 }
1095 {
1096 SI opval = tmp_tmp;
1097 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
1098 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1099 }
1100 }
1101
1102 #undef FLD
1103 }
1104 NEXT (vpc);
1105
1106 CASE (sem, INSN_ORH) : /* orh $Rj,@$Ri */
1107 {
1108 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1109 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1110 #define FLD(f) abuf->fields.sfmt_str13.f
1111 int UNUSED written = 0;
1112 IADDR UNUSED pc = abuf->addr;
1113 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1114
1115 {
1116 HI tmp_tmp;
1117 tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1118 {
1119 {
1120 BI opval = EQHI (tmp_tmp, 0);
1121 CPU (h_zbit) = opval;
1122 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1123 }
1124 {
1125 BI opval = LTHI (tmp_tmp, 0);
1126 CPU (h_nbit) = opval;
1127 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1128 }
1129 }
1130 {
1131 HI opval = tmp_tmp;
1132 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1133 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1134 }
1135 }
1136
1137 #undef FLD
1138 }
1139 NEXT (vpc);
1140
1141 CASE (sem, INSN_ORB) : /* orb $Rj,@$Ri */
1142 {
1143 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1144 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1145 #define FLD(f) abuf->fields.sfmt_str13.f
1146 int UNUSED written = 0;
1147 IADDR UNUSED pc = abuf->addr;
1148 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1149
1150 {
1151 QI tmp_tmp;
1152 tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1153 {
1154 {
1155 BI opval = EQQI (tmp_tmp, 0);
1156 CPU (h_zbit) = opval;
1157 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1158 }
1159 {
1160 BI opval = LTQI (tmp_tmp, 0);
1161 CPU (h_nbit) = opval;
1162 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1163 }
1164 }
1165 {
1166 QI opval = tmp_tmp;
1167 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1168 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1169 }
1170 }
1171
1172 #undef FLD
1173 }
1174 NEXT (vpc);
1175
1176 CASE (sem, INSN_EORM) : /* eor $Rj,@$Ri */
1177 {
1178 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1179 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1180 #define FLD(f) abuf->fields.sfmt_str13.f
1181 int UNUSED written = 0;
1182 IADDR UNUSED pc = abuf->addr;
1183 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1184
1185 {
1186 SI tmp_tmp;
1187 tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1188 {
1189 {
1190 BI opval = EQSI (tmp_tmp, 0);
1191 CPU (h_zbit) = opval;
1192 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1193 }
1194 {
1195 BI opval = LTSI (tmp_tmp, 0);
1196 CPU (h_nbit) = opval;
1197 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1198 }
1199 }
1200 {
1201 SI opval = tmp_tmp;
1202 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
1203 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1204 }
1205 }
1206
1207 #undef FLD
1208 }
1209 NEXT (vpc);
1210
1211 CASE (sem, INSN_EORH) : /* eorh $Rj,@$Ri */
1212 {
1213 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1214 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1215 #define FLD(f) abuf->fields.sfmt_str13.f
1216 int UNUSED written = 0;
1217 IADDR UNUSED pc = abuf->addr;
1218 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1219
1220 {
1221 HI tmp_tmp;
1222 tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1223 {
1224 {
1225 BI opval = EQHI (tmp_tmp, 0);
1226 CPU (h_zbit) = opval;
1227 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1228 }
1229 {
1230 BI opval = LTHI (tmp_tmp, 0);
1231 CPU (h_nbit) = opval;
1232 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1233 }
1234 }
1235 {
1236 HI opval = tmp_tmp;
1237 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1238 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1239 }
1240 }
1241
1242 #undef FLD
1243 }
1244 NEXT (vpc);
1245
1246 CASE (sem, INSN_EORB) : /* eorb $Rj,@$Ri */
1247 {
1248 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1249 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1250 #define FLD(f) abuf->fields.sfmt_str13.f
1251 int UNUSED written = 0;
1252 IADDR UNUSED pc = abuf->addr;
1253 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1254
1255 {
1256 QI tmp_tmp;
1257 tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1258 {
1259 {
1260 BI opval = EQQI (tmp_tmp, 0);
1261 CPU (h_zbit) = opval;
1262 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1263 }
1264 {
1265 BI opval = LTQI (tmp_tmp, 0);
1266 CPU (h_nbit) = opval;
1267 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1268 }
1269 }
1270 {
1271 QI opval = tmp_tmp;
1272 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1273 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1274 }
1275 }
1276
1277 #undef FLD
1278 }
1279 NEXT (vpc);
1280
1281 CASE (sem, INSN_BANDL) : /* bandl $u4,@$Ri */
1282 {
1283 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1284 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1285 #define FLD(f) abuf->fields.sfmt_addi.f
1286 int UNUSED written = 0;
1287 IADDR UNUSED pc = abuf->addr;
1288 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1289
1290 {
1291 QI opval = ANDQI (ORQI (FLD (f_u4), 240), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1292 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1293 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1294 }
1295
1296 #undef FLD
1297 }
1298 NEXT (vpc);
1299
1300 CASE (sem, INSN_BORL) : /* borl $u4,@$Ri */
1301 {
1302 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1303 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1304 #define FLD(f) abuf->fields.sfmt_addi.f
1305 int UNUSED written = 0;
1306 IADDR UNUSED pc = abuf->addr;
1307 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1308
1309 {
1310 QI opval = ORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1311 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1312 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1313 }
1314
1315 #undef FLD
1316 }
1317 NEXT (vpc);
1318
1319 CASE (sem, INSN_BEORL) : /* beorl $u4,@$Ri */
1320 {
1321 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1322 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1323 #define FLD(f) abuf->fields.sfmt_addi.f
1324 int UNUSED written = 0;
1325 IADDR UNUSED pc = abuf->addr;
1326 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1327
1328 {
1329 QI opval = XORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1330 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1331 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1332 }
1333
1334 #undef FLD
1335 }
1336 NEXT (vpc);
1337
1338 CASE (sem, INSN_BANDH) : /* bandh $u4,@$Ri */
1339 {
1340 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1341 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1342 #define FLD(f) abuf->fields.sfmt_addi.f
1343 int UNUSED written = 0;
1344 IADDR UNUSED pc = abuf->addr;
1345 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1346
1347 {
1348 QI opval = ANDQI (ORQI (SLLQI (FLD (f_u4), 4), 15), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1349 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1350 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1351 }
1352
1353 #undef FLD
1354 }
1355 NEXT (vpc);
1356
1357 CASE (sem, INSN_BORH) : /* borh $u4,@$Ri */
1358 {
1359 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1360 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1361 #define FLD(f) abuf->fields.sfmt_addi.f
1362 int UNUSED written = 0;
1363 IADDR UNUSED pc = abuf->addr;
1364 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1365
1366 {
1367 QI opval = ORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1368 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1369 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1370 }
1371
1372 #undef FLD
1373 }
1374 NEXT (vpc);
1375
1376 CASE (sem, INSN_BEORH) : /* beorh $u4,@$Ri */
1377 {
1378 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1379 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1380 #define FLD(f) abuf->fields.sfmt_addi.f
1381 int UNUSED written = 0;
1382 IADDR UNUSED pc = abuf->addr;
1383 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1384
1385 {
1386 QI opval = XORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1387 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1388 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1389 }
1390
1391 #undef FLD
1392 }
1393 NEXT (vpc);
1394
1395 CASE (sem, INSN_BTSTL) : /* btstl $u4,@$Ri */
1396 {
1397 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1398 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1399 #define FLD(f) abuf->fields.sfmt_addi.f
1400 int UNUSED written = 0;
1401 IADDR UNUSED pc = abuf->addr;
1402 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1403
1404 {
1405 QI tmp_tmp;
1406 tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1407 {
1408 BI opval = EQQI (tmp_tmp, 0);
1409 CPU (h_zbit) = opval;
1410 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1411 }
1412 {
1413 BI opval = 0;
1414 CPU (h_nbit) = opval;
1415 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1416 }
1417 }
1418
1419 #undef FLD
1420 }
1421 NEXT (vpc);
1422
1423 CASE (sem, INSN_BTSTH) : /* btsth $u4,@$Ri */
1424 {
1425 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1426 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1427 #define FLD(f) abuf->fields.sfmt_addi.f
1428 int UNUSED written = 0;
1429 IADDR UNUSED pc = abuf->addr;
1430 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1431
1432 {
1433 QI tmp_tmp;
1434 tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1435 {
1436 BI opval = EQQI (tmp_tmp, 0);
1437 CPU (h_zbit) = opval;
1438 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1439 }
1440 {
1441 BI opval = LTQI (tmp_tmp, 0);
1442 CPU (h_nbit) = opval;
1443 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1444 }
1445 }
1446
1447 #undef FLD
1448 }
1449 NEXT (vpc);
1450
1451 CASE (sem, INSN_MUL) : /* mul $Rj,$Ri */
1452 {
1453 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1454 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1455 #define FLD(f) abuf->fields.sfmt_str13.f
1456 int UNUSED written = 0;
1457 IADDR UNUSED pc = abuf->addr;
1458 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1459
1460 {
1461 DI tmp_tmp;
1462 tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri)));
1463 {
1464 SI opval = TRUNCDISI (tmp_tmp);
1465 SET_H_DR (((UINT) 5), opval);
1466 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1467 }
1468 {
1469 SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
1470 SET_H_DR (((UINT) 4), opval);
1471 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1472 }
1473 {
1474 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1475 CPU (h_nbit) = opval;
1476 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1477 }
1478 {
1479 BI opval = EQDI (tmp_tmp, MAKEDI (0, 0));
1480 CPU (h_zbit) = opval;
1481 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1482 }
1483 {
1484 BI opval = ORIF (GTDI (tmp_tmp, MAKEDI (0, 2147483647)), LTDI (tmp_tmp, NEGDI (MAKEDI (0, 0x80000000))));
1485 CPU (h_vbit) = opval;
1486 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1487 }
1488 }
1489
1490 #undef FLD
1491 }
1492 NEXT (vpc);
1493
1494 CASE (sem, INSN_MULU) : /* mulu $Rj,$Ri */
1495 {
1496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1498 #define FLD(f) abuf->fields.sfmt_str13.f
1499 int UNUSED written = 0;
1500 IADDR UNUSED pc = abuf->addr;
1501 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1502
1503 {
1504 DI tmp_tmp;
1505 tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri)));
1506 {
1507 SI opval = TRUNCDISI (tmp_tmp);
1508 SET_H_DR (((UINT) 5), opval);
1509 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1510 }
1511 {
1512 SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
1513 SET_H_DR (((UINT) 4), opval);
1514 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1515 }
1516 {
1517 BI opval = LTSI (GET_H_DR (((UINT) 4)), 0);
1518 CPU (h_nbit) = opval;
1519 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1520 }
1521 {
1522 BI opval = EQSI (GET_H_DR (((UINT) 5)), 0);
1523 CPU (h_zbit) = opval;
1524 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1525 }
1526 {
1527 BI opval = NESI (GET_H_DR (((UINT) 4)), 0);
1528 CPU (h_vbit) = opval;
1529 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1530 }
1531 }
1532
1533 #undef FLD
1534 }
1535 NEXT (vpc);
1536
1537 CASE (sem, INSN_MULH) : /* mulh $Rj,$Ri */
1538 {
1539 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1540 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1541 #define FLD(f) abuf->fields.sfmt_str13.f
1542 int UNUSED written = 0;
1543 IADDR UNUSED pc = abuf->addr;
1544 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1545
1546 {
1547 {
1548 SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri)));
1549 SET_H_DR (((UINT) 5), opval);
1550 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1551 }
1552 {
1553 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1554 CPU (h_nbit) = opval;
1555 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1556 }
1557 {
1558 BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
1559 CPU (h_zbit) = opval;
1560 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1561 }
1562 }
1563
1564 #undef FLD
1565 }
1566 NEXT (vpc);
1567
1568 CASE (sem, INSN_MULUH) : /* muluh $Rj,$Ri */
1569 {
1570 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1571 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1572 #define FLD(f) abuf->fields.sfmt_str13.f
1573 int UNUSED written = 0;
1574 IADDR UNUSED pc = abuf->addr;
1575 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1576
1577 {
1578 {
1579 SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535));
1580 SET_H_DR (((UINT) 5), opval);
1581 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1582 }
1583 {
1584 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1585 CPU (h_nbit) = opval;
1586 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1587 }
1588 {
1589 BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
1590 CPU (h_zbit) = opval;
1591 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1592 }
1593 }
1594
1595 #undef FLD
1596 }
1597 NEXT (vpc);
1598
1599 CASE (sem, INSN_DIV0S) : /* div0s $Ri */
1600 {
1601 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1602 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1603 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1604 int UNUSED written = 0;
1605 IADDR UNUSED pc = abuf->addr;
1606 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1607
1608 {
1609 {
1610 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1611 CPU (h_d0bit) = opval;
1612 TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
1613 }
1614 {
1615 BI opval = XORBI (CPU (h_d0bit), LTSI (* FLD (i_Ri), 0));
1616 CPU (h_d1bit) = opval;
1617 TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
1618 }
1619 if (NEBI (CPU (h_d0bit), 0)) {
1620 {
1621 SI opval = 0xffffffff;
1622 SET_H_DR (((UINT) 4), opval);
1623 written |= (1 << 5);
1624 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1625 }
1626 } else {
1627 {
1628 SI opval = 0;
1629 SET_H_DR (((UINT) 4), opval);
1630 written |= (1 << 5);
1631 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1632 }
1633 }
1634 }
1635
1636 abuf->written = written;
1637 #undef FLD
1638 }
1639 NEXT (vpc);
1640
1641 CASE (sem, INSN_DIV0U) : /* div0u $Ri */
1642 {
1643 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1644 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1645 #define FLD(f) abuf->fields.fmt_empty.f
1646 int UNUSED written = 0;
1647 IADDR UNUSED pc = abuf->addr;
1648 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1649
1650 {
1651 {
1652 BI opval = 0;
1653 CPU (h_d0bit) = opval;
1654 TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
1655 }
1656 {
1657 BI opval = 0;
1658 CPU (h_d1bit) = opval;
1659 TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
1660 }
1661 {
1662 SI opval = 0;
1663 SET_H_DR (((UINT) 4), opval);
1664 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1665 }
1666 }
1667
1668 #undef FLD
1669 }
1670 NEXT (vpc);
1671
1672 CASE (sem, INSN_DIV1) : /* div1 $Ri */
1673 {
1674 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1675 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1676 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1677 int UNUSED written = 0;
1678 IADDR UNUSED pc = abuf->addr;
1679 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1680
1681 {
1682 SI tmp_tmp;
1683 {
1684 SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1);
1685 SET_H_DR (((UINT) 4), opval);
1686 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1687 }
1688 if (LTSI (GET_H_DR (((UINT) 5)), 0)) {
1689 {
1690 SI opval = ADDSI (GET_H_DR (((UINT) 4)), 1);
1691 SET_H_DR (((UINT) 4), opval);
1692 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1693 }
1694 }
1695 {
1696 SI opval = SLLSI (GET_H_DR (((UINT) 5)), 1);
1697 SET_H_DR (((UINT) 5), opval);
1698 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1699 }
1700 if (EQBI (CPU (h_d1bit), 1)) {
1701 {
1702 tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1703 {
1704 BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1705 CPU (h_cbit) = opval;
1706 written |= (1 << 6);
1707 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1708 }
1709 }
1710 } else {
1711 {
1712 tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1713 {
1714 BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1715 CPU (h_cbit) = opval;
1716 written |= (1 << 6);
1717 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1718 }
1719 }
1720 }
1721 if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) {
1722 {
1723 {
1724 SI opval = tmp_tmp;
1725 SET_H_DR (((UINT) 4), opval);
1726 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1727 }
1728 {
1729 SI opval = ORSI (GET_H_DR (((UINT) 5)), 1);
1730 SET_H_DR (((UINT) 5), opval);
1731 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1732 }
1733 }
1734 }
1735 {
1736 BI opval = EQSI (GET_H_DR (((UINT) 4)), 0);
1737 CPU (h_zbit) = opval;
1738 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1739 }
1740 }
1741
1742 abuf->written = written;
1743 #undef FLD
1744 }
1745 NEXT (vpc);
1746
1747 CASE (sem, INSN_DIV2) : /* div2 $Ri */
1748 {
1749 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1750 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1751 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1752 int UNUSED written = 0;
1753 IADDR UNUSED pc = abuf->addr;
1754 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1755
1756 {
1757 SI tmp_tmp;
1758 if (EQBI (CPU (h_d1bit), 1)) {
1759 {
1760 tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1761 {
1762 BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1763 CPU (h_cbit) = opval;
1764 written |= (1 << 3);
1765 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1766 }
1767 }
1768 } else {
1769 {
1770 tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1771 {
1772 BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1773 CPU (h_cbit) = opval;
1774 written |= (1 << 3);
1775 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1776 }
1777 }
1778 }
1779 if (EQSI (tmp_tmp, 0)) {
1780 {
1781 {
1782 BI opval = 1;
1783 CPU (h_zbit) = opval;
1784 written |= (1 << 5);
1785 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1786 }
1787 {
1788 SI opval = 0;
1789 SET_H_DR (((UINT) 4), opval);
1790 written |= (1 << 4);
1791 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1792 }
1793 }
1794 } else {
1795 {
1796 BI opval = 0;
1797 CPU (h_zbit) = opval;
1798 written |= (1 << 5);
1799 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1800 }
1801 }
1802 }
1803
1804 abuf->written = written;
1805 #undef FLD
1806 }
1807 NEXT (vpc);
1808
1809 CASE (sem, INSN_DIV3) : /* div3 */
1810 {
1811 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1812 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1813 #define FLD(f) abuf->fields.fmt_empty.f
1814 int UNUSED written = 0;
1815 IADDR UNUSED pc = abuf->addr;
1816 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1817
1818 if (EQBI (CPU (h_zbit), 1)) {
1819 {
1820 SI opval = ADDSI (GET_H_DR (((UINT) 5)), 1);
1821 SET_H_DR (((UINT) 5), opval);
1822 written |= (1 << 2);
1823 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1824 }
1825 }
1826
1827 abuf->written = written;
1828 #undef FLD
1829 }
1830 NEXT (vpc);
1831
1832 CASE (sem, INSN_DIV4S) : /* div4s */
1833 {
1834 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1835 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1836 #define FLD(f) abuf->fields.fmt_empty.f
1837 int UNUSED written = 0;
1838 IADDR UNUSED pc = abuf->addr;
1839 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1840
1841 if (EQBI (CPU (h_d1bit), 1)) {
1842 {
1843 SI opval = NEGSI (GET_H_DR (((UINT) 5)));
1844 SET_H_DR (((UINT) 5), opval);
1845 written |= (1 << 2);
1846 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
1847 }
1848 }
1849
1850 abuf->written = written;
1851 #undef FLD
1852 }
1853 NEXT (vpc);
1854
1855 CASE (sem, INSN_LSL) : /* lsl $Rj,$Ri */
1856 {
1857 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1858 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1859 #define FLD(f) abuf->fields.sfmt_add.f
1860 int UNUSED written = 0;
1861 IADDR UNUSED pc = abuf->addr;
1862 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1863
1864 {
1865 SI tmp_shift;
1866 tmp_shift = ANDSI (* FLD (i_Rj), 31);
1867 if (NESI (tmp_shift, 0)) {
1868 {
1869 {
1870 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1871 CPU (h_cbit) = opval;
1872 written |= (1 << 3);
1873 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1874 }
1875 {
1876 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1877 * FLD (i_Ri) = opval;
1878 written |= (1 << 2);
1879 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1880 }
1881 }
1882 } else {
1883 {
1884 BI opval = 0;
1885 CPU (h_cbit) = opval;
1886 written |= (1 << 3);
1887 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1888 }
1889 }
1890 {
1891 BI opval = LTSI (* FLD (i_Ri), 0);
1892 CPU (h_nbit) = opval;
1893 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1894 }
1895 {
1896 BI opval = EQSI (* FLD (i_Ri), 0);
1897 CPU (h_zbit) = opval;
1898 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1899 }
1900 }
1901
1902 abuf->written = written;
1903 #undef FLD
1904 }
1905 NEXT (vpc);
1906
1907 CASE (sem, INSN_LSLI) : /* lsl $u4,$Ri */
1908 {
1909 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1910 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1911 #define FLD(f) abuf->fields.sfmt_addi.f
1912 int UNUSED written = 0;
1913 IADDR UNUSED pc = abuf->addr;
1914 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1915
1916 {
1917 SI tmp_shift;
1918 tmp_shift = FLD (f_u4);
1919 if (NESI (tmp_shift, 0)) {
1920 {
1921 {
1922 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1923 CPU (h_cbit) = opval;
1924 written |= (1 << 3);
1925 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1926 }
1927 {
1928 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1929 * FLD (i_Ri) = opval;
1930 written |= (1 << 2);
1931 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1932 }
1933 }
1934 } else {
1935 {
1936 BI opval = 0;
1937 CPU (h_cbit) = opval;
1938 written |= (1 << 3);
1939 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1940 }
1941 }
1942 {
1943 BI opval = LTSI (* FLD (i_Ri), 0);
1944 CPU (h_nbit) = opval;
1945 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1946 }
1947 {
1948 BI opval = EQSI (* FLD (i_Ri), 0);
1949 CPU (h_zbit) = opval;
1950 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1951 }
1952 }
1953
1954 abuf->written = written;
1955 #undef FLD
1956 }
1957 NEXT (vpc);
1958
1959 CASE (sem, INSN_LSL2) : /* lsl2 $u4,$Ri */
1960 {
1961 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1962 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1963 #define FLD(f) abuf->fields.sfmt_addi.f
1964 int UNUSED written = 0;
1965 IADDR UNUSED pc = abuf->addr;
1966 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1967
1968 {
1969 SI tmp_shift;
1970 tmp_shift = ADDSI (FLD (f_u4), 16);
1971 if (NESI (tmp_shift, 0)) {
1972 {
1973 {
1974 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1975 CPU (h_cbit) = opval;
1976 written |= (1 << 3);
1977 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1978 }
1979 {
1980 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1981 * FLD (i_Ri) = opval;
1982 written |= (1 << 2);
1983 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
1984 }
1985 }
1986 } else {
1987 {
1988 BI opval = 0;
1989 CPU (h_cbit) = opval;
1990 written |= (1 << 3);
1991 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1992 }
1993 }
1994 {
1995 BI opval = LTSI (* FLD (i_Ri), 0);
1996 CPU (h_nbit) = opval;
1997 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1998 }
1999 {
2000 BI opval = EQSI (* FLD (i_Ri), 0);
2001 CPU (h_zbit) = opval;
2002 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2003 }
2004 }
2005
2006 abuf->written = written;
2007 #undef FLD
2008 }
2009 NEXT (vpc);
2010
2011 CASE (sem, INSN_LSR) : /* lsr $Rj,$Ri */
2012 {
2013 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2014 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2015 #define FLD(f) abuf->fields.sfmt_add.f
2016 int UNUSED written = 0;
2017 IADDR UNUSED pc = abuf->addr;
2018 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2019
2020 {
2021 SI tmp_shift;
2022 tmp_shift = ANDSI (* FLD (i_Rj), 31);
2023 if (NESI (tmp_shift, 0)) {
2024 {
2025 {
2026 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2027 CPU (h_cbit) = opval;
2028 written |= (1 << 3);
2029 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2030 }
2031 {
2032 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2033 * FLD (i_Ri) = opval;
2034 written |= (1 << 2);
2035 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2036 }
2037 }
2038 } else {
2039 {
2040 BI opval = 0;
2041 CPU (h_cbit) = opval;
2042 written |= (1 << 3);
2043 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2044 }
2045 }
2046 {
2047 BI opval = LTSI (* FLD (i_Ri), 0);
2048 CPU (h_nbit) = opval;
2049 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2050 }
2051 {
2052 BI opval = EQSI (* FLD (i_Ri), 0);
2053 CPU (h_zbit) = opval;
2054 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2055 }
2056 }
2057
2058 abuf->written = written;
2059 #undef FLD
2060 }
2061 NEXT (vpc);
2062
2063 CASE (sem, INSN_LSRI) : /* lsr $u4,$Ri */
2064 {
2065 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2066 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2067 #define FLD(f) abuf->fields.sfmt_addi.f
2068 int UNUSED written = 0;
2069 IADDR UNUSED pc = abuf->addr;
2070 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2071
2072 {
2073 SI tmp_shift;
2074 tmp_shift = FLD (f_u4);
2075 if (NESI (tmp_shift, 0)) {
2076 {
2077 {
2078 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2079 CPU (h_cbit) = opval;
2080 written |= (1 << 3);
2081 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2082 }
2083 {
2084 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2085 * FLD (i_Ri) = opval;
2086 written |= (1 << 2);
2087 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2088 }
2089 }
2090 } else {
2091 {
2092 BI opval = 0;
2093 CPU (h_cbit) = opval;
2094 written |= (1 << 3);
2095 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2096 }
2097 }
2098 {
2099 BI opval = LTSI (* FLD (i_Ri), 0);
2100 CPU (h_nbit) = opval;
2101 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2102 }
2103 {
2104 BI opval = EQSI (* FLD (i_Ri), 0);
2105 CPU (h_zbit) = opval;
2106 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2107 }
2108 }
2109
2110 abuf->written = written;
2111 #undef FLD
2112 }
2113 NEXT (vpc);
2114
2115 CASE (sem, INSN_LSR2) : /* lsr2 $u4,$Ri */
2116 {
2117 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2118 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2119 #define FLD(f) abuf->fields.sfmt_addi.f
2120 int UNUSED written = 0;
2121 IADDR UNUSED pc = abuf->addr;
2122 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2123
2124 {
2125 SI tmp_shift;
2126 tmp_shift = ADDSI (FLD (f_u4), 16);
2127 if (NESI (tmp_shift, 0)) {
2128 {
2129 {
2130 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2131 CPU (h_cbit) = opval;
2132 written |= (1 << 3);
2133 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2134 }
2135 {
2136 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2137 * FLD (i_Ri) = opval;
2138 written |= (1 << 2);
2139 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2140 }
2141 }
2142 } else {
2143 {
2144 BI opval = 0;
2145 CPU (h_cbit) = opval;
2146 written |= (1 << 3);
2147 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2148 }
2149 }
2150 {
2151 BI opval = LTSI (* FLD (i_Ri), 0);
2152 CPU (h_nbit) = opval;
2153 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2154 }
2155 {
2156 BI opval = EQSI (* FLD (i_Ri), 0);
2157 CPU (h_zbit) = opval;
2158 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2159 }
2160 }
2161
2162 abuf->written = written;
2163 #undef FLD
2164 }
2165 NEXT (vpc);
2166
2167 CASE (sem, INSN_ASR) : /* asr $Rj,$Ri */
2168 {
2169 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2170 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2171 #define FLD(f) abuf->fields.sfmt_add.f
2172 int UNUSED written = 0;
2173 IADDR UNUSED pc = abuf->addr;
2174 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2175
2176 {
2177 SI tmp_shift;
2178 tmp_shift = ANDSI (* FLD (i_Rj), 31);
2179 if (NESI (tmp_shift, 0)) {
2180 {
2181 {
2182 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2183 CPU (h_cbit) = opval;
2184 written |= (1 << 3);
2185 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2186 }
2187 {
2188 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2189 * FLD (i_Ri) = opval;
2190 written |= (1 << 2);
2191 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2192 }
2193 }
2194 } else {
2195 {
2196 BI opval = 0;
2197 CPU (h_cbit) = opval;
2198 written |= (1 << 3);
2199 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2200 }
2201 }
2202 {
2203 BI opval = LTSI (* FLD (i_Ri), 0);
2204 CPU (h_nbit) = opval;
2205 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2206 }
2207 {
2208 BI opval = EQSI (* FLD (i_Ri), 0);
2209 CPU (h_zbit) = opval;
2210 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2211 }
2212 }
2213
2214 abuf->written = written;
2215 #undef FLD
2216 }
2217 NEXT (vpc);
2218
2219 CASE (sem, INSN_ASRI) : /* asr $u4,$Ri */
2220 {
2221 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2222 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2223 #define FLD(f) abuf->fields.sfmt_addi.f
2224 int UNUSED written = 0;
2225 IADDR UNUSED pc = abuf->addr;
2226 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2227
2228 {
2229 SI tmp_shift;
2230 tmp_shift = FLD (f_u4);
2231 if (NESI (tmp_shift, 0)) {
2232 {
2233 {
2234 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2235 CPU (h_cbit) = opval;
2236 written |= (1 << 3);
2237 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2238 }
2239 {
2240 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2241 * FLD (i_Ri) = opval;
2242 written |= (1 << 2);
2243 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2244 }
2245 }
2246 } else {
2247 {
2248 BI opval = 0;
2249 CPU (h_cbit) = opval;
2250 written |= (1 << 3);
2251 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2252 }
2253 }
2254 {
2255 BI opval = LTSI (* FLD (i_Ri), 0);
2256 CPU (h_nbit) = opval;
2257 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2258 }
2259 {
2260 BI opval = EQSI (* FLD (i_Ri), 0);
2261 CPU (h_zbit) = opval;
2262 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2263 }
2264 }
2265
2266 abuf->written = written;
2267 #undef FLD
2268 }
2269 NEXT (vpc);
2270
2271 CASE (sem, INSN_ASR2) : /* asr2 $u4,$Ri */
2272 {
2273 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2274 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2275 #define FLD(f) abuf->fields.sfmt_addi.f
2276 int UNUSED written = 0;
2277 IADDR UNUSED pc = abuf->addr;
2278 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2279
2280 {
2281 SI tmp_shift;
2282 tmp_shift = ADDSI (FLD (f_u4), 16);
2283 if (NESI (tmp_shift, 0)) {
2284 {
2285 {
2286 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2287 CPU (h_cbit) = opval;
2288 written |= (1 << 3);
2289 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2290 }
2291 {
2292 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2293 * FLD (i_Ri) = opval;
2294 written |= (1 << 2);
2295 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2296 }
2297 }
2298 } else {
2299 {
2300 BI opval = 0;
2301 CPU (h_cbit) = opval;
2302 written |= (1 << 3);
2303 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2304 }
2305 }
2306 {
2307 BI opval = LTSI (* FLD (i_Ri), 0);
2308 CPU (h_nbit) = opval;
2309 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2310 }
2311 {
2312 BI opval = EQSI (* FLD (i_Ri), 0);
2313 CPU (h_zbit) = opval;
2314 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2315 }
2316 }
2317
2318 abuf->written = written;
2319 #undef FLD
2320 }
2321 NEXT (vpc);
2322
2323 CASE (sem, INSN_LDI8) : /* ldi:8 $i8,$Ri */
2324 {
2325 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2326 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2327 #define FLD(f) abuf->fields.sfmt_ldi8.f
2328 int UNUSED written = 0;
2329 IADDR UNUSED pc = abuf->addr;
2330 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2331
2332 {
2333 SI opval = FLD (f_i8);
2334 * FLD (i_Ri) = opval;
2335 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2336 }
2337
2338 #undef FLD
2339 }
2340 NEXT (vpc);
2341
2342 CASE (sem, INSN_LDI20) : /* ldi:20 $i20,$Ri */
2343 {
2344 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2345 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2346 #define FLD(f) abuf->fields.sfmt_ldi20.f
2347 int UNUSED written = 0;
2348 IADDR UNUSED pc = abuf->addr;
2349 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2350
2351 {
2352 SI opval = FLD (f_i20);
2353 * FLD (i_Ri) = opval;
2354 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2355 }
2356
2357 #undef FLD
2358 }
2359 NEXT (vpc);
2360
2361 CASE (sem, INSN_LDI32) : /* ldi:32 $i32,$Ri */
2362 {
2363 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2364 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2365 #define FLD(f) abuf->fields.sfmt_ldi32.f
2366 int UNUSED written = 0;
2367 IADDR UNUSED pc = abuf->addr;
2368 vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
2369
2370 {
2371 SI opval = FLD (f_i32);
2372 * FLD (i_Ri) = opval;
2373 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2374 }
2375
2376 #undef FLD
2377 }
2378 NEXT (vpc);
2379
2380 CASE (sem, INSN_LD) : /* ld @$Rj,$Ri */
2381 {
2382 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2383 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2384 #define FLD(f) abuf->fields.sfmt_ldr13.f
2385 int UNUSED written = 0;
2386 IADDR UNUSED pc = abuf->addr;
2387 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2388
2389 {
2390 SI opval = GETMEMSI (current_cpu, pc, * FLD (i_Rj));
2391 * FLD (i_Ri) = opval;
2392 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2393 }
2394
2395 #undef FLD
2396 }
2397 NEXT (vpc);
2398
2399 CASE (sem, INSN_LDUH) : /* lduh @$Rj,$Ri */
2400 {
2401 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2402 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2403 #define FLD(f) abuf->fields.sfmt_ldr13.f
2404 int UNUSED written = 0;
2405 IADDR UNUSED pc = abuf->addr;
2406 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2407
2408 {
2409 SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_Rj));
2410 * FLD (i_Ri) = opval;
2411 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2412 }
2413
2414 #undef FLD
2415 }
2416 NEXT (vpc);
2417
2418 CASE (sem, INSN_LDUB) : /* ldub @$Rj,$Ri */
2419 {
2420 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2421 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2422 #define FLD(f) abuf->fields.sfmt_ldr13.f
2423 int UNUSED written = 0;
2424 IADDR UNUSED pc = abuf->addr;
2425 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2426
2427 {
2428 SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
2429 * FLD (i_Ri) = opval;
2430 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2431 }
2432
2433 #undef FLD
2434 }
2435 NEXT (vpc);
2436
2437 CASE (sem, INSN_LDR13) : /* ld @($R13,$Rj),$Ri */
2438 {
2439 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2440 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2441 #define FLD(f) abuf->fields.sfmt_ldr13.f
2442 int UNUSED written = 0;
2443 IADDR UNUSED pc = abuf->addr;
2444 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2445
2446 {
2447 SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2448 * FLD (i_Ri) = opval;
2449 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2450 }
2451
2452 #undef FLD
2453 }
2454 NEXT (vpc);
2455
2456 CASE (sem, INSN_LDR13UH) : /* lduh @($R13,$Rj),$Ri */
2457 {
2458 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2459 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2460 #define FLD(f) abuf->fields.sfmt_ldr13.f
2461 int UNUSED written = 0;
2462 IADDR UNUSED pc = abuf->addr;
2463 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2464
2465 {
2466 SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2467 * FLD (i_Ri) = opval;
2468 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2469 }
2470
2471 #undef FLD
2472 }
2473 NEXT (vpc);
2474
2475 CASE (sem, INSN_LDR13UB) : /* ldub @($R13,$Rj),$Ri */
2476 {
2477 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2478 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2479 #define FLD(f) abuf->fields.sfmt_ldr13.f
2480 int UNUSED written = 0;
2481 IADDR UNUSED pc = abuf->addr;
2482 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2483
2484 {
2485 SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2486 * FLD (i_Ri) = opval;
2487 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2488 }
2489
2490 #undef FLD
2491 }
2492 NEXT (vpc);
2493
2494 CASE (sem, INSN_LDR14) : /* ld @($R14,$disp10),$Ri */
2495 {
2496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2498 #define FLD(f) abuf->fields.sfmt_ldr14.f
2499 int UNUSED written = 0;
2500 IADDR UNUSED pc = abuf->addr;
2501 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2502
2503 {
2504 SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])));
2505 * FLD (i_Ri) = opval;
2506 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2507 }
2508
2509 #undef FLD
2510 }
2511 NEXT (vpc);
2512
2513 CASE (sem, INSN_LDR14UH) : /* lduh @($R14,$disp9),$Ri */
2514 {
2515 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2516 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2517 #define FLD(f) abuf->fields.sfmt_ldr14uh.f
2518 int UNUSED written = 0;
2519 IADDR UNUSED pc = abuf->addr;
2520 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2521
2522 {
2523 SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])));
2524 * FLD (i_Ri) = opval;
2525 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2526 }
2527
2528 #undef FLD
2529 }
2530 NEXT (vpc);
2531
2532 CASE (sem, INSN_LDR14UB) : /* ldub @($R14,$disp8),$Ri */
2533 {
2534 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2535 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2536 #define FLD(f) abuf->fields.sfmt_ldr14ub.f
2537 int UNUSED written = 0;
2538 IADDR UNUSED pc = abuf->addr;
2539 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2540
2541 {
2542 SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])));
2543 * FLD (i_Ri) = opval;
2544 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2545 }
2546
2547 #undef FLD
2548 }
2549 NEXT (vpc);
2550
2551 CASE (sem, INSN_LDR15) : /* ld @($R15,$udisp6),$Ri */
2552 {
2553 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2554 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2555 #define FLD(f) abuf->fields.sfmt_ldr15.f
2556 int UNUSED written = 0;
2557 IADDR UNUSED pc = abuf->addr;
2558 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2559
2560 {
2561 SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_udisp6), CPU (h_gr[((UINT) 15)])));
2562 * FLD (i_Ri) = opval;
2563 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2564 }
2565
2566 #undef FLD
2567 }
2568 NEXT (vpc);
2569
2570 CASE (sem, INSN_LDR15GR) : /* ld @$R15+,$Ri */
2571 {
2572 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2573 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2574 #define FLD(f) abuf->fields.sfmt_ldr15gr.f
2575 int UNUSED written = 0;
2576 IADDR UNUSED pc = abuf->addr;
2577 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2578
2579 {
2580 {
2581 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2582 * FLD (i_Ri) = opval;
2583 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2584 }
2585 if (NESI (FLD (f_Ri), 15)) {
2586 {
2587 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2588 CPU (h_gr[((UINT) 15)]) = opval;
2589 written |= (1 << 4);
2590 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2591 }
2592 }
2593 }
2594
2595 abuf->written = written;
2596 #undef FLD
2597 }
2598 NEXT (vpc);
2599
2600 CASE (sem, INSN_LDR15DR) : /* ld @$R15+,$Rs2 */
2601 {
2602 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2603 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2604 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
2605 int UNUSED written = 0;
2606 IADDR UNUSED pc = abuf->addr;
2607 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2608
2609 {
2610 SI tmp_tmp;
2611 tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2612 {
2613 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2614 CPU (h_gr[((UINT) 15)]) = opval;
2615 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2616 }
2617 {
2618 SI opval = tmp_tmp;
2619 SET_H_DR (FLD (f_Rs2), opval);
2620 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2621 }
2622 }
2623
2624 #undef FLD
2625 }
2626 NEXT (vpc);
2627
2628 CASE (sem, INSN_LDR15PS) : /* ld @$R15+,$ps */
2629 {
2630 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2631 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2632 #define FLD(f) abuf->fields.sfmt_addsp.f
2633 int UNUSED written = 0;
2634 IADDR UNUSED pc = abuf->addr;
2635 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2636
2637 {
2638 {
2639 USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2640 SET_H_PS (opval);
2641 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
2642 }
2643 {
2644 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2645 CPU (h_gr[((UINT) 15)]) = opval;
2646 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2647 }
2648 }
2649
2650 #undef FLD
2651 }
2652 NEXT (vpc);
2653
2654 CASE (sem, INSN_ST) : /* st $Ri,@$Rj */
2655 {
2656 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2657 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2658 #define FLD(f) abuf->fields.sfmt_str13.f
2659 int UNUSED written = 0;
2660 IADDR UNUSED pc = abuf->addr;
2661 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2662
2663 {
2664 SI opval = * FLD (i_Ri);
2665 SETMEMSI (current_cpu, pc, * FLD (i_Rj), opval);
2666 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2667 }
2668
2669 #undef FLD
2670 }
2671 NEXT (vpc);
2672
2673 CASE (sem, INSN_STH) : /* sth $Ri,@$Rj */
2674 {
2675 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2676 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2677 #define FLD(f) abuf->fields.sfmt_str13.f
2678 int UNUSED written = 0;
2679 IADDR UNUSED pc = abuf->addr;
2680 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2681
2682 {
2683 HI opval = * FLD (i_Ri);
2684 SETMEMHI (current_cpu, pc, * FLD (i_Rj), opval);
2685 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2686 }
2687
2688 #undef FLD
2689 }
2690 NEXT (vpc);
2691
2692 CASE (sem, INSN_STB) : /* stb $Ri,@$Rj */
2693 {
2694 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2695 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2696 #define FLD(f) abuf->fields.sfmt_str13.f
2697 int UNUSED written = 0;
2698 IADDR UNUSED pc = abuf->addr;
2699 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2700
2701 {
2702 QI opval = * FLD (i_Ri);
2703 SETMEMQI (current_cpu, pc, * FLD (i_Rj), opval);
2704 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2705 }
2706
2707 #undef FLD
2708 }
2709 NEXT (vpc);
2710
2711 CASE (sem, INSN_STR13) : /* st $Ri,@($R13,$Rj) */
2712 {
2713 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2714 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2715 #define FLD(f) abuf->fields.sfmt_str13.f
2716 int UNUSED written = 0;
2717 IADDR UNUSED pc = abuf->addr;
2718 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2719
2720 {
2721 SI opval = * FLD (i_Ri);
2722 SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2723 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2724 }
2725
2726 #undef FLD
2727 }
2728 NEXT (vpc);
2729
2730 CASE (sem, INSN_STR13H) : /* sth $Ri,@($R13,$Rj) */
2731 {
2732 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2733 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2734 #define FLD(f) abuf->fields.sfmt_str13.f
2735 int UNUSED written = 0;
2736 IADDR UNUSED pc = abuf->addr;
2737 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2738
2739 {
2740 HI opval = * FLD (i_Ri);
2741 SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2742 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2743 }
2744
2745 #undef FLD
2746 }
2747 NEXT (vpc);
2748
2749 CASE (sem, INSN_STR13B) : /* stb $Ri,@($R13,$Rj) */
2750 {
2751 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2752 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2753 #define FLD(f) abuf->fields.sfmt_str13.f
2754 int UNUSED written = 0;
2755 IADDR UNUSED pc = abuf->addr;
2756 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2757
2758 {
2759 QI opval = * FLD (i_Ri);
2760 SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2761 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2762 }
2763
2764 #undef FLD
2765 }
2766 NEXT (vpc);
2767
2768 CASE (sem, INSN_STR14) : /* st $Ri,@($R14,$disp10) */
2769 {
2770 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2771 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2772 #define FLD(f) abuf->fields.sfmt_str14.f
2773 int UNUSED written = 0;
2774 IADDR UNUSED pc = abuf->addr;
2775 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2776
2777 {
2778 SI opval = * FLD (i_Ri);
2779 SETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])), opval);
2780 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2781 }
2782
2783 #undef FLD
2784 }
2785 NEXT (vpc);
2786
2787 CASE (sem, INSN_STR14H) : /* sth $Ri,@($R14,$disp9) */
2788 {
2789 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2790 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2791 #define FLD(f) abuf->fields.sfmt_str14h.f
2792 int UNUSED written = 0;
2793 IADDR UNUSED pc = abuf->addr;
2794 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2795
2796 {
2797 HI opval = * FLD (i_Ri);
2798 SETMEMHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])), opval);
2799 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2800 }
2801
2802 #undef FLD
2803 }
2804 NEXT (vpc);
2805
2806 CASE (sem, INSN_STR14B) : /* stb $Ri,@($R14,$disp8) */
2807 {
2808 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2809 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2810 #define FLD(f) abuf->fields.sfmt_str14b.f
2811 int UNUSED written = 0;
2812 IADDR UNUSED pc = abuf->addr;
2813 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2814
2815 {
2816 QI opval = * FLD (i_Ri);
2817 SETMEMQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])), opval);
2818 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2819 }
2820
2821 #undef FLD
2822 }
2823 NEXT (vpc);
2824
2825 CASE (sem, INSN_STR15) : /* st $Ri,@($R15,$udisp6) */
2826 {
2827 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2828 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2829 #define FLD(f) abuf->fields.sfmt_str15.f
2830 int UNUSED written = 0;
2831 IADDR UNUSED pc = abuf->addr;
2832 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2833
2834 {
2835 SI opval = * FLD (i_Ri);
2836 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_udisp6)), opval);
2837 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2838 }
2839
2840 #undef FLD
2841 }
2842 NEXT (vpc);
2843
2844 CASE (sem, INSN_STR15GR) : /* st $Ri,@-$R15 */
2845 {
2846 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2847 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2848 #define FLD(f) abuf->fields.sfmt_str15gr.f
2849 int UNUSED written = 0;
2850 IADDR UNUSED pc = abuf->addr;
2851 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2852
2853 {
2854 SI tmp_tmp;
2855 tmp_tmp = * FLD (i_Ri);
2856 {
2857 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2858 CPU (h_gr[((UINT) 15)]) = opval;
2859 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2860 }
2861 {
2862 SI opval = tmp_tmp;
2863 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2864 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2865 }
2866 }
2867
2868 #undef FLD
2869 }
2870 NEXT (vpc);
2871
2872 CASE (sem, INSN_STR15DR) : /* st $Rs2,@-$R15 */
2873 {
2874 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2875 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2876 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
2877 int UNUSED written = 0;
2878 IADDR UNUSED pc = abuf->addr;
2879 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2880
2881 {
2882 SI tmp_tmp;
2883 tmp_tmp = GET_H_DR (FLD (f_Rs2));
2884 {
2885 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2886 CPU (h_gr[((UINT) 15)]) = opval;
2887 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2888 }
2889 {
2890 SI opval = tmp_tmp;
2891 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2892 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2893 }
2894 }
2895
2896 #undef FLD
2897 }
2898 NEXT (vpc);
2899
2900 CASE (sem, INSN_STR15PS) : /* st $ps,@-$R15 */
2901 {
2902 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2903 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2904 #define FLD(f) abuf->fields.sfmt_addsp.f
2905 int UNUSED written = 0;
2906 IADDR UNUSED pc = abuf->addr;
2907 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2908
2909 {
2910 {
2911 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2912 CPU (h_gr[((UINT) 15)]) = opval;
2913 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2914 }
2915 {
2916 SI opval = GET_H_PS ();
2917 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2918 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2919 }
2920 }
2921
2922 #undef FLD
2923 }
2924 NEXT (vpc);
2925
2926 CASE (sem, INSN_MOV) : /* mov $Rj,$Ri */
2927 {
2928 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2929 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2930 #define FLD(f) abuf->fields.sfmt_ldr13.f
2931 int UNUSED written = 0;
2932 IADDR UNUSED pc = abuf->addr;
2933 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2934
2935 {
2936 SI opval = * FLD (i_Rj);
2937 * FLD (i_Ri) = opval;
2938 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2939 }
2940
2941 #undef FLD
2942 }
2943 NEXT (vpc);
2944
2945 CASE (sem, INSN_MOVDR) : /* mov $Rs1,$Ri */
2946 {
2947 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2948 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2949 #define FLD(f) abuf->fields.sfmt_movdr.f
2950 int UNUSED written = 0;
2951 IADDR UNUSED pc = abuf->addr;
2952 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2953
2954 {
2955 SI opval = GET_H_DR (FLD (f_Rs1));
2956 * FLD (i_Ri) = opval;
2957 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2958 }
2959
2960 #undef FLD
2961 }
2962 NEXT (vpc);
2963
2964 CASE (sem, INSN_MOVPS) : /* mov $ps,$Ri */
2965 {
2966 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2967 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2968 #define FLD(f) abuf->fields.sfmt_movdr.f
2969 int UNUSED written = 0;
2970 IADDR UNUSED pc = abuf->addr;
2971 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2972
2973 {
2974 SI opval = GET_H_PS ();
2975 * FLD (i_Ri) = opval;
2976 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
2977 }
2978
2979 #undef FLD
2980 }
2981 NEXT (vpc);
2982
2983 CASE (sem, INSN_MOV2DR) : /* mov $Ri,$Rs1 */
2984 {
2985 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2986 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2987 #define FLD(f) abuf->fields.sfmt_mov2dr.f
2988 int UNUSED written = 0;
2989 IADDR UNUSED pc = abuf->addr;
2990 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2991
2992 {
2993 SI opval = * FLD (i_Ri);
2994 SET_H_DR (FLD (f_Rs1), opval);
2995 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
2996 }
2997
2998 #undef FLD
2999 }
3000 NEXT (vpc);
3001
3002 CASE (sem, INSN_MOV2PS) : /* mov $Ri,$ps */
3003 {
3004 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3005 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3006 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3007 int UNUSED written = 0;
3008 IADDR UNUSED pc = abuf->addr;
3009 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3010
3011 {
3012 USI opval = * FLD (i_Ri);
3013 SET_H_PS (opval);
3014 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3015 }
3016
3017 #undef FLD
3018 }
3019 NEXT (vpc);
3020
3021 CASE (sem, INSN_JMP) : /* jmp @$Ri */
3022 {
3023 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3024 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3025 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3026 int UNUSED written = 0;
3027 IADDR UNUSED pc = abuf->addr;
3028 SEM_BRANCH_INIT
3029 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3030
3031 {
3032 USI opval = * FLD (i_Ri);
3033 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3034 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3035 }
3036
3037 SEM_BRANCH_FINI (vpc);
3038 #undef FLD
3039 }
3040 NEXT (vpc);
3041
3042 CASE (sem, INSN_JMPD) : /* jmp:d @$Ri */
3043 {
3044 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3045 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3046 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3047 int UNUSED written = 0;
3048 IADDR UNUSED pc = abuf->addr;
3049 SEM_BRANCH_INIT
3050 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3051
3052 {
3053 {
3054 USI opval = * FLD (i_Ri);
3055 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3056 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3057 }
3058 }
3059
3060 SEM_BRANCH_FINI (vpc);
3061 #undef FLD
3062 }
3063 NEXT (vpc);
3064
3065 CASE (sem, INSN_CALLR) : /* call @$Ri */
3066 {
3067 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3068 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3069 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3070 int UNUSED written = 0;
3071 IADDR UNUSED pc = abuf->addr;
3072 SEM_BRANCH_INIT
3073 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3074
3075 {
3076 {
3077 SI opval = ADDSI (pc, 2);
3078 SET_H_DR (((UINT) 1), opval);
3079 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3080 }
3081 {
3082 USI opval = * FLD (i_Ri);
3083 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3084 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3085 }
3086 }
3087
3088 SEM_BRANCH_FINI (vpc);
3089 #undef FLD
3090 }
3091 NEXT (vpc);
3092
3093 CASE (sem, INSN_CALLRD) : /* call:d @$Ri */
3094 {
3095 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3096 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3097 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3098 int UNUSED written = 0;
3099 IADDR UNUSED pc = abuf->addr;
3100 SEM_BRANCH_INIT
3101 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3102
3103 {
3104 {
3105 {
3106 SI opval = ADDSI (pc, 4);
3107 SET_H_DR (((UINT) 1), opval);
3108 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3109 }
3110 {
3111 USI opval = * FLD (i_Ri);
3112 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3113 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3114 }
3115 }
3116 }
3117
3118 SEM_BRANCH_FINI (vpc);
3119 #undef FLD
3120 }
3121 NEXT (vpc);
3122
3123 CASE (sem, INSN_CALL) : /* call $label12 */
3124 {
3125 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3126 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3127 #define FLD(f) abuf->fields.sfmt_call.f
3128 int UNUSED written = 0;
3129 IADDR UNUSED pc = abuf->addr;
3130 SEM_BRANCH_INIT
3131 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3132
3133 {
3134 {
3135 SI opval = ADDSI (pc, 2);
3136 SET_H_DR (((UINT) 1), opval);
3137 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3138 }
3139 {
3140 USI opval = FLD (i_label12);
3141 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3142 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3143 }
3144 }
3145
3146 SEM_BRANCH_FINI (vpc);
3147 #undef FLD
3148 }
3149 NEXT (vpc);
3150
3151 CASE (sem, INSN_CALLD) : /* call:d $label12 */
3152 {
3153 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3154 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3155 #define FLD(f) abuf->fields.sfmt_call.f
3156 int UNUSED written = 0;
3157 IADDR UNUSED pc = abuf->addr;
3158 SEM_BRANCH_INIT
3159 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3160
3161 {
3162 {
3163 {
3164 SI opval = ADDSI (pc, 4);
3165 SET_H_DR (((UINT) 1), opval);
3166 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3167 }
3168 {
3169 USI opval = FLD (i_label12);
3170 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3171 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3172 }
3173 }
3174 }
3175
3176 SEM_BRANCH_FINI (vpc);
3177 #undef FLD
3178 }
3179 NEXT (vpc);
3180
3181 CASE (sem, INSN_RET) : /* ret */
3182 {
3183 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3184 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3185 #define FLD(f) abuf->fields.fmt_empty.f
3186 int UNUSED written = 0;
3187 IADDR UNUSED pc = abuf->addr;
3188 SEM_BRANCH_INIT
3189 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3190
3191 {
3192 USI opval = GET_H_DR (((UINT) 1));
3193 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3194 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3195 }
3196
3197 SEM_BRANCH_FINI (vpc);
3198 #undef FLD
3199 }
3200 NEXT (vpc);
3201
3202 CASE (sem, INSN_RET_D) : /* ret:d */
3203 {
3204 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3205 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3206 #define FLD(f) abuf->fields.fmt_empty.f
3207 int UNUSED written = 0;
3208 IADDR UNUSED pc = abuf->addr;
3209 SEM_BRANCH_INIT
3210 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3211
3212 {
3213 {
3214 USI opval = GET_H_DR (((UINT) 1));
3215 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3216 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3217 }
3218 }
3219
3220 SEM_BRANCH_FINI (vpc);
3221 #undef FLD
3222 }
3223 NEXT (vpc);
3224
3225 CASE (sem, INSN_INT) : /* int $u8 */
3226 {
3227 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3228 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3229 #define FLD(f) abuf->fields.sfmt_int.f
3230 int UNUSED written = 0;
3231 IADDR UNUSED pc = abuf->addr;
3232 SEM_BRANCH_INIT
3233 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3234
3235 {
3236 ; /*clobber*/
3237 ; /*clobber*/
3238 ; /*clobber*/
3239 {
3240 SI opval = fr30_int (current_cpu, pc, FLD (f_u8));
3241 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3242 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3243 }
3244 }
3245
3246 SEM_BRANCH_FINI (vpc);
3247 #undef FLD
3248 }
3249 NEXT (vpc);
3250
3251 CASE (sem, INSN_INTE) : /* inte */
3252 {
3253 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3254 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3255 #define FLD(f) abuf->fields.fmt_empty.f
3256 int UNUSED written = 0;
3257 IADDR UNUSED pc = abuf->addr;
3258 SEM_BRANCH_INIT
3259 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3260
3261 {
3262 ; /*clobber*/
3263 ; /*clobber*/
3264 ; /*clobber*/
3265 {
3266 SI opval = fr30_inte (current_cpu, pc);
3267 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3268 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3269 }
3270 }
3271
3272 SEM_BRANCH_FINI (vpc);
3273 #undef FLD
3274 }
3275 NEXT (vpc);
3276
3277 CASE (sem, INSN_RETI) : /* reti */
3278 {
3279 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3280 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3281 #define FLD(f) abuf->fields.fmt_empty.f
3282 int UNUSED written = 0;
3283 IADDR UNUSED pc = abuf->addr;
3284 SEM_BRANCH_INIT
3285 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3286
3287 if (EQBI (GET_H_SBIT (), 0)) {
3288 {
3289 {
3290 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
3291 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3292 written |= (1 << 7);
3293 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3294 }
3295 {
3296 SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
3297 SET_H_DR (((UINT) 2), opval);
3298 written |= (1 << 5);
3299 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3300 }
3301 {
3302 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
3303 SET_H_PS (opval);
3304 written |= (1 << 8);
3305 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3306 }
3307 {
3308 SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
3309 SET_H_DR (((UINT) 2), opval);
3310 written |= (1 << 5);
3311 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3312 }
3313 }
3314 } else {
3315 {
3316 {
3317 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
3318 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3319 written |= (1 << 7);
3320 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3321 }
3322 {
3323 SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
3324 SET_H_DR (((UINT) 3), opval);
3325 written |= (1 << 6);
3326 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3327 }
3328 {
3329 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
3330 SET_H_PS (opval);
3331 written |= (1 << 8);
3332 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3333 }
3334 {
3335 SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
3336 SET_H_DR (((UINT) 3), opval);
3337 written |= (1 << 6);
3338 TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
3339 }
3340 }
3341 }
3342
3343 abuf->written = written;
3344 SEM_BRANCH_FINI (vpc);
3345 #undef FLD
3346 }
3347 NEXT (vpc);
3348
3349 CASE (sem, INSN_BRAD) : /* bra:d $label9 */
3350 {
3351 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3352 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3353 #define FLD(f) abuf->fields.sfmt_brad.f
3354 int UNUSED written = 0;
3355 IADDR UNUSED pc = abuf->addr;
3356 SEM_BRANCH_INIT
3357 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3358
3359 {
3360 {
3361 USI opval = FLD (i_label9);
3362 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3363 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3364 }
3365 }
3366
3367 SEM_BRANCH_FINI (vpc);
3368 #undef FLD
3369 }
3370 NEXT (vpc);
3371
3372 CASE (sem, INSN_BRA) : /* bra $label9 */
3373 {
3374 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3375 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3376 #define FLD(f) abuf->fields.sfmt_brad.f
3377 int UNUSED written = 0;
3378 IADDR UNUSED pc = abuf->addr;
3379 SEM_BRANCH_INIT
3380 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3381
3382 {
3383 USI opval = FLD (i_label9);
3384 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3385 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3386 }
3387
3388 SEM_BRANCH_FINI (vpc);
3389 #undef FLD
3390 }
3391 NEXT (vpc);
3392
3393 CASE (sem, INSN_BNOD) : /* bno:d $label9 */
3394 {
3395 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3396 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3397 #define FLD(f) abuf->fields.fmt_empty.f
3398 int UNUSED written = 0;
3399 IADDR UNUSED pc = abuf->addr;
3400 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3401
3402 {
3403 ((void) 0); /*nop*/
3404 }
3405
3406 #undef FLD
3407 }
3408 NEXT (vpc);
3409
3410 CASE (sem, INSN_BNO) : /* bno $label9 */
3411 {
3412 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3413 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3414 #define FLD(f) abuf->fields.fmt_empty.f
3415 int UNUSED written = 0;
3416 IADDR UNUSED pc = abuf->addr;
3417 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3418
3419 ((void) 0); /*nop*/
3420
3421 #undef FLD
3422 }
3423 NEXT (vpc);
3424
3425 CASE (sem, INSN_BEQD) : /* beq:d $label9 */
3426 {
3427 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3428 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3429 #define FLD(f) abuf->fields.sfmt_brad.f
3430 int UNUSED written = 0;
3431 IADDR UNUSED pc = abuf->addr;
3432 SEM_BRANCH_INIT
3433 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3434
3435 {
3436 if (CPU (h_zbit)) {
3437 {
3438 USI opval = FLD (i_label9);
3439 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3440 written |= (1 << 2);
3441 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3442 }
3443 }
3444 }
3445
3446 abuf->written = written;
3447 SEM_BRANCH_FINI (vpc);
3448 #undef FLD
3449 }
3450 NEXT (vpc);
3451
3452 CASE (sem, INSN_BEQ) : /* beq $label9 */
3453 {
3454 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3455 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3456 #define FLD(f) abuf->fields.sfmt_brad.f
3457 int UNUSED written = 0;
3458 IADDR UNUSED pc = abuf->addr;
3459 SEM_BRANCH_INIT
3460 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3461
3462 if (CPU (h_zbit)) {
3463 {
3464 USI opval = FLD (i_label9);
3465 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3466 written |= (1 << 2);
3467 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3468 }
3469 }
3470
3471 abuf->written = written;
3472 SEM_BRANCH_FINI (vpc);
3473 #undef FLD
3474 }
3475 NEXT (vpc);
3476
3477 CASE (sem, INSN_BNED) : /* bne:d $label9 */
3478 {
3479 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3480 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3481 #define FLD(f) abuf->fields.sfmt_brad.f
3482 int UNUSED written = 0;
3483 IADDR UNUSED pc = abuf->addr;
3484 SEM_BRANCH_INIT
3485 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3486
3487 {
3488 if (NOTBI (CPU (h_zbit))) {
3489 {
3490 USI opval = FLD (i_label9);
3491 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3492 written |= (1 << 2);
3493 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3494 }
3495 }
3496 }
3497
3498 abuf->written = written;
3499 SEM_BRANCH_FINI (vpc);
3500 #undef FLD
3501 }
3502 NEXT (vpc);
3503
3504 CASE (sem, INSN_BNE) : /* bne $label9 */
3505 {
3506 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3507 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3508 #define FLD(f) abuf->fields.sfmt_brad.f
3509 int UNUSED written = 0;
3510 IADDR UNUSED pc = abuf->addr;
3511 SEM_BRANCH_INIT
3512 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3513
3514 if (NOTBI (CPU (h_zbit))) {
3515 {
3516 USI opval = FLD (i_label9);
3517 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3518 written |= (1 << 2);
3519 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3520 }
3521 }
3522
3523 abuf->written = written;
3524 SEM_BRANCH_FINI (vpc);
3525 #undef FLD
3526 }
3527 NEXT (vpc);
3528
3529 CASE (sem, INSN_BCD) : /* bc:d $label9 */
3530 {
3531 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3532 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3533 #define FLD(f) abuf->fields.sfmt_brad.f
3534 int UNUSED written = 0;
3535 IADDR UNUSED pc = abuf->addr;
3536 SEM_BRANCH_INIT
3537 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3538
3539 {
3540 if (CPU (h_cbit)) {
3541 {
3542 USI opval = FLD (i_label9);
3543 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3544 written |= (1 << 2);
3545 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3546 }
3547 }
3548 }
3549
3550 abuf->written = written;
3551 SEM_BRANCH_FINI (vpc);
3552 #undef FLD
3553 }
3554 NEXT (vpc);
3555
3556 CASE (sem, INSN_BC) : /* bc $label9 */
3557 {
3558 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3559 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3560 #define FLD(f) abuf->fields.sfmt_brad.f
3561 int UNUSED written = 0;
3562 IADDR UNUSED pc = abuf->addr;
3563 SEM_BRANCH_INIT
3564 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3565
3566 if (CPU (h_cbit)) {
3567 {
3568 USI opval = FLD (i_label9);
3569 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3570 written |= (1 << 2);
3571 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3572 }
3573 }
3574
3575 abuf->written = written;
3576 SEM_BRANCH_FINI (vpc);
3577 #undef FLD
3578 }
3579 NEXT (vpc);
3580
3581 CASE (sem, INSN_BNCD) : /* bnc:d $label9 */
3582 {
3583 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3584 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3585 #define FLD(f) abuf->fields.sfmt_brad.f
3586 int UNUSED written = 0;
3587 IADDR UNUSED pc = abuf->addr;
3588 SEM_BRANCH_INIT
3589 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3590
3591 {
3592 if (NOTBI (CPU (h_cbit))) {
3593 {
3594 USI opval = FLD (i_label9);
3595 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3596 written |= (1 << 2);
3597 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3598 }
3599 }
3600 }
3601
3602 abuf->written = written;
3603 SEM_BRANCH_FINI (vpc);
3604 #undef FLD
3605 }
3606 NEXT (vpc);
3607
3608 CASE (sem, INSN_BNC) : /* bnc $label9 */
3609 {
3610 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3611 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3612 #define FLD(f) abuf->fields.sfmt_brad.f
3613 int UNUSED written = 0;
3614 IADDR UNUSED pc = abuf->addr;
3615 SEM_BRANCH_INIT
3616 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3617
3618 if (NOTBI (CPU (h_cbit))) {
3619 {
3620 USI opval = FLD (i_label9);
3621 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3622 written |= (1 << 2);
3623 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3624 }
3625 }
3626
3627 abuf->written = written;
3628 SEM_BRANCH_FINI (vpc);
3629 #undef FLD
3630 }
3631 NEXT (vpc);
3632
3633 CASE (sem, INSN_BND) : /* bn:d $label9 */
3634 {
3635 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3636 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3637 #define FLD(f) abuf->fields.sfmt_brad.f
3638 int UNUSED written = 0;
3639 IADDR UNUSED pc = abuf->addr;
3640 SEM_BRANCH_INIT
3641 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3642
3643 {
3644 if (CPU (h_nbit)) {
3645 {
3646 USI opval = FLD (i_label9);
3647 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3648 written |= (1 << 2);
3649 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3650 }
3651 }
3652 }
3653
3654 abuf->written = written;
3655 SEM_BRANCH_FINI (vpc);
3656 #undef FLD
3657 }
3658 NEXT (vpc);
3659
3660 CASE (sem, INSN_BN) : /* bn $label9 */
3661 {
3662 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3663 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3664 #define FLD(f) abuf->fields.sfmt_brad.f
3665 int UNUSED written = 0;
3666 IADDR UNUSED pc = abuf->addr;
3667 SEM_BRANCH_INIT
3668 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3669
3670 if (CPU (h_nbit)) {
3671 {
3672 USI opval = FLD (i_label9);
3673 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3674 written |= (1 << 2);
3675 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3676 }
3677 }
3678
3679 abuf->written = written;
3680 SEM_BRANCH_FINI (vpc);
3681 #undef FLD
3682 }
3683 NEXT (vpc);
3684
3685 CASE (sem, INSN_BPD) : /* bp:d $label9 */
3686 {
3687 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3688 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3689 #define FLD(f) abuf->fields.sfmt_brad.f
3690 int UNUSED written = 0;
3691 IADDR UNUSED pc = abuf->addr;
3692 SEM_BRANCH_INIT
3693 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3694
3695 {
3696 if (NOTBI (CPU (h_nbit))) {
3697 {
3698 USI opval = FLD (i_label9);
3699 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3700 written |= (1 << 2);
3701 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3702 }
3703 }
3704 }
3705
3706 abuf->written = written;
3707 SEM_BRANCH_FINI (vpc);
3708 #undef FLD
3709 }
3710 NEXT (vpc);
3711
3712 CASE (sem, INSN_BP) : /* bp $label9 */
3713 {
3714 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3715 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3716 #define FLD(f) abuf->fields.sfmt_brad.f
3717 int UNUSED written = 0;
3718 IADDR UNUSED pc = abuf->addr;
3719 SEM_BRANCH_INIT
3720 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3721
3722 if (NOTBI (CPU (h_nbit))) {
3723 {
3724 USI opval = FLD (i_label9);
3725 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3726 written |= (1 << 2);
3727 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3728 }
3729 }
3730
3731 abuf->written = written;
3732 SEM_BRANCH_FINI (vpc);
3733 #undef FLD
3734 }
3735 NEXT (vpc);
3736
3737 CASE (sem, INSN_BVD) : /* bv:d $label9 */
3738 {
3739 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3740 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3741 #define FLD(f) abuf->fields.sfmt_brad.f
3742 int UNUSED written = 0;
3743 IADDR UNUSED pc = abuf->addr;
3744 SEM_BRANCH_INIT
3745 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3746
3747 {
3748 if (CPU (h_vbit)) {
3749 {
3750 USI opval = FLD (i_label9);
3751 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3752 written |= (1 << 2);
3753 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3754 }
3755 }
3756 }
3757
3758 abuf->written = written;
3759 SEM_BRANCH_FINI (vpc);
3760 #undef FLD
3761 }
3762 NEXT (vpc);
3763
3764 CASE (sem, INSN_BV) : /* bv $label9 */
3765 {
3766 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3767 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3768 #define FLD(f) abuf->fields.sfmt_brad.f
3769 int UNUSED written = 0;
3770 IADDR UNUSED pc = abuf->addr;
3771 SEM_BRANCH_INIT
3772 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3773
3774 if (CPU (h_vbit)) {
3775 {
3776 USI opval = FLD (i_label9);
3777 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3778 written |= (1 << 2);
3779 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3780 }
3781 }
3782
3783 abuf->written = written;
3784 SEM_BRANCH_FINI (vpc);
3785 #undef FLD
3786 }
3787 NEXT (vpc);
3788
3789 CASE (sem, INSN_BNVD) : /* bnv:d $label9 */
3790 {
3791 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3792 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3793 #define FLD(f) abuf->fields.sfmt_brad.f
3794 int UNUSED written = 0;
3795 IADDR UNUSED pc = abuf->addr;
3796 SEM_BRANCH_INIT
3797 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3798
3799 {
3800 if (NOTBI (CPU (h_vbit))) {
3801 {
3802 USI opval = FLD (i_label9);
3803 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3804 written |= (1 << 2);
3805 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3806 }
3807 }
3808 }
3809
3810 abuf->written = written;
3811 SEM_BRANCH_FINI (vpc);
3812 #undef FLD
3813 }
3814 NEXT (vpc);
3815
3816 CASE (sem, INSN_BNV) : /* bnv $label9 */
3817 {
3818 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3819 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3820 #define FLD(f) abuf->fields.sfmt_brad.f
3821 int UNUSED written = 0;
3822 IADDR UNUSED pc = abuf->addr;
3823 SEM_BRANCH_INIT
3824 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3825
3826 if (NOTBI (CPU (h_vbit))) {
3827 {
3828 USI opval = FLD (i_label9);
3829 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3830 written |= (1 << 2);
3831 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3832 }
3833 }
3834
3835 abuf->written = written;
3836 SEM_BRANCH_FINI (vpc);
3837 #undef FLD
3838 }
3839 NEXT (vpc);
3840
3841 CASE (sem, INSN_BLTD) : /* blt:d $label9 */
3842 {
3843 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3844 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3845 #define FLD(f) abuf->fields.sfmt_brad.f
3846 int UNUSED written = 0;
3847 IADDR UNUSED pc = abuf->addr;
3848 SEM_BRANCH_INIT
3849 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3850
3851 {
3852 if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
3853 {
3854 USI opval = FLD (i_label9);
3855 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3856 written |= (1 << 3);
3857 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3858 }
3859 }
3860 }
3861
3862 abuf->written = written;
3863 SEM_BRANCH_FINI (vpc);
3864 #undef FLD
3865 }
3866 NEXT (vpc);
3867
3868 CASE (sem, INSN_BLT) : /* blt $label9 */
3869 {
3870 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3871 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3872 #define FLD(f) abuf->fields.sfmt_brad.f
3873 int UNUSED written = 0;
3874 IADDR UNUSED pc = abuf->addr;
3875 SEM_BRANCH_INIT
3876 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3877
3878 if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
3879 {
3880 USI opval = FLD (i_label9);
3881 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3882 written |= (1 << 3);
3883 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3884 }
3885 }
3886
3887 abuf->written = written;
3888 SEM_BRANCH_FINI (vpc);
3889 #undef FLD
3890 }
3891 NEXT (vpc);
3892
3893 CASE (sem, INSN_BGED) : /* bge:d $label9 */
3894 {
3895 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3896 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3897 #define FLD(f) abuf->fields.sfmt_brad.f
3898 int UNUSED written = 0;
3899 IADDR UNUSED pc = abuf->addr;
3900 SEM_BRANCH_INIT
3901 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3902
3903 {
3904 if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
3905 {
3906 USI opval = FLD (i_label9);
3907 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3908 written |= (1 << 3);
3909 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3910 }
3911 }
3912 }
3913
3914 abuf->written = written;
3915 SEM_BRANCH_FINI (vpc);
3916 #undef FLD
3917 }
3918 NEXT (vpc);
3919
3920 CASE (sem, INSN_BGE) : /* bge $label9 */
3921 {
3922 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3923 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3924 #define FLD(f) abuf->fields.sfmt_brad.f
3925 int UNUSED written = 0;
3926 IADDR UNUSED pc = abuf->addr;
3927 SEM_BRANCH_INIT
3928 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3929
3930 if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
3931 {
3932 USI opval = FLD (i_label9);
3933 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3934 written |= (1 << 3);
3935 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3936 }
3937 }
3938
3939 abuf->written = written;
3940 SEM_BRANCH_FINI (vpc);
3941 #undef FLD
3942 }
3943 NEXT (vpc);
3944
3945 CASE (sem, INSN_BLED) : /* ble:d $label9 */
3946 {
3947 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3948 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3949 #define FLD(f) abuf->fields.sfmt_brad.f
3950 int UNUSED written = 0;
3951 IADDR UNUSED pc = abuf->addr;
3952 SEM_BRANCH_INIT
3953 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3954
3955 {
3956 if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
3957 {
3958 USI opval = FLD (i_label9);
3959 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3960 written |= (1 << 4);
3961 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3962 }
3963 }
3964 }
3965
3966 abuf->written = written;
3967 SEM_BRANCH_FINI (vpc);
3968 #undef FLD
3969 }
3970 NEXT (vpc);
3971
3972 CASE (sem, INSN_BLE) : /* ble $label9 */
3973 {
3974 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3975 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3976 #define FLD(f) abuf->fields.sfmt_brad.f
3977 int UNUSED written = 0;
3978 IADDR UNUSED pc = abuf->addr;
3979 SEM_BRANCH_INIT
3980 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3981
3982 if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
3983 {
3984 USI opval = FLD (i_label9);
3985 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3986 written |= (1 << 4);
3987 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3988 }
3989 }
3990
3991 abuf->written = written;
3992 SEM_BRANCH_FINI (vpc);
3993 #undef FLD
3994 }
3995 NEXT (vpc);
3996
3997 CASE (sem, INSN_BGTD) : /* bgt:d $label9 */
3998 {
3999 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4000 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4001 #define FLD(f) abuf->fields.sfmt_brad.f
4002 int UNUSED written = 0;
4003 IADDR UNUSED pc = abuf->addr;
4004 SEM_BRANCH_INIT
4005 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4006
4007 {
4008 if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
4009 {
4010 USI opval = FLD (i_label9);
4011 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4012 written |= (1 << 4);
4013 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4014 }
4015 }
4016 }
4017
4018 abuf->written = written;
4019 SEM_BRANCH_FINI (vpc);
4020 #undef FLD
4021 }
4022 NEXT (vpc);
4023
4024 CASE (sem, INSN_BGT) : /* bgt $label9 */
4025 {
4026 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4027 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4028 #define FLD(f) abuf->fields.sfmt_brad.f
4029 int UNUSED written = 0;
4030 IADDR UNUSED pc = abuf->addr;
4031 SEM_BRANCH_INIT
4032 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4033
4034 if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
4035 {
4036 USI opval = FLD (i_label9);
4037 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4038 written |= (1 << 4);
4039 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4040 }
4041 }
4042
4043 abuf->written = written;
4044 SEM_BRANCH_FINI (vpc);
4045 #undef FLD
4046 }
4047 NEXT (vpc);
4048
4049 CASE (sem, INSN_BLSD) : /* bls:d $label9 */
4050 {
4051 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4052 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4053 #define FLD(f) abuf->fields.sfmt_brad.f
4054 int UNUSED written = 0;
4055 IADDR UNUSED pc = abuf->addr;
4056 SEM_BRANCH_INIT
4057 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4058
4059 {
4060 if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
4061 {
4062 USI opval = FLD (i_label9);
4063 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4064 written |= (1 << 3);
4065 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4066 }
4067 }
4068 }
4069
4070 abuf->written = written;
4071 SEM_BRANCH_FINI (vpc);
4072 #undef FLD
4073 }
4074 NEXT (vpc);
4075
4076 CASE (sem, INSN_BLS) : /* bls $label9 */
4077 {
4078 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4079 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4080 #define FLD(f) abuf->fields.sfmt_brad.f
4081 int UNUSED written = 0;
4082 IADDR UNUSED pc = abuf->addr;
4083 SEM_BRANCH_INIT
4084 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4085
4086 if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
4087 {
4088 USI opval = FLD (i_label9);
4089 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4090 written |= (1 << 3);
4091 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4092 }
4093 }
4094
4095 abuf->written = written;
4096 SEM_BRANCH_FINI (vpc);
4097 #undef FLD
4098 }
4099 NEXT (vpc);
4100
4101 CASE (sem, INSN_BHID) : /* bhi:d $label9 */
4102 {
4103 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4104 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4105 #define FLD(f) abuf->fields.sfmt_brad.f
4106 int UNUSED written = 0;
4107 IADDR UNUSED pc = abuf->addr;
4108 SEM_BRANCH_INIT
4109 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4110
4111 {
4112 if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
4113 {
4114 USI opval = FLD (i_label9);
4115 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4116 written |= (1 << 3);
4117 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4118 }
4119 }
4120 }
4121
4122 abuf->written = written;
4123 SEM_BRANCH_FINI (vpc);
4124 #undef FLD
4125 }
4126 NEXT (vpc);
4127
4128 CASE (sem, INSN_BHI) : /* bhi $label9 */
4129 {
4130 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4131 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4132 #define FLD(f) abuf->fields.sfmt_brad.f
4133 int UNUSED written = 0;
4134 IADDR UNUSED pc = abuf->addr;
4135 SEM_BRANCH_INIT
4136 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4137
4138 if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
4139 {
4140 USI opval = FLD (i_label9);
4141 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4142 written |= (1 << 3);
4143 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4144 }
4145 }
4146
4147 abuf->written = written;
4148 SEM_BRANCH_FINI (vpc);
4149 #undef FLD
4150 }
4151 NEXT (vpc);
4152
4153 CASE (sem, INSN_DMOVR13) : /* dmov $R13,@$dir10 */
4154 {
4155 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4156 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4157 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4158 int UNUSED written = 0;
4159 IADDR UNUSED pc = abuf->addr;
4160 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4161
4162 {
4163 SI opval = CPU (h_gr[((UINT) 13)]);
4164 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4165 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4166 }
4167
4168 #undef FLD
4169 }
4170 NEXT (vpc);
4171
4172 CASE (sem, INSN_DMOVR13H) : /* dmovh $R13,@$dir9 */
4173 {
4174 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4175 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4176 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4177 int UNUSED written = 0;
4178 IADDR UNUSED pc = abuf->addr;
4179 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4180
4181 {
4182 HI opval = CPU (h_gr[((UINT) 13)]);
4183 SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
4184 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4185 }
4186
4187 #undef FLD
4188 }
4189 NEXT (vpc);
4190
4191 CASE (sem, INSN_DMOVR13B) : /* dmovb $R13,@$dir8 */
4192 {
4193 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4194 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4195 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4196 int UNUSED written = 0;
4197 IADDR UNUSED pc = abuf->addr;
4198 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4199
4200 {
4201 QI opval = CPU (h_gr[((UINT) 13)]);
4202 SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
4203 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4204 }
4205
4206 #undef FLD
4207 }
4208 NEXT (vpc);
4209
4210 CASE (sem, INSN_DMOVR13PI) : /* dmov @$R13+,@$dir10 */
4211 {
4212 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4213 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4214 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4215 int UNUSED written = 0;
4216 IADDR UNUSED pc = abuf->addr;
4217 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4218
4219 {
4220 {
4221 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4222 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4223 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4224 }
4225 {
4226 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
4227 CPU (h_gr[((UINT) 13)]) = opval;
4228 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4229 }
4230 }
4231
4232 #undef FLD
4233 }
4234 NEXT (vpc);
4235
4236 CASE (sem, INSN_DMOVR13PIH) : /* dmovh @$R13+,@$dir9 */
4237 {
4238 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4239 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4240 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4241 int UNUSED written = 0;
4242 IADDR UNUSED pc = abuf->addr;
4243 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4244
4245 {
4246 {
4247 HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4248 SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
4249 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4250 }
4251 {
4252 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
4253 CPU (h_gr[((UINT) 13)]) = opval;
4254 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4255 }
4256 }
4257
4258 #undef FLD
4259 }
4260 NEXT (vpc);
4261
4262 CASE (sem, INSN_DMOVR13PIB) : /* dmovb @$R13+,@$dir8 */
4263 {
4264 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4265 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4266 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4267 int UNUSED written = 0;
4268 IADDR UNUSED pc = abuf->addr;
4269 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4270
4271 {
4272 {
4273 QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4274 SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
4275 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4276 }
4277 {
4278 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
4279 CPU (h_gr[((UINT) 13)]) = opval;
4280 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4281 }
4282 }
4283
4284 #undef FLD
4285 }
4286 NEXT (vpc);
4287
4288 CASE (sem, INSN_DMOVR15PI) : /* dmov @$R15+,@$dir10 */
4289 {
4290 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4291 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4292 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
4293 int UNUSED written = 0;
4294 IADDR UNUSED pc = abuf->addr;
4295 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4296
4297 {
4298 {
4299 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4300 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4301 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4302 }
4303 {
4304 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4305 CPU (h_gr[((UINT) 15)]) = opval;
4306 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4307 }
4308 }
4309
4310 #undef FLD
4311 }
4312 NEXT (vpc);
4313
4314 CASE (sem, INSN_DMOV2R13) : /* dmov @$dir10,$R13 */
4315 {
4316 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4317 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4318 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4319 int UNUSED written = 0;
4320 IADDR UNUSED pc = abuf->addr;
4321 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4322
4323 {
4324 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4325 CPU (h_gr[((UINT) 13)]) = opval;
4326 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4327 }
4328
4329 #undef FLD
4330 }
4331 NEXT (vpc);
4332
4333 CASE (sem, INSN_DMOV2R13H) : /* dmovh @$dir9,$R13 */
4334 {
4335 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4336 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4337 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4338 int UNUSED written = 0;
4339 IADDR UNUSED pc = abuf->addr;
4340 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4341
4342 {
4343 SI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
4344 CPU (h_gr[((UINT) 13)]) = opval;
4345 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4346 }
4347
4348 #undef FLD
4349 }
4350 NEXT (vpc);
4351
4352 CASE (sem, INSN_DMOV2R13B) : /* dmovb @$dir8,$R13 */
4353 {
4354 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4355 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4356 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4357 int UNUSED written = 0;
4358 IADDR UNUSED pc = abuf->addr;
4359 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4360
4361 {
4362 SI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
4363 CPU (h_gr[((UINT) 13)]) = opval;
4364 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4365 }
4366
4367 #undef FLD
4368 }
4369 NEXT (vpc);
4370
4371 CASE (sem, INSN_DMOV2R13PI) : /* dmov @$dir10,@$R13+ */
4372 {
4373 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4374 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4375 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4376 int UNUSED written = 0;
4377 IADDR UNUSED pc = abuf->addr;
4378 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4379
4380 {
4381 {
4382 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4383 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4384 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4385 }
4386 {
4387 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
4388 CPU (h_gr[((UINT) 13)]) = opval;
4389 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4390 }
4391 }
4392
4393 #undef FLD
4394 }
4395 NEXT (vpc);
4396
4397 CASE (sem, INSN_DMOV2R13PIH) : /* dmovh @$dir9,@$R13+ */
4398 {
4399 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4400 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4401 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4402 int UNUSED written = 0;
4403 IADDR UNUSED pc = abuf->addr;
4404 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4405
4406 {
4407 {
4408 HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
4409 SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4410 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4411 }
4412 {
4413 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
4414 CPU (h_gr[((UINT) 13)]) = opval;
4415 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4416 }
4417 }
4418
4419 #undef FLD
4420 }
4421 NEXT (vpc);
4422
4423 CASE (sem, INSN_DMOV2R13PIB) : /* dmovb @$dir8,@$R13+ */
4424 {
4425 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4426 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4427 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4428 int UNUSED written = 0;
4429 IADDR UNUSED pc = abuf->addr;
4430 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4431
4432 {
4433 {
4434 QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
4435 SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4436 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4437 }
4438 {
4439 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
4440 CPU (h_gr[((UINT) 13)]) = opval;
4441 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4442 }
4443 }
4444
4445 #undef FLD
4446 }
4447 NEXT (vpc);
4448
4449 CASE (sem, INSN_DMOV2R15PD) : /* dmov @$dir10,@-$R15 */
4450 {
4451 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4452 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4453 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
4454 int UNUSED written = 0;
4455 IADDR UNUSED pc = abuf->addr;
4456 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4457
4458 {
4459 {
4460 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
4461 CPU (h_gr[((UINT) 15)]) = opval;
4462 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4463 }
4464 {
4465 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4466 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
4467 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4468 }
4469 }
4470
4471 #undef FLD
4472 }
4473 NEXT (vpc);
4474
4475 CASE (sem, INSN_LDRES) : /* ldres @$Ri+,$u4 */
4476 {
4477 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4478 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4479 #define FLD(f) abuf->fields.sfmt_add2.f
4480 int UNUSED written = 0;
4481 IADDR UNUSED pc = abuf->addr;
4482 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4483
4484 {
4485 SI opval = ADDSI (* FLD (i_Ri), 4);
4486 * FLD (i_Ri) = opval;
4487 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4488 }
4489
4490 #undef FLD
4491 }
4492 NEXT (vpc);
4493
4494 CASE (sem, INSN_STRES) : /* stres $u4,@$Ri+ */
4495 {
4496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4498 #define FLD(f) abuf->fields.sfmt_add2.f
4499 int UNUSED written = 0;
4500 IADDR UNUSED pc = abuf->addr;
4501 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4502
4503 {
4504 SI opval = ADDSI (* FLD (i_Ri), 4);
4505 * FLD (i_Ri) = opval;
4506 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4507 }
4508
4509 #undef FLD
4510 }
4511 NEXT (vpc);
4512
4513 CASE (sem, INSN_COPOP) : /* copop $u4c,$ccc,$CRj,$CRi */
4514 {
4515 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4516 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4517 #define FLD(f) abuf->fields.fmt_empty.f
4518 int UNUSED written = 0;
4519 IADDR UNUSED pc = abuf->addr;
4520 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4521
4522 ((void) 0); /*nop*/
4523
4524 #undef FLD
4525 }
4526 NEXT (vpc);
4527
4528 CASE (sem, INSN_COPLD) : /* copld $u4c,$ccc,$Rjc,$CRi */
4529 {
4530 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4531 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4532 #define FLD(f) abuf->fields.fmt_empty.f
4533 int UNUSED written = 0;
4534 IADDR UNUSED pc = abuf->addr;
4535 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4536
4537 ((void) 0); /*nop*/
4538
4539 #undef FLD
4540 }
4541 NEXT (vpc);
4542
4543 CASE (sem, INSN_COPST) : /* copst $u4c,$ccc,$CRj,$Ric */
4544 {
4545 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4546 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4547 #define FLD(f) abuf->fields.fmt_empty.f
4548 int UNUSED written = 0;
4549 IADDR UNUSED pc = abuf->addr;
4550 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4551
4552 ((void) 0); /*nop*/
4553
4554 #undef FLD
4555 }
4556 NEXT (vpc);
4557
4558 CASE (sem, INSN_COPSV) : /* copsv $u4c,$ccc,$CRj,$Ric */
4559 {
4560 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4561 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4562 #define FLD(f) abuf->fields.fmt_empty.f
4563 int UNUSED written = 0;
4564 IADDR UNUSED pc = abuf->addr;
4565 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4566
4567 ((void) 0); /*nop*/
4568
4569 #undef FLD
4570 }
4571 NEXT (vpc);
4572
4573 CASE (sem, INSN_NOP) : /* nop */
4574 {
4575 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4576 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4577 #define FLD(f) abuf->fields.fmt_empty.f
4578 int UNUSED written = 0;
4579 IADDR UNUSED pc = abuf->addr;
4580 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4581
4582 ((void) 0); /*nop*/
4583
4584 #undef FLD
4585 }
4586 NEXT (vpc);
4587
4588 CASE (sem, INSN_ANDCCR) : /* andccr $u8 */
4589 {
4590 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4591 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4592 #define FLD(f) abuf->fields.sfmt_int.f
4593 int UNUSED written = 0;
4594 IADDR UNUSED pc = abuf->addr;
4595 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4596
4597 {
4598 UQI opval = ANDQI (GET_H_CCR (), FLD (f_u8));
4599 SET_H_CCR (opval);
4600 TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
4601 }
4602
4603 #undef FLD
4604 }
4605 NEXT (vpc);
4606
4607 CASE (sem, INSN_ORCCR) : /* orccr $u8 */
4608 {
4609 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4610 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4611 #define FLD(f) abuf->fields.sfmt_int.f
4612 int UNUSED written = 0;
4613 IADDR UNUSED pc = abuf->addr;
4614 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4615
4616 {
4617 UQI opval = ORQI (GET_H_CCR (), FLD (f_u8));
4618 SET_H_CCR (opval);
4619 TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
4620 }
4621
4622 #undef FLD
4623 }
4624 NEXT (vpc);
4625
4626 CASE (sem, INSN_STILM) : /* stilm $u8 */
4627 {
4628 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4629 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4630 #define FLD(f) abuf->fields.sfmt_int.f
4631 int UNUSED written = 0;
4632 IADDR UNUSED pc = abuf->addr;
4633 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4634
4635 {
4636 UQI opval = ANDSI (FLD (f_u8), 31);
4637 SET_H_ILM (opval);
4638 TRACE_RESULT (current_cpu, abuf, "ilm", 'x', opval);
4639 }
4640
4641 #undef FLD
4642 }
4643 NEXT (vpc);
4644
4645 CASE (sem, INSN_ADDSP) : /* addsp $s10 */
4646 {
4647 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4648 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4649 #define FLD(f) abuf->fields.sfmt_addsp.f
4650 int UNUSED written = 0;
4651 IADDR UNUSED pc = abuf->addr;
4652 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4653
4654 {
4655 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_s10));
4656 CPU (h_gr[((UINT) 15)]) = opval;
4657 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4658 }
4659
4660 #undef FLD
4661 }
4662 NEXT (vpc);
4663
4664 CASE (sem, INSN_EXTSB) : /* extsb $Ri */
4665 {
4666 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4667 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4668 #define FLD(f) abuf->fields.sfmt_add2.f
4669 int UNUSED written = 0;
4670 IADDR UNUSED pc = abuf->addr;
4671 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4672
4673 {
4674 SI opval = EXTQISI (ANDQI (* FLD (i_Ri), 255));
4675 * FLD (i_Ri) = opval;
4676 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4677 }
4678
4679 #undef FLD
4680 }
4681 NEXT (vpc);
4682
4683 CASE (sem, INSN_EXTUB) : /* extub $Ri */
4684 {
4685 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4686 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4687 #define FLD(f) abuf->fields.sfmt_add2.f
4688 int UNUSED written = 0;
4689 IADDR UNUSED pc = abuf->addr;
4690 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4691
4692 {
4693 SI opval = ZEXTQISI (ANDQI (* FLD (i_Ri), 255));
4694 * FLD (i_Ri) = opval;
4695 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4696 }
4697
4698 #undef FLD
4699 }
4700 NEXT (vpc);
4701
4702 CASE (sem, INSN_EXTSH) : /* extsh $Ri */
4703 {
4704 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4705 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4706 #define FLD(f) abuf->fields.sfmt_add2.f
4707 int UNUSED written = 0;
4708 IADDR UNUSED pc = abuf->addr;
4709 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4710
4711 {
4712 SI opval = EXTHISI (ANDHI (* FLD (i_Ri), 65535));
4713 * FLD (i_Ri) = opval;
4714 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4715 }
4716
4717 #undef FLD
4718 }
4719 NEXT (vpc);
4720
4721 CASE (sem, INSN_EXTUH) : /* extuh $Ri */
4722 {
4723 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4724 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4725 #define FLD(f) abuf->fields.sfmt_add2.f
4726 int UNUSED written = 0;
4727 IADDR UNUSED pc = abuf->addr;
4728 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4729
4730 {
4731 SI opval = ZEXTHISI (ANDHI (* FLD (i_Ri), 65535));
4732 * FLD (i_Ri) = opval;
4733 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4734 }
4735
4736 #undef FLD
4737 }
4738 NEXT (vpc);
4739
4740 CASE (sem, INSN_LDM0) : /* ldm0 ($reglist_low_ld) */
4741 {
4742 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4743 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4744 #define FLD(f) abuf->fields.sfmt_ldm0.f
4745 int UNUSED written = 0;
4746 IADDR UNUSED pc = abuf->addr;
4747 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4748
4749 {
4750 if (ANDSI (FLD (f_reglist_low_ld), 1)) {
4751 {
4752 {
4753 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4754 CPU (h_gr[((UINT) 0)]) = opval;
4755 written |= (1 << 3);
4756 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4757 }
4758 {
4759 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4760 CPU (h_gr[((UINT) 15)]) = opval;
4761 written |= (1 << 5);
4762 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4763 }
4764 }
4765 }
4766 if (ANDSI (FLD (f_reglist_low_ld), 2)) {
4767 {
4768 {
4769 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4770 CPU (h_gr[((UINT) 1)]) = opval;
4771 written |= (1 << 4);
4772 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4773 }
4774 {
4775 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4776 CPU (h_gr[((UINT) 15)]) = opval;
4777 written |= (1 << 5);
4778 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4779 }
4780 }
4781 }
4782 if (ANDSI (FLD (f_reglist_low_ld), 4)) {
4783 {
4784 {
4785 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4786 CPU (h_gr[((UINT) 2)]) = opval;
4787 written |= (1 << 6);
4788 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4789 }
4790 {
4791 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4792 CPU (h_gr[((UINT) 15)]) = opval;
4793 written |= (1 << 5);
4794 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4795 }
4796 }
4797 }
4798 if (ANDSI (FLD (f_reglist_low_ld), 8)) {
4799 {
4800 {
4801 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4802 CPU (h_gr[((UINT) 3)]) = opval;
4803 written |= (1 << 7);
4804 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4805 }
4806 {
4807 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4808 CPU (h_gr[((UINT) 15)]) = opval;
4809 written |= (1 << 5);
4810 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4811 }
4812 }
4813 }
4814 if (ANDSI (FLD (f_reglist_low_ld), 16)) {
4815 {
4816 {
4817 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4818 CPU (h_gr[((UINT) 4)]) = opval;
4819 written |= (1 << 8);
4820 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4821 }
4822 {
4823 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4824 CPU (h_gr[((UINT) 15)]) = opval;
4825 written |= (1 << 5);
4826 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4827 }
4828 }
4829 }
4830 if (ANDSI (FLD (f_reglist_low_ld), 32)) {
4831 {
4832 {
4833 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4834 CPU (h_gr[((UINT) 5)]) = opval;
4835 written |= (1 << 9);
4836 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4837 }
4838 {
4839 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4840 CPU (h_gr[((UINT) 15)]) = opval;
4841 written |= (1 << 5);
4842 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4843 }
4844 }
4845 }
4846 if (ANDSI (FLD (f_reglist_low_ld), 64)) {
4847 {
4848 {
4849 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4850 CPU (h_gr[((UINT) 6)]) = opval;
4851 written |= (1 << 10);
4852 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4853 }
4854 {
4855 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4856 CPU (h_gr[((UINT) 15)]) = opval;
4857 written |= (1 << 5);
4858 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4859 }
4860 }
4861 }
4862 if (ANDSI (FLD (f_reglist_low_ld), 128)) {
4863 {
4864 {
4865 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4866 CPU (h_gr[((UINT) 7)]) = opval;
4867 written |= (1 << 11);
4868 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4869 }
4870 {
4871 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4872 CPU (h_gr[((UINT) 15)]) = opval;
4873 written |= (1 << 5);
4874 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4875 }
4876 }
4877 }
4878 }
4879
4880 abuf->written = written;
4881 #undef FLD
4882 }
4883 NEXT (vpc);
4884
4885 CASE (sem, INSN_LDM1) : /* ldm1 ($reglist_hi_ld) */
4886 {
4887 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4888 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4889 #define FLD(f) abuf->fields.sfmt_ldm1.f
4890 int UNUSED written = 0;
4891 IADDR UNUSED pc = abuf->addr;
4892 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4893
4894 {
4895 if (ANDSI (FLD (f_reglist_hi_ld), 1)) {
4896 {
4897 {
4898 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4899 CPU (h_gr[((UINT) 8)]) = opval;
4900 written |= (1 << 9);
4901 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4902 }
4903 {
4904 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4905 CPU (h_gr[((UINT) 15)]) = opval;
4906 written |= (1 << 8);
4907 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4908 }
4909 }
4910 }
4911 if (ANDSI (FLD (f_reglist_hi_ld), 2)) {
4912 {
4913 {
4914 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4915 CPU (h_gr[((UINT) 9)]) = opval;
4916 written |= (1 << 10);
4917 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4918 }
4919 {
4920 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4921 CPU (h_gr[((UINT) 15)]) = opval;
4922 written |= (1 << 8);
4923 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4924 }
4925 }
4926 }
4927 if (ANDSI (FLD (f_reglist_hi_ld), 4)) {
4928 {
4929 {
4930 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4931 CPU (h_gr[((UINT) 10)]) = opval;
4932 written |= (1 << 3);
4933 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4934 }
4935 {
4936 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4937 CPU (h_gr[((UINT) 15)]) = opval;
4938 written |= (1 << 8);
4939 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4940 }
4941 }
4942 }
4943 if (ANDSI (FLD (f_reglist_hi_ld), 8)) {
4944 {
4945 {
4946 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4947 CPU (h_gr[((UINT) 11)]) = opval;
4948 written |= (1 << 4);
4949 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4950 }
4951 {
4952 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4953 CPU (h_gr[((UINT) 15)]) = opval;
4954 written |= (1 << 8);
4955 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4956 }
4957 }
4958 }
4959 if (ANDSI (FLD (f_reglist_hi_ld), 16)) {
4960 {
4961 {
4962 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4963 CPU (h_gr[((UINT) 12)]) = opval;
4964 written |= (1 << 5);
4965 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4966 }
4967 {
4968 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4969 CPU (h_gr[((UINT) 15)]) = opval;
4970 written |= (1 << 8);
4971 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4972 }
4973 }
4974 }
4975 if (ANDSI (FLD (f_reglist_hi_ld), 32)) {
4976 {
4977 {
4978 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4979 CPU (h_gr[((UINT) 13)]) = opval;
4980 written |= (1 << 6);
4981 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4982 }
4983 {
4984 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4985 CPU (h_gr[((UINT) 15)]) = opval;
4986 written |= (1 << 8);
4987 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4988 }
4989 }
4990 }
4991 if (ANDSI (FLD (f_reglist_hi_ld), 64)) {
4992 {
4993 {
4994 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4995 CPU (h_gr[((UINT) 14)]) = opval;
4996 written |= (1 << 7);
4997 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
4998 }
4999 {
5000 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
5001 CPU (h_gr[((UINT) 15)]) = opval;
5002 written |= (1 << 8);
5003 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5004 }
5005 }
5006 }
5007 if (ANDSI (FLD (f_reglist_hi_ld), 128)) {
5008 {
5009 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
5010 CPU (h_gr[((UINT) 15)]) = opval;
5011 written |= (1 << 8);
5012 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5013 }
5014 }
5015 }
5016
5017 abuf->written = written;
5018 #undef FLD
5019 }
5020 NEXT (vpc);
5021
5022 CASE (sem, INSN_STM0) : /* stm0 ($reglist_low_st) */
5023 {
5024 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5025 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5026 #define FLD(f) abuf->fields.sfmt_stm0.f
5027 int UNUSED written = 0;
5028 IADDR UNUSED pc = abuf->addr;
5029 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5030
5031 {
5032 if (ANDSI (FLD (f_reglist_low_st), 1)) {
5033 {
5034 {
5035 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5036 CPU (h_gr[((UINT) 15)]) = opval;
5037 written |= (1 << 10);
5038 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5039 }
5040 {
5041 SI opval = CPU (h_gr[((UINT) 7)]);
5042 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5043 written |= (1 << 11);
5044 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5045 }
5046 }
5047 }
5048 if (ANDSI (FLD (f_reglist_low_st), 2)) {
5049 {
5050 {
5051 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5052 CPU (h_gr[((UINT) 15)]) = opval;
5053 written |= (1 << 10);
5054 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5055 }
5056 {
5057 SI opval = CPU (h_gr[((UINT) 6)]);
5058 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5059 written |= (1 << 11);
5060 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5061 }
5062 }
5063 }
5064 if (ANDSI (FLD (f_reglist_low_st), 4)) {
5065 {
5066 {
5067 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5068 CPU (h_gr[((UINT) 15)]) = opval;
5069 written |= (1 << 10);
5070 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5071 }
5072 {
5073 SI opval = CPU (h_gr[((UINT) 5)]);
5074 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5075 written |= (1 << 11);
5076 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5077 }
5078 }
5079 }
5080 if (ANDSI (FLD (f_reglist_low_st), 8)) {
5081 {
5082 {
5083 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5084 CPU (h_gr[((UINT) 15)]) = opval;
5085 written |= (1 << 10);
5086 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5087 }
5088 {
5089 SI opval = CPU (h_gr[((UINT) 4)]);
5090 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5091 written |= (1 << 11);
5092 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5093 }
5094 }
5095 }
5096 if (ANDSI (FLD (f_reglist_low_st), 16)) {
5097 {
5098 {
5099 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5100 CPU (h_gr[((UINT) 15)]) = opval;
5101 written |= (1 << 10);
5102 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5103 }
5104 {
5105 SI opval = CPU (h_gr[((UINT) 3)]);
5106 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5107 written |= (1 << 11);
5108 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5109 }
5110 }
5111 }
5112 if (ANDSI (FLD (f_reglist_low_st), 32)) {
5113 {
5114 {
5115 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5116 CPU (h_gr[((UINT) 15)]) = opval;
5117 written |= (1 << 10);
5118 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5119 }
5120 {
5121 SI opval = CPU (h_gr[((UINT) 2)]);
5122 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5123 written |= (1 << 11);
5124 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5125 }
5126 }
5127 }
5128 if (ANDSI (FLD (f_reglist_low_st), 64)) {
5129 {
5130 {
5131 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5132 CPU (h_gr[((UINT) 15)]) = opval;
5133 written |= (1 << 10);
5134 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5135 }
5136 {
5137 SI opval = CPU (h_gr[((UINT) 1)]);
5138 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5139 written |= (1 << 11);
5140 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5141 }
5142 }
5143 }
5144 if (ANDSI (FLD (f_reglist_low_st), 128)) {
5145 {
5146 {
5147 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5148 CPU (h_gr[((UINT) 15)]) = opval;
5149 written |= (1 << 10);
5150 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5151 }
5152 {
5153 SI opval = CPU (h_gr[((UINT) 0)]);
5154 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5155 written |= (1 << 11);
5156 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5157 }
5158 }
5159 }
5160 }
5161
5162 abuf->written = written;
5163 #undef FLD
5164 }
5165 NEXT (vpc);
5166
5167 CASE (sem, INSN_STM1) : /* stm1 ($reglist_hi_st) */
5168 {
5169 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5170 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5171 #define FLD(f) abuf->fields.sfmt_stm1.f
5172 int UNUSED written = 0;
5173 IADDR UNUSED pc = abuf->addr;
5174 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5175
5176 {
5177 if (ANDSI (FLD (f_reglist_hi_st), 1)) {
5178 {
5179 SI tmp_save_r15;
5180 tmp_save_r15 = CPU (h_gr[((UINT) 15)]);
5181 {
5182 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5183 CPU (h_gr[((UINT) 15)]) = opval;
5184 written |= (1 << 9);
5185 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5186 }
5187 {
5188 SI opval = tmp_save_r15;
5189 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5190 written |= (1 << 10);
5191 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5192 }
5193 }
5194 }
5195 if (ANDSI (FLD (f_reglist_hi_st), 2)) {
5196 {
5197 {
5198 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5199 CPU (h_gr[((UINT) 15)]) = opval;
5200 written |= (1 << 9);
5201 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5202 }
5203 {
5204 SI opval = CPU (h_gr[((UINT) 14)]);
5205 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5206 written |= (1 << 10);
5207 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5208 }
5209 }
5210 }
5211 if (ANDSI (FLD (f_reglist_hi_st), 4)) {
5212 {
5213 {
5214 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5215 CPU (h_gr[((UINT) 15)]) = opval;
5216 written |= (1 << 9);
5217 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5218 }
5219 {
5220 SI opval = CPU (h_gr[((UINT) 13)]);
5221 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5222 written |= (1 << 10);
5223 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5224 }
5225 }
5226 }
5227 if (ANDSI (FLD (f_reglist_hi_st), 8)) {
5228 {
5229 {
5230 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5231 CPU (h_gr[((UINT) 15)]) = opval;
5232 written |= (1 << 9);
5233 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5234 }
5235 {
5236 SI opval = CPU (h_gr[((UINT) 12)]);
5237 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5238 written |= (1 << 10);
5239 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5240 }
5241 }
5242 }
5243 if (ANDSI (FLD (f_reglist_hi_st), 16)) {
5244 {
5245 {
5246 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5247 CPU (h_gr[((UINT) 15)]) = opval;
5248 written |= (1 << 9);
5249 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5250 }
5251 {
5252 SI opval = CPU (h_gr[((UINT) 11)]);
5253 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5254 written |= (1 << 10);
5255 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5256 }
5257 }
5258 }
5259 if (ANDSI (FLD (f_reglist_hi_st), 32)) {
5260 {
5261 {
5262 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5263 CPU (h_gr[((UINT) 15)]) = opval;
5264 written |= (1 << 9);
5265 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5266 }
5267 {
5268 SI opval = CPU (h_gr[((UINT) 10)]);
5269 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5270 written |= (1 << 10);
5271 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5272 }
5273 }
5274 }
5275 if (ANDSI (FLD (f_reglist_hi_st), 64)) {
5276 {
5277 {
5278 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5279 CPU (h_gr[((UINT) 15)]) = opval;
5280 written |= (1 << 9);
5281 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5282 }
5283 {
5284 SI opval = CPU (h_gr[((UINT) 9)]);
5285 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5286 written |= (1 << 10);
5287 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5288 }
5289 }
5290 }
5291 if (ANDSI (FLD (f_reglist_hi_st), 128)) {
5292 {
5293 {
5294 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5295 CPU (h_gr[((UINT) 15)]) = opval;
5296 written |= (1 << 9);
5297 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5298 }
5299 {
5300 SI opval = CPU (h_gr[((UINT) 8)]);
5301 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5302 written |= (1 << 10);
5303 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5304 }
5305 }
5306 }
5307 }
5308
5309 abuf->written = written;
5310 #undef FLD
5311 }
5312 NEXT (vpc);
5313
5314 CASE (sem, INSN_ENTER) : /* enter $u10 */
5315 {
5316 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5317 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5318 #define FLD(f) abuf->fields.sfmt_enter.f
5319 int UNUSED written = 0;
5320 IADDR UNUSED pc = abuf->addr;
5321 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5322
5323 {
5324 SI tmp_tmp;
5325 tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5326 {
5327 SI opval = CPU (h_gr[((UINT) 14)]);
5328 SETMEMSI (current_cpu, pc, tmp_tmp, opval);
5329 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5330 }
5331 {
5332 SI opval = tmp_tmp;
5333 CPU (h_gr[((UINT) 14)]) = opval;
5334 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5335 }
5336 {
5337 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), FLD (f_u10));
5338 CPU (h_gr[((UINT) 15)]) = opval;
5339 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5340 }
5341 }
5342
5343 #undef FLD
5344 }
5345 NEXT (vpc);
5346
5347 CASE (sem, INSN_LEAVE) : /* leave */
5348 {
5349 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5350 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5351 #define FLD(f) abuf->fields.sfmt_enter.f
5352 int UNUSED written = 0;
5353 IADDR UNUSED pc = abuf->addr;
5354 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5355
5356 {
5357 {
5358 SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4);
5359 CPU (h_gr[((UINT) 15)]) = opval;
5360 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5361 }
5362 {
5363 SI opval = GETMEMSI (current_cpu, pc, SUBSI (CPU (h_gr[((UINT) 15)]), 4));
5364 CPU (h_gr[((UINT) 14)]) = opval;
5365 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5366 }
5367 }
5368
5369 #undef FLD
5370 }
5371 NEXT (vpc);
5372
5373 CASE (sem, INSN_XCHB) : /* xchb @$Rj,$Ri */
5374 {
5375 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5376 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5377 #define FLD(f) abuf->fields.sfmt_add.f
5378 int UNUSED written = 0;
5379 IADDR UNUSED pc = abuf->addr;
5380 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5381
5382 {
5383 SI tmp_tmp;
5384 tmp_tmp = * FLD (i_Ri);
5385 {
5386 SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
5387 * FLD (i_Ri) = opval;
5388 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval);
5389 }
5390 {
5391 UQI opval = tmp_tmp;
5392 SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval);
5393 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5394 }
5395 }
5396
5397 #undef FLD
5398 }
5399 NEXT (vpc);
5400
5401
5402 }
5403 ENDSWITCH (sem) /* End of semantic switch. */
5404
5405 /* At this point `vpc' contains the next insn to execute. */
5406 }
5407
5408 #undef DEFINE_SWITCH
5409 #endif /* DEFINE_SWITCH */