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import gdb-1999-08-09 snapshot
[binutils-gdb.git] / sim / fr30 / sem-switch.c
1 /* Simulator instruction semantics for fr30bf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7 This file is part of the GNU Simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #ifdef DEFINE_LABELS
26
27 /* The labels have the case they have because the enum of insn types
28 is all uppercase and in the non-stdc case the insn symbol is built
29 into the enum name. */
30
31 static struct {
32 int index;
33 void *label;
34 } labels[] = {
35 { FR30BF_INSN_X_INVALID, && case_sem_INSN_X_INVALID },
36 { FR30BF_INSN_X_AFTER, && case_sem_INSN_X_AFTER },
37 { FR30BF_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE },
38 { FR30BF_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN },
39 { FR30BF_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN },
40 { FR30BF_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN },
41 { FR30BF_INSN_ADD, && case_sem_INSN_ADD },
42 { FR30BF_INSN_ADDI, && case_sem_INSN_ADDI },
43 { FR30BF_INSN_ADD2, && case_sem_INSN_ADD2 },
44 { FR30BF_INSN_ADDC, && case_sem_INSN_ADDC },
45 { FR30BF_INSN_ADDN, && case_sem_INSN_ADDN },
46 { FR30BF_INSN_ADDNI, && case_sem_INSN_ADDNI },
47 { FR30BF_INSN_ADDN2, && case_sem_INSN_ADDN2 },
48 { FR30BF_INSN_SUB, && case_sem_INSN_SUB },
49 { FR30BF_INSN_SUBC, && case_sem_INSN_SUBC },
50 { FR30BF_INSN_SUBN, && case_sem_INSN_SUBN },
51 { FR30BF_INSN_CMP, && case_sem_INSN_CMP },
52 { FR30BF_INSN_CMPI, && case_sem_INSN_CMPI },
53 { FR30BF_INSN_CMP2, && case_sem_INSN_CMP2 },
54 { FR30BF_INSN_AND, && case_sem_INSN_AND },
55 { FR30BF_INSN_OR, && case_sem_INSN_OR },
56 { FR30BF_INSN_EOR, && case_sem_INSN_EOR },
57 { FR30BF_INSN_ANDM, && case_sem_INSN_ANDM },
58 { FR30BF_INSN_ANDH, && case_sem_INSN_ANDH },
59 { FR30BF_INSN_ANDB, && case_sem_INSN_ANDB },
60 { FR30BF_INSN_ORM, && case_sem_INSN_ORM },
61 { FR30BF_INSN_ORH, && case_sem_INSN_ORH },
62 { FR30BF_INSN_ORB, && case_sem_INSN_ORB },
63 { FR30BF_INSN_EORM, && case_sem_INSN_EORM },
64 { FR30BF_INSN_EORH, && case_sem_INSN_EORH },
65 { FR30BF_INSN_EORB, && case_sem_INSN_EORB },
66 { FR30BF_INSN_BANDL, && case_sem_INSN_BANDL },
67 { FR30BF_INSN_BORL, && case_sem_INSN_BORL },
68 { FR30BF_INSN_BEORL, && case_sem_INSN_BEORL },
69 { FR30BF_INSN_BANDH, && case_sem_INSN_BANDH },
70 { FR30BF_INSN_BORH, && case_sem_INSN_BORH },
71 { FR30BF_INSN_BEORH, && case_sem_INSN_BEORH },
72 { FR30BF_INSN_BTSTL, && case_sem_INSN_BTSTL },
73 { FR30BF_INSN_BTSTH, && case_sem_INSN_BTSTH },
74 { FR30BF_INSN_MUL, && case_sem_INSN_MUL },
75 { FR30BF_INSN_MULU, && case_sem_INSN_MULU },
76 { FR30BF_INSN_MULH, && case_sem_INSN_MULH },
77 { FR30BF_INSN_MULUH, && case_sem_INSN_MULUH },
78 { FR30BF_INSN_DIV0S, && case_sem_INSN_DIV0S },
79 { FR30BF_INSN_DIV0U, && case_sem_INSN_DIV0U },
80 { FR30BF_INSN_DIV1, && case_sem_INSN_DIV1 },
81 { FR30BF_INSN_DIV2, && case_sem_INSN_DIV2 },
82 { FR30BF_INSN_DIV3, && case_sem_INSN_DIV3 },
83 { FR30BF_INSN_DIV4S, && case_sem_INSN_DIV4S },
84 { FR30BF_INSN_LSL, && case_sem_INSN_LSL },
85 { FR30BF_INSN_LSLI, && case_sem_INSN_LSLI },
86 { FR30BF_INSN_LSL2, && case_sem_INSN_LSL2 },
87 { FR30BF_INSN_LSR, && case_sem_INSN_LSR },
88 { FR30BF_INSN_LSRI, && case_sem_INSN_LSRI },
89 { FR30BF_INSN_LSR2, && case_sem_INSN_LSR2 },
90 { FR30BF_INSN_ASR, && case_sem_INSN_ASR },
91 { FR30BF_INSN_ASRI, && case_sem_INSN_ASRI },
92 { FR30BF_INSN_ASR2, && case_sem_INSN_ASR2 },
93 { FR30BF_INSN_LDI8, && case_sem_INSN_LDI8 },
94 { FR30BF_INSN_LDI20, && case_sem_INSN_LDI20 },
95 { FR30BF_INSN_LDI32, && case_sem_INSN_LDI32 },
96 { FR30BF_INSN_LD, && case_sem_INSN_LD },
97 { FR30BF_INSN_LDUH, && case_sem_INSN_LDUH },
98 { FR30BF_INSN_LDUB, && case_sem_INSN_LDUB },
99 { FR30BF_INSN_LDR13, && case_sem_INSN_LDR13 },
100 { FR30BF_INSN_LDR13UH, && case_sem_INSN_LDR13UH },
101 { FR30BF_INSN_LDR13UB, && case_sem_INSN_LDR13UB },
102 { FR30BF_INSN_LDR14, && case_sem_INSN_LDR14 },
103 { FR30BF_INSN_LDR14UH, && case_sem_INSN_LDR14UH },
104 { FR30BF_INSN_LDR14UB, && case_sem_INSN_LDR14UB },
105 { FR30BF_INSN_LDR15, && case_sem_INSN_LDR15 },
106 { FR30BF_INSN_LDR15GR, && case_sem_INSN_LDR15GR },
107 { FR30BF_INSN_LDR15DR, && case_sem_INSN_LDR15DR },
108 { FR30BF_INSN_LDR15PS, && case_sem_INSN_LDR15PS },
109 { FR30BF_INSN_ST, && case_sem_INSN_ST },
110 { FR30BF_INSN_STH, && case_sem_INSN_STH },
111 { FR30BF_INSN_STB, && case_sem_INSN_STB },
112 { FR30BF_INSN_STR13, && case_sem_INSN_STR13 },
113 { FR30BF_INSN_STR13H, && case_sem_INSN_STR13H },
114 { FR30BF_INSN_STR13B, && case_sem_INSN_STR13B },
115 { FR30BF_INSN_STR14, && case_sem_INSN_STR14 },
116 { FR30BF_INSN_STR14H, && case_sem_INSN_STR14H },
117 { FR30BF_INSN_STR14B, && case_sem_INSN_STR14B },
118 { FR30BF_INSN_STR15, && case_sem_INSN_STR15 },
119 { FR30BF_INSN_STR15GR, && case_sem_INSN_STR15GR },
120 { FR30BF_INSN_STR15DR, && case_sem_INSN_STR15DR },
121 { FR30BF_INSN_STR15PS, && case_sem_INSN_STR15PS },
122 { FR30BF_INSN_MOV, && case_sem_INSN_MOV },
123 { FR30BF_INSN_MOVDR, && case_sem_INSN_MOVDR },
124 { FR30BF_INSN_MOVPS, && case_sem_INSN_MOVPS },
125 { FR30BF_INSN_MOV2DR, && case_sem_INSN_MOV2DR },
126 { FR30BF_INSN_MOV2PS, && case_sem_INSN_MOV2PS },
127 { FR30BF_INSN_JMP, && case_sem_INSN_JMP },
128 { FR30BF_INSN_JMPD, && case_sem_INSN_JMPD },
129 { FR30BF_INSN_CALLR, && case_sem_INSN_CALLR },
130 { FR30BF_INSN_CALLRD, && case_sem_INSN_CALLRD },
131 { FR30BF_INSN_CALL, && case_sem_INSN_CALL },
132 { FR30BF_INSN_CALLD, && case_sem_INSN_CALLD },
133 { FR30BF_INSN_RET, && case_sem_INSN_RET },
134 { FR30BF_INSN_RET_D, && case_sem_INSN_RET_D },
135 { FR30BF_INSN_INT, && case_sem_INSN_INT },
136 { FR30BF_INSN_INTE, && case_sem_INSN_INTE },
137 { FR30BF_INSN_RETI, && case_sem_INSN_RETI },
138 { FR30BF_INSN_BRAD, && case_sem_INSN_BRAD },
139 { FR30BF_INSN_BRA, && case_sem_INSN_BRA },
140 { FR30BF_INSN_BNOD, && case_sem_INSN_BNOD },
141 { FR30BF_INSN_BNO, && case_sem_INSN_BNO },
142 { FR30BF_INSN_BEQD, && case_sem_INSN_BEQD },
143 { FR30BF_INSN_BEQ, && case_sem_INSN_BEQ },
144 { FR30BF_INSN_BNED, && case_sem_INSN_BNED },
145 { FR30BF_INSN_BNE, && case_sem_INSN_BNE },
146 { FR30BF_INSN_BCD, && case_sem_INSN_BCD },
147 { FR30BF_INSN_BC, && case_sem_INSN_BC },
148 { FR30BF_INSN_BNCD, && case_sem_INSN_BNCD },
149 { FR30BF_INSN_BNC, && case_sem_INSN_BNC },
150 { FR30BF_INSN_BND, && case_sem_INSN_BND },
151 { FR30BF_INSN_BN, && case_sem_INSN_BN },
152 { FR30BF_INSN_BPD, && case_sem_INSN_BPD },
153 { FR30BF_INSN_BP, && case_sem_INSN_BP },
154 { FR30BF_INSN_BVD, && case_sem_INSN_BVD },
155 { FR30BF_INSN_BV, && case_sem_INSN_BV },
156 { FR30BF_INSN_BNVD, && case_sem_INSN_BNVD },
157 { FR30BF_INSN_BNV, && case_sem_INSN_BNV },
158 { FR30BF_INSN_BLTD, && case_sem_INSN_BLTD },
159 { FR30BF_INSN_BLT, && case_sem_INSN_BLT },
160 { FR30BF_INSN_BGED, && case_sem_INSN_BGED },
161 { FR30BF_INSN_BGE, && case_sem_INSN_BGE },
162 { FR30BF_INSN_BLED, && case_sem_INSN_BLED },
163 { FR30BF_INSN_BLE, && case_sem_INSN_BLE },
164 { FR30BF_INSN_BGTD, && case_sem_INSN_BGTD },
165 { FR30BF_INSN_BGT, && case_sem_INSN_BGT },
166 { FR30BF_INSN_BLSD, && case_sem_INSN_BLSD },
167 { FR30BF_INSN_BLS, && case_sem_INSN_BLS },
168 { FR30BF_INSN_BHID, && case_sem_INSN_BHID },
169 { FR30BF_INSN_BHI, && case_sem_INSN_BHI },
170 { FR30BF_INSN_DMOVR13, && case_sem_INSN_DMOVR13 },
171 { FR30BF_INSN_DMOVR13H, && case_sem_INSN_DMOVR13H },
172 { FR30BF_INSN_DMOVR13B, && case_sem_INSN_DMOVR13B },
173 { FR30BF_INSN_DMOVR13PI, && case_sem_INSN_DMOVR13PI },
174 { FR30BF_INSN_DMOVR13PIH, && case_sem_INSN_DMOVR13PIH },
175 { FR30BF_INSN_DMOVR13PIB, && case_sem_INSN_DMOVR13PIB },
176 { FR30BF_INSN_DMOVR15PI, && case_sem_INSN_DMOVR15PI },
177 { FR30BF_INSN_DMOV2R13, && case_sem_INSN_DMOV2R13 },
178 { FR30BF_INSN_DMOV2R13H, && case_sem_INSN_DMOV2R13H },
179 { FR30BF_INSN_DMOV2R13B, && case_sem_INSN_DMOV2R13B },
180 { FR30BF_INSN_DMOV2R13PI, && case_sem_INSN_DMOV2R13PI },
181 { FR30BF_INSN_DMOV2R13PIH, && case_sem_INSN_DMOV2R13PIH },
182 { FR30BF_INSN_DMOV2R13PIB, && case_sem_INSN_DMOV2R13PIB },
183 { FR30BF_INSN_DMOV2R15PD, && case_sem_INSN_DMOV2R15PD },
184 { FR30BF_INSN_LDRES, && case_sem_INSN_LDRES },
185 { FR30BF_INSN_STRES, && case_sem_INSN_STRES },
186 { FR30BF_INSN_COPOP, && case_sem_INSN_COPOP },
187 { FR30BF_INSN_COPLD, && case_sem_INSN_COPLD },
188 { FR30BF_INSN_COPST, && case_sem_INSN_COPST },
189 { FR30BF_INSN_COPSV, && case_sem_INSN_COPSV },
190 { FR30BF_INSN_NOP, && case_sem_INSN_NOP },
191 { FR30BF_INSN_ANDCCR, && case_sem_INSN_ANDCCR },
192 { FR30BF_INSN_ORCCR, && case_sem_INSN_ORCCR },
193 { FR30BF_INSN_STILM, && case_sem_INSN_STILM },
194 { FR30BF_INSN_ADDSP, && case_sem_INSN_ADDSP },
195 { FR30BF_INSN_EXTSB, && case_sem_INSN_EXTSB },
196 { FR30BF_INSN_EXTUB, && case_sem_INSN_EXTUB },
197 { FR30BF_INSN_EXTSH, && case_sem_INSN_EXTSH },
198 { FR30BF_INSN_EXTUH, && case_sem_INSN_EXTUH },
199 { FR30BF_INSN_LDM0, && case_sem_INSN_LDM0 },
200 { FR30BF_INSN_LDM1, && case_sem_INSN_LDM1 },
201 { FR30BF_INSN_STM0, && case_sem_INSN_STM0 },
202 { FR30BF_INSN_STM1, && case_sem_INSN_STM1 },
203 { FR30BF_INSN_ENTER, && case_sem_INSN_ENTER },
204 { FR30BF_INSN_LEAVE, && case_sem_INSN_LEAVE },
205 { FR30BF_INSN_XCHB, && case_sem_INSN_XCHB },
206 { 0, 0 }
207 };
208 int i;
209
210 for (i = 0; labels[i].label != 0; ++i)
211 {
212 #if FAST_P
213 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label;
214 #else
215 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label;
216 #endif
217 }
218
219 #undef DEFINE_LABELS
220 #endif /* DEFINE_LABELS */
221
222 #ifdef DEFINE_SWITCH
223
224 /* If hyper-fast [well not unnecessarily slow] execution is selected, turn
225 off frills like tracing and profiling. */
226 /* FIXME: A better way would be to have TRACE_RESULT check for something
227 that can cause it to be optimized out. Another way would be to emit
228 special handlers into the instruction "stream". */
229
230 #if FAST_P
231 #undef TRACE_RESULT
232 #define TRACE_RESULT(cpu, abuf, name, type, val)
233 #endif
234
235 #undef GET_ATTR
236 #define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr)
237
238 {
239
240 #if WITH_SCACHE_PBB
241
242 /* Branch to next handler without going around main loop. */
243 #define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case
244 SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
245
246 #else /* ! WITH_SCACHE_PBB */
247
248 #define NEXT(vpc) BREAK (sem)
249 #ifdef __GNUC__
250 #if FAST_P
251 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab)
252 #else
253 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab)
254 #endif
255 #else
256 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num)
257 #endif
258
259 #endif /* ! WITH_SCACHE_PBB */
260
261 {
262
263 CASE (sem, INSN_X_INVALID) : /* --invalid-- */
264 {
265 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
266 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
267 #define FLD(f) abuf->fields.fmt_empty.f
268 int UNUSED written = 0;
269 IADDR UNUSED pc = abuf->addr;
270 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
271
272 {
273 #if WITH_SCACHE
274 /* Update the recorded pc in the cpu state struct. */
275 SET_H_PC (pc);
276 #endif
277 sim_engine_invalid_insn (current_cpu, pc);
278 sim_io_error (CPU_STATE (current_cpu), "invalid insn not handled\n");
279 /* NOTREACHED */
280 }
281
282 #undef FLD
283 }
284 NEXT (vpc);
285
286 CASE (sem, INSN_X_AFTER) : /* --after-- */
287 {
288 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
289 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
290 #define FLD(f) abuf->fields.fmt_empty.f
291 int UNUSED written = 0;
292 IADDR UNUSED pc = abuf->addr;
293 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
294
295 {
296 #if WITH_SCACHE_PBB_FR30BF
297 fr30bf_pbb_after (current_cpu, sem_arg);
298 #endif
299 }
300
301 #undef FLD
302 }
303 NEXT (vpc);
304
305 CASE (sem, INSN_X_BEFORE) : /* --before-- */
306 {
307 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
308 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
309 #define FLD(f) abuf->fields.fmt_empty.f
310 int UNUSED written = 0;
311 IADDR UNUSED pc = abuf->addr;
312 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
313
314 {
315 #if WITH_SCACHE_PBB_FR30BF
316 fr30bf_pbb_before (current_cpu, sem_arg);
317 #endif
318 }
319
320 #undef FLD
321 }
322 NEXT (vpc);
323
324 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */
325 {
326 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
327 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
328 #define FLD(f) abuf->fields.fmt_empty.f
329 int UNUSED written = 0;
330 IADDR UNUSED pc = abuf->addr;
331 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
332
333 {
334 #if WITH_SCACHE_PBB_FR30BF
335 #ifdef DEFINE_SWITCH
336 vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
337 pbb_br_type, pbb_br_npc);
338 BREAK (sem);
339 #else
340 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */
341 vpc = fr30bf_pbb_cti_chain (current_cpu, sem_arg,
342 CPU_PBB_BR_TYPE (current_cpu),
343 CPU_PBB_BR_NPC (current_cpu));
344 #endif
345 #endif
346 }
347
348 #undef FLD
349 }
350 NEXT (vpc);
351
352 CASE (sem, INSN_X_CHAIN) : /* --chain-- */
353 {
354 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
355 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
356 #define FLD(f) abuf->fields.fmt_empty.f
357 int UNUSED written = 0;
358 IADDR UNUSED pc = abuf->addr;
359 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
360
361 {
362 #if WITH_SCACHE_PBB_FR30BF
363 vpc = fr30bf_pbb_chain (current_cpu, sem_arg);
364 #ifdef DEFINE_SWITCH
365 BREAK (sem);
366 #endif
367 #endif
368 }
369
370 #undef FLD
371 }
372 NEXT (vpc);
373
374 CASE (sem, INSN_X_BEGIN) : /* --begin-- */
375 {
376 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
377 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
378 #define FLD(f) abuf->fields.fmt_empty.f
379 int UNUSED written = 0;
380 IADDR UNUSED pc = abuf->addr;
381 vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
382
383 {
384 #if WITH_SCACHE_PBB_FR30BF
385 #ifdef DEFINE_SWITCH
386 /* In the switch case FAST_P is a constant, allowing several optimizations
387 in any called inline functions. */
388 vpc = fr30bf_pbb_begin (current_cpu, FAST_P);
389 #else
390 vpc = fr30bf_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu)));
391 #endif
392 #endif
393 }
394
395 #undef FLD
396 }
397 NEXT (vpc);
398
399 CASE (sem, INSN_ADD) : /* add $Rj,$Ri */
400 {
401 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
402 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
403 #define FLD(f) abuf->fields.sfmt_add.f
404 int UNUSED written = 0;
405 IADDR UNUSED pc = abuf->addr;
406 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
407
408 {
409 {
410 BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
411 CPU (h_vbit) = opval;
412 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
413 }
414 {
415 BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
416 CPU (h_cbit) = opval;
417 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
418 }
419 {
420 SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
421 * FLD (i_Ri) = opval;
422 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
423 }
424 {
425 {
426 BI opval = EQSI (* FLD (i_Ri), 0);
427 CPU (h_zbit) = opval;
428 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
429 }
430 {
431 BI opval = LTSI (* FLD (i_Ri), 0);
432 CPU (h_nbit) = opval;
433 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
434 }
435 }
436 }
437
438 #undef FLD
439 }
440 NEXT (vpc);
441
442 CASE (sem, INSN_ADDI) : /* add $u4,$Ri */
443 {
444 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
445 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
446 #define FLD(f) abuf->fields.sfmt_addi.f
447 int UNUSED written = 0;
448 IADDR UNUSED pc = abuf->addr;
449 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
450
451 {
452 {
453 BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_u4), 0);
454 CPU (h_vbit) = opval;
455 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
456 }
457 {
458 BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_u4), 0);
459 CPU (h_cbit) = opval;
460 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
461 }
462 {
463 SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
464 * FLD (i_Ri) = opval;
465 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
466 }
467 {
468 {
469 BI opval = EQSI (* FLD (i_Ri), 0);
470 CPU (h_zbit) = opval;
471 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
472 }
473 {
474 BI opval = LTSI (* FLD (i_Ri), 0);
475 CPU (h_nbit) = opval;
476 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
477 }
478 }
479 }
480
481 #undef FLD
482 }
483 NEXT (vpc);
484
485 CASE (sem, INSN_ADD2) : /* add2 $m4,$Ri */
486 {
487 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
488 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
489 #define FLD(f) abuf->fields.sfmt_add2.f
490 int UNUSED written = 0;
491 IADDR UNUSED pc = abuf->addr;
492 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
493
494 {
495 {
496 BI opval = ADDOFSI (* FLD (i_Ri), FLD (f_m4), 0);
497 CPU (h_vbit) = opval;
498 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
499 }
500 {
501 BI opval = ADDCFSI (* FLD (i_Ri), FLD (f_m4), 0);
502 CPU (h_cbit) = opval;
503 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
504 }
505 {
506 SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
507 * FLD (i_Ri) = opval;
508 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
509 }
510 {
511 {
512 BI opval = EQSI (* FLD (i_Ri), 0);
513 CPU (h_zbit) = opval;
514 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
515 }
516 {
517 BI opval = LTSI (* FLD (i_Ri), 0);
518 CPU (h_nbit) = opval;
519 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
520 }
521 }
522 }
523
524 #undef FLD
525 }
526 NEXT (vpc);
527
528 CASE (sem, INSN_ADDC) : /* addc $Rj,$Ri */
529 {
530 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
531 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
532 #define FLD(f) abuf->fields.sfmt_add.f
533 int UNUSED written = 0;
534 IADDR UNUSED pc = abuf->addr;
535 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
536
537 {
538 SI tmp_tmp;
539 tmp_tmp = ADDCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
540 {
541 BI opval = ADDOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
542 CPU (h_vbit) = opval;
543 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
544 }
545 {
546 BI opval = ADDCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
547 CPU (h_cbit) = opval;
548 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
549 }
550 {
551 SI opval = tmp_tmp;
552 * FLD (i_Ri) = opval;
553 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
554 }
555 {
556 {
557 BI opval = EQSI (* FLD (i_Ri), 0);
558 CPU (h_zbit) = opval;
559 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
560 }
561 {
562 BI opval = LTSI (* FLD (i_Ri), 0);
563 CPU (h_nbit) = opval;
564 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
565 }
566 }
567 }
568
569 #undef FLD
570 }
571 NEXT (vpc);
572
573 CASE (sem, INSN_ADDN) : /* addn $Rj,$Ri */
574 {
575 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
576 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
577 #define FLD(f) abuf->fields.sfmt_add.f
578 int UNUSED written = 0;
579 IADDR UNUSED pc = abuf->addr;
580 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
581
582 {
583 SI opval = ADDSI (* FLD (i_Ri), * FLD (i_Rj));
584 * FLD (i_Ri) = opval;
585 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
586 }
587
588 #undef FLD
589 }
590 NEXT (vpc);
591
592 CASE (sem, INSN_ADDNI) : /* addn $u4,$Ri */
593 {
594 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
595 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
596 #define FLD(f) abuf->fields.sfmt_addi.f
597 int UNUSED written = 0;
598 IADDR UNUSED pc = abuf->addr;
599 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
600
601 {
602 SI opval = ADDSI (* FLD (i_Ri), FLD (f_u4));
603 * FLD (i_Ri) = opval;
604 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
605 }
606
607 #undef FLD
608 }
609 NEXT (vpc);
610
611 CASE (sem, INSN_ADDN2) : /* addn2 $m4,$Ri */
612 {
613 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
614 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
615 #define FLD(f) abuf->fields.sfmt_add2.f
616 int UNUSED written = 0;
617 IADDR UNUSED pc = abuf->addr;
618 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
619
620 {
621 SI opval = ADDSI (* FLD (i_Ri), FLD (f_m4));
622 * FLD (i_Ri) = opval;
623 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
624 }
625
626 #undef FLD
627 }
628 NEXT (vpc);
629
630 CASE (sem, INSN_SUB) : /* sub $Rj,$Ri */
631 {
632 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
633 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
634 #define FLD(f) abuf->fields.sfmt_add.f
635 int UNUSED written = 0;
636 IADDR UNUSED pc = abuf->addr;
637 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
638
639 {
640 {
641 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
642 CPU (h_vbit) = opval;
643 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
644 }
645 {
646 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
647 CPU (h_cbit) = opval;
648 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
649 }
650 {
651 SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
652 * FLD (i_Ri) = opval;
653 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
654 }
655 {
656 {
657 BI opval = EQSI (* FLD (i_Ri), 0);
658 CPU (h_zbit) = opval;
659 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
660 }
661 {
662 BI opval = LTSI (* FLD (i_Ri), 0);
663 CPU (h_nbit) = opval;
664 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
665 }
666 }
667 }
668
669 #undef FLD
670 }
671 NEXT (vpc);
672
673 CASE (sem, INSN_SUBC) : /* subc $Rj,$Ri */
674 {
675 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
676 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
677 #define FLD(f) abuf->fields.sfmt_add.f
678 int UNUSED written = 0;
679 IADDR UNUSED pc = abuf->addr;
680 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
681
682 {
683 SI tmp_tmp;
684 tmp_tmp = SUBCSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
685 {
686 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
687 CPU (h_vbit) = opval;
688 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
689 }
690 {
691 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), CPU (h_cbit));
692 CPU (h_cbit) = opval;
693 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
694 }
695 {
696 SI opval = tmp_tmp;
697 * FLD (i_Ri) = opval;
698 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
699 }
700 {
701 {
702 BI opval = EQSI (* FLD (i_Ri), 0);
703 CPU (h_zbit) = opval;
704 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
705 }
706 {
707 BI opval = LTSI (* FLD (i_Ri), 0);
708 CPU (h_nbit) = opval;
709 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
710 }
711 }
712 }
713
714 #undef FLD
715 }
716 NEXT (vpc);
717
718 CASE (sem, INSN_SUBN) : /* subn $Rj,$Ri */
719 {
720 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
721 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
722 #define FLD(f) abuf->fields.sfmt_add.f
723 int UNUSED written = 0;
724 IADDR UNUSED pc = abuf->addr;
725 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
726
727 {
728 SI opval = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
729 * FLD (i_Ri) = opval;
730 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
731 }
732
733 #undef FLD
734 }
735 NEXT (vpc);
736
737 CASE (sem, INSN_CMP) : /* cmp $Rj,$Ri */
738 {
739 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
740 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
741 #define FLD(f) abuf->fields.sfmt_str13.f
742 int UNUSED written = 0;
743 IADDR UNUSED pc = abuf->addr;
744 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
745
746 {
747 SI tmp_tmp1;
748 {
749 BI opval = SUBOFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
750 CPU (h_vbit) = opval;
751 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
752 }
753 {
754 BI opval = SUBCFSI (* FLD (i_Ri), * FLD (i_Rj), 0);
755 CPU (h_cbit) = opval;
756 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
757 }
758 tmp_tmp1 = SUBSI (* FLD (i_Ri), * FLD (i_Rj));
759 {
760 {
761 BI opval = EQSI (tmp_tmp1, 0);
762 CPU (h_zbit) = opval;
763 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
764 }
765 {
766 BI opval = LTSI (tmp_tmp1, 0);
767 CPU (h_nbit) = opval;
768 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
769 }
770 }
771 }
772
773 #undef FLD
774 }
775 NEXT (vpc);
776
777 CASE (sem, INSN_CMPI) : /* cmp $u4,$Ri */
778 {
779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
780 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
781 #define FLD(f) abuf->fields.sfmt_addi.f
782 int UNUSED written = 0;
783 IADDR UNUSED pc = abuf->addr;
784 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
785
786 {
787 SI tmp_tmp1;
788 {
789 BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_u4), 0);
790 CPU (h_vbit) = opval;
791 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
792 }
793 {
794 BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_u4), 0);
795 CPU (h_cbit) = opval;
796 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
797 }
798 tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_u4));
799 {
800 {
801 BI opval = EQSI (tmp_tmp1, 0);
802 CPU (h_zbit) = opval;
803 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
804 }
805 {
806 BI opval = LTSI (tmp_tmp1, 0);
807 CPU (h_nbit) = opval;
808 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
809 }
810 }
811 }
812
813 #undef FLD
814 }
815 NEXT (vpc);
816
817 CASE (sem, INSN_CMP2) : /* cmp2 $m4,$Ri */
818 {
819 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
820 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
821 #define FLD(f) abuf->fields.sfmt_add2.f
822 int UNUSED written = 0;
823 IADDR UNUSED pc = abuf->addr;
824 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
825
826 {
827 SI tmp_tmp1;
828 {
829 BI opval = SUBOFSI (* FLD (i_Ri), FLD (f_m4), 0);
830 CPU (h_vbit) = opval;
831 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
832 }
833 {
834 BI opval = SUBCFSI (* FLD (i_Ri), FLD (f_m4), 0);
835 CPU (h_cbit) = opval;
836 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
837 }
838 tmp_tmp1 = SUBSI (* FLD (i_Ri), FLD (f_m4));
839 {
840 {
841 BI opval = EQSI (tmp_tmp1, 0);
842 CPU (h_zbit) = opval;
843 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
844 }
845 {
846 BI opval = LTSI (tmp_tmp1, 0);
847 CPU (h_nbit) = opval;
848 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
849 }
850 }
851 }
852
853 #undef FLD
854 }
855 NEXT (vpc);
856
857 CASE (sem, INSN_AND) : /* and $Rj,$Ri */
858 {
859 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
860 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
861 #define FLD(f) abuf->fields.sfmt_add.f
862 int UNUSED written = 0;
863 IADDR UNUSED pc = abuf->addr;
864 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
865
866 {
867 {
868 SI opval = ANDSI (* FLD (i_Ri), * FLD (i_Rj));
869 * FLD (i_Ri) = opval;
870 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
871 }
872 {
873 {
874 BI opval = EQSI (* FLD (i_Ri), 0);
875 CPU (h_zbit) = opval;
876 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
877 }
878 {
879 BI opval = LTSI (* FLD (i_Ri), 0);
880 CPU (h_nbit) = opval;
881 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
882 }
883 }
884 }
885
886 #undef FLD
887 }
888 NEXT (vpc);
889
890 CASE (sem, INSN_OR) : /* or $Rj,$Ri */
891 {
892 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
893 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
894 #define FLD(f) abuf->fields.sfmt_add.f
895 int UNUSED written = 0;
896 IADDR UNUSED pc = abuf->addr;
897 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
898
899 {
900 {
901 SI opval = ORSI (* FLD (i_Ri), * FLD (i_Rj));
902 * FLD (i_Ri) = opval;
903 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
904 }
905 {
906 {
907 BI opval = EQSI (* FLD (i_Ri), 0);
908 CPU (h_zbit) = opval;
909 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
910 }
911 {
912 BI opval = LTSI (* FLD (i_Ri), 0);
913 CPU (h_nbit) = opval;
914 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
915 }
916 }
917 }
918
919 #undef FLD
920 }
921 NEXT (vpc);
922
923 CASE (sem, INSN_EOR) : /* eor $Rj,$Ri */
924 {
925 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
926 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
927 #define FLD(f) abuf->fields.sfmt_add.f
928 int UNUSED written = 0;
929 IADDR UNUSED pc = abuf->addr;
930 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
931
932 {
933 {
934 SI opval = XORSI (* FLD (i_Ri), * FLD (i_Rj));
935 * FLD (i_Ri) = opval;
936 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
937 }
938 {
939 {
940 BI opval = EQSI (* FLD (i_Ri), 0);
941 CPU (h_zbit) = opval;
942 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
943 }
944 {
945 BI opval = LTSI (* FLD (i_Ri), 0);
946 CPU (h_nbit) = opval;
947 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
948 }
949 }
950 }
951
952 #undef FLD
953 }
954 NEXT (vpc);
955
956 CASE (sem, INSN_ANDM) : /* and $Rj,@$Ri */
957 {
958 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
959 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
960 #define FLD(f) abuf->fields.sfmt_str13.f
961 int UNUSED written = 0;
962 IADDR UNUSED pc = abuf->addr;
963 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
964
965 {
966 SI tmp_tmp;
967 tmp_tmp = ANDSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
968 {
969 {
970 BI opval = EQSI (tmp_tmp, 0);
971 CPU (h_zbit) = opval;
972 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
973 }
974 {
975 BI opval = LTSI (tmp_tmp, 0);
976 CPU (h_nbit) = opval;
977 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
978 }
979 }
980 {
981 SI opval = tmp_tmp;
982 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
983 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
984 }
985 }
986
987 #undef FLD
988 }
989 NEXT (vpc);
990
991 CASE (sem, INSN_ANDH) : /* andh $Rj,@$Ri */
992 {
993 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
994 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
995 #define FLD(f) abuf->fields.sfmt_str13.f
996 int UNUSED written = 0;
997 IADDR UNUSED pc = abuf->addr;
998 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
999
1000 {
1001 HI tmp_tmp;
1002 tmp_tmp = ANDHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1003 {
1004 {
1005 BI opval = EQHI (tmp_tmp, 0);
1006 CPU (h_zbit) = opval;
1007 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1008 }
1009 {
1010 BI opval = LTHI (tmp_tmp, 0);
1011 CPU (h_nbit) = opval;
1012 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1013 }
1014 }
1015 {
1016 HI opval = tmp_tmp;
1017 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1018 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1019 }
1020 }
1021
1022 #undef FLD
1023 }
1024 NEXT (vpc);
1025
1026 CASE (sem, INSN_ANDB) : /* andb $Rj,@$Ri */
1027 {
1028 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1029 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1030 #define FLD(f) abuf->fields.sfmt_str13.f
1031 int UNUSED written = 0;
1032 IADDR UNUSED pc = abuf->addr;
1033 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1034
1035 {
1036 QI tmp_tmp;
1037 tmp_tmp = ANDQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1038 {
1039 {
1040 BI opval = EQQI (tmp_tmp, 0);
1041 CPU (h_zbit) = opval;
1042 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1043 }
1044 {
1045 BI opval = LTQI (tmp_tmp, 0);
1046 CPU (h_nbit) = opval;
1047 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1048 }
1049 }
1050 {
1051 QI opval = tmp_tmp;
1052 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1053 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1054 }
1055 }
1056
1057 #undef FLD
1058 }
1059 NEXT (vpc);
1060
1061 CASE (sem, INSN_ORM) : /* or $Rj,@$Ri */
1062 {
1063 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1064 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1065 #define FLD(f) abuf->fields.sfmt_str13.f
1066 int UNUSED written = 0;
1067 IADDR UNUSED pc = abuf->addr;
1068 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1069
1070 {
1071 SI tmp_tmp;
1072 tmp_tmp = ORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1073 {
1074 {
1075 BI opval = EQSI (tmp_tmp, 0);
1076 CPU (h_zbit) = opval;
1077 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1078 }
1079 {
1080 BI opval = LTSI (tmp_tmp, 0);
1081 CPU (h_nbit) = opval;
1082 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1083 }
1084 }
1085 {
1086 SI opval = tmp_tmp;
1087 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
1088 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1089 }
1090 }
1091
1092 #undef FLD
1093 }
1094 NEXT (vpc);
1095
1096 CASE (sem, INSN_ORH) : /* orh $Rj,@$Ri */
1097 {
1098 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1099 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1100 #define FLD(f) abuf->fields.sfmt_str13.f
1101 int UNUSED written = 0;
1102 IADDR UNUSED pc = abuf->addr;
1103 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1104
1105 {
1106 HI tmp_tmp;
1107 tmp_tmp = ORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1108 {
1109 {
1110 BI opval = EQHI (tmp_tmp, 0);
1111 CPU (h_zbit) = opval;
1112 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1113 }
1114 {
1115 BI opval = LTHI (tmp_tmp, 0);
1116 CPU (h_nbit) = opval;
1117 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1118 }
1119 }
1120 {
1121 HI opval = tmp_tmp;
1122 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1123 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1124 }
1125 }
1126
1127 #undef FLD
1128 }
1129 NEXT (vpc);
1130
1131 CASE (sem, INSN_ORB) : /* orb $Rj,@$Ri */
1132 {
1133 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1134 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1135 #define FLD(f) abuf->fields.sfmt_str13.f
1136 int UNUSED written = 0;
1137 IADDR UNUSED pc = abuf->addr;
1138 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1139
1140 {
1141 QI tmp_tmp;
1142 tmp_tmp = ORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1143 {
1144 {
1145 BI opval = EQQI (tmp_tmp, 0);
1146 CPU (h_zbit) = opval;
1147 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1148 }
1149 {
1150 BI opval = LTQI (tmp_tmp, 0);
1151 CPU (h_nbit) = opval;
1152 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1153 }
1154 }
1155 {
1156 QI opval = tmp_tmp;
1157 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1158 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1159 }
1160 }
1161
1162 #undef FLD
1163 }
1164 NEXT (vpc);
1165
1166 CASE (sem, INSN_EORM) : /* eor $Rj,@$Ri */
1167 {
1168 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1169 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1170 #define FLD(f) abuf->fields.sfmt_str13.f
1171 int UNUSED written = 0;
1172 IADDR UNUSED pc = abuf->addr;
1173 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1174
1175 {
1176 SI tmp_tmp;
1177 tmp_tmp = XORSI (GETMEMSI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1178 {
1179 {
1180 BI opval = EQSI (tmp_tmp, 0);
1181 CPU (h_zbit) = opval;
1182 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1183 }
1184 {
1185 BI opval = LTSI (tmp_tmp, 0);
1186 CPU (h_nbit) = opval;
1187 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1188 }
1189 }
1190 {
1191 SI opval = tmp_tmp;
1192 SETMEMSI (current_cpu, pc, * FLD (i_Ri), opval);
1193 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1194 }
1195 }
1196
1197 #undef FLD
1198 }
1199 NEXT (vpc);
1200
1201 CASE (sem, INSN_EORH) : /* eorh $Rj,@$Ri */
1202 {
1203 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1204 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1205 #define FLD(f) abuf->fields.sfmt_str13.f
1206 int UNUSED written = 0;
1207 IADDR UNUSED pc = abuf->addr;
1208 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1209
1210 {
1211 HI tmp_tmp;
1212 tmp_tmp = XORHI (GETMEMHI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1213 {
1214 {
1215 BI opval = EQHI (tmp_tmp, 0);
1216 CPU (h_zbit) = opval;
1217 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1218 }
1219 {
1220 BI opval = LTHI (tmp_tmp, 0);
1221 CPU (h_nbit) = opval;
1222 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1223 }
1224 }
1225 {
1226 HI opval = tmp_tmp;
1227 SETMEMHI (current_cpu, pc, * FLD (i_Ri), opval);
1228 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1229 }
1230 }
1231
1232 #undef FLD
1233 }
1234 NEXT (vpc);
1235
1236 CASE (sem, INSN_EORB) : /* eorb $Rj,@$Ri */
1237 {
1238 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1239 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1240 #define FLD(f) abuf->fields.sfmt_str13.f
1241 int UNUSED written = 0;
1242 IADDR UNUSED pc = abuf->addr;
1243 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1244
1245 {
1246 QI tmp_tmp;
1247 tmp_tmp = XORQI (GETMEMQI (current_cpu, pc, * FLD (i_Ri)), * FLD (i_Rj));
1248 {
1249 {
1250 BI opval = EQQI (tmp_tmp, 0);
1251 CPU (h_zbit) = opval;
1252 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1253 }
1254 {
1255 BI opval = LTQI (tmp_tmp, 0);
1256 CPU (h_nbit) = opval;
1257 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1258 }
1259 }
1260 {
1261 QI opval = tmp_tmp;
1262 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1263 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1264 }
1265 }
1266
1267 #undef FLD
1268 }
1269 NEXT (vpc);
1270
1271 CASE (sem, INSN_BANDL) : /* bandl $u4,@$Ri */
1272 {
1273 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1274 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1275 #define FLD(f) abuf->fields.sfmt_addi.f
1276 int UNUSED written = 0;
1277 IADDR UNUSED pc = abuf->addr;
1278 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1279
1280 {
1281 QI opval = ANDQI (ORQI (FLD (f_u4), 240), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1282 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1283 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1284 }
1285
1286 #undef FLD
1287 }
1288 NEXT (vpc);
1289
1290 CASE (sem, INSN_BORL) : /* borl $u4,@$Ri */
1291 {
1292 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1293 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1294 #define FLD(f) abuf->fields.sfmt_addi.f
1295 int UNUSED written = 0;
1296 IADDR UNUSED pc = abuf->addr;
1297 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1298
1299 {
1300 QI opval = ORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1301 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1302 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1303 }
1304
1305 #undef FLD
1306 }
1307 NEXT (vpc);
1308
1309 CASE (sem, INSN_BEORL) : /* beorl $u4,@$Ri */
1310 {
1311 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1312 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1313 #define FLD(f) abuf->fields.sfmt_addi.f
1314 int UNUSED written = 0;
1315 IADDR UNUSED pc = abuf->addr;
1316 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1317
1318 {
1319 QI opval = XORQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1320 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1321 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1322 }
1323
1324 #undef FLD
1325 }
1326 NEXT (vpc);
1327
1328 CASE (sem, INSN_BANDH) : /* bandh $u4,@$Ri */
1329 {
1330 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1331 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1332 #define FLD(f) abuf->fields.sfmt_addi.f
1333 int UNUSED written = 0;
1334 IADDR UNUSED pc = abuf->addr;
1335 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1336
1337 {
1338 QI opval = ANDQI (ORQI (SLLQI (FLD (f_u4), 4), 15), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1339 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1340 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1341 }
1342
1343 #undef FLD
1344 }
1345 NEXT (vpc);
1346
1347 CASE (sem, INSN_BORH) : /* borh $u4,@$Ri */
1348 {
1349 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1350 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1351 #define FLD(f) abuf->fields.sfmt_addi.f
1352 int UNUSED written = 0;
1353 IADDR UNUSED pc = abuf->addr;
1354 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1355
1356 {
1357 QI opval = ORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1358 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1359 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1360 }
1361
1362 #undef FLD
1363 }
1364 NEXT (vpc);
1365
1366 CASE (sem, INSN_BEORH) : /* beorh $u4,@$Ri */
1367 {
1368 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1369 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1370 #define FLD(f) abuf->fields.sfmt_addi.f
1371 int UNUSED written = 0;
1372 IADDR UNUSED pc = abuf->addr;
1373 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1374
1375 {
1376 QI opval = XORQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1377 SETMEMQI (current_cpu, pc, * FLD (i_Ri), opval);
1378 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
1379 }
1380
1381 #undef FLD
1382 }
1383 NEXT (vpc);
1384
1385 CASE (sem, INSN_BTSTL) : /* btstl $u4,@$Ri */
1386 {
1387 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1388 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1389 #define FLD(f) abuf->fields.sfmt_addi.f
1390 int UNUSED written = 0;
1391 IADDR UNUSED pc = abuf->addr;
1392 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1393
1394 {
1395 QI tmp_tmp;
1396 tmp_tmp = ANDQI (FLD (f_u4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1397 {
1398 BI opval = EQQI (tmp_tmp, 0);
1399 CPU (h_zbit) = opval;
1400 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1401 }
1402 {
1403 BI opval = 0;
1404 CPU (h_nbit) = opval;
1405 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1406 }
1407 }
1408
1409 #undef FLD
1410 }
1411 NEXT (vpc);
1412
1413 CASE (sem, INSN_BTSTH) : /* btsth $u4,@$Ri */
1414 {
1415 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1416 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1417 #define FLD(f) abuf->fields.sfmt_addi.f
1418 int UNUSED written = 0;
1419 IADDR UNUSED pc = abuf->addr;
1420 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1421
1422 {
1423 QI tmp_tmp;
1424 tmp_tmp = ANDQI (SLLQI (FLD (f_u4), 4), GETMEMQI (current_cpu, pc, * FLD (i_Ri)));
1425 {
1426 BI opval = EQQI (tmp_tmp, 0);
1427 CPU (h_zbit) = opval;
1428 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1429 }
1430 {
1431 BI opval = LTQI (tmp_tmp, 0);
1432 CPU (h_nbit) = opval;
1433 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1434 }
1435 }
1436
1437 #undef FLD
1438 }
1439 NEXT (vpc);
1440
1441 CASE (sem, INSN_MUL) : /* mul $Rj,$Ri */
1442 {
1443 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1444 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1445 #define FLD(f) abuf->fields.sfmt_str13.f
1446 int UNUSED written = 0;
1447 IADDR UNUSED pc = abuf->addr;
1448 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1449
1450 {
1451 DI tmp_tmp;
1452 tmp_tmp = MULDI (EXTSIDI (* FLD (i_Rj)), EXTSIDI (* FLD (i_Ri)));
1453 {
1454 SI opval = TRUNCDISI (tmp_tmp);
1455 SET_H_DR (((UINT) 5), opval);
1456 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1457 }
1458 {
1459 SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
1460 SET_H_DR (((UINT) 4), opval);
1461 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1462 }
1463 {
1464 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1465 CPU (h_nbit) = opval;
1466 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1467 }
1468 {
1469 BI opval = EQDI (tmp_tmp, MAKEDI (0, 0));
1470 CPU (h_zbit) = opval;
1471 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1472 }
1473 {
1474 BI opval = ORIF (GTDI (tmp_tmp, MAKEDI (0, 2147483647)), LTDI (tmp_tmp, NEGDI (MAKEDI (0, 0x80000000))));
1475 CPU (h_vbit) = opval;
1476 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1477 }
1478 }
1479
1480 #undef FLD
1481 }
1482 NEXT (vpc);
1483
1484 CASE (sem, INSN_MULU) : /* mulu $Rj,$Ri */
1485 {
1486 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1487 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1488 #define FLD(f) abuf->fields.sfmt_str13.f
1489 int UNUSED written = 0;
1490 IADDR UNUSED pc = abuf->addr;
1491 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1492
1493 {
1494 DI tmp_tmp;
1495 tmp_tmp = MULDI (ZEXTSIDI (* FLD (i_Rj)), ZEXTSIDI (* FLD (i_Ri)));
1496 {
1497 SI opval = TRUNCDISI (tmp_tmp);
1498 SET_H_DR (((UINT) 5), opval);
1499 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1500 }
1501 {
1502 SI opval = TRUNCDISI (SRLDI (tmp_tmp, 32));
1503 SET_H_DR (((UINT) 4), opval);
1504 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1505 }
1506 {
1507 BI opval = LTSI (GET_H_DR (((UINT) 4)), 0);
1508 CPU (h_nbit) = opval;
1509 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1510 }
1511 {
1512 BI opval = EQSI (GET_H_DR (((UINT) 5)), 0);
1513 CPU (h_zbit) = opval;
1514 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1515 }
1516 {
1517 BI opval = NESI (GET_H_DR (((UINT) 4)), 0);
1518 CPU (h_vbit) = opval;
1519 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval);
1520 }
1521 }
1522
1523 #undef FLD
1524 }
1525 NEXT (vpc);
1526
1527 CASE (sem, INSN_MULH) : /* mulh $Rj,$Ri */
1528 {
1529 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1530 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1531 #define FLD(f) abuf->fields.sfmt_str13.f
1532 int UNUSED written = 0;
1533 IADDR UNUSED pc = abuf->addr;
1534 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1535
1536 {
1537 {
1538 SI opval = MULHI (TRUNCSIHI (* FLD (i_Rj)), TRUNCSIHI (* FLD (i_Ri)));
1539 SET_H_DR (((UINT) 5), opval);
1540 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1541 }
1542 {
1543 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1544 CPU (h_nbit) = opval;
1545 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1546 }
1547 {
1548 BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
1549 CPU (h_zbit) = opval;
1550 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1551 }
1552 }
1553
1554 #undef FLD
1555 }
1556 NEXT (vpc);
1557
1558 CASE (sem, INSN_MULUH) : /* muluh $Rj,$Ri */
1559 {
1560 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1561 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1562 #define FLD(f) abuf->fields.sfmt_str13.f
1563 int UNUSED written = 0;
1564 IADDR UNUSED pc = abuf->addr;
1565 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1566
1567 {
1568 {
1569 SI opval = MULSI (ANDSI (* FLD (i_Rj), 65535), ANDSI (* FLD (i_Ri), 65535));
1570 SET_H_DR (((UINT) 5), opval);
1571 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1572 }
1573 {
1574 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1575 CPU (h_nbit) = opval;
1576 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1577 }
1578 {
1579 BI opval = GESI (GET_H_DR (((UINT) 5)), 0);
1580 CPU (h_zbit) = opval;
1581 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1582 }
1583 }
1584
1585 #undef FLD
1586 }
1587 NEXT (vpc);
1588
1589 CASE (sem, INSN_DIV0S) : /* div0s $Ri */
1590 {
1591 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1592 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1593 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1594 int UNUSED written = 0;
1595 IADDR UNUSED pc = abuf->addr;
1596 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1597
1598 {
1599 {
1600 BI opval = LTSI (GET_H_DR (((UINT) 5)), 0);
1601 CPU (h_d0bit) = opval;
1602 TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
1603 }
1604 {
1605 BI opval = XORBI (CPU (h_d0bit), LTSI (* FLD (i_Ri), 0));
1606 CPU (h_d1bit) = opval;
1607 TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
1608 }
1609 if (NEBI (CPU (h_d0bit), 0)) {
1610 {
1611 SI opval = 0xffffffff;
1612 SET_H_DR (((UINT) 4), opval);
1613 written |= (1 << 5);
1614 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1615 }
1616 } else {
1617 {
1618 SI opval = 0;
1619 SET_H_DR (((UINT) 4), opval);
1620 written |= (1 << 5);
1621 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1622 }
1623 }
1624 }
1625
1626 abuf->written = written;
1627 #undef FLD
1628 }
1629 NEXT (vpc);
1630
1631 CASE (sem, INSN_DIV0U) : /* div0u $Ri */
1632 {
1633 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1634 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1635 #define FLD(f) abuf->fields.fmt_empty.f
1636 int UNUSED written = 0;
1637 IADDR UNUSED pc = abuf->addr;
1638 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1639
1640 {
1641 {
1642 BI opval = 0;
1643 CPU (h_d0bit) = opval;
1644 TRACE_RESULT (current_cpu, abuf, "d0bit", 'x', opval);
1645 }
1646 {
1647 BI opval = 0;
1648 CPU (h_d1bit) = opval;
1649 TRACE_RESULT (current_cpu, abuf, "d1bit", 'x', opval);
1650 }
1651 {
1652 SI opval = 0;
1653 SET_H_DR (((UINT) 4), opval);
1654 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1655 }
1656 }
1657
1658 #undef FLD
1659 }
1660 NEXT (vpc);
1661
1662 CASE (sem, INSN_DIV1) : /* div1 $Ri */
1663 {
1664 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1665 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1666 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1667 int UNUSED written = 0;
1668 IADDR UNUSED pc = abuf->addr;
1669 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1670
1671 {
1672 SI tmp_tmp;
1673 {
1674 SI opval = SLLSI (GET_H_DR (((UINT) 4)), 1);
1675 SET_H_DR (((UINT) 4), opval);
1676 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1677 }
1678 if (LTSI (GET_H_DR (((UINT) 5)), 0)) {
1679 {
1680 SI opval = ADDSI (GET_H_DR (((UINT) 4)), 1);
1681 SET_H_DR (((UINT) 4), opval);
1682 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1683 }
1684 }
1685 {
1686 SI opval = SLLSI (GET_H_DR (((UINT) 5)), 1);
1687 SET_H_DR (((UINT) 5), opval);
1688 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1689 }
1690 if (EQBI (CPU (h_d1bit), 1)) {
1691 {
1692 tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1693 {
1694 BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1695 CPU (h_cbit) = opval;
1696 written |= (1 << 6);
1697 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1698 }
1699 }
1700 } else {
1701 {
1702 tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1703 {
1704 BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1705 CPU (h_cbit) = opval;
1706 written |= (1 << 6);
1707 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1708 }
1709 }
1710 }
1711 if (NOTBI (XORBI (XORBI (CPU (h_d0bit), CPU (h_d1bit)), CPU (h_cbit)))) {
1712 {
1713 {
1714 SI opval = tmp_tmp;
1715 SET_H_DR (((UINT) 4), opval);
1716 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1717 }
1718 {
1719 SI opval = ORSI (GET_H_DR (((UINT) 5)), 1);
1720 SET_H_DR (((UINT) 5), opval);
1721 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1722 }
1723 }
1724 }
1725 {
1726 BI opval = EQSI (GET_H_DR (((UINT) 4)), 0);
1727 CPU (h_zbit) = opval;
1728 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1729 }
1730 }
1731
1732 abuf->written = written;
1733 #undef FLD
1734 }
1735 NEXT (vpc);
1736
1737 CASE (sem, INSN_DIV2) : /* div2 $Ri */
1738 {
1739 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1740 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1741 #define FLD(f) abuf->fields.sfmt_mov2dr.f
1742 int UNUSED written = 0;
1743 IADDR UNUSED pc = abuf->addr;
1744 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1745
1746 {
1747 SI tmp_tmp;
1748 if (EQBI (CPU (h_d1bit), 1)) {
1749 {
1750 tmp_tmp = ADDSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1751 {
1752 BI opval = ADDCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1753 CPU (h_cbit) = opval;
1754 written |= (1 << 3);
1755 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1756 }
1757 }
1758 } else {
1759 {
1760 tmp_tmp = SUBSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri));
1761 {
1762 BI opval = SUBCFSI (GET_H_DR (((UINT) 4)), * FLD (i_Ri), 0);
1763 CPU (h_cbit) = opval;
1764 written |= (1 << 3);
1765 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1766 }
1767 }
1768 }
1769 if (EQSI (tmp_tmp, 0)) {
1770 {
1771 {
1772 BI opval = 1;
1773 CPU (h_zbit) = opval;
1774 written |= (1 << 5);
1775 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1776 }
1777 {
1778 SI opval = 0;
1779 SET_H_DR (((UINT) 4), opval);
1780 written |= (1 << 4);
1781 TRACE_RESULT (current_cpu, abuf, "dr-4", 'x', opval);
1782 }
1783 }
1784 } else {
1785 {
1786 BI opval = 0;
1787 CPU (h_zbit) = opval;
1788 written |= (1 << 5);
1789 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1790 }
1791 }
1792 }
1793
1794 abuf->written = written;
1795 #undef FLD
1796 }
1797 NEXT (vpc);
1798
1799 CASE (sem, INSN_DIV3) : /* div3 */
1800 {
1801 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1802 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1803 #define FLD(f) abuf->fields.fmt_empty.f
1804 int UNUSED written = 0;
1805 IADDR UNUSED pc = abuf->addr;
1806 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1807
1808 if (EQBI (CPU (h_zbit), 1)) {
1809 {
1810 SI opval = ADDSI (GET_H_DR (((UINT) 5)), 1);
1811 SET_H_DR (((UINT) 5), opval);
1812 written |= (1 << 2);
1813 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1814 }
1815 }
1816
1817 abuf->written = written;
1818 #undef FLD
1819 }
1820 NEXT (vpc);
1821
1822 CASE (sem, INSN_DIV4S) : /* div4s */
1823 {
1824 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1825 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1826 #define FLD(f) abuf->fields.fmt_empty.f
1827 int UNUSED written = 0;
1828 IADDR UNUSED pc = abuf->addr;
1829 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1830
1831 if (EQBI (CPU (h_d1bit), 1)) {
1832 {
1833 SI opval = NEGSI (GET_H_DR (((UINT) 5)));
1834 SET_H_DR (((UINT) 5), opval);
1835 written |= (1 << 2);
1836 TRACE_RESULT (current_cpu, abuf, "dr-5", 'x', opval);
1837 }
1838 }
1839
1840 abuf->written = written;
1841 #undef FLD
1842 }
1843 NEXT (vpc);
1844
1845 CASE (sem, INSN_LSL) : /* lsl $Rj,$Ri */
1846 {
1847 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1848 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1849 #define FLD(f) abuf->fields.sfmt_add.f
1850 int UNUSED written = 0;
1851 IADDR UNUSED pc = abuf->addr;
1852 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1853
1854 {
1855 SI tmp_shift;
1856 tmp_shift = ANDSI (* FLD (i_Rj), 31);
1857 if (NESI (tmp_shift, 0)) {
1858 {
1859 {
1860 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1861 CPU (h_cbit) = opval;
1862 written |= (1 << 3);
1863 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1864 }
1865 {
1866 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1867 * FLD (i_Ri) = opval;
1868 written |= (1 << 2);
1869 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
1870 }
1871 }
1872 } else {
1873 {
1874 BI opval = 0;
1875 CPU (h_cbit) = opval;
1876 written |= (1 << 3);
1877 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1878 }
1879 }
1880 {
1881 BI opval = LTSI (* FLD (i_Ri), 0);
1882 CPU (h_nbit) = opval;
1883 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1884 }
1885 {
1886 BI opval = EQSI (* FLD (i_Ri), 0);
1887 CPU (h_zbit) = opval;
1888 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1889 }
1890 }
1891
1892 abuf->written = written;
1893 #undef FLD
1894 }
1895 NEXT (vpc);
1896
1897 CASE (sem, INSN_LSLI) : /* lsl $u4,$Ri */
1898 {
1899 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1900 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1901 #define FLD(f) abuf->fields.sfmt_addi.f
1902 int UNUSED written = 0;
1903 IADDR UNUSED pc = abuf->addr;
1904 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1905
1906 {
1907 SI tmp_shift;
1908 tmp_shift = FLD (f_u4);
1909 if (NESI (tmp_shift, 0)) {
1910 {
1911 {
1912 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1913 CPU (h_cbit) = opval;
1914 written |= (1 << 3);
1915 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1916 }
1917 {
1918 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1919 * FLD (i_Ri) = opval;
1920 written |= (1 << 2);
1921 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
1922 }
1923 }
1924 } else {
1925 {
1926 BI opval = 0;
1927 CPU (h_cbit) = opval;
1928 written |= (1 << 3);
1929 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1930 }
1931 }
1932 {
1933 BI opval = LTSI (* FLD (i_Ri), 0);
1934 CPU (h_nbit) = opval;
1935 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1936 }
1937 {
1938 BI opval = EQSI (* FLD (i_Ri), 0);
1939 CPU (h_zbit) = opval;
1940 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1941 }
1942 }
1943
1944 abuf->written = written;
1945 #undef FLD
1946 }
1947 NEXT (vpc);
1948
1949 CASE (sem, INSN_LSL2) : /* lsl2 $u4,$Ri */
1950 {
1951 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
1952 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1953 #define FLD(f) abuf->fields.sfmt_addi.f
1954 int UNUSED written = 0;
1955 IADDR UNUSED pc = abuf->addr;
1956 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
1957
1958 {
1959 SI tmp_shift;
1960 tmp_shift = ADDSI (FLD (f_u4), 16);
1961 if (NESI (tmp_shift, 0)) {
1962 {
1963 {
1964 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (32, tmp_shift))), 0);
1965 CPU (h_cbit) = opval;
1966 written |= (1 << 3);
1967 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1968 }
1969 {
1970 SI opval = SLLSI (* FLD (i_Ri), tmp_shift);
1971 * FLD (i_Ri) = opval;
1972 written |= (1 << 2);
1973 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
1974 }
1975 }
1976 } else {
1977 {
1978 BI opval = 0;
1979 CPU (h_cbit) = opval;
1980 written |= (1 << 3);
1981 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
1982 }
1983 }
1984 {
1985 BI opval = LTSI (* FLD (i_Ri), 0);
1986 CPU (h_nbit) = opval;
1987 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
1988 }
1989 {
1990 BI opval = EQSI (* FLD (i_Ri), 0);
1991 CPU (h_zbit) = opval;
1992 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
1993 }
1994 }
1995
1996 abuf->written = written;
1997 #undef FLD
1998 }
1999 NEXT (vpc);
2000
2001 CASE (sem, INSN_LSR) : /* lsr $Rj,$Ri */
2002 {
2003 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2004 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2005 #define FLD(f) abuf->fields.sfmt_add.f
2006 int UNUSED written = 0;
2007 IADDR UNUSED pc = abuf->addr;
2008 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2009
2010 {
2011 SI tmp_shift;
2012 tmp_shift = ANDSI (* FLD (i_Rj), 31);
2013 if (NESI (tmp_shift, 0)) {
2014 {
2015 {
2016 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2017 CPU (h_cbit) = opval;
2018 written |= (1 << 3);
2019 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2020 }
2021 {
2022 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2023 * FLD (i_Ri) = opval;
2024 written |= (1 << 2);
2025 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2026 }
2027 }
2028 } else {
2029 {
2030 BI opval = 0;
2031 CPU (h_cbit) = opval;
2032 written |= (1 << 3);
2033 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2034 }
2035 }
2036 {
2037 BI opval = LTSI (* FLD (i_Ri), 0);
2038 CPU (h_nbit) = opval;
2039 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2040 }
2041 {
2042 BI opval = EQSI (* FLD (i_Ri), 0);
2043 CPU (h_zbit) = opval;
2044 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2045 }
2046 }
2047
2048 abuf->written = written;
2049 #undef FLD
2050 }
2051 NEXT (vpc);
2052
2053 CASE (sem, INSN_LSRI) : /* lsr $u4,$Ri */
2054 {
2055 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2056 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2057 #define FLD(f) abuf->fields.sfmt_addi.f
2058 int UNUSED written = 0;
2059 IADDR UNUSED pc = abuf->addr;
2060 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2061
2062 {
2063 SI tmp_shift;
2064 tmp_shift = FLD (f_u4);
2065 if (NESI (tmp_shift, 0)) {
2066 {
2067 {
2068 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2069 CPU (h_cbit) = opval;
2070 written |= (1 << 3);
2071 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2072 }
2073 {
2074 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2075 * FLD (i_Ri) = opval;
2076 written |= (1 << 2);
2077 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2078 }
2079 }
2080 } else {
2081 {
2082 BI opval = 0;
2083 CPU (h_cbit) = opval;
2084 written |= (1 << 3);
2085 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2086 }
2087 }
2088 {
2089 BI opval = LTSI (* FLD (i_Ri), 0);
2090 CPU (h_nbit) = opval;
2091 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2092 }
2093 {
2094 BI opval = EQSI (* FLD (i_Ri), 0);
2095 CPU (h_zbit) = opval;
2096 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2097 }
2098 }
2099
2100 abuf->written = written;
2101 #undef FLD
2102 }
2103 NEXT (vpc);
2104
2105 CASE (sem, INSN_LSR2) : /* lsr2 $u4,$Ri */
2106 {
2107 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2108 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2109 #define FLD(f) abuf->fields.sfmt_addi.f
2110 int UNUSED written = 0;
2111 IADDR UNUSED pc = abuf->addr;
2112 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2113
2114 {
2115 SI tmp_shift;
2116 tmp_shift = ADDSI (FLD (f_u4), 16);
2117 if (NESI (tmp_shift, 0)) {
2118 {
2119 {
2120 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2121 CPU (h_cbit) = opval;
2122 written |= (1 << 3);
2123 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2124 }
2125 {
2126 SI opval = SRLSI (* FLD (i_Ri), tmp_shift);
2127 * FLD (i_Ri) = opval;
2128 written |= (1 << 2);
2129 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2130 }
2131 }
2132 } else {
2133 {
2134 BI opval = 0;
2135 CPU (h_cbit) = opval;
2136 written |= (1 << 3);
2137 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2138 }
2139 }
2140 {
2141 BI opval = LTSI (* FLD (i_Ri), 0);
2142 CPU (h_nbit) = opval;
2143 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2144 }
2145 {
2146 BI opval = EQSI (* FLD (i_Ri), 0);
2147 CPU (h_zbit) = opval;
2148 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2149 }
2150 }
2151
2152 abuf->written = written;
2153 #undef FLD
2154 }
2155 NEXT (vpc);
2156
2157 CASE (sem, INSN_ASR) : /* asr $Rj,$Ri */
2158 {
2159 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2160 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2161 #define FLD(f) abuf->fields.sfmt_add.f
2162 int UNUSED written = 0;
2163 IADDR UNUSED pc = abuf->addr;
2164 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2165
2166 {
2167 SI tmp_shift;
2168 tmp_shift = ANDSI (* FLD (i_Rj), 31);
2169 if (NESI (tmp_shift, 0)) {
2170 {
2171 {
2172 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2173 CPU (h_cbit) = opval;
2174 written |= (1 << 3);
2175 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2176 }
2177 {
2178 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2179 * FLD (i_Ri) = opval;
2180 written |= (1 << 2);
2181 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2182 }
2183 }
2184 } else {
2185 {
2186 BI opval = 0;
2187 CPU (h_cbit) = opval;
2188 written |= (1 << 3);
2189 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2190 }
2191 }
2192 {
2193 BI opval = LTSI (* FLD (i_Ri), 0);
2194 CPU (h_nbit) = opval;
2195 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2196 }
2197 {
2198 BI opval = EQSI (* FLD (i_Ri), 0);
2199 CPU (h_zbit) = opval;
2200 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2201 }
2202 }
2203
2204 abuf->written = written;
2205 #undef FLD
2206 }
2207 NEXT (vpc);
2208
2209 CASE (sem, INSN_ASRI) : /* asr $u4,$Ri */
2210 {
2211 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2212 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2213 #define FLD(f) abuf->fields.sfmt_addi.f
2214 int UNUSED written = 0;
2215 IADDR UNUSED pc = abuf->addr;
2216 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2217
2218 {
2219 SI tmp_shift;
2220 tmp_shift = FLD (f_u4);
2221 if (NESI (tmp_shift, 0)) {
2222 {
2223 {
2224 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2225 CPU (h_cbit) = opval;
2226 written |= (1 << 3);
2227 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2228 }
2229 {
2230 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2231 * FLD (i_Ri) = opval;
2232 written |= (1 << 2);
2233 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2234 }
2235 }
2236 } else {
2237 {
2238 BI opval = 0;
2239 CPU (h_cbit) = opval;
2240 written |= (1 << 3);
2241 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2242 }
2243 }
2244 {
2245 BI opval = LTSI (* FLD (i_Ri), 0);
2246 CPU (h_nbit) = opval;
2247 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2248 }
2249 {
2250 BI opval = EQSI (* FLD (i_Ri), 0);
2251 CPU (h_zbit) = opval;
2252 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2253 }
2254 }
2255
2256 abuf->written = written;
2257 #undef FLD
2258 }
2259 NEXT (vpc);
2260
2261 CASE (sem, INSN_ASR2) : /* asr2 $u4,$Ri */
2262 {
2263 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2264 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2265 #define FLD(f) abuf->fields.sfmt_addi.f
2266 int UNUSED written = 0;
2267 IADDR UNUSED pc = abuf->addr;
2268 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2269
2270 {
2271 SI tmp_shift;
2272 tmp_shift = ADDSI (FLD (f_u4), 16);
2273 if (NESI (tmp_shift, 0)) {
2274 {
2275 {
2276 BI opval = NESI (ANDSI (* FLD (i_Ri), SLLSI (1, SUBSI (tmp_shift, 1))), 0);
2277 CPU (h_cbit) = opval;
2278 written |= (1 << 3);
2279 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2280 }
2281 {
2282 SI opval = SRASI (* FLD (i_Ri), tmp_shift);
2283 * FLD (i_Ri) = opval;
2284 written |= (1 << 2);
2285 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2286 }
2287 }
2288 } else {
2289 {
2290 BI opval = 0;
2291 CPU (h_cbit) = opval;
2292 written |= (1 << 3);
2293 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval);
2294 }
2295 }
2296 {
2297 BI opval = LTSI (* FLD (i_Ri), 0);
2298 CPU (h_nbit) = opval;
2299 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval);
2300 }
2301 {
2302 BI opval = EQSI (* FLD (i_Ri), 0);
2303 CPU (h_zbit) = opval;
2304 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval);
2305 }
2306 }
2307
2308 abuf->written = written;
2309 #undef FLD
2310 }
2311 NEXT (vpc);
2312
2313 CASE (sem, INSN_LDI8) : /* ldi:8 $i8,$Ri */
2314 {
2315 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2316 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2317 #define FLD(f) abuf->fields.sfmt_ldi8.f
2318 int UNUSED written = 0;
2319 IADDR UNUSED pc = abuf->addr;
2320 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2321
2322 {
2323 SI opval = FLD (f_i8);
2324 * FLD (i_Ri) = opval;
2325 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2326 }
2327
2328 #undef FLD
2329 }
2330 NEXT (vpc);
2331
2332 CASE (sem, INSN_LDI20) : /* ldi:20 $i20,$Ri */
2333 {
2334 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2335 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2336 #define FLD(f) abuf->fields.sfmt_ldi20.f
2337 int UNUSED written = 0;
2338 IADDR UNUSED pc = abuf->addr;
2339 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
2340
2341 {
2342 SI opval = FLD (f_i20);
2343 * FLD (i_Ri) = opval;
2344 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2345 }
2346
2347 #undef FLD
2348 }
2349 NEXT (vpc);
2350
2351 CASE (sem, INSN_LDI32) : /* ldi:32 $i32,$Ri */
2352 {
2353 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2354 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2355 #define FLD(f) abuf->fields.sfmt_ldi32.f
2356 int UNUSED written = 0;
2357 IADDR UNUSED pc = abuf->addr;
2358 vpc = SEM_NEXT_VPC (sem_arg, pc, 6);
2359
2360 {
2361 SI opval = FLD (f_i32);
2362 * FLD (i_Ri) = opval;
2363 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2364 }
2365
2366 #undef FLD
2367 }
2368 NEXT (vpc);
2369
2370 CASE (sem, INSN_LD) : /* ld @$Rj,$Ri */
2371 {
2372 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2373 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2374 #define FLD(f) abuf->fields.sfmt_ldr13.f
2375 int UNUSED written = 0;
2376 IADDR UNUSED pc = abuf->addr;
2377 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2378
2379 {
2380 SI opval = GETMEMSI (current_cpu, pc, * FLD (i_Rj));
2381 * FLD (i_Ri) = opval;
2382 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2383 }
2384
2385 #undef FLD
2386 }
2387 NEXT (vpc);
2388
2389 CASE (sem, INSN_LDUH) : /* lduh @$Rj,$Ri */
2390 {
2391 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2392 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2393 #define FLD(f) abuf->fields.sfmt_ldr13.f
2394 int UNUSED written = 0;
2395 IADDR UNUSED pc = abuf->addr;
2396 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2397
2398 {
2399 SI opval = GETMEMUHI (current_cpu, pc, * FLD (i_Rj));
2400 * FLD (i_Ri) = opval;
2401 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2402 }
2403
2404 #undef FLD
2405 }
2406 NEXT (vpc);
2407
2408 CASE (sem, INSN_LDUB) : /* ldub @$Rj,$Ri */
2409 {
2410 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2411 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2412 #define FLD(f) abuf->fields.sfmt_ldr13.f
2413 int UNUSED written = 0;
2414 IADDR UNUSED pc = abuf->addr;
2415 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2416
2417 {
2418 SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
2419 * FLD (i_Ri) = opval;
2420 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2421 }
2422
2423 #undef FLD
2424 }
2425 NEXT (vpc);
2426
2427 CASE (sem, INSN_LDR13) : /* ld @($R13,$Rj),$Ri */
2428 {
2429 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2430 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2431 #define FLD(f) abuf->fields.sfmt_ldr13.f
2432 int UNUSED written = 0;
2433 IADDR UNUSED pc = abuf->addr;
2434 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2435
2436 {
2437 SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2438 * FLD (i_Ri) = opval;
2439 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2440 }
2441
2442 #undef FLD
2443 }
2444 NEXT (vpc);
2445
2446 CASE (sem, INSN_LDR13UH) : /* lduh @($R13,$Rj),$Ri */
2447 {
2448 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2449 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2450 #define FLD(f) abuf->fields.sfmt_ldr13.f
2451 int UNUSED written = 0;
2452 IADDR UNUSED pc = abuf->addr;
2453 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2454
2455 {
2456 SI opval = GETMEMUHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2457 * FLD (i_Ri) = opval;
2458 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2459 }
2460
2461 #undef FLD
2462 }
2463 NEXT (vpc);
2464
2465 CASE (sem, INSN_LDR13UB) : /* ldub @($R13,$Rj),$Ri */
2466 {
2467 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2468 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2469 #define FLD(f) abuf->fields.sfmt_ldr13.f
2470 int UNUSED written = 0;
2471 IADDR UNUSED pc = abuf->addr;
2472 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2473
2474 {
2475 SI opval = GETMEMUQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])));
2476 * FLD (i_Ri) = opval;
2477 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2478 }
2479
2480 #undef FLD
2481 }
2482 NEXT (vpc);
2483
2484 CASE (sem, INSN_LDR14) : /* ld @($R14,$disp10),$Ri */
2485 {
2486 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2487 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2488 #define FLD(f) abuf->fields.sfmt_ldr14.f
2489 int UNUSED written = 0;
2490 IADDR UNUSED pc = abuf->addr;
2491 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2492
2493 {
2494 SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])));
2495 * FLD (i_Ri) = opval;
2496 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2497 }
2498
2499 #undef FLD
2500 }
2501 NEXT (vpc);
2502
2503 CASE (sem, INSN_LDR14UH) : /* lduh @($R14,$disp9),$Ri */
2504 {
2505 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2506 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2507 #define FLD(f) abuf->fields.sfmt_ldr14uh.f
2508 int UNUSED written = 0;
2509 IADDR UNUSED pc = abuf->addr;
2510 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2511
2512 {
2513 SI opval = GETMEMUHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])));
2514 * FLD (i_Ri) = opval;
2515 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2516 }
2517
2518 #undef FLD
2519 }
2520 NEXT (vpc);
2521
2522 CASE (sem, INSN_LDR14UB) : /* ldub @($R14,$disp8),$Ri */
2523 {
2524 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2525 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2526 #define FLD(f) abuf->fields.sfmt_ldr14ub.f
2527 int UNUSED written = 0;
2528 IADDR UNUSED pc = abuf->addr;
2529 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2530
2531 {
2532 SI opval = GETMEMUQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])));
2533 * FLD (i_Ri) = opval;
2534 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2535 }
2536
2537 #undef FLD
2538 }
2539 NEXT (vpc);
2540
2541 CASE (sem, INSN_LDR15) : /* ld @($R15,$udisp6),$Ri */
2542 {
2543 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2544 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2545 #define FLD(f) abuf->fields.sfmt_ldr15.f
2546 int UNUSED written = 0;
2547 IADDR UNUSED pc = abuf->addr;
2548 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2549
2550 {
2551 SI opval = GETMEMSI (current_cpu, pc, ADDSI (FLD (f_udisp6), CPU (h_gr[((UINT) 15)])));
2552 * FLD (i_Ri) = opval;
2553 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2554 }
2555
2556 #undef FLD
2557 }
2558 NEXT (vpc);
2559
2560 CASE (sem, INSN_LDR15GR) : /* ld @$R15+,$Ri */
2561 {
2562 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2563 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2564 #define FLD(f) abuf->fields.sfmt_ldr15gr.f
2565 int UNUSED written = 0;
2566 IADDR UNUSED pc = abuf->addr;
2567 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2568
2569 {
2570 {
2571 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2572 * FLD (i_Ri) = opval;
2573 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2574 }
2575 if (NESI (FLD (f_Ri), 15)) {
2576 {
2577 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2578 CPU (h_gr[((UINT) 15)]) = opval;
2579 written |= (1 << 4);
2580 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2581 }
2582 }
2583 }
2584
2585 abuf->written = written;
2586 #undef FLD
2587 }
2588 NEXT (vpc);
2589
2590 CASE (sem, INSN_LDR15DR) : /* ld @$R15+,$Rs2 */
2591 {
2592 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2593 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2594 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
2595 int UNUSED written = 0;
2596 IADDR UNUSED pc = abuf->addr;
2597 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2598
2599 {
2600 SI tmp_tmp;
2601 tmp_tmp = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2602 {
2603 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2604 CPU (h_gr[((UINT) 15)]) = opval;
2605 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2606 }
2607 {
2608 SI opval = tmp_tmp;
2609 SET_H_DR (FLD (f_Rs2), opval);
2610 TRACE_RESULT (current_cpu, abuf, "Rs2", 'x', opval);
2611 }
2612 }
2613
2614 #undef FLD
2615 }
2616 NEXT (vpc);
2617
2618 CASE (sem, INSN_LDR15PS) : /* ld @$R15+,$ps */
2619 {
2620 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2621 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2622 #define FLD(f) abuf->fields.sfmt_addsp.f
2623 int UNUSED written = 0;
2624 IADDR UNUSED pc = abuf->addr;
2625 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2626
2627 {
2628 {
2629 USI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
2630 SET_H_PS (opval);
2631 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
2632 }
2633 {
2634 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
2635 CPU (h_gr[((UINT) 15)]) = opval;
2636 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2637 }
2638 }
2639
2640 #undef FLD
2641 }
2642 NEXT (vpc);
2643
2644 CASE (sem, INSN_ST) : /* st $Ri,@$Rj */
2645 {
2646 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2647 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2648 #define FLD(f) abuf->fields.sfmt_str13.f
2649 int UNUSED written = 0;
2650 IADDR UNUSED pc = abuf->addr;
2651 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2652
2653 {
2654 SI opval = * FLD (i_Ri);
2655 SETMEMSI (current_cpu, pc, * FLD (i_Rj), opval);
2656 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2657 }
2658
2659 #undef FLD
2660 }
2661 NEXT (vpc);
2662
2663 CASE (sem, INSN_STH) : /* sth $Ri,@$Rj */
2664 {
2665 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2666 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2667 #define FLD(f) abuf->fields.sfmt_str13.f
2668 int UNUSED written = 0;
2669 IADDR UNUSED pc = abuf->addr;
2670 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2671
2672 {
2673 HI opval = * FLD (i_Ri);
2674 SETMEMHI (current_cpu, pc, * FLD (i_Rj), opval);
2675 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2676 }
2677
2678 #undef FLD
2679 }
2680 NEXT (vpc);
2681
2682 CASE (sem, INSN_STB) : /* stb $Ri,@$Rj */
2683 {
2684 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2685 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2686 #define FLD(f) abuf->fields.sfmt_str13.f
2687 int UNUSED written = 0;
2688 IADDR UNUSED pc = abuf->addr;
2689 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2690
2691 {
2692 QI opval = * FLD (i_Ri);
2693 SETMEMQI (current_cpu, pc, * FLD (i_Rj), opval);
2694 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2695 }
2696
2697 #undef FLD
2698 }
2699 NEXT (vpc);
2700
2701 CASE (sem, INSN_STR13) : /* st $Ri,@($R13,$Rj) */
2702 {
2703 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2704 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2705 #define FLD(f) abuf->fields.sfmt_str13.f
2706 int UNUSED written = 0;
2707 IADDR UNUSED pc = abuf->addr;
2708 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2709
2710 {
2711 SI opval = * FLD (i_Ri);
2712 SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2713 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2714 }
2715
2716 #undef FLD
2717 }
2718 NEXT (vpc);
2719
2720 CASE (sem, INSN_STR13H) : /* sth $Ri,@($R13,$Rj) */
2721 {
2722 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2723 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2724 #define FLD(f) abuf->fields.sfmt_str13.f
2725 int UNUSED written = 0;
2726 IADDR UNUSED pc = abuf->addr;
2727 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2728
2729 {
2730 HI opval = * FLD (i_Ri);
2731 SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2732 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2733 }
2734
2735 #undef FLD
2736 }
2737 NEXT (vpc);
2738
2739 CASE (sem, INSN_STR13B) : /* stb $Ri,@($R13,$Rj) */
2740 {
2741 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2742 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2743 #define FLD(f) abuf->fields.sfmt_str13.f
2744 int UNUSED written = 0;
2745 IADDR UNUSED pc = abuf->addr;
2746 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2747
2748 {
2749 QI opval = * FLD (i_Ri);
2750 SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_Rj), CPU (h_gr[((UINT) 13)])), opval);
2751 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2752 }
2753
2754 #undef FLD
2755 }
2756 NEXT (vpc);
2757
2758 CASE (sem, INSN_STR14) : /* st $Ri,@($R14,$disp10) */
2759 {
2760 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2761 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2762 #define FLD(f) abuf->fields.sfmt_str14.f
2763 int UNUSED written = 0;
2764 IADDR UNUSED pc = abuf->addr;
2765 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2766
2767 {
2768 SI opval = * FLD (i_Ri);
2769 SETMEMSI (current_cpu, pc, ADDSI (FLD (f_disp10), CPU (h_gr[((UINT) 14)])), opval);
2770 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2771 }
2772
2773 #undef FLD
2774 }
2775 NEXT (vpc);
2776
2777 CASE (sem, INSN_STR14H) : /* sth $Ri,@($R14,$disp9) */
2778 {
2779 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2780 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2781 #define FLD(f) abuf->fields.sfmt_str14h.f
2782 int UNUSED written = 0;
2783 IADDR UNUSED pc = abuf->addr;
2784 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2785
2786 {
2787 HI opval = * FLD (i_Ri);
2788 SETMEMHI (current_cpu, pc, ADDSI (FLD (f_disp9), CPU (h_gr[((UINT) 14)])), opval);
2789 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2790 }
2791
2792 #undef FLD
2793 }
2794 NEXT (vpc);
2795
2796 CASE (sem, INSN_STR14B) : /* stb $Ri,@($R14,$disp8) */
2797 {
2798 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2799 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2800 #define FLD(f) abuf->fields.sfmt_str14b.f
2801 int UNUSED written = 0;
2802 IADDR UNUSED pc = abuf->addr;
2803 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2804
2805 {
2806 QI opval = * FLD (i_Ri);
2807 SETMEMQI (current_cpu, pc, ADDSI (FLD (f_disp8), CPU (h_gr[((UINT) 14)])), opval);
2808 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2809 }
2810
2811 #undef FLD
2812 }
2813 NEXT (vpc);
2814
2815 CASE (sem, INSN_STR15) : /* st $Ri,@($R15,$udisp6) */
2816 {
2817 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2818 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2819 #define FLD(f) abuf->fields.sfmt_str15.f
2820 int UNUSED written = 0;
2821 IADDR UNUSED pc = abuf->addr;
2822 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2823
2824 {
2825 SI opval = * FLD (i_Ri);
2826 SETMEMSI (current_cpu, pc, ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_udisp6)), opval);
2827 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2828 }
2829
2830 #undef FLD
2831 }
2832 NEXT (vpc);
2833
2834 CASE (sem, INSN_STR15GR) : /* st $Ri,@-$R15 */
2835 {
2836 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2837 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2838 #define FLD(f) abuf->fields.sfmt_str15gr.f
2839 int UNUSED written = 0;
2840 IADDR UNUSED pc = abuf->addr;
2841 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2842
2843 {
2844 SI tmp_tmp;
2845 tmp_tmp = * FLD (i_Ri);
2846 {
2847 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2848 CPU (h_gr[((UINT) 15)]) = opval;
2849 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2850 }
2851 {
2852 SI opval = tmp_tmp;
2853 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2854 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2855 }
2856 }
2857
2858 #undef FLD
2859 }
2860 NEXT (vpc);
2861
2862 CASE (sem, INSN_STR15DR) : /* st $Rs2,@-$R15 */
2863 {
2864 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2865 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2866 #define FLD(f) abuf->fields.sfmt_ldr15dr.f
2867 int UNUSED written = 0;
2868 IADDR UNUSED pc = abuf->addr;
2869 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2870
2871 {
2872 SI tmp_tmp;
2873 tmp_tmp = GET_H_DR (FLD (f_Rs2));
2874 {
2875 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2876 CPU (h_gr[((UINT) 15)]) = opval;
2877 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2878 }
2879 {
2880 SI opval = tmp_tmp;
2881 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2882 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2883 }
2884 }
2885
2886 #undef FLD
2887 }
2888 NEXT (vpc);
2889
2890 CASE (sem, INSN_STR15PS) : /* st $ps,@-$R15 */
2891 {
2892 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2893 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2894 #define FLD(f) abuf->fields.sfmt_addsp.f
2895 int UNUSED written = 0;
2896 IADDR UNUSED pc = abuf->addr;
2897 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2898
2899 {
2900 {
2901 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
2902 CPU (h_gr[((UINT) 15)]) = opval;
2903 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
2904 }
2905 {
2906 SI opval = GET_H_PS ();
2907 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
2908 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
2909 }
2910 }
2911
2912 #undef FLD
2913 }
2914 NEXT (vpc);
2915
2916 CASE (sem, INSN_MOV) : /* mov $Rj,$Ri */
2917 {
2918 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2919 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2920 #define FLD(f) abuf->fields.sfmt_ldr13.f
2921 int UNUSED written = 0;
2922 IADDR UNUSED pc = abuf->addr;
2923 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2924
2925 {
2926 SI opval = * FLD (i_Rj);
2927 * FLD (i_Ri) = opval;
2928 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2929 }
2930
2931 #undef FLD
2932 }
2933 NEXT (vpc);
2934
2935 CASE (sem, INSN_MOVDR) : /* mov $Rs1,$Ri */
2936 {
2937 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2938 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2939 #define FLD(f) abuf->fields.sfmt_movdr.f
2940 int UNUSED written = 0;
2941 IADDR UNUSED pc = abuf->addr;
2942 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2943
2944 {
2945 SI opval = GET_H_DR (FLD (f_Rs1));
2946 * FLD (i_Ri) = opval;
2947 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2948 }
2949
2950 #undef FLD
2951 }
2952 NEXT (vpc);
2953
2954 CASE (sem, INSN_MOVPS) : /* mov $ps,$Ri */
2955 {
2956 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2957 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2958 #define FLD(f) abuf->fields.sfmt_movdr.f
2959 int UNUSED written = 0;
2960 IADDR UNUSED pc = abuf->addr;
2961 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2962
2963 {
2964 SI opval = GET_H_PS ();
2965 * FLD (i_Ri) = opval;
2966 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
2967 }
2968
2969 #undef FLD
2970 }
2971 NEXT (vpc);
2972
2973 CASE (sem, INSN_MOV2DR) : /* mov $Ri,$Rs1 */
2974 {
2975 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2976 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2977 #define FLD(f) abuf->fields.sfmt_mov2dr.f
2978 int UNUSED written = 0;
2979 IADDR UNUSED pc = abuf->addr;
2980 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
2981
2982 {
2983 SI opval = * FLD (i_Ri);
2984 SET_H_DR (FLD (f_Rs1), opval);
2985 TRACE_RESULT (current_cpu, abuf, "Rs1", 'x', opval);
2986 }
2987
2988 #undef FLD
2989 }
2990 NEXT (vpc);
2991
2992 CASE (sem, INSN_MOV2PS) : /* mov $Ri,$ps */
2993 {
2994 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
2995 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2996 #define FLD(f) abuf->fields.sfmt_mov2dr.f
2997 int UNUSED written = 0;
2998 IADDR UNUSED pc = abuf->addr;
2999 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3000
3001 {
3002 USI opval = * FLD (i_Ri);
3003 SET_H_PS (opval);
3004 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3005 }
3006
3007 #undef FLD
3008 }
3009 NEXT (vpc);
3010
3011 CASE (sem, INSN_JMP) : /* jmp @$Ri */
3012 {
3013 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3014 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3015 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3016 int UNUSED written = 0;
3017 IADDR UNUSED pc = abuf->addr;
3018 SEM_BRANCH_INIT
3019 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3020
3021 {
3022 USI opval = * FLD (i_Ri);
3023 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3024 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3025 }
3026
3027 SEM_BRANCH_FINI (vpc);
3028 #undef FLD
3029 }
3030 NEXT (vpc);
3031
3032 CASE (sem, INSN_JMPD) : /* jmp:d @$Ri */
3033 {
3034 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3035 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3036 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3037 int UNUSED written = 0;
3038 IADDR UNUSED pc = abuf->addr;
3039 SEM_BRANCH_INIT
3040 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3041
3042 {
3043 {
3044 USI opval = * FLD (i_Ri);
3045 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3046 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3047 }
3048 }
3049
3050 SEM_BRANCH_FINI (vpc);
3051 #undef FLD
3052 }
3053 NEXT (vpc);
3054
3055 CASE (sem, INSN_CALLR) : /* call @$Ri */
3056 {
3057 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3058 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3059 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3060 int UNUSED written = 0;
3061 IADDR UNUSED pc = abuf->addr;
3062 SEM_BRANCH_INIT
3063 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3064
3065 {
3066 {
3067 SI opval = ADDSI (pc, 2);
3068 SET_H_DR (((UINT) 1), opval);
3069 TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
3070 }
3071 {
3072 USI opval = * FLD (i_Ri);
3073 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3074 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3075 }
3076 }
3077
3078 SEM_BRANCH_FINI (vpc);
3079 #undef FLD
3080 }
3081 NEXT (vpc);
3082
3083 CASE (sem, INSN_CALLRD) : /* call:d @$Ri */
3084 {
3085 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3086 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3087 #define FLD(f) abuf->fields.sfmt_mov2dr.f
3088 int UNUSED written = 0;
3089 IADDR UNUSED pc = abuf->addr;
3090 SEM_BRANCH_INIT
3091 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3092
3093 {
3094 {
3095 {
3096 SI opval = ADDSI (pc, 4);
3097 SET_H_DR (((UINT) 1), opval);
3098 TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
3099 }
3100 {
3101 USI opval = * FLD (i_Ri);
3102 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3103 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3104 }
3105 }
3106 }
3107
3108 SEM_BRANCH_FINI (vpc);
3109 #undef FLD
3110 }
3111 NEXT (vpc);
3112
3113 CASE (sem, INSN_CALL) : /* call $label12 */
3114 {
3115 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3116 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3117 #define FLD(f) abuf->fields.sfmt_call.f
3118 int UNUSED written = 0;
3119 IADDR UNUSED pc = abuf->addr;
3120 SEM_BRANCH_INIT
3121 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3122
3123 {
3124 {
3125 SI opval = ADDSI (pc, 2);
3126 SET_H_DR (((UINT) 1), opval);
3127 TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
3128 }
3129 {
3130 USI opval = FLD (i_label12);
3131 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3132 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3133 }
3134 }
3135
3136 SEM_BRANCH_FINI (vpc);
3137 #undef FLD
3138 }
3139 NEXT (vpc);
3140
3141 CASE (sem, INSN_CALLD) : /* call:d $label12 */
3142 {
3143 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3144 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3145 #define FLD(f) abuf->fields.sfmt_call.f
3146 int UNUSED written = 0;
3147 IADDR UNUSED pc = abuf->addr;
3148 SEM_BRANCH_INIT
3149 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3150
3151 {
3152 {
3153 {
3154 SI opval = ADDSI (pc, 4);
3155 SET_H_DR (((UINT) 1), opval);
3156 TRACE_RESULT (current_cpu, abuf, "dr-1", 'x', opval);
3157 }
3158 {
3159 USI opval = FLD (i_label12);
3160 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3161 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3162 }
3163 }
3164 }
3165
3166 SEM_BRANCH_FINI (vpc);
3167 #undef FLD
3168 }
3169 NEXT (vpc);
3170
3171 CASE (sem, INSN_RET) : /* ret */
3172 {
3173 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3174 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3175 #define FLD(f) abuf->fields.fmt_empty.f
3176 int UNUSED written = 0;
3177 IADDR UNUSED pc = abuf->addr;
3178 SEM_BRANCH_INIT
3179 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3180
3181 {
3182 USI opval = GET_H_DR (((UINT) 1));
3183 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3184 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3185 }
3186
3187 SEM_BRANCH_FINI (vpc);
3188 #undef FLD
3189 }
3190 NEXT (vpc);
3191
3192 CASE (sem, INSN_RET_D) : /* ret:d */
3193 {
3194 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3195 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3196 #define FLD(f) abuf->fields.fmt_empty.f
3197 int UNUSED written = 0;
3198 IADDR UNUSED pc = abuf->addr;
3199 SEM_BRANCH_INIT
3200 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3201
3202 {
3203 {
3204 USI opval = GET_H_DR (((UINT) 1));
3205 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3206 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3207 }
3208 }
3209
3210 SEM_BRANCH_FINI (vpc);
3211 #undef FLD
3212 }
3213 NEXT (vpc);
3214
3215 CASE (sem, INSN_INT) : /* int $u8 */
3216 {
3217 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3218 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3219 #define FLD(f) abuf->fields.sfmt_int.f
3220 int UNUSED written = 0;
3221 IADDR UNUSED pc = abuf->addr;
3222 SEM_BRANCH_INIT
3223 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3224
3225 {
3226 ; /*clobber*/
3227 ; /*clobber*/
3228 ; /*clobber*/
3229 {
3230 SI opval = fr30_int (current_cpu, pc, FLD (f_u8));
3231 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3232 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3233 }
3234 }
3235
3236 SEM_BRANCH_FINI (vpc);
3237 #undef FLD
3238 }
3239 NEXT (vpc);
3240
3241 CASE (sem, INSN_INTE) : /* inte */
3242 {
3243 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3244 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3245 #define FLD(f) abuf->fields.fmt_empty.f
3246 int UNUSED written = 0;
3247 IADDR UNUSED pc = abuf->addr;
3248 SEM_BRANCH_INIT
3249 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3250
3251 {
3252 ; /*clobber*/
3253 ; /*clobber*/
3254 ; /*clobber*/
3255 {
3256 SI opval = fr30_inte (current_cpu, pc);
3257 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3258 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3259 }
3260 }
3261
3262 SEM_BRANCH_FINI (vpc);
3263 #undef FLD
3264 }
3265 NEXT (vpc);
3266
3267 CASE (sem, INSN_RETI) : /* reti */
3268 {
3269 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3270 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3271 #define FLD(f) abuf->fields.fmt_empty.f
3272 int UNUSED written = 0;
3273 IADDR UNUSED pc = abuf->addr;
3274 SEM_BRANCH_INIT
3275 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3276
3277 if (EQBI (GET_H_SBIT (), 0)) {
3278 {
3279 {
3280 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
3281 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3282 written |= (1 << 7);
3283 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3284 }
3285 {
3286 SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
3287 SET_H_DR (((UINT) 2), opval);
3288 written |= (1 << 5);
3289 TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
3290 }
3291 {
3292 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 2)));
3293 SET_H_PS (opval);
3294 written |= (1 << 8);
3295 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3296 }
3297 {
3298 SI opval = ADDSI (GET_H_DR (((UINT) 2)), 4);
3299 SET_H_DR (((UINT) 2), opval);
3300 written |= (1 << 5);
3301 TRACE_RESULT (current_cpu, abuf, "dr-2", 'x', opval);
3302 }
3303 }
3304 } else {
3305 {
3306 {
3307 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
3308 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
3309 written |= (1 << 7);
3310 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3311 }
3312 {
3313 SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
3314 SET_H_DR (((UINT) 3), opval);
3315 written |= (1 << 6);
3316 TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
3317 }
3318 {
3319 SI opval = GETMEMSI (current_cpu, pc, GET_H_DR (((UINT) 3)));
3320 SET_H_PS (opval);
3321 written |= (1 << 8);
3322 TRACE_RESULT (current_cpu, abuf, "ps", 'x', opval);
3323 }
3324 {
3325 SI opval = ADDSI (GET_H_DR (((UINT) 3)), 4);
3326 SET_H_DR (((UINT) 3), opval);
3327 written |= (1 << 6);
3328 TRACE_RESULT (current_cpu, abuf, "dr-3", 'x', opval);
3329 }
3330 }
3331 }
3332
3333 abuf->written = written;
3334 SEM_BRANCH_FINI (vpc);
3335 #undef FLD
3336 }
3337 NEXT (vpc);
3338
3339 CASE (sem, INSN_BRAD) : /* bra:d $label9 */
3340 {
3341 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3342 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3343 #define FLD(f) abuf->fields.sfmt_brad.f
3344 int UNUSED written = 0;
3345 IADDR UNUSED pc = abuf->addr;
3346 SEM_BRANCH_INIT
3347 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3348
3349 {
3350 {
3351 USI opval = FLD (i_label9);
3352 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3353 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3354 }
3355 }
3356
3357 SEM_BRANCH_FINI (vpc);
3358 #undef FLD
3359 }
3360 NEXT (vpc);
3361
3362 CASE (sem, INSN_BRA) : /* bra $label9 */
3363 {
3364 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3365 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3366 #define FLD(f) abuf->fields.sfmt_brad.f
3367 int UNUSED written = 0;
3368 IADDR UNUSED pc = abuf->addr;
3369 SEM_BRANCH_INIT
3370 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3371
3372 {
3373 USI opval = FLD (i_label9);
3374 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3375 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3376 }
3377
3378 SEM_BRANCH_FINI (vpc);
3379 #undef FLD
3380 }
3381 NEXT (vpc);
3382
3383 CASE (sem, INSN_BNOD) : /* bno:d $label9 */
3384 {
3385 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3386 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3387 #define FLD(f) abuf->fields.fmt_empty.f
3388 int UNUSED written = 0;
3389 IADDR UNUSED pc = abuf->addr;
3390 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3391
3392 {
3393 do { } while (0); /*nop*/
3394 }
3395
3396 #undef FLD
3397 }
3398 NEXT (vpc);
3399
3400 CASE (sem, INSN_BNO) : /* bno $label9 */
3401 {
3402 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3403 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3404 #define FLD(f) abuf->fields.fmt_empty.f
3405 int UNUSED written = 0;
3406 IADDR UNUSED pc = abuf->addr;
3407 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3408
3409 do { } while (0); /*nop*/
3410
3411 #undef FLD
3412 }
3413 NEXT (vpc);
3414
3415 CASE (sem, INSN_BEQD) : /* beq:d $label9 */
3416 {
3417 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3418 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3419 #define FLD(f) abuf->fields.sfmt_brad.f
3420 int UNUSED written = 0;
3421 IADDR UNUSED pc = abuf->addr;
3422 SEM_BRANCH_INIT
3423 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3424
3425 {
3426 if (CPU (h_zbit)) {
3427 {
3428 USI opval = FLD (i_label9);
3429 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3430 written |= (1 << 2);
3431 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3432 }
3433 }
3434 }
3435
3436 abuf->written = written;
3437 SEM_BRANCH_FINI (vpc);
3438 #undef FLD
3439 }
3440 NEXT (vpc);
3441
3442 CASE (sem, INSN_BEQ) : /* beq $label9 */
3443 {
3444 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3445 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3446 #define FLD(f) abuf->fields.sfmt_brad.f
3447 int UNUSED written = 0;
3448 IADDR UNUSED pc = abuf->addr;
3449 SEM_BRANCH_INIT
3450 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3451
3452 if (CPU (h_zbit)) {
3453 {
3454 USI opval = FLD (i_label9);
3455 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3456 written |= (1 << 2);
3457 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3458 }
3459 }
3460
3461 abuf->written = written;
3462 SEM_BRANCH_FINI (vpc);
3463 #undef FLD
3464 }
3465 NEXT (vpc);
3466
3467 CASE (sem, INSN_BNED) : /* bne:d $label9 */
3468 {
3469 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3470 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3471 #define FLD(f) abuf->fields.sfmt_brad.f
3472 int UNUSED written = 0;
3473 IADDR UNUSED pc = abuf->addr;
3474 SEM_BRANCH_INIT
3475 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3476
3477 {
3478 if (NOTBI (CPU (h_zbit))) {
3479 {
3480 USI opval = FLD (i_label9);
3481 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3482 written |= (1 << 2);
3483 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3484 }
3485 }
3486 }
3487
3488 abuf->written = written;
3489 SEM_BRANCH_FINI (vpc);
3490 #undef FLD
3491 }
3492 NEXT (vpc);
3493
3494 CASE (sem, INSN_BNE) : /* bne $label9 */
3495 {
3496 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3497 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3498 #define FLD(f) abuf->fields.sfmt_brad.f
3499 int UNUSED written = 0;
3500 IADDR UNUSED pc = abuf->addr;
3501 SEM_BRANCH_INIT
3502 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3503
3504 if (NOTBI (CPU (h_zbit))) {
3505 {
3506 USI opval = FLD (i_label9);
3507 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3508 written |= (1 << 2);
3509 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3510 }
3511 }
3512
3513 abuf->written = written;
3514 SEM_BRANCH_FINI (vpc);
3515 #undef FLD
3516 }
3517 NEXT (vpc);
3518
3519 CASE (sem, INSN_BCD) : /* bc:d $label9 */
3520 {
3521 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3522 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3523 #define FLD(f) abuf->fields.sfmt_brad.f
3524 int UNUSED written = 0;
3525 IADDR UNUSED pc = abuf->addr;
3526 SEM_BRANCH_INIT
3527 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3528
3529 {
3530 if (CPU (h_cbit)) {
3531 {
3532 USI opval = FLD (i_label9);
3533 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3534 written |= (1 << 2);
3535 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3536 }
3537 }
3538 }
3539
3540 abuf->written = written;
3541 SEM_BRANCH_FINI (vpc);
3542 #undef FLD
3543 }
3544 NEXT (vpc);
3545
3546 CASE (sem, INSN_BC) : /* bc $label9 */
3547 {
3548 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3549 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3550 #define FLD(f) abuf->fields.sfmt_brad.f
3551 int UNUSED written = 0;
3552 IADDR UNUSED pc = abuf->addr;
3553 SEM_BRANCH_INIT
3554 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3555
3556 if (CPU (h_cbit)) {
3557 {
3558 USI opval = FLD (i_label9);
3559 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3560 written |= (1 << 2);
3561 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3562 }
3563 }
3564
3565 abuf->written = written;
3566 SEM_BRANCH_FINI (vpc);
3567 #undef FLD
3568 }
3569 NEXT (vpc);
3570
3571 CASE (sem, INSN_BNCD) : /* bnc:d $label9 */
3572 {
3573 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3574 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3575 #define FLD(f) abuf->fields.sfmt_brad.f
3576 int UNUSED written = 0;
3577 IADDR UNUSED pc = abuf->addr;
3578 SEM_BRANCH_INIT
3579 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3580
3581 {
3582 if (NOTBI (CPU (h_cbit))) {
3583 {
3584 USI opval = FLD (i_label9);
3585 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3586 written |= (1 << 2);
3587 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3588 }
3589 }
3590 }
3591
3592 abuf->written = written;
3593 SEM_BRANCH_FINI (vpc);
3594 #undef FLD
3595 }
3596 NEXT (vpc);
3597
3598 CASE (sem, INSN_BNC) : /* bnc $label9 */
3599 {
3600 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3601 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3602 #define FLD(f) abuf->fields.sfmt_brad.f
3603 int UNUSED written = 0;
3604 IADDR UNUSED pc = abuf->addr;
3605 SEM_BRANCH_INIT
3606 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3607
3608 if (NOTBI (CPU (h_cbit))) {
3609 {
3610 USI opval = FLD (i_label9);
3611 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3612 written |= (1 << 2);
3613 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3614 }
3615 }
3616
3617 abuf->written = written;
3618 SEM_BRANCH_FINI (vpc);
3619 #undef FLD
3620 }
3621 NEXT (vpc);
3622
3623 CASE (sem, INSN_BND) : /* bn:d $label9 */
3624 {
3625 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3626 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3627 #define FLD(f) abuf->fields.sfmt_brad.f
3628 int UNUSED written = 0;
3629 IADDR UNUSED pc = abuf->addr;
3630 SEM_BRANCH_INIT
3631 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3632
3633 {
3634 if (CPU (h_nbit)) {
3635 {
3636 USI opval = FLD (i_label9);
3637 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3638 written |= (1 << 2);
3639 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3640 }
3641 }
3642 }
3643
3644 abuf->written = written;
3645 SEM_BRANCH_FINI (vpc);
3646 #undef FLD
3647 }
3648 NEXT (vpc);
3649
3650 CASE (sem, INSN_BN) : /* bn $label9 */
3651 {
3652 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3653 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3654 #define FLD(f) abuf->fields.sfmt_brad.f
3655 int UNUSED written = 0;
3656 IADDR UNUSED pc = abuf->addr;
3657 SEM_BRANCH_INIT
3658 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3659
3660 if (CPU (h_nbit)) {
3661 {
3662 USI opval = FLD (i_label9);
3663 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3664 written |= (1 << 2);
3665 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3666 }
3667 }
3668
3669 abuf->written = written;
3670 SEM_BRANCH_FINI (vpc);
3671 #undef FLD
3672 }
3673 NEXT (vpc);
3674
3675 CASE (sem, INSN_BPD) : /* bp:d $label9 */
3676 {
3677 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3678 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3679 #define FLD(f) abuf->fields.sfmt_brad.f
3680 int UNUSED written = 0;
3681 IADDR UNUSED pc = abuf->addr;
3682 SEM_BRANCH_INIT
3683 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3684
3685 {
3686 if (NOTBI (CPU (h_nbit))) {
3687 {
3688 USI opval = FLD (i_label9);
3689 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3690 written |= (1 << 2);
3691 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3692 }
3693 }
3694 }
3695
3696 abuf->written = written;
3697 SEM_BRANCH_FINI (vpc);
3698 #undef FLD
3699 }
3700 NEXT (vpc);
3701
3702 CASE (sem, INSN_BP) : /* bp $label9 */
3703 {
3704 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3705 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3706 #define FLD(f) abuf->fields.sfmt_brad.f
3707 int UNUSED written = 0;
3708 IADDR UNUSED pc = abuf->addr;
3709 SEM_BRANCH_INIT
3710 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3711
3712 if (NOTBI (CPU (h_nbit))) {
3713 {
3714 USI opval = FLD (i_label9);
3715 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3716 written |= (1 << 2);
3717 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3718 }
3719 }
3720
3721 abuf->written = written;
3722 SEM_BRANCH_FINI (vpc);
3723 #undef FLD
3724 }
3725 NEXT (vpc);
3726
3727 CASE (sem, INSN_BVD) : /* bv:d $label9 */
3728 {
3729 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3730 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3731 #define FLD(f) abuf->fields.sfmt_brad.f
3732 int UNUSED written = 0;
3733 IADDR UNUSED pc = abuf->addr;
3734 SEM_BRANCH_INIT
3735 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3736
3737 {
3738 if (CPU (h_vbit)) {
3739 {
3740 USI opval = FLD (i_label9);
3741 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3742 written |= (1 << 2);
3743 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3744 }
3745 }
3746 }
3747
3748 abuf->written = written;
3749 SEM_BRANCH_FINI (vpc);
3750 #undef FLD
3751 }
3752 NEXT (vpc);
3753
3754 CASE (sem, INSN_BV) : /* bv $label9 */
3755 {
3756 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3757 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3758 #define FLD(f) abuf->fields.sfmt_brad.f
3759 int UNUSED written = 0;
3760 IADDR UNUSED pc = abuf->addr;
3761 SEM_BRANCH_INIT
3762 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3763
3764 if (CPU (h_vbit)) {
3765 {
3766 USI opval = FLD (i_label9);
3767 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3768 written |= (1 << 2);
3769 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3770 }
3771 }
3772
3773 abuf->written = written;
3774 SEM_BRANCH_FINI (vpc);
3775 #undef FLD
3776 }
3777 NEXT (vpc);
3778
3779 CASE (sem, INSN_BNVD) : /* bnv:d $label9 */
3780 {
3781 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3782 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3783 #define FLD(f) abuf->fields.sfmt_brad.f
3784 int UNUSED written = 0;
3785 IADDR UNUSED pc = abuf->addr;
3786 SEM_BRANCH_INIT
3787 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3788
3789 {
3790 if (NOTBI (CPU (h_vbit))) {
3791 {
3792 USI opval = FLD (i_label9);
3793 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3794 written |= (1 << 2);
3795 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3796 }
3797 }
3798 }
3799
3800 abuf->written = written;
3801 SEM_BRANCH_FINI (vpc);
3802 #undef FLD
3803 }
3804 NEXT (vpc);
3805
3806 CASE (sem, INSN_BNV) : /* bnv $label9 */
3807 {
3808 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3809 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3810 #define FLD(f) abuf->fields.sfmt_brad.f
3811 int UNUSED written = 0;
3812 IADDR UNUSED pc = abuf->addr;
3813 SEM_BRANCH_INIT
3814 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3815
3816 if (NOTBI (CPU (h_vbit))) {
3817 {
3818 USI opval = FLD (i_label9);
3819 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3820 written |= (1 << 2);
3821 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3822 }
3823 }
3824
3825 abuf->written = written;
3826 SEM_BRANCH_FINI (vpc);
3827 #undef FLD
3828 }
3829 NEXT (vpc);
3830
3831 CASE (sem, INSN_BLTD) : /* blt:d $label9 */
3832 {
3833 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3834 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3835 #define FLD(f) abuf->fields.sfmt_brad.f
3836 int UNUSED written = 0;
3837 IADDR UNUSED pc = abuf->addr;
3838 SEM_BRANCH_INIT
3839 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3840
3841 {
3842 if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
3843 {
3844 USI opval = FLD (i_label9);
3845 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3846 written |= (1 << 3);
3847 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3848 }
3849 }
3850 }
3851
3852 abuf->written = written;
3853 SEM_BRANCH_FINI (vpc);
3854 #undef FLD
3855 }
3856 NEXT (vpc);
3857
3858 CASE (sem, INSN_BLT) : /* blt $label9 */
3859 {
3860 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3861 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3862 #define FLD(f) abuf->fields.sfmt_brad.f
3863 int UNUSED written = 0;
3864 IADDR UNUSED pc = abuf->addr;
3865 SEM_BRANCH_INIT
3866 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3867
3868 if (XORBI (CPU (h_vbit), CPU (h_nbit))) {
3869 {
3870 USI opval = FLD (i_label9);
3871 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3872 written |= (1 << 3);
3873 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3874 }
3875 }
3876
3877 abuf->written = written;
3878 SEM_BRANCH_FINI (vpc);
3879 #undef FLD
3880 }
3881 NEXT (vpc);
3882
3883 CASE (sem, INSN_BGED) : /* bge:d $label9 */
3884 {
3885 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3886 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3887 #define FLD(f) abuf->fields.sfmt_brad.f
3888 int UNUSED written = 0;
3889 IADDR UNUSED pc = abuf->addr;
3890 SEM_BRANCH_INIT
3891 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3892
3893 {
3894 if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
3895 {
3896 USI opval = FLD (i_label9);
3897 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3898 written |= (1 << 3);
3899 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3900 }
3901 }
3902 }
3903
3904 abuf->written = written;
3905 SEM_BRANCH_FINI (vpc);
3906 #undef FLD
3907 }
3908 NEXT (vpc);
3909
3910 CASE (sem, INSN_BGE) : /* bge $label9 */
3911 {
3912 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3913 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3914 #define FLD(f) abuf->fields.sfmt_brad.f
3915 int UNUSED written = 0;
3916 IADDR UNUSED pc = abuf->addr;
3917 SEM_BRANCH_INIT
3918 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3919
3920 if (NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit)))) {
3921 {
3922 USI opval = FLD (i_label9);
3923 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3924 written |= (1 << 3);
3925 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3926 }
3927 }
3928
3929 abuf->written = written;
3930 SEM_BRANCH_FINI (vpc);
3931 #undef FLD
3932 }
3933 NEXT (vpc);
3934
3935 CASE (sem, INSN_BLED) : /* ble:d $label9 */
3936 {
3937 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3938 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3939 #define FLD(f) abuf->fields.sfmt_brad.f
3940 int UNUSED written = 0;
3941 IADDR UNUSED pc = abuf->addr;
3942 SEM_BRANCH_INIT
3943 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3944
3945 {
3946 if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
3947 {
3948 USI opval = FLD (i_label9);
3949 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3950 written |= (1 << 4);
3951 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3952 }
3953 }
3954 }
3955
3956 abuf->written = written;
3957 SEM_BRANCH_FINI (vpc);
3958 #undef FLD
3959 }
3960 NEXT (vpc);
3961
3962 CASE (sem, INSN_BLE) : /* ble $label9 */
3963 {
3964 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3965 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3966 #define FLD(f) abuf->fields.sfmt_brad.f
3967 int UNUSED written = 0;
3968 IADDR UNUSED pc = abuf->addr;
3969 SEM_BRANCH_INIT
3970 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3971
3972 if (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))) {
3973 {
3974 USI opval = FLD (i_label9);
3975 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
3976 written |= (1 << 4);
3977 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
3978 }
3979 }
3980
3981 abuf->written = written;
3982 SEM_BRANCH_FINI (vpc);
3983 #undef FLD
3984 }
3985 NEXT (vpc);
3986
3987 CASE (sem, INSN_BGTD) : /* bgt:d $label9 */
3988 {
3989 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
3990 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3991 #define FLD(f) abuf->fields.sfmt_brad.f
3992 int UNUSED written = 0;
3993 IADDR UNUSED pc = abuf->addr;
3994 SEM_BRANCH_INIT
3995 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
3996
3997 {
3998 if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
3999 {
4000 USI opval = FLD (i_label9);
4001 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4002 written |= (1 << 4);
4003 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4004 }
4005 }
4006 }
4007
4008 abuf->written = written;
4009 SEM_BRANCH_FINI (vpc);
4010 #undef FLD
4011 }
4012 NEXT (vpc);
4013
4014 CASE (sem, INSN_BGT) : /* bgt $label9 */
4015 {
4016 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4017 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4018 #define FLD(f) abuf->fields.sfmt_brad.f
4019 int UNUSED written = 0;
4020 IADDR UNUSED pc = abuf->addr;
4021 SEM_BRANCH_INIT
4022 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4023
4024 if (NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)))) {
4025 {
4026 USI opval = FLD (i_label9);
4027 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4028 written |= (1 << 4);
4029 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4030 }
4031 }
4032
4033 abuf->written = written;
4034 SEM_BRANCH_FINI (vpc);
4035 #undef FLD
4036 }
4037 NEXT (vpc);
4038
4039 CASE (sem, INSN_BLSD) : /* bls:d $label9 */
4040 {
4041 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4042 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4043 #define FLD(f) abuf->fields.sfmt_brad.f
4044 int UNUSED written = 0;
4045 IADDR UNUSED pc = abuf->addr;
4046 SEM_BRANCH_INIT
4047 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4048
4049 {
4050 if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
4051 {
4052 USI opval = FLD (i_label9);
4053 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4054 written |= (1 << 3);
4055 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4056 }
4057 }
4058 }
4059
4060 abuf->written = written;
4061 SEM_BRANCH_FINI (vpc);
4062 #undef FLD
4063 }
4064 NEXT (vpc);
4065
4066 CASE (sem, INSN_BLS) : /* bls $label9 */
4067 {
4068 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4069 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4070 #define FLD(f) abuf->fields.sfmt_brad.f
4071 int UNUSED written = 0;
4072 IADDR UNUSED pc = abuf->addr;
4073 SEM_BRANCH_INIT
4074 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4075
4076 if (ORBI (CPU (h_cbit), CPU (h_zbit))) {
4077 {
4078 USI opval = FLD (i_label9);
4079 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4080 written |= (1 << 3);
4081 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4082 }
4083 }
4084
4085 abuf->written = written;
4086 SEM_BRANCH_FINI (vpc);
4087 #undef FLD
4088 }
4089 NEXT (vpc);
4090
4091 CASE (sem, INSN_BHID) : /* bhi:d $label9 */
4092 {
4093 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4094 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4095 #define FLD(f) abuf->fields.sfmt_brad.f
4096 int UNUSED written = 0;
4097 IADDR UNUSED pc = abuf->addr;
4098 SEM_BRANCH_INIT
4099 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4100
4101 {
4102 if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
4103 {
4104 USI opval = FLD (i_label9);
4105 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4106 written |= (1 << 3);
4107 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4108 }
4109 }
4110 }
4111
4112 abuf->written = written;
4113 SEM_BRANCH_FINI (vpc);
4114 #undef FLD
4115 }
4116 NEXT (vpc);
4117
4118 CASE (sem, INSN_BHI) : /* bhi $label9 */
4119 {
4120 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4121 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4122 #define FLD(f) abuf->fields.sfmt_brad.f
4123 int UNUSED written = 0;
4124 IADDR UNUSED pc = abuf->addr;
4125 SEM_BRANCH_INIT
4126 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4127
4128 if (NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit)))) {
4129 {
4130 USI opval = FLD (i_label9);
4131 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
4132 written |= (1 << 3);
4133 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
4134 }
4135 }
4136
4137 abuf->written = written;
4138 SEM_BRANCH_FINI (vpc);
4139 #undef FLD
4140 }
4141 NEXT (vpc);
4142
4143 CASE (sem, INSN_DMOVR13) : /* dmov $R13,@$dir10 */
4144 {
4145 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4146 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4147 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4148 int UNUSED written = 0;
4149 IADDR UNUSED pc = abuf->addr;
4150 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4151
4152 {
4153 SI opval = CPU (h_gr[((UINT) 13)]);
4154 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4155 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4156 }
4157
4158 #undef FLD
4159 }
4160 NEXT (vpc);
4161
4162 CASE (sem, INSN_DMOVR13H) : /* dmovh $R13,@$dir9 */
4163 {
4164 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4165 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4166 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4167 int UNUSED written = 0;
4168 IADDR UNUSED pc = abuf->addr;
4169 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4170
4171 {
4172 HI opval = CPU (h_gr[((UINT) 13)]);
4173 SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
4174 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4175 }
4176
4177 #undef FLD
4178 }
4179 NEXT (vpc);
4180
4181 CASE (sem, INSN_DMOVR13B) : /* dmovb $R13,@$dir8 */
4182 {
4183 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4184 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4185 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4186 int UNUSED written = 0;
4187 IADDR UNUSED pc = abuf->addr;
4188 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4189
4190 {
4191 QI opval = CPU (h_gr[((UINT) 13)]);
4192 SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
4193 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4194 }
4195
4196 #undef FLD
4197 }
4198 NEXT (vpc);
4199
4200 CASE (sem, INSN_DMOVR13PI) : /* dmov @$R13+,@$dir10 */
4201 {
4202 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4203 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4204 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4205 int UNUSED written = 0;
4206 IADDR UNUSED pc = abuf->addr;
4207 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4208
4209 {
4210 {
4211 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4212 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4213 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4214 }
4215 {
4216 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
4217 CPU (h_gr[((UINT) 13)]) = opval;
4218 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4219 }
4220 }
4221
4222 #undef FLD
4223 }
4224 NEXT (vpc);
4225
4226 CASE (sem, INSN_DMOVR13PIH) : /* dmovh @$R13+,@$dir9 */
4227 {
4228 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4229 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4230 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4231 int UNUSED written = 0;
4232 IADDR UNUSED pc = abuf->addr;
4233 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4234
4235 {
4236 {
4237 HI opval = GETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4238 SETMEMHI (current_cpu, pc, FLD (f_dir9), opval);
4239 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4240 }
4241 {
4242 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
4243 CPU (h_gr[((UINT) 13)]) = opval;
4244 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4245 }
4246 }
4247
4248 #undef FLD
4249 }
4250 NEXT (vpc);
4251
4252 CASE (sem, INSN_DMOVR13PIB) : /* dmovb @$R13+,@$dir8 */
4253 {
4254 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4255 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4256 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4257 int UNUSED written = 0;
4258 IADDR UNUSED pc = abuf->addr;
4259 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4260
4261 {
4262 {
4263 QI opval = GETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]));
4264 SETMEMQI (current_cpu, pc, FLD (f_dir8), opval);
4265 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4266 }
4267 {
4268 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
4269 CPU (h_gr[((UINT) 13)]) = opval;
4270 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4271 }
4272 }
4273
4274 #undef FLD
4275 }
4276 NEXT (vpc);
4277
4278 CASE (sem, INSN_DMOVR15PI) : /* dmov @$R15+,@$dir10 */
4279 {
4280 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4281 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4282 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
4283 int UNUSED written = 0;
4284 IADDR UNUSED pc = abuf->addr;
4285 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4286
4287 {
4288 {
4289 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4290 SETMEMSI (current_cpu, pc, FLD (f_dir10), opval);
4291 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4292 }
4293 {
4294 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4295 CPU (h_gr[((UINT) 15)]) = opval;
4296 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4297 }
4298 }
4299
4300 #undef FLD
4301 }
4302 NEXT (vpc);
4303
4304 CASE (sem, INSN_DMOV2R13) : /* dmov @$dir10,$R13 */
4305 {
4306 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4307 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4308 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4309 int UNUSED written = 0;
4310 IADDR UNUSED pc = abuf->addr;
4311 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4312
4313 {
4314 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4315 CPU (h_gr[((UINT) 13)]) = opval;
4316 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4317 }
4318
4319 #undef FLD
4320 }
4321 NEXT (vpc);
4322
4323 CASE (sem, INSN_DMOV2R13H) : /* dmovh @$dir9,$R13 */
4324 {
4325 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4326 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4327 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4328 int UNUSED written = 0;
4329 IADDR UNUSED pc = abuf->addr;
4330 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4331
4332 {
4333 SI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
4334 CPU (h_gr[((UINT) 13)]) = opval;
4335 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4336 }
4337
4338 #undef FLD
4339 }
4340 NEXT (vpc);
4341
4342 CASE (sem, INSN_DMOV2R13B) : /* dmovb @$dir8,$R13 */
4343 {
4344 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4345 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4346 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4347 int UNUSED written = 0;
4348 IADDR UNUSED pc = abuf->addr;
4349 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4350
4351 {
4352 SI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
4353 CPU (h_gr[((UINT) 13)]) = opval;
4354 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4355 }
4356
4357 #undef FLD
4358 }
4359 NEXT (vpc);
4360
4361 CASE (sem, INSN_DMOV2R13PI) : /* dmov @$dir10,@$R13+ */
4362 {
4363 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4364 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4365 #define FLD(f) abuf->fields.sfmt_dmovr13pi.f
4366 int UNUSED written = 0;
4367 IADDR UNUSED pc = abuf->addr;
4368 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4369
4370 {
4371 {
4372 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4373 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4374 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4375 }
4376 {
4377 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 4);
4378 CPU (h_gr[((UINT) 13)]) = opval;
4379 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4380 }
4381 }
4382
4383 #undef FLD
4384 }
4385 NEXT (vpc);
4386
4387 CASE (sem, INSN_DMOV2R13PIH) : /* dmovh @$dir9,@$R13+ */
4388 {
4389 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4390 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4391 #define FLD(f) abuf->fields.sfmt_dmovr13pih.f
4392 int UNUSED written = 0;
4393 IADDR UNUSED pc = abuf->addr;
4394 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4395
4396 {
4397 {
4398 HI opval = GETMEMHI (current_cpu, pc, FLD (f_dir9));
4399 SETMEMHI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4400 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4401 }
4402 {
4403 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 2);
4404 CPU (h_gr[((UINT) 13)]) = opval;
4405 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4406 }
4407 }
4408
4409 #undef FLD
4410 }
4411 NEXT (vpc);
4412
4413 CASE (sem, INSN_DMOV2R13PIB) : /* dmovb @$dir8,@$R13+ */
4414 {
4415 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4416 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4417 #define FLD(f) abuf->fields.sfmt_dmovr13pib.f
4418 int UNUSED written = 0;
4419 IADDR UNUSED pc = abuf->addr;
4420 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4421
4422 {
4423 {
4424 QI opval = GETMEMQI (current_cpu, pc, FLD (f_dir8));
4425 SETMEMQI (current_cpu, pc, CPU (h_gr[((UINT) 13)]), opval);
4426 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4427 }
4428 {
4429 SI opval = ADDSI (CPU (h_gr[((UINT) 13)]), 1);
4430 CPU (h_gr[((UINT) 13)]) = opval;
4431 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4432 }
4433 }
4434
4435 #undef FLD
4436 }
4437 NEXT (vpc);
4438
4439 CASE (sem, INSN_DMOV2R15PD) : /* dmov @$dir10,@-$R15 */
4440 {
4441 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4442 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4443 #define FLD(f) abuf->fields.sfmt_dmovr15pi.f
4444 int UNUSED written = 0;
4445 IADDR UNUSED pc = abuf->addr;
4446 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4447
4448 {
4449 {
4450 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
4451 CPU (h_gr[((UINT) 15)]) = opval;
4452 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4453 }
4454 {
4455 SI opval = GETMEMSI (current_cpu, pc, FLD (f_dir10));
4456 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
4457 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
4458 }
4459 }
4460
4461 #undef FLD
4462 }
4463 NEXT (vpc);
4464
4465 CASE (sem, INSN_LDRES) : /* ldres @$Ri+,$u4 */
4466 {
4467 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4468 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4469 #define FLD(f) abuf->fields.sfmt_add2.f
4470 int UNUSED written = 0;
4471 IADDR UNUSED pc = abuf->addr;
4472 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4473
4474 {
4475 SI opval = ADDSI (* FLD (i_Ri), 4);
4476 * FLD (i_Ri) = opval;
4477 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4478 }
4479
4480 #undef FLD
4481 }
4482 NEXT (vpc);
4483
4484 CASE (sem, INSN_STRES) : /* stres $u4,@$Ri+ */
4485 {
4486 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4487 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4488 #define FLD(f) abuf->fields.sfmt_add2.f
4489 int UNUSED written = 0;
4490 IADDR UNUSED pc = abuf->addr;
4491 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4492
4493 {
4494 SI opval = ADDSI (* FLD (i_Ri), 4);
4495 * FLD (i_Ri) = opval;
4496 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4497 }
4498
4499 #undef FLD
4500 }
4501 NEXT (vpc);
4502
4503 CASE (sem, INSN_COPOP) : /* copop $u4c,$ccc,$CRj,$CRi */
4504 {
4505 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4506 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4507 #define FLD(f) abuf->fields.fmt_empty.f
4508 int UNUSED written = 0;
4509 IADDR UNUSED pc = abuf->addr;
4510 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4511
4512 do { } while (0); /*nop*/
4513
4514 #undef FLD
4515 }
4516 NEXT (vpc);
4517
4518 CASE (sem, INSN_COPLD) : /* copld $u4c,$ccc,$Rjc,$CRi */
4519 {
4520 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4521 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4522 #define FLD(f) abuf->fields.fmt_empty.f
4523 int UNUSED written = 0;
4524 IADDR UNUSED pc = abuf->addr;
4525 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4526
4527 do { } while (0); /*nop*/
4528
4529 #undef FLD
4530 }
4531 NEXT (vpc);
4532
4533 CASE (sem, INSN_COPST) : /* copst $u4c,$ccc,$CRj,$Ric */
4534 {
4535 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4536 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4537 #define FLD(f) abuf->fields.fmt_empty.f
4538 int UNUSED written = 0;
4539 IADDR UNUSED pc = abuf->addr;
4540 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4541
4542 do { } while (0); /*nop*/
4543
4544 #undef FLD
4545 }
4546 NEXT (vpc);
4547
4548 CASE (sem, INSN_COPSV) : /* copsv $u4c,$ccc,$CRj,$Ric */
4549 {
4550 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4551 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4552 #define FLD(f) abuf->fields.fmt_empty.f
4553 int UNUSED written = 0;
4554 IADDR UNUSED pc = abuf->addr;
4555 vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
4556
4557 do { } while (0); /*nop*/
4558
4559 #undef FLD
4560 }
4561 NEXT (vpc);
4562
4563 CASE (sem, INSN_NOP) : /* nop */
4564 {
4565 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4566 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4567 #define FLD(f) abuf->fields.fmt_empty.f
4568 int UNUSED written = 0;
4569 IADDR UNUSED pc = abuf->addr;
4570 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4571
4572 do { } while (0); /*nop*/
4573
4574 #undef FLD
4575 }
4576 NEXT (vpc);
4577
4578 CASE (sem, INSN_ANDCCR) : /* andccr $u8 */
4579 {
4580 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4581 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4582 #define FLD(f) abuf->fields.sfmt_int.f
4583 int UNUSED written = 0;
4584 IADDR UNUSED pc = abuf->addr;
4585 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4586
4587 {
4588 UQI opval = ANDQI (GET_H_CCR (), FLD (f_u8));
4589 SET_H_CCR (opval);
4590 TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
4591 }
4592
4593 #undef FLD
4594 }
4595 NEXT (vpc);
4596
4597 CASE (sem, INSN_ORCCR) : /* orccr $u8 */
4598 {
4599 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4600 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4601 #define FLD(f) abuf->fields.sfmt_int.f
4602 int UNUSED written = 0;
4603 IADDR UNUSED pc = abuf->addr;
4604 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4605
4606 {
4607 UQI opval = ORQI (GET_H_CCR (), FLD (f_u8));
4608 SET_H_CCR (opval);
4609 TRACE_RESULT (current_cpu, abuf, "ccr", 'x', opval);
4610 }
4611
4612 #undef FLD
4613 }
4614 NEXT (vpc);
4615
4616 CASE (sem, INSN_STILM) : /* stilm $u8 */
4617 {
4618 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4619 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4620 #define FLD(f) abuf->fields.sfmt_int.f
4621 int UNUSED written = 0;
4622 IADDR UNUSED pc = abuf->addr;
4623 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4624
4625 {
4626 UQI opval = ANDSI (FLD (f_u8), 31);
4627 SET_H_ILM (opval);
4628 TRACE_RESULT (current_cpu, abuf, "ilm", 'x', opval);
4629 }
4630
4631 #undef FLD
4632 }
4633 NEXT (vpc);
4634
4635 CASE (sem, INSN_ADDSP) : /* addsp $s10 */
4636 {
4637 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4638 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4639 #define FLD(f) abuf->fields.sfmt_addsp.f
4640 int UNUSED written = 0;
4641 IADDR UNUSED pc = abuf->addr;
4642 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4643
4644 {
4645 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), FLD (f_s10));
4646 CPU (h_gr[((UINT) 15)]) = opval;
4647 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4648 }
4649
4650 #undef FLD
4651 }
4652 NEXT (vpc);
4653
4654 CASE (sem, INSN_EXTSB) : /* extsb $Ri */
4655 {
4656 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4657 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4658 #define FLD(f) abuf->fields.sfmt_add2.f
4659 int UNUSED written = 0;
4660 IADDR UNUSED pc = abuf->addr;
4661 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4662
4663 {
4664 SI opval = EXTQISI (ANDQI (* FLD (i_Ri), 255));
4665 * FLD (i_Ri) = opval;
4666 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4667 }
4668
4669 #undef FLD
4670 }
4671 NEXT (vpc);
4672
4673 CASE (sem, INSN_EXTUB) : /* extub $Ri */
4674 {
4675 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4676 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4677 #define FLD(f) abuf->fields.sfmt_add2.f
4678 int UNUSED written = 0;
4679 IADDR UNUSED pc = abuf->addr;
4680 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4681
4682 {
4683 SI opval = ZEXTQISI (ANDQI (* FLD (i_Ri), 255));
4684 * FLD (i_Ri) = opval;
4685 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4686 }
4687
4688 #undef FLD
4689 }
4690 NEXT (vpc);
4691
4692 CASE (sem, INSN_EXTSH) : /* extsh $Ri */
4693 {
4694 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4695 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4696 #define FLD(f) abuf->fields.sfmt_add2.f
4697 int UNUSED written = 0;
4698 IADDR UNUSED pc = abuf->addr;
4699 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4700
4701 {
4702 SI opval = EXTHISI (ANDHI (* FLD (i_Ri), 65535));
4703 * FLD (i_Ri) = opval;
4704 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4705 }
4706
4707 #undef FLD
4708 }
4709 NEXT (vpc);
4710
4711 CASE (sem, INSN_EXTUH) : /* extuh $Ri */
4712 {
4713 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4714 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4715 #define FLD(f) abuf->fields.sfmt_add2.f
4716 int UNUSED written = 0;
4717 IADDR UNUSED pc = abuf->addr;
4718 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4719
4720 {
4721 SI opval = ZEXTHISI (ANDHI (* FLD (i_Ri), 65535));
4722 * FLD (i_Ri) = opval;
4723 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
4724 }
4725
4726 #undef FLD
4727 }
4728 NEXT (vpc);
4729
4730 CASE (sem, INSN_LDM0) : /* ldm0 ($reglist_low_ld) */
4731 {
4732 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4733 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4734 #define FLD(f) abuf->fields.sfmt_ldm0.f
4735 int UNUSED written = 0;
4736 IADDR UNUSED pc = abuf->addr;
4737 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4738
4739 {
4740 if (ANDSI (FLD (f_reglist_low_ld), 1)) {
4741 {
4742 {
4743 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4744 CPU (h_gr[((UINT) 0)]) = opval;
4745 written |= (1 << 3);
4746 TRACE_RESULT (current_cpu, abuf, "gr-0", 'x', opval);
4747 }
4748 {
4749 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4750 CPU (h_gr[((UINT) 15)]) = opval;
4751 written |= (1 << 5);
4752 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4753 }
4754 }
4755 }
4756 if (ANDSI (FLD (f_reglist_low_ld), 2)) {
4757 {
4758 {
4759 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4760 CPU (h_gr[((UINT) 1)]) = opval;
4761 written |= (1 << 4);
4762 TRACE_RESULT (current_cpu, abuf, "gr-1", 'x', opval);
4763 }
4764 {
4765 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4766 CPU (h_gr[((UINT) 15)]) = opval;
4767 written |= (1 << 5);
4768 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4769 }
4770 }
4771 }
4772 if (ANDSI (FLD (f_reglist_low_ld), 4)) {
4773 {
4774 {
4775 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4776 CPU (h_gr[((UINT) 2)]) = opval;
4777 written |= (1 << 6);
4778 TRACE_RESULT (current_cpu, abuf, "gr-2", 'x', opval);
4779 }
4780 {
4781 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4782 CPU (h_gr[((UINT) 15)]) = opval;
4783 written |= (1 << 5);
4784 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4785 }
4786 }
4787 }
4788 if (ANDSI (FLD (f_reglist_low_ld), 8)) {
4789 {
4790 {
4791 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4792 CPU (h_gr[((UINT) 3)]) = opval;
4793 written |= (1 << 7);
4794 TRACE_RESULT (current_cpu, abuf, "gr-3", 'x', opval);
4795 }
4796 {
4797 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4798 CPU (h_gr[((UINT) 15)]) = opval;
4799 written |= (1 << 5);
4800 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4801 }
4802 }
4803 }
4804 if (ANDSI (FLD (f_reglist_low_ld), 16)) {
4805 {
4806 {
4807 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4808 CPU (h_gr[((UINT) 4)]) = opval;
4809 written |= (1 << 8);
4810 TRACE_RESULT (current_cpu, abuf, "gr-4", 'x', opval);
4811 }
4812 {
4813 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4814 CPU (h_gr[((UINT) 15)]) = opval;
4815 written |= (1 << 5);
4816 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4817 }
4818 }
4819 }
4820 if (ANDSI (FLD (f_reglist_low_ld), 32)) {
4821 {
4822 {
4823 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4824 CPU (h_gr[((UINT) 5)]) = opval;
4825 written |= (1 << 9);
4826 TRACE_RESULT (current_cpu, abuf, "gr-5", 'x', opval);
4827 }
4828 {
4829 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4830 CPU (h_gr[((UINT) 15)]) = opval;
4831 written |= (1 << 5);
4832 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4833 }
4834 }
4835 }
4836 if (ANDSI (FLD (f_reglist_low_ld), 64)) {
4837 {
4838 {
4839 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4840 CPU (h_gr[((UINT) 6)]) = opval;
4841 written |= (1 << 10);
4842 TRACE_RESULT (current_cpu, abuf, "gr-6", 'x', opval);
4843 }
4844 {
4845 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4846 CPU (h_gr[((UINT) 15)]) = opval;
4847 written |= (1 << 5);
4848 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4849 }
4850 }
4851 }
4852 if (ANDSI (FLD (f_reglist_low_ld), 128)) {
4853 {
4854 {
4855 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4856 CPU (h_gr[((UINT) 7)]) = opval;
4857 written |= (1 << 11);
4858 TRACE_RESULT (current_cpu, abuf, "gr-7", 'x', opval);
4859 }
4860 {
4861 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4862 CPU (h_gr[((UINT) 15)]) = opval;
4863 written |= (1 << 5);
4864 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4865 }
4866 }
4867 }
4868 }
4869
4870 abuf->written = written;
4871 #undef FLD
4872 }
4873 NEXT (vpc);
4874
4875 CASE (sem, INSN_LDM1) : /* ldm1 ($reglist_hi_ld) */
4876 {
4877 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
4878 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
4879 #define FLD(f) abuf->fields.sfmt_ldm1.f
4880 int UNUSED written = 0;
4881 IADDR UNUSED pc = abuf->addr;
4882 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
4883
4884 {
4885 if (ANDSI (FLD (f_reglist_hi_ld), 1)) {
4886 {
4887 {
4888 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4889 CPU (h_gr[((UINT) 8)]) = opval;
4890 written |= (1 << 9);
4891 TRACE_RESULT (current_cpu, abuf, "gr-8", 'x', opval);
4892 }
4893 {
4894 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4895 CPU (h_gr[((UINT) 15)]) = opval;
4896 written |= (1 << 8);
4897 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4898 }
4899 }
4900 }
4901 if (ANDSI (FLD (f_reglist_hi_ld), 2)) {
4902 {
4903 {
4904 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4905 CPU (h_gr[((UINT) 9)]) = opval;
4906 written |= (1 << 10);
4907 TRACE_RESULT (current_cpu, abuf, "gr-9", 'x', opval);
4908 }
4909 {
4910 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4911 CPU (h_gr[((UINT) 15)]) = opval;
4912 written |= (1 << 8);
4913 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4914 }
4915 }
4916 }
4917 if (ANDSI (FLD (f_reglist_hi_ld), 4)) {
4918 {
4919 {
4920 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4921 CPU (h_gr[((UINT) 10)]) = opval;
4922 written |= (1 << 3);
4923 TRACE_RESULT (current_cpu, abuf, "gr-10", 'x', opval);
4924 }
4925 {
4926 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4927 CPU (h_gr[((UINT) 15)]) = opval;
4928 written |= (1 << 8);
4929 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4930 }
4931 }
4932 }
4933 if (ANDSI (FLD (f_reglist_hi_ld), 8)) {
4934 {
4935 {
4936 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4937 CPU (h_gr[((UINT) 11)]) = opval;
4938 written |= (1 << 4);
4939 TRACE_RESULT (current_cpu, abuf, "gr-11", 'x', opval);
4940 }
4941 {
4942 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4943 CPU (h_gr[((UINT) 15)]) = opval;
4944 written |= (1 << 8);
4945 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4946 }
4947 }
4948 }
4949 if (ANDSI (FLD (f_reglist_hi_ld), 16)) {
4950 {
4951 {
4952 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4953 CPU (h_gr[((UINT) 12)]) = opval;
4954 written |= (1 << 5);
4955 TRACE_RESULT (current_cpu, abuf, "gr-12", 'x', opval);
4956 }
4957 {
4958 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4959 CPU (h_gr[((UINT) 15)]) = opval;
4960 written |= (1 << 8);
4961 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4962 }
4963 }
4964 }
4965 if (ANDSI (FLD (f_reglist_hi_ld), 32)) {
4966 {
4967 {
4968 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4969 CPU (h_gr[((UINT) 13)]) = opval;
4970 written |= (1 << 6);
4971 TRACE_RESULT (current_cpu, abuf, "gr-13", 'x', opval);
4972 }
4973 {
4974 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4975 CPU (h_gr[((UINT) 15)]) = opval;
4976 written |= (1 << 8);
4977 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4978 }
4979 }
4980 }
4981 if (ANDSI (FLD (f_reglist_hi_ld), 64)) {
4982 {
4983 {
4984 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
4985 CPU (h_gr[((UINT) 14)]) = opval;
4986 written |= (1 << 7);
4987 TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
4988 }
4989 {
4990 SI opval = ADDSI (CPU (h_gr[((UINT) 15)]), 4);
4991 CPU (h_gr[((UINT) 15)]) = opval;
4992 written |= (1 << 8);
4993 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
4994 }
4995 }
4996 }
4997 if (ANDSI (FLD (f_reglist_hi_ld), 128)) {
4998 {
4999 SI opval = GETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]));
5000 CPU (h_gr[((UINT) 15)]) = opval;
5001 written |= (1 << 8);
5002 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5003 }
5004 }
5005 }
5006
5007 abuf->written = written;
5008 #undef FLD
5009 }
5010 NEXT (vpc);
5011
5012 CASE (sem, INSN_STM0) : /* stm0 ($reglist_low_st) */
5013 {
5014 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5015 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5016 #define FLD(f) abuf->fields.sfmt_stm0.f
5017 int UNUSED written = 0;
5018 IADDR UNUSED pc = abuf->addr;
5019 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5020
5021 {
5022 if (ANDSI (FLD (f_reglist_low_st), 1)) {
5023 {
5024 {
5025 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5026 CPU (h_gr[((UINT) 15)]) = opval;
5027 written |= (1 << 10);
5028 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5029 }
5030 {
5031 SI opval = CPU (h_gr[((UINT) 7)]);
5032 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5033 written |= (1 << 11);
5034 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5035 }
5036 }
5037 }
5038 if (ANDSI (FLD (f_reglist_low_st), 2)) {
5039 {
5040 {
5041 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5042 CPU (h_gr[((UINT) 15)]) = opval;
5043 written |= (1 << 10);
5044 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5045 }
5046 {
5047 SI opval = CPU (h_gr[((UINT) 6)]);
5048 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5049 written |= (1 << 11);
5050 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5051 }
5052 }
5053 }
5054 if (ANDSI (FLD (f_reglist_low_st), 4)) {
5055 {
5056 {
5057 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5058 CPU (h_gr[((UINT) 15)]) = opval;
5059 written |= (1 << 10);
5060 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5061 }
5062 {
5063 SI opval = CPU (h_gr[((UINT) 5)]);
5064 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5065 written |= (1 << 11);
5066 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5067 }
5068 }
5069 }
5070 if (ANDSI (FLD (f_reglist_low_st), 8)) {
5071 {
5072 {
5073 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5074 CPU (h_gr[((UINT) 15)]) = opval;
5075 written |= (1 << 10);
5076 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5077 }
5078 {
5079 SI opval = CPU (h_gr[((UINT) 4)]);
5080 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5081 written |= (1 << 11);
5082 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5083 }
5084 }
5085 }
5086 if (ANDSI (FLD (f_reglist_low_st), 16)) {
5087 {
5088 {
5089 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5090 CPU (h_gr[((UINT) 15)]) = opval;
5091 written |= (1 << 10);
5092 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5093 }
5094 {
5095 SI opval = CPU (h_gr[((UINT) 3)]);
5096 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5097 written |= (1 << 11);
5098 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5099 }
5100 }
5101 }
5102 if (ANDSI (FLD (f_reglist_low_st), 32)) {
5103 {
5104 {
5105 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5106 CPU (h_gr[((UINT) 15)]) = opval;
5107 written |= (1 << 10);
5108 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5109 }
5110 {
5111 SI opval = CPU (h_gr[((UINT) 2)]);
5112 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5113 written |= (1 << 11);
5114 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5115 }
5116 }
5117 }
5118 if (ANDSI (FLD (f_reglist_low_st), 64)) {
5119 {
5120 {
5121 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5122 CPU (h_gr[((UINT) 15)]) = opval;
5123 written |= (1 << 10);
5124 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5125 }
5126 {
5127 SI opval = CPU (h_gr[((UINT) 1)]);
5128 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5129 written |= (1 << 11);
5130 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5131 }
5132 }
5133 }
5134 if (ANDSI (FLD (f_reglist_low_st), 128)) {
5135 {
5136 {
5137 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5138 CPU (h_gr[((UINT) 15)]) = opval;
5139 written |= (1 << 10);
5140 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5141 }
5142 {
5143 SI opval = CPU (h_gr[((UINT) 0)]);
5144 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5145 written |= (1 << 11);
5146 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5147 }
5148 }
5149 }
5150 }
5151
5152 abuf->written = written;
5153 #undef FLD
5154 }
5155 NEXT (vpc);
5156
5157 CASE (sem, INSN_STM1) : /* stm1 ($reglist_hi_st) */
5158 {
5159 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5160 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5161 #define FLD(f) abuf->fields.sfmt_stm1.f
5162 int UNUSED written = 0;
5163 IADDR UNUSED pc = abuf->addr;
5164 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5165
5166 {
5167 if (ANDSI (FLD (f_reglist_hi_st), 1)) {
5168 {
5169 SI tmp_save_r15;
5170 tmp_save_r15 = CPU (h_gr[((UINT) 15)]);
5171 {
5172 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5173 CPU (h_gr[((UINT) 15)]) = opval;
5174 written |= (1 << 9);
5175 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5176 }
5177 {
5178 SI opval = tmp_save_r15;
5179 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5180 written |= (1 << 10);
5181 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5182 }
5183 }
5184 }
5185 if (ANDSI (FLD (f_reglist_hi_st), 2)) {
5186 {
5187 {
5188 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5189 CPU (h_gr[((UINT) 15)]) = opval;
5190 written |= (1 << 9);
5191 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5192 }
5193 {
5194 SI opval = CPU (h_gr[((UINT) 14)]);
5195 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5196 written |= (1 << 10);
5197 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5198 }
5199 }
5200 }
5201 if (ANDSI (FLD (f_reglist_hi_st), 4)) {
5202 {
5203 {
5204 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5205 CPU (h_gr[((UINT) 15)]) = opval;
5206 written |= (1 << 9);
5207 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5208 }
5209 {
5210 SI opval = CPU (h_gr[((UINT) 13)]);
5211 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5212 written |= (1 << 10);
5213 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5214 }
5215 }
5216 }
5217 if (ANDSI (FLD (f_reglist_hi_st), 8)) {
5218 {
5219 {
5220 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5221 CPU (h_gr[((UINT) 15)]) = opval;
5222 written |= (1 << 9);
5223 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5224 }
5225 {
5226 SI opval = CPU (h_gr[((UINT) 12)]);
5227 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5228 written |= (1 << 10);
5229 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5230 }
5231 }
5232 }
5233 if (ANDSI (FLD (f_reglist_hi_st), 16)) {
5234 {
5235 {
5236 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5237 CPU (h_gr[((UINT) 15)]) = opval;
5238 written |= (1 << 9);
5239 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5240 }
5241 {
5242 SI opval = CPU (h_gr[((UINT) 11)]);
5243 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5244 written |= (1 << 10);
5245 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5246 }
5247 }
5248 }
5249 if (ANDSI (FLD (f_reglist_hi_st), 32)) {
5250 {
5251 {
5252 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5253 CPU (h_gr[((UINT) 15)]) = opval;
5254 written |= (1 << 9);
5255 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5256 }
5257 {
5258 SI opval = CPU (h_gr[((UINT) 10)]);
5259 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5260 written |= (1 << 10);
5261 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5262 }
5263 }
5264 }
5265 if (ANDSI (FLD (f_reglist_hi_st), 64)) {
5266 {
5267 {
5268 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5269 CPU (h_gr[((UINT) 15)]) = opval;
5270 written |= (1 << 9);
5271 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5272 }
5273 {
5274 SI opval = CPU (h_gr[((UINT) 9)]);
5275 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5276 written |= (1 << 10);
5277 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5278 }
5279 }
5280 }
5281 if (ANDSI (FLD (f_reglist_hi_st), 128)) {
5282 {
5283 {
5284 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5285 CPU (h_gr[((UINT) 15)]) = opval;
5286 written |= (1 << 9);
5287 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5288 }
5289 {
5290 SI opval = CPU (h_gr[((UINT) 8)]);
5291 SETMEMSI (current_cpu, pc, CPU (h_gr[((UINT) 15)]), opval);
5292 written |= (1 << 10);
5293 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5294 }
5295 }
5296 }
5297 }
5298
5299 abuf->written = written;
5300 #undef FLD
5301 }
5302 NEXT (vpc);
5303
5304 CASE (sem, INSN_ENTER) : /* enter $u10 */
5305 {
5306 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5307 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5308 #define FLD(f) abuf->fields.sfmt_enter.f
5309 int UNUSED written = 0;
5310 IADDR UNUSED pc = abuf->addr;
5311 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5312
5313 {
5314 SI tmp_tmp;
5315 tmp_tmp = SUBSI (CPU (h_gr[((UINT) 15)]), 4);
5316 {
5317 SI opval = CPU (h_gr[((UINT) 14)]);
5318 SETMEMSI (current_cpu, pc, tmp_tmp, opval);
5319 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5320 }
5321 {
5322 SI opval = tmp_tmp;
5323 CPU (h_gr[((UINT) 14)]) = opval;
5324 TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
5325 }
5326 {
5327 SI opval = SUBSI (CPU (h_gr[((UINT) 15)]), FLD (f_u10));
5328 CPU (h_gr[((UINT) 15)]) = opval;
5329 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5330 }
5331 }
5332
5333 #undef FLD
5334 }
5335 NEXT (vpc);
5336
5337 CASE (sem, INSN_LEAVE) : /* leave */
5338 {
5339 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5340 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5341 #define FLD(f) abuf->fields.sfmt_enter.f
5342 int UNUSED written = 0;
5343 IADDR UNUSED pc = abuf->addr;
5344 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5345
5346 {
5347 {
5348 SI opval = ADDSI (CPU (h_gr[((UINT) 14)]), 4);
5349 CPU (h_gr[((UINT) 15)]) = opval;
5350 TRACE_RESULT (current_cpu, abuf, "gr-15", 'x', opval);
5351 }
5352 {
5353 SI opval = GETMEMSI (current_cpu, pc, SUBSI (CPU (h_gr[((UINT) 15)]), 4));
5354 CPU (h_gr[((UINT) 14)]) = opval;
5355 TRACE_RESULT (current_cpu, abuf, "gr-14", 'x', opval);
5356 }
5357 }
5358
5359 #undef FLD
5360 }
5361 NEXT (vpc);
5362
5363 CASE (sem, INSN_XCHB) : /* xchb @$Rj,$Ri */
5364 {
5365 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
5366 ARGBUF *abuf = SEM_ARGBUF (sem_arg);
5367 #define FLD(f) abuf->fields.sfmt_add.f
5368 int UNUSED written = 0;
5369 IADDR UNUSED pc = abuf->addr;
5370 vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
5371
5372 {
5373 SI tmp_tmp;
5374 tmp_tmp = * FLD (i_Ri);
5375 {
5376 SI opval = GETMEMUQI (current_cpu, pc, * FLD (i_Rj));
5377 * FLD (i_Ri) = opval;
5378 TRACE_RESULT (current_cpu, abuf, "Ri", 'x', opval);
5379 }
5380 {
5381 UQI opval = tmp_tmp;
5382 SETMEMUQI (current_cpu, pc, * FLD (i_Rj), opval);
5383 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
5384 }
5385 }
5386
5387 #undef FLD
5388 }
5389 NEXT (vpc);
5390
5391
5392 }
5393 ENDSWITCH (sem) /* End of semantic switch. */
5394
5395 /* At this point `vpc' contains the next insn to execute. */
5396 }
5397
5398 #undef DEFINE_SWITCH
5399 #endif /* DEFINE_SWITCH */