1 /* frv simulator fr400 dependent profiling code.
3 Copyright (C) 2001 Free Software Foundation, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License along
19 with this program; if not, write to the Free Software Foundation, Inc.,
20 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 #define WANT_CPU_FRVBF
29 #if WITH_PROFILE_MODEL_P
32 #include "profile-fr400.h"
34 /* These functions get and set flags representing the use of
35 registers/resources. */
36 static void set_use_not_fp_load (SIM_CPU
*, INT
);
37 static void set_use_not_media_p4 (SIM_CPU
*, INT
);
38 static void set_use_not_media_p6 (SIM_CPU
*, INT
);
40 static void set_acc_use_not_media_p2 (SIM_CPU
*, INT
);
41 static void set_acc_use_not_media_p4 (SIM_CPU
*, INT
);
44 fr400_reset_gr_flags (SIM_CPU
*cpu
, INT fr
)
46 set_use_not_gr_complex (cpu
, fr
);
50 fr400_reset_fr_flags (SIM_CPU
*cpu
, INT fr
)
52 set_use_not_fp_load (cpu
, fr
);
53 set_use_not_media_p4 (cpu
, fr
);
54 set_use_not_media_p6 (cpu
, fr
);
58 fr400_reset_acc_flags (SIM_CPU
*cpu
, INT acc
)
60 set_acc_use_not_media_p2 (cpu
, acc
);
61 set_acc_use_not_media_p4 (cpu
, acc
);
65 set_use_is_fp_load (SIM_CPU
*cpu
, INT fr
, INT fr_double
)
67 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
70 fr400_reset_fr_flags (cpu
, fr
);
71 d
->cur_fp_load
|= (((DI
)1) << fr
);
75 fr400_reset_fr_flags (cpu
, fr_double
);
76 d
->cur_fp_load
|= (((DI
)1) << fr_double
);
79 fr400_reset_fr_flags (cpu
, fr_double
+ 1);
80 d
->cur_fp_load
|= (((DI
)1) << (fr_double
+ 1));
87 set_use_not_fp_load (SIM_CPU
*cpu
, INT fr
)
89 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
91 d
->cur_fp_load
&= ~(((DI
)1) << fr
);
95 use_is_fp_load (SIM_CPU
*cpu
, INT fr
)
97 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
99 return (d
->prev_fp_load
>> fr
) & 1;
104 set_acc_use_is_media_p2 (SIM_CPU
*cpu
, INT acc
)
106 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
109 fr400_reset_acc_flags (cpu
, acc
);
110 d
->cur_acc_p2
|= (((DI
)1) << acc
);
115 set_acc_use_not_media_p2 (SIM_CPU
*cpu
, INT acc
)
117 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
119 d
->cur_acc_p2
&= ~(((DI
)1) << acc
);
123 acc_use_is_media_p2 (SIM_CPU
*cpu
, INT acc
)
125 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
127 return d
->cur_acc_p2
& (((DI
)1) << acc
);
132 set_use_is_media_p4 (SIM_CPU
*cpu
, INT fr
)
134 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
137 fr400_reset_fr_flags (cpu
, fr
);
138 d
->cur_fr_p4
|= (((DI
)1) << fr
);
143 set_use_not_media_p4 (SIM_CPU
*cpu
, INT fr
)
145 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
147 d
->cur_fr_p4
&= ~(((DI
)1) << fr
);
151 use_is_media_p4 (SIM_CPU
*cpu
, INT fr
)
153 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
155 return d
->cur_fr_p4
& (((DI
)1) << fr
);
160 set_acc_use_is_media_p4 (SIM_CPU
*cpu
, INT acc
)
162 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
165 fr400_reset_acc_flags (cpu
, acc
);
166 d
->cur_acc_p4
|= (((DI
)1) << acc
);
171 set_acc_use_not_media_p4 (SIM_CPU
*cpu
, INT acc
)
173 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
175 d
->cur_acc_p4
&= ~(((DI
)1) << acc
);
179 acc_use_is_media_p4 (SIM_CPU
*cpu
, INT acc
)
181 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
183 return d
->cur_acc_p4
& (((DI
)1) << acc
);
188 set_use_is_media_p6 (SIM_CPU
*cpu
, INT fr
)
190 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
193 fr400_reset_fr_flags (cpu
, fr
);
194 d
->cur_fr_p6
|= (((DI
)1) << fr
);
199 set_use_not_media_p6 (SIM_CPU
*cpu
, INT fr
)
201 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
203 d
->cur_fr_p6
&= ~(((DI
)1) << fr
);
207 use_is_media_p6 (SIM_CPU
*cpu
, INT fr
)
209 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
211 return d
->cur_fr_p6
& (((DI
)1) << fr
);
215 /* Initialize cycle counting for an insn.
216 FIRST_P is non-zero if this is the first insn in a set of parallel
219 fr400_model_insn_before (SIM_CPU
*cpu
, int first_p
)
223 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
224 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
225 ps
->cur_gr_complex
= ps
->prev_gr_complex
;
226 d
->cur_fp_load
= d
->prev_fp_load
;
227 d
->cur_fr_p4
= d
->prev_fr_p4
;
228 d
->cur_fr_p6
= d
->prev_fr_p6
;
229 d
->cur_acc_p2
= d
->prev_acc_p2
;
230 d
->cur_acc_p4
= d
->prev_acc_p4
;
234 /* Record the cycles computed for an insn.
235 LAST_P is non-zero if this is the last insn in a set of parallel insns,
236 and we update the total cycle count.
237 CYCLES is the cycle count of the insn. */
239 fr400_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
243 MODEL_FR400_DATA
*d
= CPU_MODEL_DATA (cpu
);
244 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
245 ps
->prev_gr_complex
= ps
->cur_gr_complex
;
246 d
->prev_fp_load
= d
->cur_fp_load
;
247 d
->prev_fr_p4
= d
->cur_fr_p4
;
248 d
->prev_fr_p6
= d
->cur_fr_p6
;
249 d
->prev_acc_p2
= d
->cur_acc_p2
;
250 d
->prev_acc_p4
= d
->cur_acc_p4
;
255 frvbf_model_fr400_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
256 int unit_num
, int referenced
)
258 return idesc
->timing
->units
[unit_num
].done
;
262 frvbf_model_fr400_u_integer (SIM_CPU
*cpu
, const IDESC
*idesc
,
263 int unit_num
, int referenced
,
264 INT in_GRi
, INT in_GRj
, INT out_GRk
,
267 /* Modelling for this unit is the same as for fr500. */
268 return frvbf_model_fr500_u_integer (cpu
, idesc
, unit_num
, referenced
,
269 in_GRi
, in_GRj
, out_GRk
, out_ICCi_1
);
273 frvbf_model_fr400_u_imul (SIM_CPU
*cpu
, const IDESC
*idesc
,
274 int unit_num
, int referenced
,
275 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
277 /* Modelling for this unit is the same as for fr500. */
278 return frvbf_model_fr500_u_imul (cpu
, idesc
, unit_num
, referenced
,
279 in_GRi
, in_GRj
, out_GRk
, out_ICCi_1
);
283 frvbf_model_fr400_u_idiv (SIM_CPU
*cpu
, const IDESC
*idesc
,
284 int unit_num
, int referenced
,
285 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
291 /* icc0-icc4 are the upper 4 fields of the CCR. */
295 vliw
= CPU_VLIW (cpu
);
296 slot
= vliw
->next_slot
- 1;
297 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_I0
;
299 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
301 /* The entire VLIW insn must wait if there is a dependency on a register
302 which is not ready yet.
303 The latency of the registers may be less than previously recorded,
304 depending on how they were used previously.
305 See Table 13-8 in the LSI. */
306 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
308 if (use_is_gr_complex (cpu
, in_GRi
))
309 decrease_GR_busy (cpu
, in_GRi
, 1);
311 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
313 if (use_is_gr_complex (cpu
, in_GRj
))
314 decrease_GR_busy (cpu
, in_GRj
, 1);
316 vliw_wait_for_GR (cpu
, in_GRi
);
317 vliw_wait_for_GR (cpu
, in_GRj
);
318 vliw_wait_for_GR (cpu
, out_GRk
);
319 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
320 vliw_wait_for_idiv_resource (cpu
, slot
);
321 handle_resource_wait (cpu
);
322 load_wait_for_GR (cpu
, in_GRi
);
323 load_wait_for_GR (cpu
, in_GRj
);
324 load_wait_for_GR (cpu
, out_GRk
);
325 trace_vliw_wait_cycles (cpu
);
329 /* GRk has a latency of 19 cycles! */
330 cycles
= idesc
->timing
->units
[unit_num
].done
;
331 update_GR_latency (cpu
, out_GRk
, cycles
+ 19);
332 set_use_is_gr_complex (cpu
, out_GRk
);
334 /* ICCi_1 has a latency of 18 cycles. */
335 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 18);
337 /* the idiv resource has a latency of 18 cycles! */
338 update_idiv_resource_latency (cpu
, slot
, cycles
+ 18);
344 frvbf_model_fr400_u_branch (SIM_CPU
*cpu
, const IDESC
*idesc
,
345 int unit_num
, int referenced
,
346 INT in_GRi
, INT in_GRj
,
347 INT in_ICCi_2
, INT in_ICCi_3
)
349 #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2)
350 FRV_PROFILE_STATE
*ps
;
353 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
355 /* Modelling for this unit is the same as for fr500 in pass 1. */
356 return frvbf_model_fr500_u_branch (cpu
, idesc
, unit_num
, referenced
,
357 in_GRi
, in_GRj
, in_ICCi_2
, in_ICCi_3
);
360 cycles
= idesc
->timing
->units
[unit_num
].done
;
362 /* Compute the branch penalty, based on the the prediction and the out
363 come. When counting branches taken or not taken, don't consider branches
364 after the first taken branch in a vliw insn. */
365 ps
= CPU_PROFILE_STATE (cpu
);
366 if (! ps
->vliw_branch_taken
)
369 /* (1 << 4): The pc is the 5th element in inputs, outputs.
370 ??? can be cleaned up */
371 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
372 int taken
= (referenced
& (1 << 4)) != 0;
375 ++PROFILE_MODEL_TAKEN_COUNT (p
);
376 ps
->vliw_branch_taken
= 1;
377 if (BRANCH_PREDICTED (ps
))
384 ++PROFILE_MODEL_UNTAKEN_COUNT (p
);
385 if (BRANCH_PREDICTED (ps
))
392 /* Additional 1 cycle penalty if the branch address is not 8 byte
394 if (ps
->branch_address
& 7)
396 update_branch_penalty (cpu
, penalty
);
397 PROFILE_MODEL_CTI_STALL_CYCLES (p
) += penalty
;
405 frvbf_model_fr400_u_trap (SIM_CPU
*cpu
, const IDESC
*idesc
,
406 int unit_num
, int referenced
,
407 INT in_GRi
, INT in_GRj
,
408 INT in_ICCi_2
, INT in_FCCi_2
)
410 /* Modelling for this unit is the same as for fr500. */
411 return frvbf_model_fr500_u_trap (cpu
, idesc
, unit_num
, referenced
,
412 in_GRi
, in_GRj
, in_ICCi_2
, in_FCCi_2
);
416 frvbf_model_fr400_u_check (SIM_CPU
*cpu
, const IDESC
*idesc
,
417 int unit_num
, int referenced
,
418 INT in_ICCi_3
, INT in_FCCi_3
)
420 /* Modelling for this unit is the same as for fr500. */
421 return frvbf_model_fr500_u_check (cpu
, idesc
, unit_num
, referenced
,
422 in_ICCi_3
, in_FCCi_3
);
426 frvbf_model_fr400_u_set_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
427 int unit_num
, int referenced
,
428 INT out_GRkhi
, INT out_GRklo
)
430 /* Modelling for this unit is the same as for fr500. */
431 return frvbf_model_fr500_u_set_hilo (cpu
, idesc
, unit_num
, referenced
,
432 out_GRkhi
, out_GRklo
);
436 frvbf_model_fr400_u_gr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
437 int unit_num
, int referenced
,
438 INT in_GRi
, INT in_GRj
,
439 INT out_GRk
, INT out_GRdoublek
)
441 /* Modelling for this unit is the same as for fr500. */
442 return frvbf_model_fr500_u_gr_load (cpu
, idesc
, unit_num
, referenced
,
443 in_GRi
, in_GRj
, out_GRk
, out_GRdoublek
);
447 frvbf_model_fr400_u_gr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
448 int unit_num
, int referenced
,
449 INT in_GRi
, INT in_GRj
,
450 INT in_GRk
, INT in_GRdoublek
)
452 /* Modelling for this unit is the same as for fr500. */
453 return frvbf_model_fr500_u_gr_store (cpu
, idesc
, unit_num
, referenced
,
454 in_GRi
, in_GRj
, in_GRk
, in_GRdoublek
);
458 frvbf_model_fr400_u_fr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
459 int unit_num
, int referenced
,
460 INT in_GRi
, INT in_GRj
,
461 INT out_FRk
, INT out_FRdoublek
)
465 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
467 /* Pass 1 is the same as for fr500. */
468 return frvbf_model_fr500_u_fr_load (cpu
, idesc
, unit_num
, referenced
,
469 in_GRi
, in_GRj
, out_FRk
,
473 cycles
= idesc
->timing
->units
[unit_num
].done
;
475 /* The latency of FRk for a load will depend on how long it takes to retrieve
476 the the data from the cache or memory. */
477 update_FR_latency_for_load (cpu
, out_FRk
, cycles
);
478 update_FRdouble_latency_for_load (cpu
, out_FRdoublek
, cycles
);
480 set_use_is_fp_load (cpu
, out_FRk
, out_FRdoublek
);
486 frvbf_model_fr400_u_fr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
487 int unit_num
, int referenced
,
488 INT in_GRi
, INT in_GRj
,
489 INT in_FRk
, INT in_FRdoublek
)
493 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
495 /* The entire VLIW insn must wait if there is a dependency on a register
496 which is not ready yet.
497 The latency of the registers may be less than previously recorded,
498 depending on how they were used previously.
499 See Table 13-8 in the LSI. */
502 if (use_is_gr_complex (cpu
, in_GRi
))
503 decrease_GR_busy (cpu
, in_GRi
, 1);
505 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
507 if (use_is_gr_complex (cpu
, in_GRj
))
508 decrease_GR_busy (cpu
, in_GRj
, 1);
512 if (use_is_media_p4 (cpu
, in_FRk
) || use_is_media_p6 (cpu
, in_FRk
))
513 decrease_FR_busy (cpu
, in_FRk
, 1);
515 enforce_full_fr_latency (cpu
, in_FRk
);
517 vliw_wait_for_GR (cpu
, in_GRi
);
518 vliw_wait_for_GR (cpu
, in_GRj
);
519 vliw_wait_for_FR (cpu
, in_FRk
);
520 vliw_wait_for_FRdouble (cpu
, in_FRdoublek
);
521 handle_resource_wait (cpu
);
522 load_wait_for_GR (cpu
, in_GRi
);
523 load_wait_for_GR (cpu
, in_GRj
);
524 load_wait_for_FR (cpu
, in_FRk
);
525 load_wait_for_FRdouble (cpu
, in_FRdoublek
);
526 trace_vliw_wait_cycles (cpu
);
530 cycles
= idesc
->timing
->units
[unit_num
].done
;
536 frvbf_model_fr400_u_swap (SIM_CPU
*cpu
, const IDESC
*idesc
,
537 int unit_num
, int referenced
,
538 INT in_GRi
, INT in_GRj
, INT out_GRk
)
540 /* Modelling for this unit is the same as for fr500. */
541 return frvbf_model_fr500_u_swap (cpu
, idesc
, unit_num
, referenced
,
542 in_GRi
, in_GRj
, out_GRk
);
546 frvbf_model_fr400_u_fr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
547 int unit_num
, int referenced
,
548 INT in_FRk
, INT out_GRj
)
552 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
554 /* The entire VLIW insn must wait if there is a dependency on a register
555 which is not ready yet.
556 The latency of the registers may be less than previously recorded,
557 depending on how they were used previously.
558 See Table 13-8 in the LSI. */
561 if (use_is_media_p4 (cpu
, in_FRk
) || use_is_media_p6 (cpu
, in_FRk
))
562 decrease_FR_busy (cpu
, in_FRk
, 1);
564 enforce_full_fr_latency (cpu
, in_FRk
);
566 vliw_wait_for_FR (cpu
, in_FRk
);
567 vliw_wait_for_GR (cpu
, out_GRj
);
568 handle_resource_wait (cpu
);
569 load_wait_for_FR (cpu
, in_FRk
);
570 load_wait_for_GR (cpu
, out_GRj
);
571 trace_vliw_wait_cycles (cpu
);
575 /* The latency of GRj is 2 cycles. */
576 cycles
= idesc
->timing
->units
[unit_num
].done
;
577 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
578 set_use_is_gr_complex (cpu
, out_GRj
);
584 frvbf_model_fr400_u_spr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
585 int unit_num
, int referenced
,
586 INT in_spr
, INT out_GRj
)
588 /* Modelling for this unit is the same as for fr500. */
589 return frvbf_model_fr500_u_spr2gr (cpu
, idesc
, unit_num
, referenced
,
594 frvbf_model_fr400_u_gr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
595 int unit_num
, int referenced
,
596 INT in_GRj
, INT out_FRk
)
600 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
602 /* Pass 1 is the same as for fr500. */
603 frvbf_model_fr500_u_gr2fr (cpu
, idesc
, unit_num
, referenced
,
607 /* The latency of FRk is 1 cycles. */
608 cycles
= idesc
->timing
->units
[unit_num
].done
;
609 update_FR_latency (cpu
, out_FRk
, cycles
+ 1);
615 frvbf_model_fr400_u_gr2spr (SIM_CPU
*cpu
, const IDESC
*idesc
,
616 int unit_num
, int referenced
,
617 INT in_GRj
, INT out_spr
)
619 /* Modelling for this unit is the same as for fr500. */
620 return frvbf_model_fr500_u_gr2spr (cpu
, idesc
, unit_num
, referenced
,
624 /* Top up the post-processing time of the given FR by the given number of
627 update_FR_ptime (SIM_CPU
*cpu
, INT out_FR
, int cycles
)
631 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
632 /* If a load is pending on this register, then add the cycles to
633 the post processing time for this register. Otherwise apply it
634 directly to the latency of the register. */
635 if (! load_pending_for_register (cpu
, out_FR
, 1, REGTYPE_FR
))
637 int *fr
= ps
->fr_latency
;
638 fr
[out_FR
] += cycles
;
641 ps
->fr_ptime
[out_FR
] += cycles
;
646 update_FRdouble_ptime (SIM_CPU
*cpu
, INT out_FR
, int cycles
)
650 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
651 /* If a load is pending on this register, then add the cycles to
652 the post processing time for this register. Otherwise apply it
653 directly to the latency of the register. */
654 if (! load_pending_for_register (cpu
, out_FR
, 2, REGTYPE_FR
))
656 int *fr
= ps
->fr_latency
;
657 fr
[out_FR
] += cycles
;
659 fr
[out_FR
+ 1] += cycles
;
663 /* On the fr400, loads are available to media insns one cycle early,
664 so knock one cycle off the post processing time to account for
666 ps
->fr_ptime
[out_FR
] += cycles
- 1;
668 ps
->fr_ptime
[out_FR
+ 1] += cycles
- 1;
674 frvbf_model_fr400_u_media_1 (SIM_CPU
*cpu
, const IDESC
*idesc
,
675 int unit_num
, int referenced
,
676 INT in_FRi
, INT in_FRj
,
680 FRV_PROFILE_STATE
*ps
;
681 const CGEN_INSN
*insn
;
682 int busy_adjustment
[] = {0, 0};
685 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
688 /* The preprocessing can execute right away. */
689 cycles
= idesc
->timing
->units
[unit_num
].done
;
691 ps
= CPU_PROFILE_STATE (cpu
);
694 /* The latency of the registers may be less than previously recorded,
695 depending on how they were used previously.
696 See Table 13-8 in the LSI. */
699 if (use_is_fp_load (cpu
, in_FRi
))
701 busy_adjustment
[0] = 1;
702 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
705 enforce_full_fr_latency (cpu
, in_FRi
);
707 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
709 if (use_is_fp_load (cpu
, in_FRj
))
711 busy_adjustment
[1] = 1;
712 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
715 enforce_full_fr_latency (cpu
, in_FRj
);
718 /* The post processing must wait if there is a dependency on a FR
719 which is not ready yet. */
720 ps
->post_wait
= cycles
;
721 post_wait_for_FR (cpu
, in_FRi
);
722 post_wait_for_FR (cpu
, in_FRj
);
723 post_wait_for_FR (cpu
, out_FRk
);
725 /* Restore the busy cycles of the registers we used. */
728 fr
[in_FRi
] += busy_adjustment
[0];
730 fr
[in_FRj
] += busy_adjustment
[1];
732 /* The latency of the output register will be at least the latency of the
733 other inputs. Once initiated, post-processing has no latency. */
736 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
737 update_FR_ptime (cpu
, out_FRk
, 0);
744 frvbf_model_fr400_u_media_1_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
745 int unit_num
, int referenced
,
746 INT in_FRi
, INT in_FRj
,
753 FRV_PROFILE_STATE
*ps
;
754 int busy_adjustment
[] = {0, 0, 0, 0};
757 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
760 /* The preprocessing can execute right away. */
761 cycles
= idesc
->timing
->units
[unit_num
].done
;
763 ps
= CPU_PROFILE_STATE (cpu
);
764 dual_FRi
= DUAL_REG (in_FRi
);
765 dual_FRj
= DUAL_REG (in_FRj
);
766 dual_FRk
= DUAL_REG (out_FRk
);
768 /* The latency of the registers may be less than previously recorded,
769 depending on how they were used previously.
770 See Table 13-8 in the LSI. */
771 if (use_is_fp_load (cpu
, in_FRi
))
773 busy_adjustment
[0] = 1;
774 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
777 enforce_full_fr_latency (cpu
, in_FRi
);
778 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
780 busy_adjustment
[1] = 1;
781 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
784 enforce_full_fr_latency (cpu
, dual_FRi
);
785 if (in_FRj
!= in_FRi
)
787 if (use_is_fp_load (cpu
, in_FRj
))
789 busy_adjustment
[2] = 1;
790 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
793 enforce_full_fr_latency (cpu
, in_FRj
);
794 if (dual_FRj
>= 0 && use_is_fp_load (cpu
, dual_FRj
))
796 busy_adjustment
[3] = 1;
797 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
800 enforce_full_fr_latency (cpu
, dual_FRj
);
803 /* The post processing must wait if there is a dependency on a FR
804 which is not ready yet. */
805 ps
->post_wait
= cycles
;
806 post_wait_for_FR (cpu
, in_FRi
);
807 post_wait_for_FR (cpu
, dual_FRi
);
808 post_wait_for_FR (cpu
, in_FRj
);
809 post_wait_for_FR (cpu
, dual_FRj
);
810 post_wait_for_FR (cpu
, out_FRk
);
811 post_wait_for_FR (cpu
, dual_FRk
);
813 /* Restore the busy cycles of the registers we used. */
815 fr
[in_FRi
] += busy_adjustment
[0];
817 fr
[dual_FRi
] += busy_adjustment
[1];
818 fr
[in_FRj
] += busy_adjustment
[2];
820 fr
[dual_FRj
] += busy_adjustment
[3];
822 /* The latency of the output register will be at least the latency of the
824 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
826 /* Once initiated, post-processing has no latency. */
827 update_FR_ptime (cpu
, out_FRk
, 0);
831 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
832 update_FR_ptime (cpu
, dual_FRk
, 0);
839 frvbf_model_fr400_u_media_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
840 int unit_num
, int referenced
,
841 INT out_FRkhi
, INT out_FRklo
)
844 FRV_PROFILE_STATE
*ps
;
846 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
849 /* The preprocessing can execute right away. */
850 cycles
= idesc
->timing
->units
[unit_num
].done
;
852 ps
= CPU_PROFILE_STATE (cpu
);
854 /* The post processing must wait if there is a dependency on a FR
855 which is not ready yet. */
856 ps
->post_wait
= cycles
;
857 post_wait_for_FR (cpu
, out_FRkhi
);
858 post_wait_for_FR (cpu
, out_FRklo
);
860 /* The latency of the output register will be at least the latency of the
861 other inputs. Once initiated, post-processing has no latency. */
864 update_FR_latency (cpu
, out_FRkhi
, ps
->post_wait
);
865 update_FR_ptime (cpu
, out_FRkhi
, 0);
869 update_FR_latency (cpu
, out_FRklo
, ps
->post_wait
);
870 update_FR_ptime (cpu
, out_FRklo
, 0);
877 frvbf_model_fr400_u_media_2 (SIM_CPU
*cpu
, const IDESC
*idesc
,
878 int unit_num
, int referenced
,
879 INT in_FRi
, INT in_FRj
,
880 INT out_ACC40Sk
, INT out_ACC40Uk
)
885 FRV_PROFILE_STATE
*ps
;
886 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
890 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
893 /* The preprocessing can execute right away. */
894 cycles
= idesc
->timing
->units
[unit_num
].done
;
896 ps
= CPU_PROFILE_STATE (cpu
);
897 dual_ACC40Sk
= DUAL_REG (out_ACC40Sk
);
898 dual_ACC40Uk
= DUAL_REG (out_ACC40Uk
);
900 /* The latency of the registers may be less than previously recorded,
901 depending on how they were used previously.
902 See Table 13-8 in the LSI. */
905 if (use_is_fp_load (cpu
, in_FRi
))
907 busy_adjustment
[0] = 1;
908 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
911 enforce_full_fr_latency (cpu
, in_FRi
);
913 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
915 if (use_is_fp_load (cpu
, in_FRj
))
917 busy_adjustment
[1] = 1;
918 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
921 enforce_full_fr_latency (cpu
, in_FRj
);
923 if (out_ACC40Sk
>= 0)
925 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
927 busy_adjustment
[2] = 1;
928 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
931 if (dual_ACC40Sk
>= 0)
933 if (acc_use_is_media_p2 (cpu
, dual_ACC40Sk
))
935 busy_adjustment
[3] = 1;
936 decrease_ACC_busy (cpu
, dual_ACC40Sk
, busy_adjustment
[3]);
939 if (out_ACC40Uk
>= 0)
941 if (acc_use_is_media_p2 (cpu
, out_ACC40Uk
))
943 busy_adjustment
[4] = 1;
944 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
947 if (dual_ACC40Uk
>= 0)
949 if (acc_use_is_media_p2 (cpu
, dual_ACC40Uk
))
951 busy_adjustment
[5] = 1;
952 decrease_ACC_busy (cpu
, dual_ACC40Uk
, busy_adjustment
[5]);
956 /* The post processing must wait if there is a dependency on a FR
957 which is not ready yet. */
958 ps
->post_wait
= cycles
;
959 post_wait_for_FR (cpu
, in_FRi
);
960 post_wait_for_FR (cpu
, in_FRj
);
961 post_wait_for_ACC (cpu
, out_ACC40Sk
);
962 post_wait_for_ACC (cpu
, dual_ACC40Sk
);
963 post_wait_for_ACC (cpu
, out_ACC40Uk
);
964 post_wait_for_ACC (cpu
, dual_ACC40Uk
);
966 /* Restore the busy cycles of the registers we used. */
969 fr
[in_FRi
] += busy_adjustment
[0];
970 fr
[in_FRj
] += busy_adjustment
[1];
971 if (out_ACC40Sk
>= 0)
972 acc
[out_ACC40Sk
] += busy_adjustment
[2];
973 if (dual_ACC40Sk
>= 0)
974 acc
[dual_ACC40Sk
] += busy_adjustment
[3];
975 if (out_ACC40Uk
>= 0)
976 acc
[out_ACC40Uk
] += busy_adjustment
[4];
977 if (dual_ACC40Uk
>= 0)
978 acc
[dual_ACC40Uk
] += busy_adjustment
[5];
980 /* The latency of the output register will be at least the latency of the
981 other inputs. Once initiated, post-processing will take 1 cycles. */
982 if (out_ACC40Sk
>= 0)
984 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
985 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
987 if (dual_ACC40Sk
>= 0)
989 update_ACC_latency (cpu
, dual_ACC40Sk
, ps
->post_wait
+ 1);
990 set_acc_use_is_media_p2 (cpu
, dual_ACC40Sk
);
992 if (out_ACC40Uk
>= 0)
994 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
995 set_acc_use_is_media_p2 (cpu
, out_ACC40Uk
);
997 if (dual_ACC40Uk
>= 0)
999 update_ACC_latency (cpu
, dual_ACC40Uk
, ps
->post_wait
+ 1);
1000 set_acc_use_is_media_p2 (cpu
, dual_ACC40Uk
);
1007 frvbf_model_fr400_u_media_2_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
1008 int unit_num
, int referenced
,
1009 INT in_FRi
, INT in_FRj
,
1010 INT out_ACC40Sk
, INT out_ACC40Uk
)
1021 FRV_PROFILE_STATE
*ps
;
1022 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0 ,0};
1026 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1029 /* The preprocessing can execute right away. */
1030 cycles
= idesc
->timing
->units
[unit_num
].done
;
1032 dual_FRi
= DUAL_REG (in_FRi
);
1033 dual_FRj
= DUAL_REG (in_FRj
);
1034 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1035 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
1036 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
1037 ACC40Uk_1
= DUAL_REG (out_ACC40Uk
);
1038 ACC40Uk_2
= DUAL_REG (ACC40Uk_1
);
1039 ACC40Uk_3
= DUAL_REG (ACC40Uk_2
);
1041 ps
= CPU_PROFILE_STATE (cpu
);
1042 /* The latency of the registers may be less than previously recorded,
1043 depending on how they were used previously.
1044 See Table 13-8 in the LSI. */
1045 if (use_is_fp_load (cpu
, in_FRi
))
1047 busy_adjustment
[0] = 1;
1048 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1051 enforce_full_fr_latency (cpu
, in_FRi
);
1052 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
1054 busy_adjustment
[1] = 1;
1055 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
1058 enforce_full_fr_latency (cpu
, dual_FRi
);
1059 if (in_FRj
!= in_FRi
)
1061 if (use_is_fp_load (cpu
, in_FRj
))
1063 busy_adjustment
[2] = 1;
1064 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
1067 enforce_full_fr_latency (cpu
, in_FRj
);
1068 if (dual_FRj
>= 0 && use_is_fp_load (cpu
, dual_FRj
))
1070 busy_adjustment
[3] = 1;
1071 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
1074 enforce_full_fr_latency (cpu
, dual_FRj
);
1076 if (out_ACC40Sk
>= 0)
1078 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1080 busy_adjustment
[4] = 1;
1081 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1085 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1087 busy_adjustment
[5] = 1;
1088 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1093 if (acc_use_is_media_p2 (cpu
, ACC40Sk_2
))
1095 busy_adjustment
[6] = 1;
1096 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
1101 if (acc_use_is_media_p2 (cpu
, ACC40Sk_3
))
1103 busy_adjustment
[7] = 1;
1104 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
1108 else if (out_ACC40Uk
>= 0)
1110 if (acc_use_is_media_p2 (cpu
, out_ACC40Uk
))
1112 busy_adjustment
[4] = 1;
1113 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
1117 if (acc_use_is_media_p2 (cpu
, ACC40Uk_1
))
1119 busy_adjustment
[5] = 1;
1120 decrease_ACC_busy (cpu
, ACC40Uk_1
, busy_adjustment
[5]);
1125 if (acc_use_is_media_p2 (cpu
, ACC40Uk_2
))
1127 busy_adjustment
[6] = 1;
1128 decrease_ACC_busy (cpu
, ACC40Uk_2
, busy_adjustment
[6]);
1133 if (acc_use_is_media_p2 (cpu
, ACC40Uk_3
))
1135 busy_adjustment
[7] = 1;
1136 decrease_ACC_busy (cpu
, ACC40Uk_3
, busy_adjustment
[7]);
1141 /* The post processing must wait if there is a dependency on a FR
1142 which is not ready yet. */
1143 ps
->post_wait
= cycles
;
1144 post_wait_for_FR (cpu
, in_FRi
);
1145 post_wait_for_FR (cpu
, dual_FRi
);
1146 post_wait_for_FR (cpu
, in_FRj
);
1147 post_wait_for_FR (cpu
, dual_FRj
);
1148 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1149 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1150 post_wait_for_ACC (cpu
, ACC40Sk_2
);
1151 post_wait_for_ACC (cpu
, ACC40Sk_3
);
1152 post_wait_for_ACC (cpu
, out_ACC40Uk
);
1153 post_wait_for_ACC (cpu
, ACC40Uk_1
);
1154 post_wait_for_ACC (cpu
, ACC40Uk_2
);
1155 post_wait_for_ACC (cpu
, ACC40Uk_3
);
1157 /* Restore the busy cycles of the registers we used. */
1160 fr
[in_FRi
] += busy_adjustment
[0];
1162 fr
[dual_FRi
] += busy_adjustment
[1];
1163 fr
[in_FRj
] += busy_adjustment
[2];
1165 fr
[dual_FRj
] += busy_adjustment
[3];
1166 if (out_ACC40Sk
>= 0)
1168 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1170 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1172 acc
[ACC40Sk_2
] += busy_adjustment
[6];
1174 acc
[ACC40Sk_3
] += busy_adjustment
[7];
1176 else if (out_ACC40Uk
>= 0)
1178 acc
[out_ACC40Uk
] += busy_adjustment
[4];
1180 acc
[ACC40Uk_1
] += busy_adjustment
[5];
1182 acc
[ACC40Uk_2
] += busy_adjustment
[6];
1184 acc
[ACC40Uk_3
] += busy_adjustment
[7];
1187 /* The latency of the output register will be at least the latency of the
1188 other inputs. Once initiated, post-processing will take 1 cycle. */
1189 if (out_ACC40Sk
>= 0)
1191 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1193 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1196 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1198 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1202 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
1204 set_acc_use_is_media_p2 (cpu
, ACC40Sk_2
);
1208 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
1210 set_acc_use_is_media_p2 (cpu
, ACC40Sk_3
);
1213 else if (out_ACC40Uk
>= 0)
1215 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
1217 set_acc_use_is_media_p2 (cpu
, out_ACC40Uk
);
1220 update_ACC_latency (cpu
, ACC40Uk_1
, ps
->post_wait
+ 1);
1222 set_acc_use_is_media_p2 (cpu
, ACC40Uk_1
);
1226 update_ACC_latency (cpu
, ACC40Uk_2
, ps
->post_wait
+ 1);
1228 set_acc_use_is_media_p2 (cpu
, ACC40Uk_2
);
1232 update_ACC_latency (cpu
, ACC40Uk_3
, ps
->post_wait
+ 1);
1234 set_acc_use_is_media_p2 (cpu
, ACC40Uk_3
);
1242 frvbf_model_fr400_u_media_2_acc (SIM_CPU
*cpu
, const IDESC
*idesc
,
1243 int unit_num
, int referenced
,
1244 INT in_ACC40Si
, INT out_ACC40Sk
)
1248 FRV_PROFILE_STATE
*ps
;
1249 int busy_adjustment
[] = {0, 0, 0};
1252 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1255 /* The preprocessing can execute right away. */
1256 cycles
= idesc
->timing
->units
[unit_num
].done
;
1258 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1260 ps
= CPU_PROFILE_STATE (cpu
);
1261 /* The latency of the registers may be less than previously recorded,
1262 depending on how they were used previously.
1263 See Table 13-8 in the LSI. */
1264 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1266 busy_adjustment
[0] = 1;
1267 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1269 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1271 busy_adjustment
[1] = 1;
1272 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1274 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1275 && acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1277 busy_adjustment
[2] = 1;
1278 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
1281 /* The post processing must wait if there is a dependency on a register
1282 which is not ready yet. */
1283 ps
->post_wait
= cycles
;
1284 post_wait_for_ACC (cpu
, in_ACC40Si
);
1285 post_wait_for_ACC (cpu
, ACC40Si_1
);
1286 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1288 /* Restore the busy cycles of the registers we used. */
1290 acc
[in_ACC40Si
] += busy_adjustment
[0];
1292 acc
[ACC40Si_1
] += busy_adjustment
[1];
1293 acc
[out_ACC40Sk
] += busy_adjustment
[2];
1295 /* The latency of the output register will be at least the latency of the
1296 other inputs. Once initiated, post-processing will take 1 cycle. */
1297 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1298 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1304 frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1305 int unit_num
, int referenced
,
1306 INT in_ACC40Si
, INT out_ACC40Sk
)
1313 FRV_PROFILE_STATE
*ps
;
1314 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
1317 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1320 /* The preprocessing can execute right away. */
1321 cycles
= idesc
->timing
->units
[unit_num
].done
;
1323 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1324 ACC40Si_2
= DUAL_REG (ACC40Si_1
);
1325 ACC40Si_3
= DUAL_REG (ACC40Si_2
);
1326 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1328 ps
= CPU_PROFILE_STATE (cpu
);
1329 /* The latency of the registers may be less than previously recorded,
1330 depending on how they were used previously.
1331 See Table 13-8 in the LSI. */
1332 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1334 busy_adjustment
[0] = 1;
1335 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1337 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1339 busy_adjustment
[1] = 1;
1340 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1342 if (ACC40Si_2
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_2
))
1344 busy_adjustment
[2] = 1;
1345 decrease_ACC_busy (cpu
, ACC40Si_2
, busy_adjustment
[2]);
1347 if (ACC40Si_3
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_3
))
1349 busy_adjustment
[3] = 1;
1350 decrease_ACC_busy (cpu
, ACC40Si_3
, busy_adjustment
[3]);
1352 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1353 && out_ACC40Sk
!= ACC40Si_2
&& out_ACC40Sk
!= ACC40Si_3
)
1355 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1357 busy_adjustment
[4] = 1;
1358 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1361 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
1362 && ACC40Sk_1
!= ACC40Si_2
&& ACC40Sk_1
!= ACC40Si_3
)
1364 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1366 busy_adjustment
[5] = 1;
1367 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1371 /* The post processing must wait if there is a dependency on a register
1372 which is not ready yet. */
1373 ps
->post_wait
= cycles
;
1374 post_wait_for_ACC (cpu
, in_ACC40Si
);
1375 post_wait_for_ACC (cpu
, ACC40Si_1
);
1376 post_wait_for_ACC (cpu
, ACC40Si_2
);
1377 post_wait_for_ACC (cpu
, ACC40Si_3
);
1378 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1379 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1381 /* Restore the busy cycles of the registers we used. */
1383 acc
[in_ACC40Si
] += busy_adjustment
[0];
1385 acc
[ACC40Si_1
] += busy_adjustment
[1];
1387 acc
[ACC40Si_2
] += busy_adjustment
[2];
1389 acc
[ACC40Si_3
] += busy_adjustment
[3];
1390 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1392 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1394 /* The latency of the output register will be at least the latency of the
1395 other inputs. Once initiated, post-processing will take 1 cycle. */
1396 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1397 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1400 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1401 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1408 frvbf_model_fr400_u_media_2_add_sub (SIM_CPU
*cpu
, const IDESC
*idesc
,
1409 int unit_num
, int referenced
,
1410 INT in_ACC40Si
, INT out_ACC40Sk
)
1415 FRV_PROFILE_STATE
*ps
;
1416 int busy_adjustment
[] = {0, 0, 0, 0};
1419 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1422 /* The preprocessing can execute right away. */
1423 cycles
= idesc
->timing
->units
[unit_num
].done
;
1425 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1426 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1428 ps
= CPU_PROFILE_STATE (cpu
);
1429 /* The latency of the registers may be less than previously recorded,
1430 depending on how they were used previously.
1431 See Table 13-8 in the LSI. */
1432 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1434 busy_adjustment
[0] = 1;
1435 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1437 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1439 busy_adjustment
[1] = 1;
1440 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1442 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
)
1444 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1446 busy_adjustment
[2] = 1;
1447 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
1450 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
)
1452 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1454 busy_adjustment
[3] = 1;
1455 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[3]);
1459 /* The post processing must wait if there is a dependency on a register
1460 which is not ready yet. */
1461 ps
->post_wait
= cycles
;
1462 post_wait_for_ACC (cpu
, in_ACC40Si
);
1463 post_wait_for_ACC (cpu
, ACC40Si_1
);
1464 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1465 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1467 /* Restore the busy cycles of the registers we used. */
1469 acc
[in_ACC40Si
] += busy_adjustment
[0];
1471 acc
[ACC40Si_1
] += busy_adjustment
[1];
1472 acc
[out_ACC40Sk
] += busy_adjustment
[2];
1474 acc
[ACC40Sk_1
] += busy_adjustment
[3];
1476 /* The latency of the output register will be at least the latency of the
1477 other inputs. Once initiated, post-processing will take 1 cycle. */
1478 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1479 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1482 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1483 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1490 frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1491 int unit_num
, int referenced
,
1492 INT in_ACC40Si
, INT out_ACC40Sk
)
1501 FRV_PROFILE_STATE
*ps
;
1502 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0, 0};
1505 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1508 /* The preprocessing can execute right away. */
1509 cycles
= idesc
->timing
->units
[unit_num
].done
;
1511 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1512 ACC40Si_2
= DUAL_REG (ACC40Si_1
);
1513 ACC40Si_3
= DUAL_REG (ACC40Si_2
);
1514 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
1515 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
1516 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
1518 ps
= CPU_PROFILE_STATE (cpu
);
1519 /* The latency of the registers may be less than previously recorded,
1520 depending on how they were used previously.
1521 See Table 13-8 in the LSI. */
1522 if (acc_use_is_media_p2 (cpu
, in_ACC40Si
))
1524 busy_adjustment
[0] = 1;
1525 decrease_ACC_busy (cpu
, in_ACC40Si
, busy_adjustment
[0]);
1527 if (ACC40Si_1
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_1
))
1529 busy_adjustment
[1] = 1;
1530 decrease_ACC_busy (cpu
, ACC40Si_1
, busy_adjustment
[1]);
1532 if (ACC40Si_2
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_2
))
1534 busy_adjustment
[2] = 1;
1535 decrease_ACC_busy (cpu
, ACC40Si_2
, busy_adjustment
[2]);
1537 if (ACC40Si_3
>= 0 && acc_use_is_media_p2 (cpu
, ACC40Si_3
))
1539 busy_adjustment
[3] = 1;
1540 decrease_ACC_busy (cpu
, ACC40Si_3
, busy_adjustment
[3]);
1542 if (out_ACC40Sk
!= in_ACC40Si
&& out_ACC40Sk
!= ACC40Si_1
1543 && out_ACC40Sk
!= ACC40Si_2
&& out_ACC40Sk
!= ACC40Si_3
)
1545 if (acc_use_is_media_p2 (cpu
, out_ACC40Sk
))
1547 busy_adjustment
[4] = 1;
1548 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
1551 if (ACC40Sk_1
!= in_ACC40Si
&& ACC40Sk_1
!= ACC40Si_1
1552 && ACC40Sk_1
!= ACC40Si_2
&& ACC40Sk_1
!= ACC40Si_3
)
1554 if (acc_use_is_media_p2 (cpu
, ACC40Sk_1
))
1556 busy_adjustment
[5] = 1;
1557 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
1560 if (ACC40Sk_2
!= in_ACC40Si
&& ACC40Sk_2
!= ACC40Si_1
1561 && ACC40Sk_2
!= ACC40Si_2
&& ACC40Sk_2
!= ACC40Si_3
)
1563 if (acc_use_is_media_p2 (cpu
, ACC40Sk_2
))
1565 busy_adjustment
[6] = 1;
1566 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
1569 if (ACC40Sk_3
!= in_ACC40Si
&& ACC40Sk_3
!= ACC40Si_1
1570 && ACC40Sk_3
!= ACC40Si_2
&& ACC40Sk_3
!= ACC40Si_3
)
1572 if (acc_use_is_media_p2 (cpu
, ACC40Sk_3
))
1574 busy_adjustment
[7] = 1;
1575 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
1579 /* The post processing must wait if there is a dependency on a register
1580 which is not ready yet. */
1581 ps
->post_wait
= cycles
;
1582 post_wait_for_ACC (cpu
, in_ACC40Si
);
1583 post_wait_for_ACC (cpu
, ACC40Si_1
);
1584 post_wait_for_ACC (cpu
, ACC40Si_2
);
1585 post_wait_for_ACC (cpu
, ACC40Si_3
);
1586 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1587 post_wait_for_ACC (cpu
, ACC40Sk_1
);
1588 post_wait_for_ACC (cpu
, ACC40Sk_2
);
1589 post_wait_for_ACC (cpu
, ACC40Sk_3
);
1591 /* Restore the busy cycles of the registers we used. */
1593 acc
[in_ACC40Si
] += busy_adjustment
[0];
1595 acc
[ACC40Si_1
] += busy_adjustment
[1];
1597 acc
[ACC40Si_2
] += busy_adjustment
[2];
1599 acc
[ACC40Si_3
] += busy_adjustment
[3];
1600 acc
[out_ACC40Sk
] += busy_adjustment
[4];
1602 acc
[ACC40Sk_1
] += busy_adjustment
[5];
1604 acc
[ACC40Sk_2
] += busy_adjustment
[6];
1606 acc
[ACC40Sk_3
] += busy_adjustment
[7];
1608 /* The latency of the output register will be at least the latency of the
1609 other inputs. Once initiated, post-processing will take 1 cycle. */
1610 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
1611 set_acc_use_is_media_p2 (cpu
, out_ACC40Sk
);
1614 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
1615 set_acc_use_is_media_p2 (cpu
, ACC40Sk_1
);
1619 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
1620 set_acc_use_is_media_p2 (cpu
, ACC40Sk_2
);
1624 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
1625 set_acc_use_is_media_p2 (cpu
, ACC40Sk_3
);
1632 frvbf_model_fr400_u_media_3 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1633 int unit_num
, int referenced
,
1634 INT in_FRi
, INT in_FRj
,
1637 /* Modelling is the same as media unit 1. */
1638 return frvbf_model_fr400_u_media_1 (cpu
, idesc
, unit_num
, referenced
,
1639 in_FRi
, in_FRj
, out_FRk
);
1643 frvbf_model_fr400_u_media_3_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1644 int unit_num
, int referenced
,
1645 INT in_FRi
, INT out_FRk
)
1649 FRV_PROFILE_STATE
*ps
;
1650 int busy_adjustment
[] = {0, 0};
1653 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1656 /* The preprocessing can execute right away. */
1657 cycles
= idesc
->timing
->units
[unit_num
].done
;
1659 ps
= CPU_PROFILE_STATE (cpu
);
1660 dual_FRi
= DUAL_REG (in_FRi
);
1662 /* The latency of the registers may be less than previously recorded,
1663 depending on how they were used previously.
1664 See Table 13-8 in the LSI. */
1665 if (use_is_fp_load (cpu
, in_FRi
))
1667 busy_adjustment
[0] = 1;
1668 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1671 enforce_full_fr_latency (cpu
, in_FRi
);
1672 if (dual_FRi
>= 0 && use_is_fp_load (cpu
, dual_FRi
))
1674 busy_adjustment
[1] = 1;
1675 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
1678 enforce_full_fr_latency (cpu
, dual_FRi
);
1680 /* The post processing must wait if there is a dependency on a FR
1681 which is not ready yet. */
1682 ps
->post_wait
= cycles
;
1683 post_wait_for_FR (cpu
, in_FRi
);
1684 post_wait_for_FR (cpu
, dual_FRi
);
1685 post_wait_for_FR (cpu
, out_FRk
);
1687 /* Restore the busy cycles of the registers we used. */
1689 fr
[in_FRi
] += busy_adjustment
[0];
1691 fr
[dual_FRi
] += busy_adjustment
[1];
1693 /* The latency of the output register will be at least the latency of the
1695 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1697 /* Once initiated, post-processing has no latency. */
1698 update_FR_ptime (cpu
, out_FRk
, 0);
1704 frvbf_model_fr400_u_media_3_quad (SIM_CPU
*cpu
, const IDESC
*idesc
,
1705 int unit_num
, int referenced
,
1706 INT in_FRi
, INT in_FRj
,
1709 /* Modelling is the same as media unit 1. */
1710 return frvbf_model_fr400_u_media_1_quad (cpu
, idesc
, unit_num
, referenced
,
1711 in_FRi
, in_FRj
, out_FRk
);
1715 frvbf_model_fr400_u_media_4 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1716 int unit_num
, int referenced
,
1717 INT in_ACC40Si
, INT in_FRj
,
1718 INT out_ACC40Sk
, INT out_FRk
)
1721 FRV_PROFILE_STATE
*ps
;
1722 const CGEN_INSN
*insn
;
1723 int busy_adjustment
[] = {0};
1726 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1729 /* The preprocessing can execute right away. */
1730 cycles
= idesc
->timing
->units
[unit_num
].done
;
1732 ps
= CPU_PROFILE_STATE (cpu
);
1733 insn
= idesc
->idata
;
1735 /* The latency of the registers may be less than previously recorded,
1736 depending on how they were used previously.
1737 See Table 13-8 in the LSI. */
1740 if (use_is_fp_load (cpu
, in_FRj
))
1742 busy_adjustment
[0] = 1;
1743 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
1746 enforce_full_fr_latency (cpu
, in_FRj
);
1749 /* The post processing must wait if there is a dependency on a FR
1750 which is not ready yet. */
1751 ps
->post_wait
= cycles
;
1752 post_wait_for_ACC (cpu
, in_ACC40Si
);
1753 post_wait_for_ACC (cpu
, out_ACC40Sk
);
1754 post_wait_for_FR (cpu
, in_FRj
);
1755 post_wait_for_FR (cpu
, out_FRk
);
1757 /* Restore the busy cycles of the registers we used. */
1760 /* The latency of the output register will be at least the latency of the
1761 other inputs. Once initiated, post-processing will take 1 cycle. */
1764 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1765 update_FR_ptime (cpu
, out_FRk
, 1);
1766 /* Mark this use of the register as media unit 4. */
1767 set_use_is_media_p4 (cpu
, out_FRk
);
1769 else if (out_ACC40Sk
>= 0)
1771 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
);
1772 update_ACC_ptime (cpu
, out_ACC40Sk
, 1);
1773 /* Mark this use of the register as media unit 4. */
1774 set_acc_use_is_media_p4 (cpu
, out_ACC40Sk
);
1781 frvbf_model_fr400_u_media_4_accg (SIM_CPU
*cpu
, const IDESC
*idesc
,
1782 int unit_num
, int referenced
,
1783 INT in_ACCGi
, INT in_FRinti
,
1784 INT out_ACCGk
, INT out_FRintk
)
1786 /* Modelling is the same as media-4 unit except use accumulator guards
1787 as input instead of accumulators. */
1788 return frvbf_model_fr400_u_media_4 (cpu
, idesc
, unit_num
, referenced
,
1789 in_ACCGi
, in_FRinti
,
1790 out_ACCGk
, out_FRintk
);
1794 frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU
*cpu
, const IDESC
*idesc
,
1795 int unit_num
, int referenced
,
1796 INT in_ACC40Si
, INT out_FRk
)
1799 FRV_PROFILE_STATE
*ps
;
1800 const CGEN_INSN
*insn
;
1804 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1807 /* The preprocessing can execute right away. */
1808 cycles
= idesc
->timing
->units
[unit_num
].done
;
1810 ps
= CPU_PROFILE_STATE (cpu
);
1811 ACC40Si_1
= DUAL_REG (in_ACC40Si
);
1812 FRk_1
= DUAL_REG (out_FRk
);
1814 insn
= idesc
->idata
;
1816 /* The post processing must wait if there is a dependency on a FR
1817 which is not ready yet. */
1818 ps
->post_wait
= cycles
;
1819 post_wait_for_ACC (cpu
, in_ACC40Si
);
1820 post_wait_for_ACC (cpu
, ACC40Si_1
);
1821 post_wait_for_FR (cpu
, out_FRk
);
1822 post_wait_for_FR (cpu
, FRk_1
);
1824 /* The latency of the output register will be at least the latency of the
1825 other inputs. Once initiated, post-processing will take 1 cycle. */
1828 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1829 update_FR_ptime (cpu
, out_FRk
, 1);
1830 /* Mark this use of the register as media unit 4. */
1831 set_use_is_media_p4 (cpu
, out_FRk
);
1835 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
1836 update_FR_ptime (cpu
, FRk_1
, 1);
1837 /* Mark this use of the register as media unit 4. */
1838 set_use_is_media_p4 (cpu
, FRk_1
);
1845 frvbf_model_fr400_u_media_6 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1846 int unit_num
, int referenced
,
1847 INT in_FRi
, INT out_FRk
)
1850 FRV_PROFILE_STATE
*ps
;
1851 const CGEN_INSN
*insn
;
1852 int busy_adjustment
[] = {0};
1855 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1858 /* The preprocessing can execute right away. */
1859 cycles
= idesc
->timing
->units
[unit_num
].done
;
1861 ps
= CPU_PROFILE_STATE (cpu
);
1862 insn
= idesc
->idata
;
1864 /* The latency of the registers may be less than previously recorded,
1865 depending on how they were used previously.
1866 See Table 13-8 in the LSI. */
1869 if (use_is_fp_load (cpu
, in_FRi
))
1871 busy_adjustment
[0] = 1;
1872 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1875 enforce_full_fr_latency (cpu
, in_FRi
);
1878 /* The post processing must wait if there is a dependency on a FR
1879 which is not ready yet. */
1880 ps
->post_wait
= cycles
;
1881 post_wait_for_FR (cpu
, in_FRi
);
1882 post_wait_for_FR (cpu
, out_FRk
);
1884 /* Restore the busy cycles of the registers we used. */
1887 fr
[in_FRi
] += busy_adjustment
[0];
1889 /* The latency of the output register will be at least the latency of the
1890 other inputs. Once initiated, post-processing will take 1 cycle. */
1893 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1894 update_FR_ptime (cpu
, out_FRk
, 1);
1896 /* Mark this use of the register as media unit 1. */
1897 set_use_is_media_p6 (cpu
, out_FRk
);
1904 frvbf_model_fr400_u_media_7 (SIM_CPU
*cpu
, const IDESC
*idesc
,
1905 int unit_num
, int referenced
,
1906 INT in_FRinti
, INT in_FRintj
,
1910 FRV_PROFILE_STATE
*ps
;
1911 int busy_adjustment
[] = {0, 0};
1914 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1917 /* The preprocessing can execute right away. */
1918 cycles
= idesc
->timing
->units
[unit_num
].done
;
1920 /* The post processing must wait if there is a dependency on a FR
1921 which is not ready yet. */
1922 ps
= CPU_PROFILE_STATE (cpu
);
1924 /* The latency of the registers may be less than previously recorded,
1925 depending on how they were used previously.
1926 See Table 13-8 in the LSI. */
1929 if (use_is_fp_load (cpu
, in_FRinti
))
1931 busy_adjustment
[0] = 1;
1932 decrease_FR_busy (cpu
, in_FRinti
, busy_adjustment
[0]);
1935 enforce_full_fr_latency (cpu
, in_FRinti
);
1937 if (in_FRintj
>= 0 && in_FRintj
!= in_FRinti
)
1939 if (use_is_fp_load (cpu
, in_FRintj
))
1941 busy_adjustment
[1] = 1;
1942 decrease_FR_busy (cpu
, in_FRintj
, busy_adjustment
[1]);
1945 enforce_full_fr_latency (cpu
, in_FRintj
);
1948 ps
->post_wait
= cycles
;
1949 post_wait_for_FR (cpu
, in_FRinti
);
1950 post_wait_for_FR (cpu
, in_FRintj
);
1951 post_wait_for_CCR (cpu
, out_FCCk
);
1953 /* Restore the busy cycles of the registers we used. */
1956 fr
[in_FRinti
] += busy_adjustment
[0];
1958 fr
[in_FRintj
] += busy_adjustment
[1];
1960 /* The latency of FCCi_2 will be the latency of the other inputs plus 1
1962 update_CCR_latency (cpu
, out_FCCk
, ps
->post_wait
+ 1);
1968 frvbf_model_fr400_u_media_dual_expand (SIM_CPU
*cpu
, const IDESC
*idesc
,
1969 int unit_num
, int referenced
,
1973 /* Insns using this unit are media-3 class insns, with a dual FRk output. */
1976 FRV_PROFILE_STATE
*ps
;
1977 int busy_adjustment
[] = {0};
1980 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1983 /* The preprocessing can execute right away. */
1984 cycles
= idesc
->timing
->units
[unit_num
].done
;
1986 /* If the previous use of the registers was a media op,
1987 then their latency will be less than previously recorded.
1988 See Table 13-13 in the LSI. */
1989 dual_FRk
= DUAL_REG (out_FRk
);
1990 ps
= CPU_PROFILE_STATE (cpu
);
1991 if (use_is_fp_load (cpu
, in_FRi
))
1993 busy_adjustment
[0] = 1;
1994 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
1997 enforce_full_fr_latency (cpu
, in_FRi
);
1999 /* The post processing must wait if there is a dependency on a FR
2000 which is not ready yet. */
2001 ps
->post_wait
= cycles
;
2002 post_wait_for_FR (cpu
, in_FRi
);
2003 post_wait_for_FR (cpu
, out_FRk
);
2004 post_wait_for_FR (cpu
, dual_FRk
);
2006 /* Restore the busy cycles of the registers we used. */
2008 fr
[in_FRi
] += busy_adjustment
[0];
2010 /* The latency of the output register will be at least the latency of the
2011 other inputs. Once initiated, post-processing has no latency. */
2012 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2013 update_FR_ptime (cpu
, out_FRk
, 0);
2017 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2018 update_FR_ptime (cpu
, dual_FRk
, 0);
2025 frvbf_model_fr400_u_media_dual_htob (SIM_CPU
*cpu
, const IDESC
*idesc
,
2026 int unit_num
, int referenced
,
2030 /* Insns using this unit are media-3 class insns, with a dual FRj input. */
2033 FRV_PROFILE_STATE
*ps
;
2034 int busy_adjustment
[] = {0, 0};
2037 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2040 /* The preprocessing can execute right away. */
2041 cycles
= idesc
->timing
->units
[unit_num
].done
;
2043 /* If the previous use of the registers was a media op,
2044 then their latency will be less than previously recorded.
2045 See Table 13-13 in the LSI. */
2046 dual_FRj
= DUAL_REG (in_FRj
);
2047 ps
= CPU_PROFILE_STATE (cpu
);
2048 if (use_is_fp_load (cpu
, in_FRj
))
2050 busy_adjustment
[0] = 1;
2051 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
2054 enforce_full_fr_latency (cpu
, in_FRj
);
2057 if (use_is_fp_load (cpu
, dual_FRj
))
2059 busy_adjustment
[1] = 1;
2060 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[1]);
2063 enforce_full_fr_latency (cpu
, dual_FRj
);
2066 /* The post processing must wait if there is a dependency on a FR
2067 which is not ready yet. */
2068 ps
->post_wait
= cycles
;
2069 post_wait_for_FR (cpu
, in_FRj
);
2070 post_wait_for_FR (cpu
, dual_FRj
);
2071 post_wait_for_FR (cpu
, out_FRk
);
2073 /* Restore the busy cycles of the registers we used. */
2075 fr
[in_FRj
] += busy_adjustment
[0];
2077 fr
[dual_FRj
] += busy_adjustment
[1];
2079 /* The latency of the output register will be at least the latency of the
2081 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2083 /* Once initiated, post-processing has no latency. */
2084 update_FR_ptime (cpu
, out_FRk
, 0);
2090 frvbf_model_fr400_u_ici (SIM_CPU
*cpu
, const IDESC
*idesc
,
2091 int unit_num
, int referenced
,
2092 INT in_GRi
, INT in_GRj
)
2094 /* Modelling for this unit is the same as for fr500. */
2095 return frvbf_model_fr500_u_ici (cpu
, idesc
, unit_num
, referenced
,
2100 frvbf_model_fr400_u_dci (SIM_CPU
*cpu
, const IDESC
*idesc
,
2101 int unit_num
, int referenced
,
2102 INT in_GRi
, INT in_GRj
)
2104 /* Modelling for this unit is the same as for fr500. */
2105 return frvbf_model_fr500_u_dci (cpu
, idesc
, unit_num
, referenced
,
2110 frvbf_model_fr400_u_dcf (SIM_CPU
*cpu
, const IDESC
*idesc
,
2111 int unit_num
, int referenced
,
2112 INT in_GRi
, INT in_GRj
)
2114 /* Modelling for this unit is the same as for fr500. */
2115 return frvbf_model_fr500_u_dcf (cpu
, idesc
, unit_num
, referenced
,
2120 frvbf_model_fr400_u_icpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
2121 int unit_num
, int referenced
,
2122 INT in_GRi
, INT in_GRj
)
2124 /* Modelling for this unit is the same as for fr500. */
2125 return frvbf_model_fr500_u_icpl (cpu
, idesc
, unit_num
, referenced
,
2130 frvbf_model_fr400_u_dcpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
2131 int unit_num
, int referenced
,
2132 INT in_GRi
, INT in_GRj
)
2134 /* Modelling for this unit is the same as for fr500. */
2135 return frvbf_model_fr500_u_dcpl (cpu
, idesc
, unit_num
, referenced
,
2140 frvbf_model_fr400_u_icul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2141 int unit_num
, int referenced
,
2142 INT in_GRi
, INT in_GRj
)
2144 /* Modelling for this unit is the same as for fr500. */
2145 return frvbf_model_fr500_u_icul (cpu
, idesc
, unit_num
, referenced
,
2150 frvbf_model_fr400_u_dcul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2151 int unit_num
, int referenced
,
2152 INT in_GRi
, INT in_GRj
)
2154 /* Modelling for this unit is the same as for fr500. */
2155 return frvbf_model_fr500_u_dcul (cpu
, idesc
, unit_num
, referenced
,
2160 frvbf_model_fr400_u_barrier (SIM_CPU
*cpu
, const IDESC
*idesc
,
2161 int unit_num
, int referenced
)
2163 /* Modelling for this unit is the same as for fr500. */
2164 return frvbf_model_fr500_u_barrier (cpu
, idesc
, unit_num
, referenced
);
2168 frvbf_model_fr400_u_membar (SIM_CPU
*cpu
, const IDESC
*idesc
,
2169 int unit_num
, int referenced
)
2171 /* Modelling for this unit is the same as for fr500. */
2172 return frvbf_model_fr500_u_membar (cpu
, idesc
, unit_num
, referenced
);
2175 #endif /* WITH_PROFILE_MODEL_P */