1 /* frv simulator fr500 dependent profiling code.
3 Copyright (C) 1998-2023 Free Software Foundation, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
25 #define WANT_CPU_FRVBF
30 #if WITH_PROFILE_MODEL_P
33 #include "profile-fr500.h"
35 /* Initialize cycle counting for an insn.
36 FIRST_P is non-zero if this is the first insn in a set of parallel
39 fr500_model_insn_before (SIM_CPU
*cpu
, int first_p
)
43 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
44 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
45 ps
->cur_gr_complex
= ps
->prev_gr_complex
;
46 d
->cur_fpop
= d
->prev_fpop
;
47 d
->cur_media
= d
->prev_media
;
48 d
->cur_cc_complex
= d
->prev_cc_complex
;
52 /* Record the cycles computed for an insn.
53 LAST_P is non-zero if this is the last insn in a set of parallel insns,
54 and we update the total cycle count.
55 CYCLES is the cycle count of the insn. */
57 fr500_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
61 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
62 FRV_PROFILE_STATE
*ps
= CPU_PROFILE_STATE (cpu
);
63 ps
->prev_gr_complex
= ps
->cur_gr_complex
;
64 d
->prev_fpop
= d
->cur_fpop
;
65 d
->prev_media
= d
->cur_media
;
66 d
->prev_cc_complex
= d
->cur_cc_complex
;
71 set_use_is_fpop (SIM_CPU
*cpu
, INT fr
)
73 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
74 fr500_reset_fr_flags (cpu
, (fr
));
75 d
->cur_fpop
|= (((DI
)1) << (fr
));
79 set_use_not_fpop (SIM_CPU
*cpu
, INT fr
)
81 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
82 d
->cur_fpop
&= ~(((DI
)1) << (fr
));
86 use_is_fpop (SIM_CPU
*cpu
, INT fr
)
88 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
89 return d
->prev_fpop
& (((DI
)1) << (fr
));
93 set_use_is_media ( SIM_CPU
*cpu
, INT fr
)
95 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
96 fr500_reset_fr_flags (cpu
, (fr
));
97 d
->cur_media
|= (((DI
)1) << (fr
));
101 set_use_not_media (SIM_CPU
*cpu
, INT fr
)
103 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
104 d
->cur_media
&= ~(((DI
)1) << (fr
));
108 use_is_media (SIM_CPU
*cpu
, INT fr
)
110 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
111 return d
->prev_media
& (((DI
)1) << (fr
));
115 set_use_is_cc_complex (SIM_CPU
*cpu
, INT cc
)
117 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
118 fr500_reset_cc_flags (cpu
, cc
);
119 d
->cur_cc_complex
|= (((DI
)1) << (cc
));
123 set_use_not_cc_complex (SIM_CPU
*cpu
, INT cc
)
125 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
126 d
->cur_cc_complex
&= ~(((DI
)1) << (cc
));
131 use_is_cc_complex (SIM_CPU
*cpu
, INT cc
)
133 MODEL_FR500_DATA
*d
= CPU_MODEL_DATA (cpu
);
134 return d
->prev_cc_complex
& (((DI
)1) << (cc
));
139 fr500_reset_fr_flags (SIM_CPU
*cpu
, INT fr
)
141 set_use_not_fpop (cpu
, fr
);
142 set_use_not_media (cpu
, fr
);
146 fr500_reset_cc_flags (SIM_CPU
*cpu
, INT cc
)
148 set_use_not_cc_complex (cpu
, cc
);
151 /* Latency of floating point registers may be less than recorded when followed
152 by another floating point insn. */
154 adjust_float_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
157 /* If the registers were previously used in a floating point op,
158 then their latency will be less than previously recorded.
159 See Table 13-13 in the LSI. */
162 if (use_is_fpop (cpu
, in_FRi
))
163 decrease_FR_busy (cpu
, in_FRi
, cycles
);
165 enforce_full_fr_latency (cpu
, in_FRi
);
168 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
170 if (use_is_fpop (cpu
, in_FRj
))
171 decrease_FR_busy (cpu
, in_FRj
, cycles
);
173 enforce_full_fr_latency (cpu
, in_FRj
);
176 if (out_FRk
>= 0 && out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
178 if (use_is_fpop (cpu
, out_FRk
))
179 decrease_FR_busy (cpu
, out_FRk
, cycles
);
181 enforce_full_fr_latency (cpu
, out_FRk
);
185 /* Latency of floating point registers may be less than recorded when followed
186 by another floating point insn. */
188 adjust_double_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
191 /* If the registers were previously used in a floating point op,
192 then their latency will be less than previously recorded.
193 See Table 13-13 in the LSI. */
194 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
195 if (in_FRi
>= 0) ++in_FRi
;
196 if (in_FRj
>= 0) ++in_FRj
;
197 if (out_FRk
>= 0) ++out_FRk
;
198 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
201 /* Latency of floating point registers is less than recorded when followed
202 by another floating point insn. */
204 restore_float_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
207 /* If the registers were previously used in a floating point op,
208 then their latency will be less than previously recorded.
209 See Table 13-13 in the LSI. */
210 if (in_FRi
>= 0 && use_is_fpop (cpu
, in_FRi
))
211 increase_FR_busy (cpu
, in_FRi
, cycles
);
212 if (in_FRj
!= in_FRi
&& use_is_fpop (cpu
, in_FRj
))
213 increase_FR_busy (cpu
, in_FRj
, cycles
);
214 if (out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
&& use_is_fpop (cpu
, out_FRk
))
215 increase_FR_busy (cpu
, out_FRk
, cycles
);
218 /* Latency of floating point registers is less than recorded when followed
219 by another floating point insn. */
221 restore_double_register_busy (SIM_CPU
*cpu
, INT in_FRi
, INT in_FRj
, INT out_FRk
,
224 /* If the registers were previously used in a floating point op,
225 then their latency will be less than previously recorded.
226 See Table 13-13 in the LSI. */
227 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
228 if (in_FRi
>= 0) ++in_FRi
;
229 if (in_FRj
>= 0) ++in_FRj
;
230 if (out_FRk
>= 0) ++out_FRk
;
231 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, cycles
);
235 frvbf_model_fr500_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
236 int unit_num
, int referenced
)
238 return idesc
->timing
->units
[unit_num
].done
;
242 frvbf_model_fr500_u_integer (SIM_CPU
*cpu
, const IDESC
*idesc
,
243 int unit_num
, int referenced
,
244 INT in_GRi
, INT in_GRj
, INT out_GRk
,
249 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
251 /* icc0-icc4 are the upper 4 fields of the CCR. */
255 /* The entire VLIW insn must wait if there is a dependency on a register
256 which is not ready yet.
257 The latency of the registers may be less than previously recorded,
258 depending on how they were used previously.
259 See Table 13-8 in the LSI. */
260 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
262 if (use_is_gr_complex (cpu
, in_GRi
))
263 decrease_GR_busy (cpu
, in_GRi
, 1);
265 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
267 if (use_is_gr_complex (cpu
, in_GRj
))
268 decrease_GR_busy (cpu
, in_GRj
, 1);
270 vliw_wait_for_GR (cpu
, in_GRi
);
271 vliw_wait_for_GR (cpu
, in_GRj
);
272 vliw_wait_for_GR (cpu
, out_GRk
);
273 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
274 handle_resource_wait (cpu
);
275 load_wait_for_GR (cpu
, in_GRi
);
276 load_wait_for_GR (cpu
, in_GRj
);
277 load_wait_for_GR (cpu
, out_GRk
);
278 trace_vliw_wait_cycles (cpu
);
282 /* GRk is available immediately to the next VLIW insn as is ICCi_1. */
283 cycles
= idesc
->timing
->units
[unit_num
].done
;
288 frvbf_model_fr500_u_imul (SIM_CPU
*cpu
, const IDESC
*idesc
,
289 int unit_num
, int referenced
,
290 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
293 /* icc0-icc4 are the upper 4 fields of the CCR. */
297 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
299 /* The entire VLIW insn must wait if there is a dependency on a register
300 which is not ready yet.
301 The latency of the registers may be less than previously recorded,
302 depending on how they were used previously.
303 See Table 13-8 in the LSI. */
304 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
306 if (use_is_gr_complex (cpu
, in_GRi
))
307 decrease_GR_busy (cpu
, in_GRi
, 1);
309 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
311 if (use_is_gr_complex (cpu
, in_GRj
))
312 decrease_GR_busy (cpu
, in_GRj
, 1);
314 vliw_wait_for_GR (cpu
, in_GRi
);
315 vliw_wait_for_GR (cpu
, in_GRj
);
316 vliw_wait_for_GRdouble (cpu
, out_GRk
);
317 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
318 handle_resource_wait (cpu
);
319 load_wait_for_GR (cpu
, in_GRi
);
320 load_wait_for_GR (cpu
, in_GRj
);
321 load_wait_for_GRdouble (cpu
, out_GRk
);
322 trace_vliw_wait_cycles (cpu
);
326 /* GRk has a latency of 2 cycles. */
327 cycles
= idesc
->timing
->units
[unit_num
].done
;
328 update_GRdouble_latency (cpu
, out_GRk
, cycles
+ 2);
329 set_use_is_gr_complex (cpu
, out_GRk
);
330 set_use_is_gr_complex (cpu
, out_GRk
+ 1);
332 /* ICCi_1 has a latency of 1 cycle. */
333 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 1);
339 frvbf_model_fr500_u_idiv (SIM_CPU
*cpu
, const IDESC
*idesc
,
340 int unit_num
, int referenced
,
341 INT in_GRi
, INT in_GRj
, INT out_GRk
, INT out_ICCi_1
)
347 /* icc0-icc4 are the upper 4 fields of the CCR. */
351 vliw
= CPU_VLIW (cpu
);
352 slot
= vliw
->next_slot
- 1;
353 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_I0
;
355 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
357 /* The entire VLIW insn must wait if there is a dependency on a register
358 which is not ready yet.
359 The latency of the registers may be less than previously recorded,
360 depending on how they were used previously.
361 See Table 13-8 in the LSI. */
362 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
364 if (use_is_gr_complex (cpu
, in_GRi
))
365 decrease_GR_busy (cpu
, in_GRi
, 1);
367 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
369 if (use_is_gr_complex (cpu
, in_GRj
))
370 decrease_GR_busy (cpu
, in_GRj
, 1);
372 vliw_wait_for_GR (cpu
, in_GRi
);
373 vliw_wait_for_GR (cpu
, in_GRj
);
374 vliw_wait_for_GR (cpu
, out_GRk
);
375 vliw_wait_for_CCR (cpu
, out_ICCi_1
);
376 vliw_wait_for_idiv_resource (cpu
, slot
);
377 handle_resource_wait (cpu
);
378 load_wait_for_GR (cpu
, in_GRi
);
379 load_wait_for_GR (cpu
, in_GRj
);
380 load_wait_for_GR (cpu
, out_GRk
);
381 trace_vliw_wait_cycles (cpu
);
385 /* GRk has a latency of 19 cycles! */
386 cycles
= idesc
->timing
->units
[unit_num
].done
;
387 update_GR_latency (cpu
, out_GRk
, cycles
+ 19);
388 set_use_is_gr_complex (cpu
, out_GRk
);
390 /* ICCi_1 has a latency of 19 cycles. */
391 update_CCR_latency (cpu
, out_ICCi_1
, cycles
+ 19);
392 set_use_is_cc_complex (cpu
, out_ICCi_1
);
394 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
396 /* GNER has a latency of 18 cycles. */
397 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRk
), cycles
+ 18);
400 /* the idiv resource has a latency of 18 cycles! */
401 update_idiv_resource_latency (cpu
, slot
, cycles
+ 18);
407 frvbf_model_fr500_u_branch (SIM_CPU
*cpu
, const IDESC
*idesc
,
408 int unit_num
, int referenced
,
409 INT in_GRi
, INT in_GRj
,
410 INT in_ICCi_2
, INT in_FCCi_2
)
413 FRV_PROFILE_STATE
*ps
;
415 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
417 /* icc0-icc4 are the upper 4 fields of the CCR. */
421 /* The entire VLIW insn must wait if there is a dependency on a register
422 which is not ready yet.
423 The latency of the registers may be less than previously recorded,
424 depending on how they were used previously.
425 See Table 13-8 in the LSI. */
428 if (use_is_gr_complex (cpu
, in_GRi
))
429 decrease_GR_busy (cpu
, in_GRi
, 1);
431 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
433 if (use_is_gr_complex (cpu
, in_GRj
))
434 decrease_GR_busy (cpu
, in_GRj
, 1);
436 vliw_wait_for_GR (cpu
, in_GRi
);
437 vliw_wait_for_GR (cpu
, in_GRj
);
438 vliw_wait_for_CCR (cpu
, in_ICCi_2
);
439 vliw_wait_for_CCR (cpu
, in_FCCi_2
);
440 handle_resource_wait (cpu
);
441 load_wait_for_GR (cpu
, in_GRi
);
442 load_wait_for_GR (cpu
, in_GRj
);
443 trace_vliw_wait_cycles (cpu
);
447 /* When counting branches taken or not taken, don't consider branches after
448 the first taken branch in a vliw insn. */
449 ps
= CPU_PROFILE_STATE (cpu
);
450 if (! ps
->vliw_branch_taken
)
452 /* (1 << 4): The pc is the 5th element in inputs, outputs.
453 ??? can be cleaned up */
454 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
455 int taken
= (referenced
& (1 << 4)) != 0;
458 ++PROFILE_MODEL_TAKEN_COUNT (p
);
459 ps
->vliw_branch_taken
= 1;
462 ++PROFILE_MODEL_UNTAKEN_COUNT (p
);
465 cycles
= idesc
->timing
->units
[unit_num
].done
;
470 frvbf_model_fr500_u_trap (SIM_CPU
*cpu
, const IDESC
*idesc
,
471 int unit_num
, int referenced
,
472 INT in_GRi
, INT in_GRj
,
473 INT in_ICCi_2
, INT in_FCCi_2
)
477 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
479 /* icc0-icc4 are the upper 4 fields of the CCR. */
483 /* The entire VLIW insn must wait if there is a dependency on a register
484 which is not ready yet.
485 The latency of the registers may be less than previously recorded,
486 depending on how they were used previously.
487 See Table 13-8 in the LSI. */
490 if (use_is_gr_complex (cpu
, in_GRi
))
491 decrease_GR_busy (cpu
, in_GRi
, 1);
493 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
495 if (use_is_gr_complex (cpu
, in_GRj
))
496 decrease_GR_busy (cpu
, in_GRj
, 1);
498 vliw_wait_for_GR (cpu
, in_GRi
);
499 vliw_wait_for_GR (cpu
, in_GRj
);
500 vliw_wait_for_CCR (cpu
, in_ICCi_2
);
501 vliw_wait_for_CCR (cpu
, in_FCCi_2
);
502 handle_resource_wait (cpu
);
503 load_wait_for_GR (cpu
, in_GRi
);
504 load_wait_for_GR (cpu
, in_GRj
);
505 trace_vliw_wait_cycles (cpu
);
509 cycles
= idesc
->timing
->units
[unit_num
].done
;
514 frvbf_model_fr500_u_check (SIM_CPU
*cpu
, const IDESC
*idesc
,
515 int unit_num
, int referenced
,
516 INT in_ICCi_3
, INT in_FCCi_3
)
520 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
522 /* icc0-icc4 are the upper 4 fields of the CCR. */
526 /* The entire VLIW insn must wait if there is a dependency on a register
527 which is not ready yet. */
528 vliw_wait_for_CCR (cpu
, in_ICCi_3
);
529 vliw_wait_for_CCR (cpu
, in_FCCi_3
);
530 handle_resource_wait (cpu
);
531 trace_vliw_wait_cycles (cpu
);
535 cycles
= idesc
->timing
->units
[unit_num
].done
;
540 frvbf_model_fr500_u_clrgr (SIM_CPU
*cpu
, const IDESC
*idesc
,
541 int unit_num
, int referenced
,
546 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
548 /* Wait for both GNER registers or just the one specified. */
551 vliw_wait_for_SPR (cpu
, H_SPR_GNER0
);
552 vliw_wait_for_SPR (cpu
, H_SPR_GNER1
);
555 vliw_wait_for_SPR (cpu
, GNER_FOR_GR (in_GRk
));
556 handle_resource_wait (cpu
);
557 trace_vliw_wait_cycles (cpu
);
561 cycles
= idesc
->timing
->units
[unit_num
].done
;
566 frvbf_model_fr500_u_clrfr (SIM_CPU
*cpu
, const IDESC
*idesc
,
567 int unit_num
, int referenced
,
572 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
574 /* Wait for both GNER registers or just the one specified. */
577 vliw_wait_for_SPR (cpu
, H_SPR_FNER0
);
578 vliw_wait_for_SPR (cpu
, H_SPR_FNER1
);
581 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (in_FRk
));
582 handle_resource_wait (cpu
);
583 trace_vliw_wait_cycles (cpu
);
587 cycles
= idesc
->timing
->units
[unit_num
].done
;
592 frvbf_model_fr500_u_commit (SIM_CPU
*cpu
, const IDESC
*idesc
,
593 int unit_num
, int referenced
,
594 INT in_GRk
, INT in_FRk
)
598 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
600 /* If GR is specified, then FR is not and vice-versa. If neither is
601 then it's a commitga or commitfa. Check the insn attribute to
604 vliw_wait_for_SPR (cpu
, GNER_FOR_GR (in_GRk
));
605 else if (in_FRk
!= -1)
606 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (in_FRk
));
607 else if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_FR_ACCESS
))
609 vliw_wait_for_SPR (cpu
, H_SPR_FNER0
);
610 vliw_wait_for_SPR (cpu
, H_SPR_FNER1
);
614 vliw_wait_for_SPR (cpu
, H_SPR_GNER0
);
615 vliw_wait_for_SPR (cpu
, H_SPR_GNER1
);
617 handle_resource_wait (cpu
);
618 trace_vliw_wait_cycles (cpu
);
622 cycles
= idesc
->timing
->units
[unit_num
].done
;
627 frvbf_model_fr500_u_set_hilo (SIM_CPU
*cpu
, const IDESC
*idesc
,
628 int unit_num
, int referenced
,
629 INT out_GRkhi
, INT out_GRklo
)
633 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
635 /* The entire VLIW insn must wait if there is a dependency on a GR
636 which is not ready yet. */
637 vliw_wait_for_GR (cpu
, out_GRkhi
);
638 vliw_wait_for_GR (cpu
, out_GRklo
);
639 handle_resource_wait (cpu
);
640 load_wait_for_GR (cpu
, out_GRkhi
);
641 load_wait_for_GR (cpu
, out_GRklo
);
642 trace_vliw_wait_cycles (cpu
);
646 /* GRk is available immediately to the next VLIW insn. */
647 cycles
= idesc
->timing
->units
[unit_num
].done
;
649 set_use_not_gr_complex (cpu
, out_GRkhi
);
650 set_use_not_gr_complex (cpu
, out_GRklo
);
656 frvbf_model_fr500_u_gr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
657 int unit_num
, int referenced
,
658 INT in_GRi
, INT in_GRj
,
659 INT out_GRk
, INT out_GRdoublek
)
663 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
665 /* The entire VLIW insn must wait if there is a dependency on a register
666 which is not ready yet.
667 The latency of the registers may be less than previously recorded,
668 depending on how they were used previously.
669 See Table 13-8 in the LSI. */
670 if (in_GRi
!= out_GRk
&& in_GRi
!= out_GRdoublek
671 && in_GRi
!= out_GRdoublek
+ 1 && in_GRi
>= 0)
673 if (use_is_gr_complex (cpu
, in_GRi
))
674 decrease_GR_busy (cpu
, in_GRi
, 1);
676 if (in_GRj
!= in_GRi
&& in_GRj
!= out_GRk
&& in_GRj
!= out_GRdoublek
677 && in_GRj
!= out_GRdoublek
+ 1 && in_GRj
>= 0)
680 if (use_is_gr_complex (cpu
, in_GRj
))
681 decrease_GR_busy (cpu
, in_GRj
, 1);
683 vliw_wait_for_GR (cpu
, in_GRi
);
684 vliw_wait_for_GR (cpu
, in_GRj
);
685 vliw_wait_for_GR (cpu
, out_GRk
);
686 vliw_wait_for_GRdouble (cpu
, out_GRdoublek
);
687 handle_resource_wait (cpu
);
688 load_wait_for_GR (cpu
, in_GRi
);
689 load_wait_for_GR (cpu
, in_GRj
);
690 load_wait_for_GR (cpu
, out_GRk
);
691 load_wait_for_GRdouble (cpu
, out_GRdoublek
);
692 trace_vliw_wait_cycles (cpu
);
696 cycles
= idesc
->timing
->units
[unit_num
].done
;
698 /* The latency of GRk for a load will depend on how long it takes to retrieve
699 the the data from the cache or memory. */
700 update_GR_latency_for_load (cpu
, out_GRk
, cycles
);
701 update_GRdouble_latency_for_load (cpu
, out_GRdoublek
, cycles
);
703 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
705 /* GNER has a latency of 2 cycles. */
706 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRk
), cycles
+ 2);
707 update_SPR_latency (cpu
, GNER_FOR_GR (out_GRdoublek
), cycles
+ 2);
711 set_use_is_gr_complex (cpu
, out_GRk
);
712 if (out_GRdoublek
!= -1)
714 set_use_is_gr_complex (cpu
, out_GRdoublek
);
715 set_use_is_gr_complex (cpu
, out_GRdoublek
+ 1);
722 frvbf_model_fr500_u_gr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
723 int unit_num
, int referenced
,
724 INT in_GRi
, INT in_GRj
,
725 INT in_GRk
, INT in_GRdoublek
)
729 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
731 /* The entire VLIW insn must wait if there is a dependency on a register
732 which is not ready yet.
733 The latency of the registers may be less than previously recorded,
734 depending on how they were used previously.
735 See Table 13-8 in the LSI. */
738 if (use_is_gr_complex (cpu
, in_GRi
))
739 decrease_GR_busy (cpu
, in_GRi
, 1);
741 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
743 if (use_is_gr_complex (cpu
, in_GRj
))
744 decrease_GR_busy (cpu
, in_GRj
, 1);
746 if (in_GRk
!= in_GRi
&& in_GRk
!= in_GRj
&& in_GRk
>= 0)
748 if (use_is_gr_complex (cpu
, in_GRk
))
749 decrease_GR_busy (cpu
, in_GRk
, 1);
751 if (in_GRdoublek
!= in_GRi
&& in_GRdoublek
!= in_GRj
752 && in_GRdoublek
+ 1 != in_GRi
&& in_GRdoublek
+ 1 != in_GRj
753 && in_GRdoublek
>= 0)
755 if (use_is_gr_complex (cpu
, in_GRdoublek
))
756 decrease_GR_busy (cpu
, in_GRdoublek
, 1);
757 if (use_is_gr_complex (cpu
, in_GRdoublek
+ 1))
758 decrease_GR_busy (cpu
, in_GRdoublek
+ 1, 1);
760 vliw_wait_for_GR (cpu
, in_GRi
);
761 vliw_wait_for_GR (cpu
, in_GRj
);
762 vliw_wait_for_GR (cpu
, in_GRk
);
763 vliw_wait_for_GRdouble (cpu
, in_GRdoublek
);
764 handle_resource_wait (cpu
);
765 load_wait_for_GR (cpu
, in_GRi
);
766 load_wait_for_GR (cpu
, in_GRj
);
767 load_wait_for_GR (cpu
, in_GRk
);
768 load_wait_for_GRdouble (cpu
, in_GRdoublek
);
769 trace_vliw_wait_cycles (cpu
);
773 cycles
= idesc
->timing
->units
[unit_num
].done
;
779 frvbf_model_fr500_u_gr_r_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
780 int unit_num
, int referenced
,
781 INT in_GRi
, INT in_GRj
,
782 INT in_GRk
, INT in_GRdoublek
)
784 int cycles
= frvbf_model_fr500_u_gr_store (cpu
, idesc
, unit_num
, referenced
,
785 in_GRi
, in_GRj
, in_GRk
,
788 if (model_insn
== FRV_INSN_MODEL_PASS_2
)
790 if (CPU_RSTR_INVALIDATE(cpu
))
791 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
798 frvbf_model_fr500_u_fr_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
799 int unit_num
, int referenced
,
800 INT in_GRi
, INT in_GRj
,
801 INT out_FRk
, INT out_FRdoublek
)
805 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
807 /* The entire VLIW insn must wait if there is a dependency on a register
808 which is not ready yet.
809 The latency of the registers may be less than previously recorded,
810 depending on how they were used previously.
811 See Table 13-8 in the LSI. */
814 if (use_is_gr_complex (cpu
, in_GRi
))
815 decrease_GR_busy (cpu
, in_GRi
, 1);
817 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
819 if (use_is_gr_complex (cpu
, in_GRj
))
820 decrease_GR_busy (cpu
, in_GRj
, 1);
824 if (use_is_media (cpu
, out_FRk
))
825 decrease_FR_busy (cpu
, out_FRk
, 1);
827 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
829 if (out_FRdoublek
>= 0)
831 if (use_is_media (cpu
, out_FRdoublek
))
832 decrease_FR_busy (cpu
, out_FRdoublek
, 1);
834 adjust_float_register_busy (cpu
, -1, -1, out_FRdoublek
, 1);
835 if (use_is_media (cpu
, out_FRdoublek
+ 1))
836 decrease_FR_busy (cpu
, out_FRdoublek
+ 1, 1);
838 adjust_float_register_busy (cpu
, -1, -1, out_FRdoublek
+ 1, 1);
840 vliw_wait_for_GR (cpu
, in_GRi
);
841 vliw_wait_for_GR (cpu
, in_GRj
);
842 vliw_wait_for_FR (cpu
, out_FRk
);
843 vliw_wait_for_FRdouble (cpu
, out_FRdoublek
);
844 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
846 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
847 vliw_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
849 handle_resource_wait (cpu
);
850 load_wait_for_GR (cpu
, in_GRi
);
851 load_wait_for_GR (cpu
, in_GRj
);
852 load_wait_for_FR (cpu
, out_FRk
);
853 load_wait_for_FRdouble (cpu
, out_FRdoublek
);
854 trace_vliw_wait_cycles (cpu
);
858 cycles
= idesc
->timing
->units
[unit_num
].done
;
860 /* The latency of FRk for a load will depend on how long it takes to retrieve
861 the the data from the cache or memory. */
862 update_FR_latency_for_load (cpu
, out_FRk
, cycles
);
863 update_FRdouble_latency_for_load (cpu
, out_FRdoublek
, cycles
);
865 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
867 /* FNER has a latency of 3 cycles. */
868 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), cycles
+ 3);
869 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), cycles
+ 3);
872 fr500_reset_fr_flags (cpu
, out_FRk
);
878 frvbf_model_fr500_u_fr_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
879 int unit_num
, int referenced
,
880 INT in_GRi
, INT in_GRj
,
881 INT in_FRk
, INT in_FRdoublek
)
885 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
887 /* The entire VLIW insn must wait if there is a dependency on a register
888 which is not ready yet.
889 The latency of the registers may be less than previously recorded,
890 depending on how they were used previously.
891 See Table 13-8 in the LSI. */
894 if (use_is_gr_complex (cpu
, in_GRi
))
895 decrease_GR_busy (cpu
, in_GRi
, 1);
897 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
899 if (use_is_gr_complex (cpu
, in_GRj
))
900 decrease_GR_busy (cpu
, in_GRj
, 1);
904 if (use_is_media (cpu
, in_FRk
))
905 decrease_FR_busy (cpu
, in_FRk
, 1);
907 adjust_float_register_busy (cpu
, -1, -1, in_FRk
, 1);
909 if (in_FRdoublek
>= 0)
911 if (use_is_media (cpu
, in_FRdoublek
))
912 decrease_FR_busy (cpu
, in_FRdoublek
, 1);
914 adjust_float_register_busy (cpu
, -1, -1, in_FRdoublek
, 1);
915 if (use_is_media (cpu
, in_FRdoublek
+ 1))
916 decrease_FR_busy (cpu
, in_FRdoublek
+ 1, 1);
918 adjust_float_register_busy (cpu
, -1, -1, in_FRdoublek
+ 1, 1);
920 vliw_wait_for_GR (cpu
, in_GRi
);
921 vliw_wait_for_GR (cpu
, in_GRj
);
922 vliw_wait_for_FR (cpu
, in_FRk
);
923 vliw_wait_for_FRdouble (cpu
, in_FRdoublek
);
924 handle_resource_wait (cpu
);
925 load_wait_for_GR (cpu
, in_GRi
);
926 load_wait_for_GR (cpu
, in_GRj
);
927 load_wait_for_FR (cpu
, in_FRk
);
928 load_wait_for_FRdouble (cpu
, in_FRdoublek
);
929 trace_vliw_wait_cycles (cpu
);
933 cycles
= idesc
->timing
->units
[unit_num
].done
;
939 frvbf_model_fr500_u_fr_r_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
940 int unit_num
, int referenced
,
941 INT in_GRi
, INT in_GRj
,
942 INT in_FRk
, INT in_FRdoublek
)
944 int cycles
= frvbf_model_fr500_u_fr_store (cpu
, idesc
, unit_num
, referenced
,
945 in_GRi
, in_GRj
, in_FRk
,
948 if (model_insn
== FRV_INSN_MODEL_PASS_2
)
950 if (CPU_RSTR_INVALIDATE(cpu
))
951 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
958 frvbf_model_fr500_u_swap (SIM_CPU
*cpu
, const IDESC
*idesc
,
959 int unit_num
, int referenced
,
960 INT in_GRi
, INT in_GRj
, INT out_GRk
)
964 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
966 /* The entire VLIW insn must wait if there is a dependency on a register
967 which is not ready yet.
968 The latency of the registers may be less than previously recorded,
969 depending on how they were used previously.
970 See Table 13-8 in the LSI. */
971 if (in_GRi
!= out_GRk
&& in_GRi
>= 0)
973 if (use_is_gr_complex (cpu
, in_GRi
))
974 decrease_GR_busy (cpu
, in_GRi
, 1);
976 if (in_GRj
!= out_GRk
&& in_GRj
!= in_GRi
&& in_GRj
>= 0)
978 if (use_is_gr_complex (cpu
, in_GRj
))
979 decrease_GR_busy (cpu
, in_GRj
, 1);
981 vliw_wait_for_GR (cpu
, in_GRi
);
982 vliw_wait_for_GR (cpu
, in_GRj
);
983 vliw_wait_for_GR (cpu
, out_GRk
);
984 handle_resource_wait (cpu
);
985 load_wait_for_GR (cpu
, in_GRi
);
986 load_wait_for_GR (cpu
, in_GRj
);
987 load_wait_for_GR (cpu
, out_GRk
);
988 trace_vliw_wait_cycles (cpu
);
992 cycles
= idesc
->timing
->units
[unit_num
].done
;
994 /* The latency of GRk will depend on how long it takes to swap
995 the the data from the cache or memory. */
996 update_GR_latency_for_swap (cpu
, out_GRk
, cycles
);
997 set_use_is_gr_complex (cpu
, out_GRk
);
1003 frvbf_model_fr500_u_fr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1004 int unit_num
, int referenced
,
1005 INT in_FRj
, INT out_FRk
)
1009 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1011 /* The entire VLIW insn must wait if there is a dependency on a register
1012 which is not ready yet. */
1015 if (use_is_media (cpu
, in_FRj
))
1016 decrease_FR_busy (cpu
, in_FRj
, 1);
1018 adjust_float_register_busy (cpu
, -1, in_FRj
, -1, 1);
1020 if (out_FRk
>= 0 && out_FRk
!= in_FRj
)
1022 if (use_is_media (cpu
, out_FRk
))
1023 decrease_FR_busy (cpu
, out_FRk
, 1);
1025 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
1027 vliw_wait_for_FR (cpu
, in_FRj
);
1028 vliw_wait_for_FR (cpu
, out_FRk
);
1029 handle_resource_wait (cpu
);
1030 load_wait_for_FR (cpu
, in_FRj
);
1031 load_wait_for_FR (cpu
, out_FRk
);
1032 trace_vliw_wait_cycles (cpu
);
1036 /* The latency of FRj is 3 cycles. */
1037 cycles
= idesc
->timing
->units
[unit_num
].done
;
1038 update_FR_latency (cpu
, out_FRk
, cycles
+ 3);
1044 frvbf_model_fr500_u_fr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1045 int unit_num
, int referenced
,
1046 INT in_FRk
, INT out_GRj
)
1050 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1052 /* The entire VLIW insn must wait if there is a dependency on a register
1053 which is not ready yet. */
1056 if (use_is_media (cpu
, in_FRk
))
1057 decrease_FR_busy (cpu
, in_FRk
, 1);
1059 adjust_float_register_busy (cpu
, -1, in_FRk
, -1, 1);
1061 vliw_wait_for_FR (cpu
, in_FRk
);
1062 vliw_wait_for_GR (cpu
, out_GRj
);
1063 handle_resource_wait (cpu
);
1064 load_wait_for_FR (cpu
, in_FRk
);
1065 load_wait_for_GR (cpu
, out_GRj
);
1066 trace_vliw_wait_cycles (cpu
);
1070 /* The latency of GRj is 2 cycles. */
1071 cycles
= idesc
->timing
->units
[unit_num
].done
;
1072 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
1073 set_use_is_gr_complex (cpu
, out_GRj
);
1079 frvbf_model_fr500_u_spr2gr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1080 int unit_num
, int referenced
,
1081 INT in_spr
, INT out_GRj
)
1085 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1087 /* The entire VLIW insn must wait if there is a dependency on a register
1088 which is not ready yet. */
1089 vliw_wait_for_SPR (cpu
, in_spr
);
1090 vliw_wait_for_GR (cpu
, out_GRj
);
1091 handle_resource_wait (cpu
);
1092 load_wait_for_GR (cpu
, out_GRj
);
1093 trace_vliw_wait_cycles (cpu
);
1097 cycles
= idesc
->timing
->units
[unit_num
].done
;
1099 #if 0 /* no latency? */
1100 /* The latency of GRj is 2 cycles. */
1101 update_GR_latency (cpu
, out_GRj
, cycles
+ 2);
1108 frvbf_model_fr500_u_gr2fr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1109 int unit_num
, int referenced
,
1110 INT in_GRj
, INT out_FRk
)
1114 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1116 /* The entire VLIW insn must wait if there is a dependency on a register
1117 which is not ready yet.
1118 The latency of the registers may be less than previously recorded,
1119 depending on how they were used previously.
1120 See Table 13-8 in the LSI. */
1123 if (use_is_gr_complex (cpu
, in_GRj
))
1124 decrease_GR_busy (cpu
, in_GRj
, 1);
1128 if (use_is_media (cpu
, out_FRk
))
1129 decrease_FR_busy (cpu
, out_FRk
, 1);
1131 adjust_float_register_busy (cpu
, -1, -1, out_FRk
, 1);
1133 vliw_wait_for_GR (cpu
, in_GRj
);
1134 vliw_wait_for_FR (cpu
, out_FRk
);
1135 handle_resource_wait (cpu
);
1136 load_wait_for_GR (cpu
, in_GRj
);
1137 load_wait_for_FR (cpu
, out_FRk
);
1138 trace_vliw_wait_cycles (cpu
);
1142 /* The latency of FRk is 2 cycles. */
1143 cycles
= idesc
->timing
->units
[unit_num
].done
;
1144 update_FR_latency (cpu
, out_FRk
, cycles
+ 2);
1146 /* Mark this use of the register as NOT a floating point op. */
1147 fr500_reset_fr_flags (cpu
, out_FRk
);
1153 frvbf_model_fr500_u_gr2spr (SIM_CPU
*cpu
, const IDESC
*idesc
,
1154 int unit_num
, int referenced
,
1155 INT in_GRj
, INT out_spr
)
1159 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1161 /* The entire VLIW insn must wait if there is a dependency on a register
1162 which is not ready yet.
1163 The latency of the registers may be less than previously recorded,
1164 depending on how they were used previously.
1165 See Table 13-8 in the LSI. */
1168 if (use_is_gr_complex (cpu
, in_GRj
))
1169 decrease_GR_busy (cpu
, in_GRj
, 1);
1171 vliw_wait_for_GR (cpu
, in_GRj
);
1172 vliw_wait_for_SPR (cpu
, out_spr
);
1173 handle_resource_wait (cpu
);
1174 load_wait_for_GR (cpu
, in_GRj
);
1175 trace_vliw_wait_cycles (cpu
);
1179 cycles
= idesc
->timing
->units
[unit_num
].done
;
1182 /* The latency of spr is ? cycles. */
1183 update_SPR_latency (cpu
, out_spr
, cycles
+ ?);
1190 frvbf_model_fr500_u_ici (SIM_CPU
*cpu
, const IDESC
*idesc
,
1191 int unit_num
, int referenced
,
1192 INT in_GRi
, INT in_GRj
)
1196 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1198 /* The entire VLIW insn must wait if there is a dependency on a register
1199 which is not ready yet.
1200 The latency of the registers may be less than previously recorded,
1201 depending on how they were used previously.
1202 See Table 13-8 in the LSI. */
1205 if (use_is_gr_complex (cpu
, in_GRi
))
1206 decrease_GR_busy (cpu
, in_GRi
, 1);
1208 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1210 if (use_is_gr_complex (cpu
, in_GRj
))
1211 decrease_GR_busy (cpu
, in_GRj
, 1);
1213 vliw_wait_for_GR (cpu
, in_GRi
);
1214 vliw_wait_for_GR (cpu
, in_GRj
);
1215 handle_resource_wait (cpu
);
1216 load_wait_for_GR (cpu
, in_GRi
);
1217 load_wait_for_GR (cpu
, in_GRj
);
1218 trace_vliw_wait_cycles (cpu
);
1222 cycles
= idesc
->timing
->units
[unit_num
].done
;
1223 request_cache_invalidate (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1228 frvbf_model_fr500_u_dci (SIM_CPU
*cpu
, const IDESC
*idesc
,
1229 int unit_num
, int referenced
,
1230 INT in_GRi
, INT in_GRj
)
1234 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1236 /* The entire VLIW insn must wait if there is a dependency on a register
1237 which is not ready yet.
1238 The latency of the registers may be less than previously recorded,
1239 depending on how they were used previously.
1240 See Table 13-8 in the LSI. */
1243 if (use_is_gr_complex (cpu
, in_GRi
))
1244 decrease_GR_busy (cpu
, in_GRi
, 1);
1246 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1248 if (use_is_gr_complex (cpu
, in_GRj
))
1249 decrease_GR_busy (cpu
, in_GRj
, 1);
1251 vliw_wait_for_GR (cpu
, in_GRi
);
1252 vliw_wait_for_GR (cpu
, in_GRj
);
1253 handle_resource_wait (cpu
);
1254 load_wait_for_GR (cpu
, in_GRi
);
1255 load_wait_for_GR (cpu
, in_GRj
);
1256 trace_vliw_wait_cycles (cpu
);
1260 cycles
= idesc
->timing
->units
[unit_num
].done
;
1261 request_cache_invalidate (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1266 frvbf_model_fr500_u_dcf (SIM_CPU
*cpu
, const IDESC
*idesc
,
1267 int unit_num
, int referenced
,
1268 INT in_GRi
, INT in_GRj
)
1272 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1274 /* The entire VLIW insn must wait if there is a dependency on a register
1275 which is not ready yet.
1276 The latency of the registers may be less than previously recorded,
1277 depending on how they were used previously.
1278 See Table 13-8 in the LSI. */
1281 if (use_is_gr_complex (cpu
, in_GRi
))
1282 decrease_GR_busy (cpu
, in_GRi
, 1);
1284 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1286 if (use_is_gr_complex (cpu
, in_GRj
))
1287 decrease_GR_busy (cpu
, in_GRj
, 1);
1289 vliw_wait_for_GR (cpu
, in_GRi
);
1290 vliw_wait_for_GR (cpu
, in_GRj
);
1291 handle_resource_wait (cpu
);
1292 load_wait_for_GR (cpu
, in_GRi
);
1293 load_wait_for_GR (cpu
, in_GRj
);
1294 trace_vliw_wait_cycles (cpu
);
1298 cycles
= idesc
->timing
->units
[unit_num
].done
;
1299 request_cache_flush (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1304 frvbf_model_fr500_u_icpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
1305 int unit_num
, int referenced
,
1306 INT in_GRi
, INT in_GRj
)
1310 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1312 /* The entire VLIW insn must wait if there is a dependency on a register
1313 which is not ready yet.
1314 The latency of the registers may be less than previously recorded,
1315 depending on how they were used previously.
1316 See Table 13-8 in the LSI. */
1319 if (use_is_gr_complex (cpu
, in_GRi
))
1320 decrease_GR_busy (cpu
, in_GRi
, 1);
1322 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1324 if (use_is_gr_complex (cpu
, in_GRj
))
1325 decrease_GR_busy (cpu
, in_GRj
, 1);
1327 vliw_wait_for_GR (cpu
, in_GRi
);
1328 vliw_wait_for_GR (cpu
, in_GRj
);
1329 handle_resource_wait (cpu
);
1330 load_wait_for_GR (cpu
, in_GRi
);
1331 load_wait_for_GR (cpu
, in_GRj
);
1332 trace_vliw_wait_cycles (cpu
);
1336 cycles
= idesc
->timing
->units
[unit_num
].done
;
1337 request_cache_preload (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1342 frvbf_model_fr500_u_dcpl (SIM_CPU
*cpu
, const IDESC
*idesc
,
1343 int unit_num
, int referenced
,
1344 INT in_GRi
, INT in_GRj
)
1348 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1350 /* The entire VLIW insn must wait if there is a dependency on a register
1351 which is not ready yet.
1352 The latency of the registers may be less than previously recorded,
1353 depending on how they were used previously.
1354 See Table 13-8 in the LSI. */
1357 if (use_is_gr_complex (cpu
, in_GRi
))
1358 decrease_GR_busy (cpu
, in_GRi
, 1);
1360 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1362 if (use_is_gr_complex (cpu
, in_GRj
))
1363 decrease_GR_busy (cpu
, in_GRj
, 1);
1365 vliw_wait_for_GR (cpu
, in_GRi
);
1366 vliw_wait_for_GR (cpu
, in_GRj
);
1367 handle_resource_wait (cpu
);
1368 load_wait_for_GR (cpu
, in_GRi
);
1369 load_wait_for_GR (cpu
, in_GRj
);
1370 trace_vliw_wait_cycles (cpu
);
1374 cycles
= idesc
->timing
->units
[unit_num
].done
;
1375 request_cache_preload (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1380 frvbf_model_fr500_u_icul (SIM_CPU
*cpu
, const IDESC
*idesc
,
1381 int unit_num
, int referenced
,
1382 INT in_GRi
, INT in_GRj
)
1386 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1388 /* The entire VLIW insn must wait if there is a dependency on a register
1389 which is not ready yet.
1390 The latency of the registers may be less than previously recorded,
1391 depending on how they were used previously.
1392 See Table 13-8 in the LSI. */
1395 if (use_is_gr_complex (cpu
, in_GRi
))
1396 decrease_GR_busy (cpu
, in_GRi
, 1);
1398 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1400 if (use_is_gr_complex (cpu
, in_GRj
))
1401 decrease_GR_busy (cpu
, in_GRj
, 1);
1403 vliw_wait_for_GR (cpu
, in_GRi
);
1404 vliw_wait_for_GR (cpu
, in_GRj
);
1405 handle_resource_wait (cpu
);
1406 load_wait_for_GR (cpu
, in_GRi
);
1407 load_wait_for_GR (cpu
, in_GRj
);
1408 trace_vliw_wait_cycles (cpu
);
1412 cycles
= idesc
->timing
->units
[unit_num
].done
;
1413 request_cache_unlock (cpu
, CPU_INSN_CACHE (cpu
), cycles
);
1418 frvbf_model_fr500_u_dcul (SIM_CPU
*cpu
, const IDESC
*idesc
,
1419 int unit_num
, int referenced
,
1420 INT in_GRi
, INT in_GRj
)
1424 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1426 /* The entire VLIW insn must wait if there is a dependency on a register
1427 which is not ready yet.
1428 The latency of the registers may be less than previously recorded,
1429 depending on how they were used previously.
1430 See Table 13-8 in the LSI. */
1433 if (use_is_gr_complex (cpu
, in_GRi
))
1434 decrease_GR_busy (cpu
, in_GRi
, 1);
1436 if (in_GRj
!= in_GRi
&& in_GRj
>= 0)
1438 if (use_is_gr_complex (cpu
, in_GRj
))
1439 decrease_GR_busy (cpu
, in_GRj
, 1);
1441 vliw_wait_for_GR (cpu
, in_GRi
);
1442 vliw_wait_for_GR (cpu
, in_GRj
);
1443 handle_resource_wait (cpu
);
1444 load_wait_for_GR (cpu
, in_GRi
);
1445 load_wait_for_GR (cpu
, in_GRj
);
1446 trace_vliw_wait_cycles (cpu
);
1450 cycles
= idesc
->timing
->units
[unit_num
].done
;
1451 request_cache_unlock (cpu
, CPU_DATA_CACHE (cpu
), cycles
);
1456 frvbf_model_fr500_u_float_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
1457 int unit_num
, int referenced
,
1458 INT in_FRi
, INT in_FRj
,
1459 INT in_FRdoublei
, INT in_FRdoublej
,
1460 INT out_FRk
, INT out_FRdoublek
)
1463 FRV_PROFILE_STATE
*ps
;
1465 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1468 /* The preprocessing can execute right away. */
1469 cycles
= idesc
->timing
->units
[unit_num
].done
;
1471 /* The post processing must wait if there is a dependency on a FR
1472 which is not ready yet. */
1473 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1474 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1476 ps
= CPU_PROFILE_STATE (cpu
);
1477 ps
->post_wait
= cycles
;
1478 post_wait_for_FR (cpu
, in_FRi
);
1479 post_wait_for_FR (cpu
, in_FRj
);
1480 post_wait_for_FR (cpu
, out_FRk
);
1481 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1482 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1483 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1484 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1486 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1487 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1489 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1490 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1493 /* The latency of FRk will be at least the latency of the other inputs. */
1494 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1495 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1497 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1499 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1500 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1503 /* Once initiated, post-processing will take 3 cycles. */
1504 update_FR_ptime (cpu
, out_FRk
, 3);
1505 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1507 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1509 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1510 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1513 /* Mark this use of the register as a floating point op. */
1515 set_use_is_fpop (cpu
, out_FRk
);
1516 if (out_FRdoublek
>= 0)
1518 set_use_is_fpop (cpu
, out_FRdoublek
);
1519 if (out_FRdoublek
< 63)
1520 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1527 frvbf_model_fr500_u_float_dual_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
1528 int unit_num
, int referenced
,
1529 INT in_FRi
, INT in_FRj
,
1530 INT in_FRdoublei
, INT in_FRdoublej
,
1531 INT out_FRk
, INT out_FRdoublek
)
1540 FRV_PROFILE_STATE
*ps
;
1542 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1545 /* The preprocessing can execute right away. */
1546 cycles
= idesc
->timing
->units
[unit_num
].done
;
1548 /* The post processing must wait if there is a dependency on a FR
1549 which is not ready yet. */
1550 dual_FRi
= DUAL_REG (in_FRi
);
1551 dual_FRj
= DUAL_REG (in_FRj
);
1552 dual_FRk
= DUAL_REG (out_FRk
);
1553 dual_FRdoublei
= DUAL_DOUBLE (in_FRdoublei
);
1554 dual_FRdoublej
= DUAL_DOUBLE (in_FRdoublej
);
1555 dual_FRdoublek
= DUAL_DOUBLE (out_FRdoublek
);
1557 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1558 adjust_float_register_busy (cpu
, dual_FRi
, dual_FRj
, dual_FRk
, 1);
1559 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1561 adjust_double_register_busy (cpu
, dual_FRdoublei
, dual_FRdoublej
,
1563 ps
= CPU_PROFILE_STATE (cpu
);
1564 ps
->post_wait
= cycles
;
1565 post_wait_for_FR (cpu
, in_FRi
);
1566 post_wait_for_FR (cpu
, in_FRj
);
1567 post_wait_for_FR (cpu
, out_FRk
);
1568 post_wait_for_FR (cpu
, dual_FRi
);
1569 post_wait_for_FR (cpu
, dual_FRj
);
1570 post_wait_for_FR (cpu
, dual_FRk
);
1571 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1572 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1573 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1574 post_wait_for_FRdouble (cpu
, dual_FRdoublei
);
1575 post_wait_for_FRdouble (cpu
, dual_FRdoublej
);
1576 post_wait_for_FRdouble (cpu
, dual_FRdoublek
);
1577 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1579 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1580 post_wait_for_SPR (cpu
, FNER_FOR_FR (dual_FRk
));
1581 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1582 post_wait_for_SPR (cpu
, FNER_FOR_FR (dual_FRdoublek
));
1584 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1585 restore_float_register_busy (cpu
, dual_FRi
, dual_FRj
, dual_FRk
, 1);
1586 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, out_FRdoublek
,
1588 restore_double_register_busy (cpu
, dual_FRdoublei
, dual_FRdoublej
,
1591 /* The latency of FRk will be at least the latency of the other inputs. */
1592 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1593 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
1594 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1595 update_FRdouble_latency (cpu
, dual_FRdoublek
, ps
->post_wait
);
1597 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1599 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1600 update_SPR_latency (cpu
, FNER_FOR_FR (dual_FRk
), ps
->post_wait
);
1601 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1602 update_SPR_latency (cpu
, FNER_FOR_FR (dual_FRdoublek
), ps
->post_wait
);
1605 /* Once initiated, post-processing will take 3 cycles. */
1606 update_FR_ptime (cpu
, out_FRk
, 3);
1607 update_FR_ptime (cpu
, dual_FRk
, 3);
1608 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1609 update_FRdouble_ptime (cpu
, dual_FRdoublek
, 3);
1611 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1613 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1614 update_SPR_ptime (cpu
, FNER_FOR_FR (dual_FRk
), 3);
1615 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1616 update_SPR_ptime (cpu
, FNER_FOR_FR (dual_FRdoublek
), 3);
1619 /* Mark this use of the register as a floating point op. */
1621 set_use_is_fpop (cpu
, out_FRk
);
1623 set_use_is_fpop (cpu
, dual_FRk
);
1624 if (out_FRdoublek
>= 0)
1626 set_use_is_fpop (cpu
, out_FRdoublek
);
1627 if (out_FRdoublek
< 63)
1628 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1630 if (dual_FRdoublek
>= 0)
1632 set_use_is_fpop (cpu
, dual_FRdoublek
);
1633 if (dual_FRdoublek
< 63)
1634 set_use_is_fpop (cpu
, dual_FRdoublek
+ 1);
1641 frvbf_model_fr500_u_float_div (SIM_CPU
*cpu
, const IDESC
*idesc
,
1642 int unit_num
, int referenced
,
1643 INT in_FRi
, INT in_FRj
, INT out_FRk
)
1648 FRV_PROFILE_STATE
*ps
;
1650 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1653 cycles
= idesc
->timing
->units
[unit_num
].done
;
1655 /* The post processing must wait if there is a dependency on a FR
1656 which is not ready yet. */
1657 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1658 ps
= CPU_PROFILE_STATE (cpu
);
1659 ps
->post_wait
= cycles
;
1660 post_wait_for_FR (cpu
, in_FRi
);
1661 post_wait_for_FR (cpu
, in_FRj
);
1662 post_wait_for_FR (cpu
, out_FRk
);
1663 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1664 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1665 vliw
= CPU_VLIW (cpu
);
1666 slot
= vliw
->next_slot
- 1;
1667 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1668 post_wait_for_fdiv (cpu
, slot
);
1669 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, out_FRk
, 1);
1671 /* The latency of FRk will be at least the latency of the other inputs. */
1672 /* Once initiated, post-processing will take 10 cycles. */
1673 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1674 update_FR_ptime (cpu
, out_FRk
, 10);
1676 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1678 /* FNER has a latency of 10 cycles. */
1679 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1680 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 10);
1683 /* The latency of the fdiv unit will be at least the latency of the other
1684 inputs. Once initiated, post-processing will take 9 cycles. */
1685 update_fdiv_resource_latency (cpu
, slot
, ps
->post_wait
+ 9);
1687 /* Mark this use of the register as a floating point op. */
1688 set_use_is_fpop (cpu
, out_FRk
);
1694 frvbf_model_fr500_u_float_sqrt (SIM_CPU
*cpu
, const IDESC
*idesc
,
1695 int unit_num
, int referenced
,
1696 INT in_FRj
, INT in_FRdoublej
,
1697 INT out_FRk
, INT out_FRdoublek
)
1702 FRV_PROFILE_STATE
*ps
;
1704 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1707 cycles
= idesc
->timing
->units
[unit_num
].done
;
1709 /* The post processing must wait if there is a dependency on a FR
1710 which is not ready yet. */
1711 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1712 adjust_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1713 ps
= CPU_PROFILE_STATE (cpu
);
1714 ps
->post_wait
= cycles
;
1715 post_wait_for_FR (cpu
, in_FRj
);
1716 post_wait_for_FR (cpu
, out_FRk
);
1717 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1718 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1719 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1720 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1721 vliw
= CPU_VLIW (cpu
);
1722 slot
= vliw
->next_slot
- 1;
1723 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1724 post_wait_for_fsqrt (cpu
, slot
);
1725 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1726 restore_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1728 /* The latency of FRk will be at least the latency of the other inputs. */
1729 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1730 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1731 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1732 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1734 /* Once initiated, post-processing will take 15 cycles. */
1735 update_FR_ptime (cpu
, out_FRk
, 15);
1736 update_FRdouble_ptime (cpu
, out_FRdoublek
, 15);
1738 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1739 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 15);
1741 /* The latency of the sqrt unit will be the latency of the other
1742 inputs plus 14 cycles. */
1743 update_fsqrt_resource_latency (cpu
, slot
, ps
->post_wait
+ 14);
1745 /* Mark this use of the register as a floating point op. */
1747 set_use_is_fpop (cpu
, out_FRk
);
1748 if (out_FRdoublek
>= 0)
1750 set_use_is_fpop (cpu
, out_FRdoublek
);
1751 if (out_FRdoublek
< 63)
1752 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1759 frvbf_model_fr500_u_float_dual_sqrt (SIM_CPU
*cpu
, const IDESC
*idesc
,
1760 int unit_num
, int referenced
,
1761 INT in_FRj
, INT out_FRk
)
1768 FRV_PROFILE_STATE
*ps
;
1770 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1773 cycles
= idesc
->timing
->units
[unit_num
].done
;
1775 /* The post processing must wait if there is a dependency on a FR
1776 which is not ready yet. */
1777 dual_FRj
= DUAL_REG (in_FRj
);
1778 dual_FRk
= DUAL_REG (out_FRk
);
1779 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1780 adjust_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
1781 ps
= CPU_PROFILE_STATE (cpu
);
1782 ps
->post_wait
= cycles
;
1783 post_wait_for_FR (cpu
, in_FRj
);
1784 post_wait_for_FR (cpu
, out_FRk
);
1785 post_wait_for_FR (cpu
, dual_FRj
);
1786 post_wait_for_FR (cpu
, dual_FRk
);
1788 vliw
= CPU_VLIW (cpu
);
1789 slot
= vliw
->next_slot
- 1;
1790 slot
= (*vliw
->current_vliw
)[slot
] - UNIT_FM0
;
1791 post_wait_for_fsqrt (cpu
, slot
);
1792 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1793 restore_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
1795 /* The latency of FRk will be at least the latency of the other inputs. */
1796 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1797 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
1799 /* Once initiated, post-processing will take 15 cycles. */
1800 update_FR_ptime (cpu
, out_FRk
, 15);
1801 update_FR_ptime (cpu
, dual_FRk
, 15);
1803 /* The latency of the sqrt unit will be at least the latency of the other
1805 update_fsqrt_resource_latency (cpu
, slot
, ps
->post_wait
+ 14);
1807 /* Mark this use of the register as a floating point op. */
1809 set_use_is_fpop (cpu
, out_FRk
);
1811 set_use_is_fpop (cpu
, dual_FRk
);
1817 frvbf_model_fr500_u_float_compare (SIM_CPU
*cpu
, const IDESC
*idesc
,
1818 int unit_num
, int referenced
,
1819 INT in_FRi
, INT in_FRj
,
1820 INT in_FRdoublei
, INT in_FRdoublej
,
1824 FRV_PROFILE_STATE
*ps
;
1826 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1829 /* The preprocessing can execute right away. */
1830 cycles
= idesc
->timing
->units
[unit_num
].done
;
1832 /* The post processing must wait if there is a dependency on a FR
1833 which is not ready yet. */
1834 adjust_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, -1, 1);
1835 ps
= CPU_PROFILE_STATE (cpu
);
1836 ps
->post_wait
= cycles
;
1837 post_wait_for_FR (cpu
, in_FRi
);
1838 post_wait_for_FR (cpu
, in_FRj
);
1839 post_wait_for_FRdouble (cpu
, in_FRdoublei
);
1840 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1841 post_wait_for_CCR (cpu
, out_FCCi_2
);
1842 restore_double_register_busy (cpu
, in_FRdoublei
, in_FRdoublej
, -1, 1);
1844 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1846 update_CCR_latency (cpu
, out_FCCi_2
, ps
->post_wait
+ 3);
1852 frvbf_model_fr500_u_float_dual_compare (SIM_CPU
*cpu
, const IDESC
*idesc
,
1853 int unit_num
, int referenced
,
1854 INT in_FRi
, INT in_FRj
,
1861 FRV_PROFILE_STATE
*ps
;
1863 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1866 /* The preprocessing can execute right away. */
1867 cycles
= idesc
->timing
->units
[unit_num
].done
;
1869 /* The post processing must wait if there is a dependency on a FR
1870 which is not ready yet. */
1871 ps
= CPU_PROFILE_STATE (cpu
);
1872 ps
->post_wait
= cycles
;
1873 dual_FRi
= DUAL_REG (in_FRi
);
1874 dual_FRj
= DUAL_REG (in_FRj
);
1875 dual_FCCi_2
= out_FCCi_2
+ 1;
1876 adjust_float_register_busy (cpu
, in_FRi
, in_FRj
, -1, 1);
1877 adjust_float_register_busy (cpu
, dual_FRi
, dual_FRj
, -1, 1);
1878 post_wait_for_FR (cpu
, in_FRi
);
1879 post_wait_for_FR (cpu
, in_FRj
);
1880 post_wait_for_FR (cpu
, dual_FRi
);
1881 post_wait_for_FR (cpu
, dual_FRj
);
1882 post_wait_for_CCR (cpu
, out_FCCi_2
);
1883 post_wait_for_CCR (cpu
, dual_FCCi_2
);
1884 restore_float_register_busy (cpu
, in_FRi
, in_FRj
, -1, 1);
1885 restore_float_register_busy (cpu
, dual_FRi
, dual_FRj
, -1, 1);
1887 /* The latency of FCCi_2 will be the latency of the other inputs plus 3
1889 update_CCR_latency (cpu
, out_FCCi_2
, ps
->post_wait
+ 3);
1890 update_CCR_latency (cpu
, dual_FCCi_2
, ps
->post_wait
+ 3);
1896 frvbf_model_fr500_u_float_convert (SIM_CPU
*cpu
, const IDESC
*idesc
,
1897 int unit_num
, int referenced
,
1898 INT in_FRj
, INT in_FRintj
, INT in_FRdoublej
,
1899 INT out_FRk
, INT out_FRintk
,
1903 FRV_PROFILE_STATE
*ps
;
1905 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1908 /* The preprocessing can execute right away. */
1909 cycles
= idesc
->timing
->units
[unit_num
].done
;
1911 /* The post processing must wait if there is a dependency on a FR
1912 which is not ready yet. */
1913 ps
= CPU_PROFILE_STATE (cpu
);
1914 ps
->post_wait
= cycles
;
1915 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1916 adjust_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
1917 adjust_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1918 post_wait_for_FR (cpu
, in_FRj
);
1919 post_wait_for_FR (cpu
, in_FRintj
);
1920 post_wait_for_FRdouble (cpu
, in_FRdoublej
);
1921 post_wait_for_FR (cpu
, out_FRk
);
1922 post_wait_for_FR (cpu
, out_FRintk
);
1923 post_wait_for_FRdouble (cpu
, out_FRdoublek
);
1924 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1926 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRk
));
1927 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRintk
));
1928 post_wait_for_SPR (cpu
, FNER_FOR_FR (out_FRdoublek
));
1930 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
1931 restore_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
1932 restore_double_register_busy (cpu
, -1, in_FRdoublej
, out_FRdoublek
, 1);
1934 /* The latency of FRk will be at least the latency of the other inputs. */
1935 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
1936 update_FR_latency (cpu
, out_FRintk
, ps
->post_wait
);
1937 update_FRdouble_latency (cpu
, out_FRdoublek
, ps
->post_wait
);
1939 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1941 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRk
), ps
->post_wait
);
1942 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRintk
), ps
->post_wait
);
1943 update_SPR_latency (cpu
, FNER_FOR_FR (out_FRdoublek
), ps
->post_wait
);
1946 /* Once initiated, post-processing will take 3 cycles. */
1947 update_FR_ptime (cpu
, out_FRk
, 3);
1948 update_FR_ptime (cpu
, out_FRintk
, 3);
1949 update_FRdouble_ptime (cpu
, out_FRdoublek
, 3);
1951 if (CGEN_ATTR_VALUE(idesc
, idesc
->attrs
, CGEN_INSN_NON_EXCEPTING
))
1953 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRk
), 3);
1954 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRintk
), 3);
1955 update_SPR_ptime (cpu
, FNER_FOR_FR (out_FRdoublek
), 3);
1958 /* Mark this use of the register as a floating point op. */
1960 set_use_is_fpop (cpu
, out_FRk
);
1961 if (out_FRintk
>= 0)
1962 set_use_is_fpop (cpu
, out_FRintk
);
1963 if (out_FRdoublek
>= 0)
1965 set_use_is_fpop (cpu
, out_FRdoublek
);
1966 set_use_is_fpop (cpu
, out_FRdoublek
+ 1);
1973 frvbf_model_fr500_u_float_dual_convert (SIM_CPU
*cpu
, const IDESC
*idesc
,
1974 int unit_num
, int referenced
,
1975 INT in_FRj
, INT in_FRintj
,
1976 INT out_FRk
, INT out_FRintk
)
1983 FRV_PROFILE_STATE
*ps
;
1985 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
1988 /* The preprocessing can execute right away. */
1989 cycles
= idesc
->timing
->units
[unit_num
].done
;
1991 /* The post processing must wait if there is a dependency on a FR
1992 which is not ready yet. */
1993 ps
= CPU_PROFILE_STATE (cpu
);
1994 ps
->post_wait
= cycles
;
1995 dual_FRj
= DUAL_REG (in_FRj
);
1996 dual_FRintj
= DUAL_REG (in_FRintj
);
1997 dual_FRk
= DUAL_REG (out_FRk
);
1998 dual_FRintk
= DUAL_REG (out_FRintk
);
1999 adjust_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
2000 adjust_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
2001 adjust_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
2002 adjust_float_register_busy (cpu
, -1, dual_FRintj
, dual_FRintk
, 1);
2003 post_wait_for_FR (cpu
, in_FRj
);
2004 post_wait_for_FR (cpu
, in_FRintj
);
2005 post_wait_for_FR (cpu
, out_FRk
);
2006 post_wait_for_FR (cpu
, out_FRintk
);
2007 post_wait_for_FR (cpu
, dual_FRj
);
2008 post_wait_for_FR (cpu
, dual_FRintj
);
2009 post_wait_for_FR (cpu
, dual_FRk
);
2010 post_wait_for_FR (cpu
, dual_FRintk
);
2011 restore_float_register_busy (cpu
, -1, in_FRj
, out_FRk
, 1);
2012 restore_float_register_busy (cpu
, -1, dual_FRj
, dual_FRk
, 1);
2013 restore_float_register_busy (cpu
, -1, in_FRintj
, out_FRintk
, 1);
2014 restore_float_register_busy (cpu
, -1, dual_FRintj
, dual_FRintk
, 1);
2016 /* The latency of FRk will be at least the latency of the other inputs. */
2017 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2018 update_FR_latency (cpu
, out_FRintk
, ps
->post_wait
);
2019 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2020 update_FR_latency (cpu
, dual_FRintk
, ps
->post_wait
);
2022 /* Once initiated, post-processing will take 3 cycles. */
2023 update_FR_ptime (cpu
, out_FRk
, 3);
2024 update_FR_ptime (cpu
, out_FRintk
, 3);
2025 update_FR_ptime (cpu
, dual_FRk
, 3);
2026 update_FR_ptime (cpu
, dual_FRintk
, 3);
2028 /* Mark this use of the register as a floating point op. */
2030 set_use_is_fpop (cpu
, out_FRk
);
2031 if (out_FRintk
>= 0)
2032 set_use_is_fpop (cpu
, out_FRintk
);
2038 frvbf_model_fr500_u_media (SIM_CPU
*cpu
, const IDESC
*idesc
,
2039 int unit_num
, int referenced
,
2040 INT in_FRi
, INT in_FRj
, INT in_ACC40Si
, INT in_ACCGi
,
2042 INT out_ACC40Sk
, INT out_ACC40Uk
, INT out_ACCGk
)
2045 FRV_PROFILE_STATE
*ps
;
2046 const CGEN_INSN
*insn
;
2049 int busy_adjustment
[] = {0, 0, 0};
2053 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2056 /* The preprocessing can execute right away. */
2057 cycles
= idesc
->timing
->units
[unit_num
].done
;
2059 ps
= CPU_PROFILE_STATE (cpu
);
2060 insn
= idesc
->idata
;
2062 /* If the previous use of the registers was a media op,
2063 then their latency will be less than previously recorded.
2064 See Table 13-13 in the LSI. */
2067 if (use_is_media (cpu
, in_FRi
))
2069 busy_adjustment
[0] = 2;
2070 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2073 enforce_full_fr_latency (cpu
, in_FRi
);
2075 if (in_FRj
>= 0 && in_FRj
!= in_FRi
)
2077 if (use_is_media (cpu
, in_FRj
))
2079 busy_adjustment
[1] = 2;
2080 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
2083 enforce_full_fr_latency (cpu
, in_FRj
);
2085 if (out_FRk
>= 0 && out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
2087 if (use_is_media (cpu
, out_FRk
))
2089 busy_adjustment
[2] = 2;
2090 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2093 enforce_full_fr_latency (cpu
, out_FRk
);
2096 /* The post processing must wait if there is a dependency on a FR
2097 which is not ready yet. */
2098 ps
->post_wait
= cycles
;
2099 post_wait_for_FR (cpu
, in_FRi
);
2100 post_wait_for_FR (cpu
, in_FRj
);
2101 post_wait_for_FR (cpu
, out_FRk
);
2102 post_wait_for_ACC (cpu
, in_ACC40Si
);
2103 post_wait_for_ACC (cpu
, in_ACCGi
);
2104 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2105 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2106 post_wait_for_ACC (cpu
, out_ACCGk
);
2108 /* Restore the busy cycles of the registers we used. */
2111 fr
[in_FRi
] += busy_adjustment
[0];
2113 fr
[in_FRj
] += busy_adjustment
[1];
2115 fr
[out_FRk
] += busy_adjustment
[2];
2117 /* The latency of tht output register will be at least the latency of the
2118 other inputs. Once initiated, post-processing will take 3 cycles. */
2121 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2122 update_FR_ptime (cpu
, out_FRk
, 3);
2123 /* Mark this use of the register as a media op. */
2124 set_use_is_media (cpu
, out_FRk
);
2126 /* The latency of tht output accumulator will be at least the latency of the
2127 other inputs. Once initiated, post-processing will take 1 cycle. */
2128 if (out_ACC40Sk
>= 0)
2129 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2130 if (out_ACC40Uk
>= 0)
2131 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2133 update_ACC_latency (cpu
, out_ACCGk
, ps
->post_wait
+ 1);
2139 frvbf_model_fr500_u_media_quad_arith (SIM_CPU
*cpu
, const IDESC
*idesc
,
2140 int unit_num
, int referenced
,
2141 INT in_FRi
, INT in_FRj
,
2148 FRV_PROFILE_STATE
*ps
;
2149 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2152 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2155 /* The preprocessing can execute right away. */
2156 cycles
= idesc
->timing
->units
[unit_num
].done
;
2158 ps
= CPU_PROFILE_STATE (cpu
);
2159 dual_FRi
= DUAL_REG (in_FRi
);
2160 dual_FRj
= DUAL_REG (in_FRj
);
2161 dual_FRk
= DUAL_REG (out_FRk
);
2163 /* If the previous use of the registers was a media op,
2164 then their latency will be less than previously recorded.
2165 See Table 13-13 in the LSI. */
2166 if (use_is_media (cpu
, in_FRi
))
2168 busy_adjustment
[0] = 2;
2169 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2172 enforce_full_fr_latency (cpu
, in_FRi
);
2173 if (dual_FRi
>= 0 && use_is_media (cpu
, dual_FRi
))
2175 busy_adjustment
[1] = 2;
2176 decrease_FR_busy (cpu
, dual_FRi
, busy_adjustment
[1]);
2179 enforce_full_fr_latency (cpu
, dual_FRi
);
2180 if (in_FRj
!= in_FRi
)
2182 if (use_is_media (cpu
, in_FRj
))
2184 busy_adjustment
[2] = 2;
2185 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2188 enforce_full_fr_latency (cpu
, in_FRj
);
2189 if (dual_FRj
>= 0 && use_is_media (cpu
, dual_FRj
))
2191 busy_adjustment
[3] = 2;
2192 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[3]);
2195 enforce_full_fr_latency (cpu
, dual_FRj
+ 1);
2197 if (out_FRk
!= in_FRi
&& out_FRk
!= in_FRj
)
2199 if (use_is_media (cpu
, out_FRk
))
2201 busy_adjustment
[4] = 2;
2202 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[4]);
2205 enforce_full_fr_latency (cpu
, out_FRk
);
2206 if (dual_FRk
>= 0 && use_is_media (cpu
, dual_FRk
))
2208 busy_adjustment
[5] = 2;
2209 decrease_FR_busy (cpu
, dual_FRk
, busy_adjustment
[5]);
2212 enforce_full_fr_latency (cpu
, dual_FRk
);
2215 /* The post processing must wait if there is a dependency on a FR
2216 which is not ready yet. */
2217 ps
->post_wait
= cycles
;
2218 post_wait_for_FR (cpu
, in_FRi
);
2219 post_wait_for_FR (cpu
, dual_FRi
);
2220 post_wait_for_FR (cpu
, in_FRj
);
2221 post_wait_for_FR (cpu
, dual_FRj
);
2222 post_wait_for_FR (cpu
, out_FRk
);
2223 post_wait_for_FR (cpu
, dual_FRk
);
2225 /* Restore the busy cycles of the registers we used. */
2227 fr
[in_FRi
] += busy_adjustment
[0];
2229 fr
[dual_FRi
] += busy_adjustment
[1];
2230 fr
[in_FRj
] += busy_adjustment
[2];
2232 fr
[dual_FRj
] += busy_adjustment
[3];
2233 fr
[out_FRk
] += busy_adjustment
[4];
2235 fr
[dual_FRk
] += busy_adjustment
[5];
2237 /* The latency of tht output register will be at least the latency of the
2239 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2241 /* Once initiated, post-processing will take 3 cycles. */
2242 update_FR_ptime (cpu
, out_FRk
, 3);
2244 /* Mark this use of the register as a media op. */
2245 set_use_is_media (cpu
, out_FRk
);
2248 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2249 update_FR_ptime (cpu
, dual_FRk
, 3);
2250 /* Mark this use of the register as a media op. */
2251 set_use_is_media (cpu
, dual_FRk
);
2258 frvbf_model_fr500_u_media_dual_mul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2259 int unit_num
, int referenced
,
2260 INT in_FRi
, INT in_FRj
,
2261 INT out_ACC40Sk
, INT out_ACC40Uk
)
2266 FRV_PROFILE_STATE
*ps
;
2267 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2271 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2274 /* The preprocessing can execute right away. */
2275 cycles
= idesc
->timing
->units
[unit_num
].done
;
2277 ps
= CPU_PROFILE_STATE (cpu
);
2278 dual_ACC40Sk
= DUAL_REG (out_ACC40Sk
);
2279 dual_ACC40Uk
= DUAL_REG (out_ACC40Uk
);
2281 /* If the previous use of the registers was a media op,
2282 then their latency will be less than previously recorded.
2283 See Table 13-13 in the LSI. */
2284 if (use_is_media (cpu
, in_FRi
))
2286 busy_adjustment
[0] = 2;
2287 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2290 enforce_full_fr_latency (cpu
, in_FRi
);
2291 if (in_FRj
!= in_FRi
)
2293 if (use_is_media (cpu
, in_FRj
))
2295 busy_adjustment
[1] = 2;
2296 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[1]);
2299 enforce_full_fr_latency (cpu
, in_FRj
);
2301 if (out_ACC40Sk
>= 0)
2303 busy_adjustment
[2] = 1;
2304 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[2]);
2306 if (dual_ACC40Sk
>= 0)
2308 busy_adjustment
[3] = 1;
2309 decrease_ACC_busy (cpu
, dual_ACC40Sk
, busy_adjustment
[3]);
2311 if (out_ACC40Uk
>= 0)
2313 busy_adjustment
[4] = 1;
2314 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
2316 if (dual_ACC40Uk
>= 0)
2318 busy_adjustment
[5] = 1;
2319 decrease_ACC_busy (cpu
, dual_ACC40Uk
, busy_adjustment
[5]);
2322 /* The post processing must wait if there is a dependency on a FR
2323 which is not ready yet. */
2324 ps
->post_wait
= cycles
;
2325 post_wait_for_FR (cpu
, in_FRi
);
2326 post_wait_for_FR (cpu
, in_FRj
);
2327 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2328 post_wait_for_ACC (cpu
, dual_ACC40Sk
);
2329 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2330 post_wait_for_ACC (cpu
, dual_ACC40Uk
);
2332 /* Restore the busy cycles of the registers we used. */
2335 fr
[in_FRi
] += busy_adjustment
[0];
2336 fr
[in_FRj
] += busy_adjustment
[1];
2337 if (out_ACC40Sk
>= 0)
2338 acc
[out_ACC40Sk
] += busy_adjustment
[2];
2339 if (dual_ACC40Sk
>= 0)
2340 acc
[dual_ACC40Sk
] += busy_adjustment
[3];
2341 if (out_ACC40Uk
>= 0)
2342 acc
[out_ACC40Uk
] += busy_adjustment
[4];
2343 if (dual_ACC40Uk
>= 0)
2344 acc
[dual_ACC40Uk
] += busy_adjustment
[5];
2346 /* The latency of tht output register will be at least the latency of the
2347 other inputs. Once initiated, post-processing will take 1 cycle. */
2348 if (out_ACC40Sk
>= 0)
2349 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2350 if (dual_ACC40Sk
>= 0)
2351 update_ACC_latency (cpu
, dual_ACC40Sk
, ps
->post_wait
+ 1);
2352 if (out_ACC40Uk
>= 0)
2353 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2354 if (dual_ACC40Uk
>= 0)
2355 update_ACC_latency (cpu
, dual_ACC40Uk
, ps
->post_wait
+ 1);
2361 frvbf_model_fr500_u_media_quad_mul (SIM_CPU
*cpu
, const IDESC
*idesc
,
2362 int unit_num
, int referenced
,
2363 INT in_FRi
, INT in_FRj
,
2364 INT out_ACC40Sk
, INT out_ACC40Uk
)
2375 FRV_PROFILE_STATE
*ps
;
2376 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0, 0 ,0};
2380 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2383 /* The preprocessing can execute right away. */
2384 cycles
= idesc
->timing
->units
[unit_num
].done
;
2386 FRi_1
= DUAL_REG (in_FRi
);
2387 FRj_1
= DUAL_REG (in_FRj
);
2388 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
2389 ACC40Sk_2
= DUAL_REG (ACC40Sk_1
);
2390 ACC40Sk_3
= DUAL_REG (ACC40Sk_2
);
2391 ACC40Uk_1
= DUAL_REG (out_ACC40Uk
);
2392 ACC40Uk_2
= DUAL_REG (ACC40Uk_1
);
2393 ACC40Uk_3
= DUAL_REG (ACC40Uk_2
);
2395 /* If the previous use of the registers was a media op,
2396 then their latency will be less than previously recorded.
2397 See Table 13-13 in the LSI. */
2398 ps
= CPU_PROFILE_STATE (cpu
);
2399 if (use_is_media (cpu
, in_FRi
))
2401 busy_adjustment
[0] = 2;
2402 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2405 enforce_full_fr_latency (cpu
, in_FRi
);
2408 if (use_is_media (cpu
, FRi_1
))
2410 busy_adjustment
[1] = 2;
2411 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2414 enforce_full_fr_latency (cpu
, FRi_1
);
2416 if (in_FRj
!= in_FRi
)
2418 if (use_is_media (cpu
, in_FRj
))
2420 busy_adjustment
[2] = 2;
2421 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2424 enforce_full_fr_latency (cpu
, in_FRj
);
2427 if (use_is_media (cpu
, FRj_1
))
2429 busy_adjustment
[3] = 2;
2430 decrease_FR_busy (cpu
, FRj_1
, busy_adjustment
[3]);
2433 enforce_full_fr_latency (cpu
, FRj_1
);
2436 if (out_ACC40Sk
>= 0)
2438 busy_adjustment
[4] = 1;
2439 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
2443 busy_adjustment
[5] = 1;
2444 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
2448 busy_adjustment
[6] = 1;
2449 decrease_ACC_busy (cpu
, ACC40Sk_2
, busy_adjustment
[6]);
2453 busy_adjustment
[7] = 1;
2454 decrease_ACC_busy (cpu
, ACC40Sk_3
, busy_adjustment
[7]);
2457 else if (out_ACC40Uk
>= 0)
2459 busy_adjustment
[4] = 1;
2460 decrease_ACC_busy (cpu
, out_ACC40Uk
, busy_adjustment
[4]);
2464 busy_adjustment
[5] = 1;
2465 decrease_ACC_busy (cpu
, ACC40Uk_1
, busy_adjustment
[5]);
2469 busy_adjustment
[6] = 1;
2470 decrease_ACC_busy (cpu
, ACC40Uk_2
, busy_adjustment
[6]);
2474 busy_adjustment
[7] = 1;
2475 decrease_ACC_busy (cpu
, ACC40Uk_3
, busy_adjustment
[7]);
2479 /* The post processing must wait if there is a dependency on a FR
2480 which is not ready yet. */
2481 ps
->post_wait
= cycles
;
2482 post_wait_for_FR (cpu
, in_FRi
);
2483 post_wait_for_FR (cpu
, FRi_1
);
2484 post_wait_for_FR (cpu
, in_FRj
);
2485 post_wait_for_FR (cpu
, FRj_1
);
2486 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2487 post_wait_for_ACC (cpu
, ACC40Sk_1
);
2488 post_wait_for_ACC (cpu
, ACC40Sk_2
);
2489 post_wait_for_ACC (cpu
, ACC40Sk_3
);
2490 post_wait_for_ACC (cpu
, out_ACC40Uk
);
2491 post_wait_for_ACC (cpu
, ACC40Uk_1
);
2492 post_wait_for_ACC (cpu
, ACC40Uk_2
);
2493 post_wait_for_ACC (cpu
, ACC40Uk_3
);
2495 /* Restore the busy cycles of the registers we used. */
2498 fr
[in_FRi
] += busy_adjustment
[0];
2500 fr
[FRi_1
] += busy_adjustment
[1];
2501 fr
[in_FRj
] += busy_adjustment
[2];
2503 fr
[FRj_1
] += busy_adjustment
[3];
2504 if (out_ACC40Sk
>= 0)
2506 acc
[out_ACC40Sk
] += busy_adjustment
[4];
2508 acc
[ACC40Sk_1
] += busy_adjustment
[5];
2510 acc
[ACC40Sk_2
] += busy_adjustment
[6];
2512 acc
[ACC40Sk_3
] += busy_adjustment
[7];
2514 else if (out_ACC40Uk
>= 0)
2516 acc
[out_ACC40Uk
] += busy_adjustment
[4];
2518 acc
[ACC40Uk_1
] += busy_adjustment
[5];
2520 acc
[ACC40Uk_2
] += busy_adjustment
[6];
2522 acc
[ACC40Uk_3
] += busy_adjustment
[7];
2525 /* The latency of tht output register will be at least the latency of the
2526 other inputs. Once initiated, post-processing will take 1 cycle. */
2527 if (out_ACC40Sk
>= 0)
2529 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2531 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
2533 update_ACC_latency (cpu
, ACC40Sk_2
, ps
->post_wait
+ 1);
2535 update_ACC_latency (cpu
, ACC40Sk_3
, ps
->post_wait
+ 1);
2537 else if (out_ACC40Uk
>= 0)
2539 update_ACC_latency (cpu
, out_ACC40Uk
, ps
->post_wait
+ 1);
2541 update_ACC_latency (cpu
, ACC40Uk_1
, ps
->post_wait
+ 1);
2543 update_ACC_latency (cpu
, ACC40Uk_2
, ps
->post_wait
+ 1);
2545 update_ACC_latency (cpu
, ACC40Uk_3
, ps
->post_wait
+ 1);
2552 frvbf_model_fr500_u_media_quad_complex (SIM_CPU
*cpu
, const IDESC
*idesc
,
2553 int unit_num
, int referenced
,
2554 INT in_FRi
, INT in_FRj
,
2561 FRV_PROFILE_STATE
*ps
;
2562 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2566 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2569 /* The preprocessing can execute right away. */
2570 cycles
= idesc
->timing
->units
[unit_num
].done
;
2572 FRi_1
= DUAL_REG (in_FRi
);
2573 FRj_1
= DUAL_REG (in_FRj
);
2574 ACC40Sk_1
= DUAL_REG (out_ACC40Sk
);
2576 /* If the previous use of the registers was a media op,
2577 then their latency will be less than previously recorded.
2578 See Table 13-13 in the LSI. */
2579 ps
= CPU_PROFILE_STATE (cpu
);
2580 if (use_is_media (cpu
, in_FRi
))
2582 busy_adjustment
[0] = 2;
2583 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2586 enforce_full_fr_latency (cpu
, in_FRi
);
2589 if (use_is_media (cpu
, FRi_1
))
2591 busy_adjustment
[1] = 2;
2592 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2595 enforce_full_fr_latency (cpu
, FRi_1
);
2597 if (in_FRj
!= in_FRi
)
2599 if (use_is_media (cpu
, in_FRj
))
2601 busy_adjustment
[2] = 2;
2602 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[2]);
2605 enforce_full_fr_latency (cpu
, in_FRj
);
2608 if (use_is_media (cpu
, FRj_1
))
2610 busy_adjustment
[3] = 2;
2611 decrease_FR_busy (cpu
, FRj_1
, busy_adjustment
[3]);
2614 enforce_full_fr_latency (cpu
, FRj_1
);
2617 if (out_ACC40Sk
>= 0)
2619 busy_adjustment
[4] = 1;
2620 decrease_ACC_busy (cpu
, out_ACC40Sk
, busy_adjustment
[4]);
2624 busy_adjustment
[5] = 1;
2625 decrease_ACC_busy (cpu
, ACC40Sk_1
, busy_adjustment
[5]);
2629 /* The post processing must wait if there is a dependency on a FR
2630 which is not ready yet. */
2631 ps
->post_wait
= cycles
;
2632 post_wait_for_FR (cpu
, in_FRi
);
2633 post_wait_for_FR (cpu
, FRi_1
);
2634 post_wait_for_FR (cpu
, in_FRj
);
2635 post_wait_for_FR (cpu
, FRj_1
);
2636 post_wait_for_ACC (cpu
, out_ACC40Sk
);
2637 post_wait_for_ACC (cpu
, ACC40Sk_1
);
2639 /* Restore the busy cycles of the registers we used. */
2642 fr
[in_FRi
] += busy_adjustment
[0];
2644 fr
[FRi_1
] += busy_adjustment
[1];
2645 fr
[in_FRj
] += busy_adjustment
[2];
2647 fr
[FRj_1
] += busy_adjustment
[3];
2648 if (out_ACC40Sk
>= 0)
2650 acc
[out_ACC40Sk
] += busy_adjustment
[4];
2652 acc
[ACC40Sk_1
] += busy_adjustment
[5];
2655 /* The latency of tht output register will be at least the latency of the
2656 other inputs. Once initiated, post-processing will take 1 cycle. */
2657 if (out_ACC40Sk
>= 0)
2659 update_ACC_latency (cpu
, out_ACC40Sk
, ps
->post_wait
+ 1);
2661 update_ACC_latency (cpu
, ACC40Sk_1
, ps
->post_wait
+ 1);
2668 frvbf_model_fr500_u_media_dual_expand (SIM_CPU
*cpu
, const IDESC
*idesc
,
2669 int unit_num
, int referenced
,
2675 FRV_PROFILE_STATE
*ps
;
2676 int busy_adjustment
[] = {0, 0, 0};
2679 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2682 /* The preprocessing can execute right away. */
2683 cycles
= idesc
->timing
->units
[unit_num
].done
;
2685 /* If the previous use of the registers was a media op,
2686 then their latency will be less than previously recorded.
2687 See Table 13-13 in the LSI. */
2688 dual_FRk
= DUAL_REG (out_FRk
);
2689 ps
= CPU_PROFILE_STATE (cpu
);
2690 if (use_is_media (cpu
, in_FRi
))
2692 busy_adjustment
[0] = 2;
2693 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2696 enforce_full_fr_latency (cpu
, in_FRi
);
2697 if (out_FRk
!= in_FRi
)
2699 if (use_is_media (cpu
, out_FRk
))
2701 busy_adjustment
[1] = 2;
2702 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[1]);
2705 enforce_full_fr_latency (cpu
, out_FRk
);
2707 if (dual_FRk
>= 0 && dual_FRk
!= in_FRi
)
2709 if (use_is_media (cpu
, dual_FRk
))
2711 busy_adjustment
[2] = 2;
2712 decrease_FR_busy (cpu
, dual_FRk
, busy_adjustment
[2]);
2715 enforce_full_fr_latency (cpu
, dual_FRk
);
2718 /* The post processing must wait if there is a dependency on a FR
2719 which is not ready yet. */
2720 ps
->post_wait
= cycles
;
2721 post_wait_for_FR (cpu
, in_FRi
);
2722 post_wait_for_FR (cpu
, out_FRk
);
2723 post_wait_for_FR (cpu
, dual_FRk
);
2725 /* Restore the busy cycles of the registers we used. */
2727 fr
[in_FRi
] += busy_adjustment
[0];
2728 fr
[out_FRk
] += busy_adjustment
[1];
2730 fr
[dual_FRk
] += busy_adjustment
[2];
2732 /* The latency of the output register will be at least the latency of the
2733 other inputs. Once initiated, post-processing will take 3 cycles. */
2734 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2735 update_FR_ptime (cpu
, out_FRk
, 3);
2737 /* Mark this use of the register as a media op. */
2738 set_use_is_media (cpu
, out_FRk
);
2741 update_FR_latency (cpu
, dual_FRk
, ps
->post_wait
);
2742 update_FR_ptime (cpu
, dual_FRk
, 3);
2744 /* Mark this use of the register as a media op. */
2745 set_use_is_media (cpu
, dual_FRk
);
2752 frvbf_model_fr500_u_media_dual_unpack (SIM_CPU
*cpu
, const IDESC
*idesc
,
2753 int unit_num
, int referenced
,
2762 FRV_PROFILE_STATE
*ps
;
2763 int busy_adjustment
[] = {0, 0, 0, 0, 0, 0};
2766 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2769 /* The preprocessing can execute right away. */
2770 cycles
= idesc
->timing
->units
[unit_num
].done
;
2772 FRi_1
= DUAL_REG (in_FRi
);
2773 FRk_1
= DUAL_REG (out_FRk
);
2774 FRk_2
= DUAL_REG (FRk_1
);
2775 FRk_3
= DUAL_REG (FRk_2
);
2777 /* If the previous use of the registers was a media op,
2778 then their latency will be less than previously recorded.
2779 See Table 13-13 in the LSI. */
2780 ps
= CPU_PROFILE_STATE (cpu
);
2781 if (use_is_media (cpu
, in_FRi
))
2783 busy_adjustment
[0] = 2;
2784 decrease_FR_busy (cpu
, in_FRi
, busy_adjustment
[0]);
2787 enforce_full_fr_latency (cpu
, in_FRi
);
2788 if (FRi_1
>= 0 && use_is_media (cpu
, FRi_1
))
2790 busy_adjustment
[1] = 2;
2791 decrease_FR_busy (cpu
, FRi_1
, busy_adjustment
[1]);
2794 enforce_full_fr_latency (cpu
, FRi_1
);
2795 if (out_FRk
!= in_FRi
)
2797 if (use_is_media (cpu
, out_FRk
))
2799 busy_adjustment
[2] = 2;
2800 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2803 enforce_full_fr_latency (cpu
, out_FRk
);
2804 if (FRk_1
>= 0 && FRk_1
!= in_FRi
)
2806 if (use_is_media (cpu
, FRk_1
))
2808 busy_adjustment
[3] = 2;
2809 decrease_FR_busy (cpu
, FRk_1
, busy_adjustment
[3]);
2812 enforce_full_fr_latency (cpu
, FRk_1
);
2814 if (FRk_2
>= 0 && FRk_2
!= in_FRi
)
2816 if (use_is_media (cpu
, FRk_2
))
2818 busy_adjustment
[4] = 2;
2819 decrease_FR_busy (cpu
, FRk_2
, busy_adjustment
[4]);
2822 enforce_full_fr_latency (cpu
, FRk_2
);
2824 if (FRk_3
>= 0 && FRk_3
!= in_FRi
)
2826 if (use_is_media (cpu
, FRk_3
))
2828 busy_adjustment
[5] = 2;
2829 decrease_FR_busy (cpu
, FRk_3
, busy_adjustment
[5]);
2832 enforce_full_fr_latency (cpu
, FRk_3
);
2836 /* The post processing must wait if there is a dependency on a FR
2837 which is not ready yet. */
2838 ps
->post_wait
= cycles
;
2839 post_wait_for_FR (cpu
, in_FRi
);
2840 post_wait_for_FR (cpu
, FRi_1
);
2841 post_wait_for_FR (cpu
, out_FRk
);
2842 post_wait_for_FR (cpu
, FRk_1
);
2843 post_wait_for_FR (cpu
, FRk_2
);
2844 post_wait_for_FR (cpu
, FRk_3
);
2846 /* Restore the busy cycles of the registers we used. */
2848 fr
[in_FRi
] += busy_adjustment
[0];
2850 fr
[FRi_1
] += busy_adjustment
[1];
2851 fr
[out_FRk
] += busy_adjustment
[2];
2853 fr
[FRk_1
] += busy_adjustment
[3];
2855 fr
[FRk_2
] += busy_adjustment
[4];
2857 fr
[FRk_3
] += busy_adjustment
[5];
2859 /* The latency of tht output register will be at least the latency of the
2860 other inputs. Once initiated, post-processing will take 3 cycles. */
2861 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2862 update_FR_ptime (cpu
, out_FRk
, 3);
2864 /* Mark this use of the register as a media op. */
2865 set_use_is_media (cpu
, out_FRk
);
2868 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
2869 update_FR_ptime (cpu
, FRk_1
, 3);
2871 /* Mark this use of the register as a media op. */
2872 set_use_is_media (cpu
, FRk_1
);
2876 update_FR_latency (cpu
, FRk_2
, ps
->post_wait
);
2877 update_FR_ptime (cpu
, FRk_2
, 3);
2879 /* Mark this use of the register as a media op. */
2880 set_use_is_media (cpu
, FRk_2
);
2884 update_FR_latency (cpu
, FRk_3
, ps
->post_wait
);
2885 update_FR_ptime (cpu
, FRk_3
, 3);
2887 /* Mark this use of the register as a media op. */
2888 set_use_is_media (cpu
, FRk_3
);
2895 frvbf_model_fr500_u_media_dual_btoh (SIM_CPU
*cpu
, const IDESC
*idesc
,
2896 int unit_num
, int referenced
,
2900 return frvbf_model_fr500_u_media_dual_expand (cpu
, idesc
, unit_num
,
2901 referenced
, in_FRj
, out_FRk
);
2905 frvbf_model_fr500_u_media_dual_htob (SIM_CPU
*cpu
, const IDESC
*idesc
,
2906 int unit_num
, int referenced
,
2912 FRV_PROFILE_STATE
*ps
;
2913 int busy_adjustment
[] = {0, 0, 0};
2916 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2919 /* The preprocessing can execute right away. */
2920 cycles
= idesc
->timing
->units
[unit_num
].done
;
2922 /* If the previous use of the registers was a media op,
2923 then their latency will be less than previously recorded.
2924 See Table 13-13 in the LSI. */
2925 dual_FRj
= DUAL_REG (in_FRj
);
2926 ps
= CPU_PROFILE_STATE (cpu
);
2927 if (use_is_media (cpu
, in_FRj
))
2929 busy_adjustment
[0] = 2;
2930 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
2933 enforce_full_fr_latency (cpu
, in_FRj
);
2936 if (use_is_media (cpu
, dual_FRj
))
2938 busy_adjustment
[1] = 2;
2939 decrease_FR_busy (cpu
, dual_FRj
, busy_adjustment
[1]);
2942 enforce_full_fr_latency (cpu
, dual_FRj
);
2944 if (out_FRk
!= in_FRj
)
2946 if (use_is_media (cpu
, out_FRk
))
2948 busy_adjustment
[2] = 2;
2949 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[2]);
2952 enforce_full_fr_latency (cpu
, out_FRk
);
2955 /* The post processing must wait if there is a dependency on a FR
2956 which is not ready yet. */
2957 ps
->post_wait
= cycles
;
2958 post_wait_for_FR (cpu
, in_FRj
);
2959 post_wait_for_FR (cpu
, dual_FRj
);
2960 post_wait_for_FR (cpu
, out_FRk
);
2962 /* Restore the busy cycles of the registers we used. */
2964 fr
[in_FRj
] += busy_adjustment
[0];
2966 fr
[dual_FRj
] += busy_adjustment
[1];
2967 fr
[out_FRk
] += busy_adjustment
[2];
2969 /* The latency of tht output register will be at least the latency of the
2971 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
2973 /* Once initiated, post-processing will take 3 cycles. */
2974 update_FR_ptime (cpu
, out_FRk
, 3);
2976 /* Mark this use of the register as a media op. */
2977 set_use_is_media (cpu
, out_FRk
);
2983 frvbf_model_fr500_u_media_dual_btohe (SIM_CPU
*cpu
, const IDESC
*idesc
,
2984 int unit_num
, int referenced
,
2992 FRV_PROFILE_STATE
*ps
;
2993 int busy_adjustment
[] = {0, 0, 0, 0, 0};
2996 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
2999 /* The preprocessing can execute right away. */
3000 cycles
= idesc
->timing
->units
[unit_num
].done
;
3002 FRk_1
= DUAL_REG (out_FRk
);
3003 FRk_2
= DUAL_REG (FRk_1
);
3004 FRk_3
= DUAL_REG (FRk_2
);
3006 /* If the previous use of the registers was a media op,
3007 then their latency will be less than previously recorded.
3008 See Table 13-13 in the LSI. */
3009 ps
= CPU_PROFILE_STATE (cpu
);
3010 if (use_is_media (cpu
, in_FRj
))
3012 busy_adjustment
[0] = 2;
3013 decrease_FR_busy (cpu
, in_FRj
, busy_adjustment
[0]);
3016 enforce_full_fr_latency (cpu
, in_FRj
);
3017 if (out_FRk
!= in_FRj
)
3019 if (use_is_media (cpu
, out_FRk
))
3021 busy_adjustment
[1] = 2;
3022 decrease_FR_busy (cpu
, out_FRk
, busy_adjustment
[1]);
3025 enforce_full_fr_latency (cpu
, out_FRk
);
3026 if (FRk_1
>= 0 && FRk_1
!= in_FRj
)
3028 if (use_is_media (cpu
, FRk_1
))
3030 busy_adjustment
[2] = 2;
3031 decrease_FR_busy (cpu
, FRk_1
, busy_adjustment
[2]);
3034 enforce_full_fr_latency (cpu
, FRk_1
);
3036 if (FRk_2
>= 0 && FRk_2
!= in_FRj
)
3038 if (use_is_media (cpu
, FRk_2
))
3040 busy_adjustment
[3] = 2;
3041 decrease_FR_busy (cpu
, FRk_2
, busy_adjustment
[3]);
3044 enforce_full_fr_latency (cpu
, FRk_2
);
3046 if (FRk_3
>= 0 && FRk_3
!= in_FRj
)
3048 if (use_is_media (cpu
, FRk_3
))
3050 busy_adjustment
[4] = 2;
3051 decrease_FR_busy (cpu
, FRk_3
, busy_adjustment
[4]);
3054 enforce_full_fr_latency (cpu
, FRk_3
);
3058 /* The post processing must wait if there is a dependency on a FR
3059 which is not ready yet. */
3060 ps
->post_wait
= cycles
;
3061 post_wait_for_FR (cpu
, in_FRj
);
3062 post_wait_for_FR (cpu
, out_FRk
);
3063 post_wait_for_FR (cpu
, FRk_1
);
3064 post_wait_for_FR (cpu
, FRk_2
);
3065 post_wait_for_FR (cpu
, FRk_3
);
3067 /* Restore the busy cycles of the registers we used. */
3069 fr
[in_FRj
] += busy_adjustment
[0];
3070 fr
[out_FRk
] += busy_adjustment
[1];
3072 fr
[FRk_1
] += busy_adjustment
[2];
3074 fr
[FRk_2
] += busy_adjustment
[3];
3076 fr
[FRk_3
] += busy_adjustment
[4];
3078 /* The latency of tht output register will be at least the latency of the
3079 other inputs. Once initiated, post-processing will take 3 cycles. */
3080 update_FR_latency (cpu
, out_FRk
, ps
->post_wait
);
3081 update_FR_ptime (cpu
, out_FRk
, 3);
3083 /* Mark this use of the register as a media op. */
3084 set_use_is_media (cpu
, out_FRk
);
3087 update_FR_latency (cpu
, FRk_1
, ps
->post_wait
);
3088 update_FR_ptime (cpu
, FRk_1
, 3);
3090 /* Mark this use of the register as a media op. */
3091 set_use_is_media (cpu
, FRk_1
);
3095 update_FR_latency (cpu
, FRk_2
, ps
->post_wait
);
3096 update_FR_ptime (cpu
, FRk_2
, 3);
3098 /* Mark this use of the register as a media op. */
3099 set_use_is_media (cpu
, FRk_2
);
3103 update_FR_latency (cpu
, FRk_3
, ps
->post_wait
);
3104 update_FR_ptime (cpu
, FRk_3
, 3);
3106 /* Mark this use of the register as a media op. */
3107 set_use_is_media (cpu
, FRk_3
);
3114 frvbf_model_fr500_u_barrier (SIM_CPU
*cpu
, const IDESC
*idesc
,
3115 int unit_num
, int referenced
)
3118 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
3121 /* Wait for ALL resources. */
3122 for (i
= 0; i
< 64; ++i
)
3124 enforce_full_fr_latency (cpu
, i
);
3125 vliw_wait_for_GR (cpu
, i
);
3126 vliw_wait_for_FR (cpu
, i
);
3127 vliw_wait_for_ACC (cpu
, i
);
3129 for (i
= 0; i
< 8; ++i
)
3130 vliw_wait_for_CCR (cpu
, i
);
3131 for (i
= 0; i
< 2; ++i
)
3133 vliw_wait_for_idiv_resource (cpu
, i
);
3134 vliw_wait_for_fdiv_resource (cpu
, i
);
3135 vliw_wait_for_fsqrt_resource (cpu
, i
);
3137 handle_resource_wait (cpu
);
3138 for (i
= 0; i
< 64; ++i
)
3140 load_wait_for_GR (cpu
, i
);
3141 load_wait_for_FR (cpu
, i
);
3143 trace_vliw_wait_cycles (cpu
);
3147 cycles
= idesc
->timing
->units
[unit_num
].done
;
3152 frvbf_model_fr500_u_membar (SIM_CPU
*cpu
, const IDESC
*idesc
,
3153 int unit_num
, int referenced
)
3156 if (model_insn
== FRV_INSN_MODEL_PASS_1
)
3159 /* Wait for ALL resources, except GR and ICC. */
3160 for (i
= 0; i
< 64; ++i
)
3162 enforce_full_fr_latency (cpu
, i
);
3163 vliw_wait_for_FR (cpu
, i
);
3164 vliw_wait_for_ACC (cpu
, i
);
3166 for (i
= 0; i
< 4; ++i
)
3167 vliw_wait_for_CCR (cpu
, i
);
3168 for (i
= 0; i
< 2; ++i
)
3170 vliw_wait_for_idiv_resource (cpu
, i
);
3171 vliw_wait_for_fdiv_resource (cpu
, i
);
3172 vliw_wait_for_fsqrt_resource (cpu
, i
);
3174 handle_resource_wait (cpu
);
3175 for (i
= 0; i
< 64; ++i
)
3177 load_wait_for_FR (cpu
, i
);
3179 trace_vliw_wait_cycles (cpu
);
3183 cycles
= idesc
->timing
->units
[unit_num
].done
;
3187 /* The frv machine is a fictional implementation of the fr500 which implements
3188 all frv architectural features. */
3190 frvbf_model_frv_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3191 int unit_num
, int referenced
)
3193 return idesc
->timing
->units
[unit_num
].done
;
3196 /* The simple machine is a fictional implementation of the fr500 which
3197 implements limited frv architectural features. */
3199 frvbf_model_simple_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3200 int unit_num
, int referenced
)
3202 return idesc
->timing
->units
[unit_num
].done
;
3205 /* The tomcat machine is models a prototype fr500 machine which had a few
3206 bugs and restrictions to work around. */
3208 frvbf_model_tomcat_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
3209 int unit_num
, int referenced
)
3211 return idesc
->timing
->units
[unit_num
].done
;
3214 #endif /* WITH_PROFILE_MODEL_P */