sim/frv/profile.h

   1 /* Profiling definitions for the FRV simulator
   2    Copyright (C) 1998, 1999, 2000, 2001, 2003 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef PROFILE_H
  22 #define PROFILE_H
  23
  24 #include "frv-desc.h"
  25
  26 /* This struct defines the state of profiling.  All fields are of general
  27    use to all machines.  */
  28 typedef struct
  29 {
  30   long vliw_insns; /* total number of VLIW insns.  */
  31   long vliw_wait;  /* number of cycles that the current VLIW insn must wait.  */
  32   long post_wait;  /* number of cycles that post processing in the current
  33                       VLIW insn must wait.  */
  34   long vliw_cycles;/* number of cycles used by current VLIW insn.  */
  35
  36   int  past_first_p; /* Not the first insns in the VLIW */
  37
  38   /* Register latencies.  Must be signed since they can be temporarily
  39      negative.  */
  40   int gr_busy[64];       /* Cycles until GR is available.  */
  41   int fr_busy[64];       /* Cycles until FR is available.  */
  42   int acc_busy[64];      /* Cycles until FR is available.  */
  43   int ccr_busy[8];       /* Cycles until ICC/FCC is available.  */
  44   int spr_busy[4096];    /* Cycles until spr is available.  */
  45   int idiv_busy[2];      /* Cycles until integer division unit is available.  */
  46   int fdiv_busy[2];      /* Cycles until float division unit is available.  */
  47   int fsqrt_busy[2];     /* Cycles until square root unit is available.  */
  48   int branch_penalty;    /* Cycles until branch is complete.  */
  49
  50   int gr_latency[64];    /* Cycles until target GR is available.  */
  51   int fr_latency[64];    /* Cycles until target FR is available.  */
  52   int acc_latency[64];   /* Cycles until target FR is available.  */
  53   int ccr_latency[8];    /* Cycles until target ICC/FCC is available.  */
  54   int spr_latency[4096]; /* Cycles until target spr is available.  */
  55
  56   /* Some registers are busy for a shorter number of cycles than normal
  57      depending on how they are used next. the xxx_busy_adjust arrays keep track
  58      of how many cycles to adjust down.
  59   */
  60   int fr_busy_adjust[64];
  61   int acc_busy_adjust[64];
  62
  63   /* Register flags.  Each bit represents one register.  */
  64   DI cur_gr_complex;
  65   DI prev_gr_complex;
  66
  67   /* Keep track of the total queued post-processing time required before a
  68      resource is available.  This is applied to the resource's latency once all
  69      pending loads for the resource are completed.  */
  70   int fr_ptime[64];
  71
  72   int branch_hint;       /* hint field from branch insn.  */
  73   USI branch_address;    /* Address of predicted branch.  */
  74   USI insn_fetch_address;/* Address of sequential insns fetched.  */
  75
  76   /* We need to know when the first branch of a vliw insn is taken, so that
  77      we don't consider the remaining branches in the vliw insn.  */
  78   int vliw_branch_taken;
  79
  80   /* Keep track of the maximum load stall for each VLIW insn.  */
  81   int vliw_load_stall;
  82
  83   /* Need to know if all cache entries are affected by various cache
  84      operations.  */
  85   int all_cache_entries;
  86 } FRV_PROFILE_STATE;
  87
  88 #define DUAL_REG(reg) ((reg) >= 0 && (reg) < 63 ? (reg) + 1 : -1)
  89 #define DUAL_DOUBLE(reg) ((reg) >= 0 && (reg) < 61 ? (reg) + 2 : -1)
  90
  91 /* Return the GNER register associated with the given GR register.
  92    There is no GNER associated with gr0.  */
  93 #define GNER_FOR_GR(gr) ((gr) > 63 ? -1 : \
  94                          (gr) > 31 ? H_SPR_GNER0 : \
  95                          (gr) >  0 ? H_SPR_GNER1 : \
  96                          -1)
  97 /* Return the GNER register associated with the given GR register.
  98    There is no GNER associated with gr0.  */
  99 #define FNER_FOR_FR(fr) ((fr) > 63 ? -1 : \
 100                          (fr) > 31 ? H_SPR_FNER0 : \
 101                          (fr) >  0 ? H_SPR_FNER1 : \
 102                          -1)
 103
 104 /* Top up the latency of the given GR by the given number of cycles.  */
 105 void update_GR_latency (SIM_CPU *, INT, int);
 106 void update_GRdouble_latency (SIM_CPU *, INT, int);
 107 void update_GR_latency_for_load (SIM_CPU *, INT, int);
 108 void update_GRdouble_latency_for_load (SIM_CPU *, INT, int);
 109 void update_GR_latency_for_swap (SIM_CPU *, INT, int);
 110 void update_FR_latency (SIM_CPU *, INT, int);
 111 void update_FRdouble_latency (SIM_CPU *, INT, int);
 112 void update_FR_latency_for_load (SIM_CPU *, INT, int);
 113 void update_FRdouble_latency_for_load (SIM_CPU *, INT, int);
 114 void update_FR_ptime (SIM_CPU *, INT, int);
 115 void update_FRdouble_ptime (SIM_CPU *, INT, int);
 116 void decrease_ACC_busy (SIM_CPU *, INT, int);
 117 void decrease_FR_busy (SIM_CPU *, INT, int);
 118 void decrease_GR_busy (SIM_CPU *, INT, int);
 119 void increase_FR_busy (SIM_CPU *, INT, int);
 120 void update_ACC_latency (SIM_CPU *, INT, int);
 121 void update_CCR_latency (SIM_CPU *, INT, int);
 122 void update_SPR_latency (SIM_CPU *, INT, int);
 123 void update_idiv_resource_latency (SIM_CPU *, INT, int);
 124 void update_fdiv_resource_latency (SIM_CPU *, INT, int);
 125 void update_fsqrt_resource_latency (SIM_CPU *, INT, int);
 126 void update_branch_penalty (SIM_CPU *, int);
 127 void update_ACC_ptime (SIM_CPU *, INT, int);
 128 void update_SPR_ptime (SIM_CPU *, INT, int);
 129 void vliw_wait_for_GR (SIM_CPU *, INT);
 130 void vliw_wait_for_GRdouble (SIM_CPU *, INT);
 131 void vliw_wait_for_FR (SIM_CPU *, INT);
 132 void vliw_wait_for_FRdouble (SIM_CPU *, INT);
 133 void vliw_wait_for_CCR (SIM_CPU *, INT);
 134 void vliw_wait_for_ACC (SIM_CPU *, INT);
 135 void vliw_wait_for_SPR (SIM_CPU *, INT);
 136 void vliw_wait_for_idiv_resource (SIM_CPU *, INT);
 137 void vliw_wait_for_fdiv_resource (SIM_CPU *, INT);
 138 void vliw_wait_for_fsqrt_resource (SIM_CPU *, INT);
 139 void load_wait_for_GR (SIM_CPU *, INT);
 140 void load_wait_for_FR (SIM_CPU *, INT);
 141 void load_wait_for_GRdouble (SIM_CPU *, INT);
 142 void load_wait_for_FRdouble (SIM_CPU *, INT);
 143 void enforce_full_fr_latency (SIM_CPU *, INT);
 144 int post_wait_for_FR (SIM_CPU *, INT);
 145 int post_wait_for_FRdouble (SIM_CPU *, INT);
 146 int post_wait_for_ACC (SIM_CPU *, INT);
 147 int post_wait_for_CCR (SIM_CPU *, INT);
 148 int post_wait_for_SPR (SIM_CPU *, INT);
 149 int post_wait_for_fdiv (SIM_CPU *, INT);
 150 int post_wait_for_fsqrt (SIM_CPU *, INT);
 151
 152 void trace_vliw_wait_cycles (SIM_CPU *);
 153 void handle_resource_wait (SIM_CPU *);
 154
 155 void request_cache_load (SIM_CPU *, INT, int, int);
 156 void request_cache_flush (SIM_CPU *, FRV_CACHE *, int);
 157 void request_cache_invalidate (SIM_CPU *, FRV_CACHE *, int);
 158 void request_cache_preload (SIM_CPU *, FRV_CACHE *, int);
 159 void request_cache_unlock (SIM_CPU *, FRV_CACHE *, int);
 160 int  load_pending_for_register (SIM_CPU *, int, int, int);
 161
 162 void set_use_is_gr_complex (SIM_CPU *, INT);
 163 void set_use_not_gr_complex (SIM_CPU *, INT);
 164 int  use_is_gr_complex (SIM_CPU *, INT);
 165
 166 typedef struct
 167 {
 168   SI address;
 169   unsigned reqno;
 170 } FRV_INSN_FETCH_BUFFER;
 171
 172 extern FRV_INSN_FETCH_BUFFER frv_insn_fetch_buffer[];
 173
 174 PROFILE_INFO_CPU_CALLBACK_FN frv_profile_info;
 175
 176 enum {
 177   /* Simulator specific profile bits begin here.  */
 178   /* Profile caches.  */
 179   PROFILE_CACHE_IDX = PROFILE_NEXT_IDX,
 180   /* Profile parallelization.  */
 181   PROFILE_PARALLEL_IDX
 182 };
 183
 184 /* Masks so WITH_PROFILE can have symbolic values.
 185    The case choice here is on purpose.  The lowercase parts are args to
 186    --with-profile.  */
 187 #define PROFILE_cache    (1 << PROFILE_INSN_IDX)
 188 #define PROFILE_parallel (1 << PROFILE_INSN_IDX)
 189
 190 /* Preprocessor macros to simplify tests of WITH_PROFILE.  */
 191 #define WITH_PROFILE_CACHE_P    (WITH_PROFILE & PROFILE_insn)
 192 #define WITH_PROFILE_PARALLEL_P (WITH_PROFILE & PROFILE_insn)
 193
 194 #define FRV_COUNT_CYCLES(cpu, condition) \
 195   ((PROFILE_MODEL_P (cpu) && (condition)) || frv_interrupt_state.timer.enabled)
 196
 197 /* Modelling support.  */
 198 extern int frv_save_profile_model_p;
 199
 200 extern enum FRV_INSN_MODELING {
 201   FRV_INSN_NO_MODELING = 0,
 202   FRV_INSN_MODEL_PASS_1,
 203   FRV_INSN_MODEL_PASS_2,
 204   FRV_INSN_MODEL_WRITEBACK
 205 } model_insn;
 206
 207 void
 208 frv_model_advance_cycles (SIM_CPU *, int);
 209 void
 210 frv_model_trace_wait_cycles (SIM_CPU *, int, const char *);
 211
 212 /* Register types for queued load requests.  */
 213 #define REGTYPE_NONE 0
 214 #define REGTYPE_FR   1
 215 #define REGTYPE_ACC  2
 216
 217 #endif /* PROFILE_H */