sim/frv/sim-main.h

   1 /* frv simulator support code
   2    Copyright (C) 1998-2015 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5 This file is part of the GNU simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3 of the License, or
  10 (at your option) any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* Main header for the frv.  */
  21
  22 #define USING_SIM_BASE_H /* FIXME: quick hack */
  23
  24 struct _sim_cpu; /* FIXME: should be in sim-basics.h */
  25 typedef struct _sim_cpu SIM_CPU;
  26
  27 /* Set the mask of unsupported traces.  */
  28 #define WITH_TRACE \
  29   (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
  30      | TRACE_branch | TRACE_debug))
  31
  32 /* sim-basics.h includes config.h but cgen-types.h must be included before
  33    sim-basics.h and cgen-types.h needs config.h.  */
  34 #include "config.h"
  35
  36 #include "symcat.h"
  37 #include "sim-basics.h"
  38 #include "cgen-types.h"
  39 #include "frv-desc.h"
  40 #include "frv-opc.h"
  41 #include "arch.h"
  42
  43 /* These must be defined before sim-base.h.  */
  44 typedef USI sim_cia;
  45
  46 void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
  47 #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
  48   frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
  49
  50 #define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
  51
  52 #include "sim-base.h"
  53 #include "cgen-sim.h"
  54 #include "frv-sim.h"
  55 #include "cache.h"
  56 #include "registers.h"
  57 #include "profile.h"
  58 \f
  59 /* The _sim_cpu struct.  */
  60
  61 struct _sim_cpu {
  62   /* sim/common cpu base.  */
  63   sim_cpu_base base;
  64
  65   /* Static parts of cgen.  */
  66   CGEN_CPU cgen_cpu;
  67
  68   /* CPU specific parts go here.
  69      Note that in files that don't need to access these pieces WANT_CPU_FOO
  70      won't be defined and thus these parts won't appear.  This is ok in the
  71      sense that things work.  It is a source of bugs though.
  72      One has to of course be careful to not take the size of this
  73      struct and no structure members accessed in non-cpu specific files can
  74      go after here.  Oh for a better language.  */
  75 #if defined (WANT_CPU_FRVBF)
  76   FRVBF_CPU_DATA cpu_data;
  77
  78   /* Control information for registers */
  79   FRV_REGISTER_CONTROL register_control;
  80 #define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
  81
  82   FRV_VLIW vliw;
  83 #define CPU_VLIW(cpu) (& (cpu)->vliw)
  84
  85   FRV_CACHE insn_cache;
  86 #define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
  87
  88   FRV_CACHE data_cache;
  89 #define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
  90
  91   FRV_PROFILE_STATE profile_state;
  92 #define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
  93
  94   int debug_state;
  95 #define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
  96
  97   SI load_address;
  98 #define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
  99
 100   SI load_length;
 101 #define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
 102
 103   SI load_flag;
 104 #define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
 105 #define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
 106
 107   SI store_flag;
 108 #define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
 109
 110   unsigned long elf_flags;
 111 #define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
 112 #endif /* defined (WANT_CPU_FRVBF) */
 113 };
 114 \f
 115 /* The sim_state struct.  */
 116
 117 struct sim_state {
 118   sim_cpu *cpu[MAX_NR_PROCESSORS];
 119
 120   CGEN_STATE cgen_state;
 121
 122   sim_state_base base;
 123 };
 124 \f
 125 /* Misc.  */
 126
 127 /* Catch address exceptions.  */
 128 extern SIM_CORE_SIGNAL_FN frv_core_signal;
 129 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
 130 frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
 131                   (TRANSFER), (ERROR))
 132
 133 /* Default memory size.  */
 134 #define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */