2 Copyright (C) 1999-2021 Free Software Foundation, Inc.
3 Contributed by Red Hat.
5 This file is part of the GNU simulators.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #define WANT_CPU frvbf
21 #define WANT_CPU_FRVBF
24 #include "targ-vals.h"
25 #include "cgen-engine.h"
30 #include "libiberty.h"
34 CGEN_ATTR_VALUE_ENUM_TYPE frv_current_fm_slot
;
36 /* The semantic code invokes this for invalid (unrecognized) instructions. */
39 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
41 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
45 /* Process an address exception. */
48 frv_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
49 unsigned int map
, int nr_bytes
, address_word addr
,
50 transfer_type transfer
, sim_core_signals sig
)
52 if (sig
== sim_core_unaligned_signal
)
54 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr400
55 || STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_fr450
)
56 frv_queue_data_access_error_interrupt (current_cpu
, addr
);
58 frv_queue_mem_address_not_aligned_interrupt (current_cpu
, addr
);
62 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
, transfer
, sig
);
66 frv_sim_engine_halt_hook (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
)
69 if (current_cpu
!= NULL
)
70 CPU_PC_SET (current_cpu
, cia
);
72 /* Invalidate the insn and data caches of all cpus. */
73 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
75 current_cpu
= STATE_CPU (sd
, i
);
76 frv_cache_invalidate_all (CPU_INSN_CACHE (current_cpu
), 0);
77 frv_cache_invalidate_all (CPU_DATA_CACHE (current_cpu
), 1);
82 /* Read/write functions for system call interface. */
85 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
86 unsigned long taddr
, char *buf
, int bytes
)
88 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
89 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
91 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
92 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
96 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
97 unsigned long taddr
, const char *buf
, int bytes
)
99 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
100 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
102 frv_cache_invalidate_all (CPU_INSN_CACHE (cpu
), 0);
103 frv_cache_invalidate_all (CPU_DATA_CACHE (cpu
), 1);
104 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
107 /* Handle TRA and TIRA insns. */
109 frv_itrap (SIM_CPU
*current_cpu
, PCADDR pc
, USI base
, SI offset
)
111 SIM_DESC sd
= CPU_STATE (current_cpu
);
112 host_callback
*cb
= STATE_CALLBACK (sd
);
113 USI num
= ((base
+ offset
) & 0x7f) + 0x80;
115 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
117 frv_queue_software_interrupt (current_cpu
, num
);
126 CB_SYSCALL_INIT (&s
);
127 s
.func
= GET_H_GR (7);
128 s
.arg1
= GET_H_GR (8);
129 s
.arg2
= GET_H_GR (9);
130 s
.arg3
= GET_H_GR (10);
132 if (s
.func
== TARGET_SYS_exit
)
134 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
138 s
.p2
= (PTR
) current_cpu
;
139 s
.read_mem
= syscall_read_mem
;
140 s
.write_mem
= syscall_write_mem
;
142 SET_H_GR (8, s
.result
);
143 SET_H_GR (9, s
.result2
);
144 SET_H_GR (10, s
.errcode
);
148 case TRAP_BREAKPOINT
:
149 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
152 /* Add support for dumping registers, either at fixed traps, or all
153 unknown traps if configured with --enable-sim-trapdump. */
156 frv_queue_software_interrupt (current_cpu
, num
);
168 #if TRAPDUMP || (defined (TRAP_REGDUMP1)) || (defined (TRAP_REGDUMP2))
174 if (STATE_TEXT_SECTION (sd
)
175 && pc
>= STATE_TEXT_START (sd
)
176 && pc
< STATE_TEXT_END (sd
))
178 const char *pc_filename
= (const char *)0;
179 const char *pc_function
= (const char *)0;
180 unsigned int pc_linenum
= 0;
182 if (bfd_find_nearest_line (STATE_PROG_BFD (sd
),
183 STATE_TEXT_SECTION (sd
),
184 (struct bfd_symbol
**) 0,
185 pc
- STATE_TEXT_START (sd
),
186 &pc_filename
, &pc_function
, &pc_linenum
)
187 && (pc_function
|| pc_filename
))
194 strcpy (p
, pc_function
);
199 char *q
= (char *) strrchr (pc_filename
, '/');
200 strcpy (p
, (q
) ? q
+1 : pc_filename
);
206 sprintf (p
, " line %d", pc_linenum
);
212 if ((p
+1) - buf
> sizeof (buf
))
218 "\nRegister dump, pc = 0x%.8x%s, base = %u, offset = %d\n",
219 (unsigned)pc
, buf
, (unsigned)base
, (int)offset
);
221 for (i
= 0; i
< 64; i
+= 8)
223 long g0
= (long)GET_H_GR (i
);
224 long g1
= (long)GET_H_GR (i
+1);
225 long g2
= (long)GET_H_GR (i
+2);
226 long g3
= (long)GET_H_GR (i
+3);
227 long g4
= (long)GET_H_GR (i
+4);
228 long g5
= (long)GET_H_GR (i
+5);
229 long g6
= (long)GET_H_GR (i
+6);
230 long g7
= (long)GET_H_GR (i
+7);
232 if ((g0
| g1
| g2
| g3
| g4
| g5
| g6
| g7
) != 0)
234 "\tgr%02d - gr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
235 i
, i
+7, g0
, g1
, g2
, g3
, g4
, g5
, g6
, g7
);
238 for (i
= 0; i
< 64; i
+= 8)
240 long f0
= (long)GET_H_FR (i
);
241 long f1
= (long)GET_H_FR (i
+1);
242 long f2
= (long)GET_H_FR (i
+2);
243 long f3
= (long)GET_H_FR (i
+3);
244 long f4
= (long)GET_H_FR (i
+4);
245 long f5
= (long)GET_H_FR (i
+5);
246 long f6
= (long)GET_H_FR (i
+6);
247 long f7
= (long)GET_H_FR (i
+7);
249 if ((f0
| f1
| f2
| f3
| f4
| f5
| f6
| f7
) != 0)
251 "\tfr%02d - fr%02d: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
252 i
, i
+7, f0
, f1
, f2
, f3
, f4
, f5
, f6
, f7
);
256 "\tlr/lcr/cc/ccc: 0x%.8lx 0x%.8lx 0x%.8lx 0x%.8lx\n",
257 (long)GET_H_SPR (272),
258 (long)GET_H_SPR (273),
259 (long)GET_H_SPR (256),
260 (long)GET_H_SPR (263));
267 /* Handle the MTRAP insn. */
269 frv_mtrap (SIM_CPU
*current_cpu
)
271 SIM_DESC sd
= CPU_STATE (current_cpu
);
273 /* Check the status of media exceptions in MSR0. */
274 SI msr
= GET_MSR (0);
275 if (GET_MSR_AOVF (msr
) || GET_MSR_MTT (msr
) && STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
276 frv_queue_program_interrupt (current_cpu
, FRV_MP_EXCEPTION
);
279 /* Handle the BREAK insn. */
281 frv_break (SIM_CPU
*current_cpu
)
284 SIM_DESC sd
= CPU_STATE (current_cpu
);
286 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
288 /* Invalidate the insn cache because the debugger will presumably
289 replace the breakpoint insn with the real one. */
290 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
293 frv_queue_break_interrupt (current_cpu
);
296 /* Return from trap. */
298 frv_rett (SIM_CPU
*current_cpu
, PCADDR pc
, BI debug_field
)
301 /* if (normal running mode and debug_field==0
305 else if (debug running mode and debug_field==1)
309 change to normal running mode
311 int psr_s
= GET_H_PSR_S ();
312 int psr_et
= GET_H_PSR_ET ();
314 /* Check for exceptions in the priority order listed in the FRV Architecture
318 /* Halt if PSR.ET is not set. See chapter 6 of the LSI. */
321 SIM_DESC sd
= CPU_STATE (current_cpu
);
322 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
325 /* privileged_instruction interrupt will have already been queued by
326 frv_detect_insn_access_interrupts. */
331 /* Halt if PSR.S is set. See chapter 6 of the LSI. */
334 SIM_DESC sd
= CPU_STATE (current_cpu
);
335 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
338 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
341 else if (! CPU_DEBUG_STATE (current_cpu
) && debug_field
== 0)
343 USI psr
= GET_PSR ();
344 /* Return from normal running state. */
345 new_pc
= GET_H_SPR (H_SPR_PCSR
);
347 SET_PSR_S (psr
, GET_PSR_PS (psr
));
348 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
350 else if (CPU_DEBUG_STATE (current_cpu
) && debug_field
== 1)
352 USI psr
= GET_PSR ();
353 /* Return from debug state. */
354 new_pc
= GET_H_SPR (H_SPR_BPCSR
);
355 SET_PSR_ET (psr
, GET_H_BPSR_BET ());
356 SET_PSR_S (psr
, GET_H_BPSR_BS ());
357 sim_queue_fn_si_write (current_cpu
, frvbf_h_spr_set
, H_SPR_PSR
, psr
);
358 CPU_DEBUG_STATE (current_cpu
) = 0;
366 /* Functions for handling non-excepting instruction side effects. */
367 static SI
next_available_nesr (SIM_CPU
*current_cpu
, SI current_index
)
369 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
370 if (control
->spr
[H_SPR_NECR
].implemented
)
373 USI necr
= GET_NECR ();
375 /* See if any NESRs are implemented. First need to check the validity of
377 if (! GET_NECR_VALID (necr
))
380 limit
= GET_NECR_NEN (necr
);
381 for (++current_index
; current_index
< limit
; ++current_index
)
383 SI nesr
= GET_NESR (current_index
);
384 if (! GET_NESR_VALID (nesr
))
385 return current_index
;
391 static SI
next_valid_nesr (SIM_CPU
*current_cpu
, SI current_index
)
393 FRV_REGISTER_CONTROL
*control
= CPU_REGISTER_CONTROL (current_cpu
);
394 if (control
->spr
[H_SPR_NECR
].implemented
)
397 USI necr
= GET_NECR ();
399 /* See if any NESRs are implemented. First need to check the validity of
401 if (! GET_NECR_VALID (necr
))
404 limit
= GET_NECR_NEN (necr
);
405 for (++current_index
; current_index
< limit
; ++current_index
)
407 SI nesr
= GET_NESR (current_index
);
408 if (GET_NESR_VALID (nesr
))
409 return current_index
;
416 frvbf_check_non_excepting_load (
417 SIM_CPU
*current_cpu
, SI base_index
, SI disp_index
, SI target_index
,
418 SI immediate_disp
, QI data_size
, BI is_float
421 BI rc
= 1; /* perform the load. */
422 SIM_DESC sd
= CPU_STATE (current_cpu
);
432 FRV_REGISTER_CONTROL
*control
;
434 SI address
= GET_H_GR (base_index
);
436 address
+= GET_H_GR (disp_index
);
438 address
+= immediate_disp
;
440 /* Check for interrupt factors. */
458 if (target_index
& 1)
464 if (target_index
& 3)
469 IADDR pc
= GET_H_PC ();
470 sim_engine_abort (sd
, current_cpu
, pc
,
471 "check_non_excepting_load: Incorrect data_size\n");
476 control
= CPU_REGISTER_CONTROL (current_cpu
);
477 if (control
->spr
[H_SPR_NECR
].implemented
)
480 do_elos
= GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
);
485 /* NECR, NESR, NEEAR are only implemented for the full frv machine. */
488 ne_index
= next_available_nesr (current_cpu
, NO_NESR
);
489 if (ne_index
== NO_NESR
)
491 IADDR pc
= GET_H_PC ();
492 sim_engine_abort (sd
, current_cpu
, pc
,
493 "No available NESR register\n");
496 /* Fill in the basic fields of the NESR. */
497 nesr
= GET_NESR (ne_index
);
498 SET_NESR_VALID (nesr
);
500 SET_NESR_DRN (nesr
, target_index
);
501 SET_NESR_SIZE (nesr
, data_size
);
502 SET_NESR_NEAN (nesr
, ne_index
);
506 CLEAR_NESR_FR (nesr
);
508 /* Set the corresponding NEEAR. */
509 SET_NEEAR (ne_index
, address
);
511 SET_NESR_DAEC (nesr
, 0);
512 SET_NESR_REC (nesr
, 0);
513 SET_NESR_EC (nesr
, 0);
516 /* Set the NE flag corresponding to the target register if an interrupt
518 daec is not checked here yet, but is declared for future reference. */
520 NE_base
= H_SPR_FNER0
;
522 NE_base
= H_SPR_GNER0
;
524 GET_NE_FLAGS (NE_flags
, NE_base
);
527 SET_NE_FLAG (NE_flags
, target_index
);
529 SET_NESR_REC (nesr
, NESR_REGISTER_NOT_ALIGNED
);
534 SET_NE_FLAG (NE_flags
, target_index
);
536 SET_NESR_EC (nesr
, NESR_MEM_ADDRESS_NOT_ALIGNED
);
540 SET_NESR (ne_index
, nesr
);
542 /* If no interrupt factor was detected then set the NE flag on the
543 target register if the NE flag on one of the input registers
545 if (! rec
&& ! ec
&& ! daec
)
547 BI ne_flag
= GET_NE_FLAG (NE_flags
, base_index
);
549 ne_flag
|= GET_NE_FLAG (NE_flags
, disp_index
);
552 SET_NE_FLAG (NE_flags
, target_index
);
553 rc
= 0; /* Do not perform the load. */
556 CLEAR_NE_FLAG (NE_flags
, target_index
);
559 SET_NE_FLAGS (NE_base
, NE_flags
);
561 return rc
; /* perform the load? */
564 /* Record state for media exception: media_cr_not_aligned. */
566 frvbf_media_cr_not_aligned (SIM_CPU
*current_cpu
)
568 SIM_DESC sd
= CPU_STATE (current_cpu
);
570 /* On some machines this generates an illegal_instruction interrupt. */
571 switch (STATE_ARCHITECTURE (sd
)->mach
)
573 /* Note: there is a discrepancy between V2.2 of the FR400
574 instruction manual and the various FR4xx LSI specs. The former
575 claims that unaligned registers cause an mp_exception while the
576 latter say it's an illegal_instruction. The LSI specs appear
577 to be correct since MTT is fixed at 1. */
581 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
584 frv_set_mp_exception_registers (current_cpu
, MTT_CR_NOT_ALIGNED
, 0);
589 /* Record state for media exception: media_acc_not_aligned. */
591 frvbf_media_acc_not_aligned (SIM_CPU
*current_cpu
)
593 SIM_DESC sd
= CPU_STATE (current_cpu
);
595 /* On some machines this generates an illegal_instruction interrupt. */
596 switch (STATE_ARCHITECTURE (sd
)->mach
)
598 /* See comment in frvbf_cr_not_aligned(). */
602 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
605 frv_set_mp_exception_registers (current_cpu
, MTT_ACC_NOT_ALIGNED
, 0);
610 /* Record state for media exception: media_register_not_aligned. */
612 frvbf_media_register_not_aligned (SIM_CPU
*current_cpu
)
614 SIM_DESC sd
= CPU_STATE (current_cpu
);
616 /* On some machines this generates an illegal_instruction interrupt. */
617 switch (STATE_ARCHITECTURE (sd
)->mach
)
619 /* See comment in frvbf_cr_not_aligned(). */
623 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
626 frv_set_mp_exception_registers (current_cpu
, MTT_INVALID_FR
, 0);
631 /* Record state for media exception: media_overflow. */
633 frvbf_media_overflow (SIM_CPU
*current_cpu
, int sie
)
635 frv_set_mp_exception_registers (current_cpu
, MTT_OVERFLOW
, sie
);
638 /* Queue a division exception. */
640 frvbf_division_exception (SIM_CPU
*current_cpu
, enum frv_dtt dtt
,
641 int target_index
, int non_excepting
)
643 /* If there was an overflow and it is masked, then record it in
645 USI isr
= GET_ISR ();
646 if ((dtt
& FRV_DTT_OVERFLOW
) && GET_ISR_EDE (isr
))
648 dtt
&= ~FRV_DTT_OVERFLOW
;
652 if (dtt
!= FRV_DTT_NO_EXCEPTION
)
656 /* Non excepting instruction, simply set the NE flag for the target
659 GET_NE_FLAGS (NE_flags
, H_SPR_GNER0
);
660 SET_NE_FLAG (NE_flags
, target_index
);
661 SET_NE_FLAGS (H_SPR_GNER0
, NE_flags
);
664 frv_queue_division_exception_interrupt (current_cpu
, dtt
);
670 frvbf_check_recovering_store (
671 SIM_CPU
*current_cpu
, PCADDR address
, SI regno
, int size
, int is_float
674 FRV_CACHE
*cache
= CPU_DATA_CACHE (current_cpu
);
677 CPU_RSTR_INVALIDATE(current_cpu
) = 0;
679 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
681 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
683 if (address
== GET_H_SPR (H_SPR_NEEAR0
+ reg_ix
))
685 SI nesr
= GET_NESR (reg_ix
);
686 int nesr_drn
= GET_NESR_DRN (nesr
);
687 BI nesr_fr
= GET_NESR_FR (nesr
);
690 /* Invalidate cache block containing this address.
691 If we need to count cycles, then the cache operation will be
692 initiated from the model profiling functions.
693 See frvbf_model_.... */
696 CPU_RSTR_INVALIDATE(current_cpu
) = 1;
697 CPU_LOAD_ADDRESS (current_cpu
) = address
;
700 frv_cache_invalidate (cache
, address
, 1/* flush */);
702 /* Copy the stored value to the register indicated by NESR.DRN. */
703 for (remain
= size
; remain
> 0; remain
-= 4)
708 value
= GET_H_FR (regno
);
710 value
= GET_H_GR (regno
);
725 sim_queue_fn_sf_write (current_cpu
, frvbf_h_fr_set
, nesr_drn
,
728 sim_queue_fn_si_write (current_cpu
, frvbf_h_gr_set
, nesr_drn
,
734 break; /* Only consider the first matching register. */
736 } /* loop over active neear registers. */
740 frvbf_check_acc_range (SIM_CPU
*current_cpu
, SI regno
)
742 /* Only applicable to fr550 */
743 SIM_DESC sd
= CPU_STATE (current_cpu
);
744 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
747 /* On the fr550, media insns in slots 0 and 2 can only access
748 accumulators acc0-acc3. Insns in slots 1 and 3 can only access
749 accumulators acc4-acc7 */
750 switch (frv_current_fm_slot
)
755 return 1; /* all is ok */
760 return 1; /* all is ok */
764 /* The specified accumulator is out of range. Queue an illegal_instruction
766 frv_queue_program_interrupt (current_cpu
, FRV_ILLEGAL_INSTRUCTION
);
771 frvbf_check_swap_address (SIM_CPU
*current_cpu
, SI address
)
773 /* Only applicable to fr550 */
774 SIM_DESC sd
= CPU_STATE (current_cpu
);
775 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_fr550
)
778 /* Adress must be aligned on a word boundary. */
780 frv_queue_data_access_exception_interrupt (current_cpu
);
784 clear_nesr_neear (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
788 /* Only implemented for full frv. */
789 SIM_DESC sd
= CPU_STATE (current_cpu
);
790 if (STATE_ARCHITECTURE (sd
)->mach
!= bfd_mach_frv
)
793 /* Clear the appropriate NESR and NEEAR registers. */
794 for (reg_ix
= next_valid_nesr (current_cpu
, NO_NESR
);
796 reg_ix
= next_valid_nesr (current_cpu
, reg_ix
))
799 /* The register is available, now check if it is active. */
800 nesr
= GET_NESR (reg_ix
);
801 if (GET_NESR_FR (nesr
) == is_float
)
803 if (target_index
< 0 || GET_NESR_DRN (nesr
) == target_index
)
805 SET_NESR (reg_ix
, 0);
806 SET_NEEAR (reg_ix
, 0);
814 SIM_CPU
*current_cpu
,
824 GET_NE_FLAGS (NE_flags
, NE_base
);
825 if (target_index
>= 0)
826 CLEAR_NE_FLAG (NE_flags
, target_index
);
834 SET_NE_FLAGS (NE_base
, NE_flags
);
837 /* Return 1 if the given register is available, 0 otherwise. TARGET_INDEX==-1
838 means to check for any register available. */
840 which_registers_available (
841 SIM_CPU
*current_cpu
, int *hi_available
, int *lo_available
, int is_float
845 frv_fr_registers_available (current_cpu
, hi_available
, lo_available
);
847 frv_gr_registers_available (current_cpu
, hi_available
, lo_available
);
851 frvbf_clear_ne_flags (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
858 FRV_REGISTER_CONTROL
*control
;
860 /* Check for availability of the target register(s). */
861 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
864 /* Check to make sure that the target register is available. */
865 if (! frv_check_register_access (current_cpu
, target_index
,
866 hi_available
, lo_available
))
869 /* Determine whether we're working with GR or FR registers. */
871 NE_base
= H_SPR_FNER0
;
873 NE_base
= H_SPR_GNER0
;
875 /* Always clear the appropriate NE flags. */
876 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
879 /* Clear the appropriate NESR and NEEAR registers. */
880 control
= CPU_REGISTER_CONTROL (current_cpu
);
881 if (control
->spr
[H_SPR_NECR
].implemented
)
884 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
))
885 clear_nesr_neear (current_cpu
, target_index
, is_float
);
890 frvbf_commit (SIM_CPU
*current_cpu
, SI target_index
, BI is_float
)
899 FRV_REGISTER_CONTROL
*control
;
901 /* Check for availability of the target register(s). */
902 which_registers_available (current_cpu
, & hi_available
, & lo_available
,
905 /* Check to make sure that the target register is available. */
906 if (! frv_check_register_access (current_cpu
, target_index
,
907 hi_available
, lo_available
))
910 /* Determine whether we're working with GR or FR registers. */
912 NE_base
= H_SPR_FNER0
;
914 NE_base
= H_SPR_GNER0
;
916 /* Determine whether a ne exception is pending. */
917 GET_NE_FLAGS (NE_flags
, NE_base
);
918 if (target_index
>= 0)
919 NE_flag
= GET_NE_FLAG (NE_flags
, target_index
);
923 hi_available
&& NE_flags
[0] != 0 || lo_available
&& NE_flags
[1] != 0;
926 /* Always clear the appropriate NE flags. */
927 clear_ne_flags (current_cpu
, target_index
, hi_available
, lo_available
,
930 control
= CPU_REGISTER_CONTROL (current_cpu
);
931 if (control
->spr
[H_SPR_NECR
].implemented
)
934 if (GET_NECR_VALID (necr
) && GET_NECR_ELOS (necr
) && NE_flag
)
936 /* Clear the appropriate NESR and NEEAR registers. */
937 clear_nesr_neear (current_cpu
, target_index
, is_float
);
938 frv_queue_program_interrupt (current_cpu
, FRV_COMMIT_EXCEPTION
);
943 /* Generate the appropriate fp_exception(s) based on the given status code. */
945 frvbf_fpu_error (CGEN_FPU
* fpu
, int status
)
947 struct frv_fp_exception_info fp_info
= {
948 FSR_NO_EXCEPTION
, FTT_IEEE_754_EXCEPTION
952 (sim_fpu_status_invalid_snan
|
953 sim_fpu_status_invalid_qnan
|
954 sim_fpu_status_invalid_isi
|
955 sim_fpu_status_invalid_idi
|
956 sim_fpu_status_invalid_zdz
|
957 sim_fpu_status_invalid_imz
|
958 sim_fpu_status_invalid_cvi
|
959 sim_fpu_status_invalid_cmp
|
960 sim_fpu_status_invalid_sqrt
))
961 fp_info
.fsr_mask
|= FSR_INVALID_OPERATION
;
963 if (status
& sim_fpu_status_invalid_div0
)
964 fp_info
.fsr_mask
|= FSR_DIVISION_BY_ZERO
;
966 if (status
& sim_fpu_status_inexact
)
967 fp_info
.fsr_mask
|= FSR_INEXACT
;
969 if (status
& sim_fpu_status_overflow
)
970 fp_info
.fsr_mask
|= FSR_OVERFLOW
;
972 if (status
& sim_fpu_status_underflow
)
973 fp_info
.fsr_mask
|= FSR_UNDERFLOW
;
975 if (status
& sim_fpu_status_denorm
)
977 fp_info
.fsr_mask
|= FSR_DENORMAL_INPUT
;
978 fp_info
.ftt
= FTT_DENORMAL_INPUT
;
981 if (fp_info
.fsr_mask
!= FSR_NO_EXCEPTION
)
983 SIM_CPU
*current_cpu
= (SIM_CPU
*)fpu
->owner
;
984 frv_queue_fp_exception_interrupt (current_cpu
, & fp_info
);