2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
20 /* This must come before any other includes. */
26 #ifdef HAVE_SYS_PARAM_H
27 #include <sys/param.h>
32 #include "gdb/sim-h8300.h"
34 #include "sys/types.h"
35 #include "sim-options.h"
43 static int memory_size
;
45 #define X(op, size) (op * 4 + size)
47 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
49 #define h8_opcodes ops
51 #include "opcode/h8300.h"
53 /* CPU data object: */
56 h8_get_pc (SIM_DESC sd
)
58 return (STATE_CPU (sd
, 0)) -> pc
;
62 h8_set_pc (SIM_DESC sd
, unsigned int val
)
64 (STATE_CPU (sd
, 0)) -> pc
= val
;
68 h8_get_ccr (SIM_DESC sd
)
70 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
74 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
76 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
80 h8_get_exr (SIM_DESC sd
)
82 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
86 h8_set_exr (SIM_DESC sd
, unsigned int val
)
88 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
92 h8_get_sbr (SIM_DESC sd
)
94 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
98 h8_set_sbr (SIM_DESC sd
, int val
)
100 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
104 h8_get_vbr (SIM_DESC sd
)
106 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
110 h8_set_vbr (SIM_DESC sd
, int val
)
112 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
116 h8_get_mask (SIM_DESC sd
)
118 return (STATE_CPU (sd
, 0)) -> mask
;
122 h8_set_mask (SIM_DESC sd
, int val
)
124 (STATE_CPU (sd
, 0)) -> mask
= val
;
128 h8_get_exception (SIM_DESC sd
)
130 return (STATE_CPU (sd
, 0)) -> exception
;
134 h8_set_exception (SIM_DESC sd
, int val
)
136 (STATE_CPU (sd
, 0)) -> exception
= val
;
139 static enum h8300_sim_state
140 h8_get_state (SIM_DESC sd
)
142 return H8300_SIM_STATE (sd
)->state
;
146 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
148 H8300_SIM_STATE (sd
)->state
= val
;
152 h8_get_cycles (SIM_DESC sd
)
154 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
158 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
160 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
164 h8_get_insts (SIM_DESC sd
)
166 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
170 h8_set_insts (SIM_DESC sd
, unsigned int val
)
172 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
176 h8_get_ticks (SIM_DESC sd
)
178 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
182 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
184 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
188 h8_get_mach (SIM_DESC sd
)
190 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
194 h8_set_mach (SIM_DESC sd
, unsigned int val
)
196 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
200 h8_get_macl (SIM_DESC sd
)
202 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
206 h8_set_macl (SIM_DESC sd
, unsigned int val
)
208 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
211 static unsigned int *
212 h8_get_reg_buf (SIM_DESC sd
)
214 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
218 h8_get_reg (SIM_DESC sd
, int regnum
)
220 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
224 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
226 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
231 h8_get_stats (SIM_DESC sd
, int idx
)
233 return H8300_SIM_STATE (sd
)->stats
[idx
];
237 h8_increment_stats (SIM_DESC sd
, int idx
)
239 H8300_SIM_STATE (sd
)->stats
[idx
] ++;
243 static unsigned char *
244 h8_get_memory_buf (SIM_DESC sd
)
246 return (STATE_CPU (sd
, 0)) -> memory
;
250 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
252 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
256 h8_get_memory (SIM_DESC sd
, int idx
)
258 ASSERT (idx
< memory_size
);
259 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
263 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
265 ASSERT (idx
< memory_size
);
266 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
270 h8_get_delayed_branch (SIM_DESC sd
)
272 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
276 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
278 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
282 h8_get_command_line (SIM_DESC sd
)
284 return (STATE_CPU (sd
, 0)) -> command_line
;
288 h8_set_command_line (SIM_DESC sd
, char ** val
)
290 (STATE_CPU (sd
, 0)) -> command_line
= val
;
294 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
296 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
300 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
302 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
305 /* MAC Saturation Mode */
307 h8_get_macS (SIM_DESC sd
)
309 return (STATE_CPU (sd
, 0)) -> macS
;
314 h8_set_macS (SIM_DESC sd
, int val
)
316 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
322 h8_get_macZ (SIM_DESC sd
)
324 return (STATE_CPU (sd
, 0)) -> macZ
;
328 h8_set_macZ (SIM_DESC sd
, int val
)
330 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
333 /* MAC Negative Flag */
335 h8_get_macN (SIM_DESC sd
)
337 return (STATE_CPU (sd
, 0)) -> macN
;
341 h8_set_macN (SIM_DESC sd
, int val
)
343 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
346 /* MAC Overflow Flag */
348 h8_get_macV (SIM_DESC sd
)
350 return (STATE_CPU (sd
, 0)) -> macV
;
354 h8_set_macV (SIM_DESC sd
, int val
)
356 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
359 /* End CPU data object. */
361 /* The rate at which to call the host's poll_quit callback. */
363 enum { POLL_QUIT_INTERVAL
= 0x80000 };
365 #define LOW_BYTE(x) ((x) & 0xff)
366 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
367 #define P(X, Y) ((X << 8) | Y)
376 #define I (intMaskBit != 0)
378 #define BUILDSR(SD) \
379 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
380 | (N << 3) | (Z << 2) | (V << 1) | C)
383 /* Get Status Register (flags). */ \
384 c = (h8_get_ccr (sd) >> 0) & 1; \
385 v = (h8_get_ccr (sd) >> 1) & 1; \
386 nz = !((h8_get_ccr (sd) >> 2) & 1); \
387 n = (h8_get_ccr (sd) >> 3) & 1; \
388 u = (h8_get_ccr (sd) >> 4) & 1; \
389 h = (h8_get_ccr (sd) >> 5) & 1; \
390 ui = ((h8_get_ccr (sd) >> 6) & 1); \
391 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
394 #ifdef __CHAR_IS_SIGNED__
395 #define SEXTCHAR(x) ((char) (x))
399 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
402 #define UEXTCHAR(x) ((x) & 0xff)
403 #define UEXTSHORT(x) ((x) & 0xffff)
404 #define SEXTSHORT(x) ((short) (x))
408 int h8300_normal_mode
= 0;
414 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
436 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
441 /* Simulate an indirection / dereference.
442 return 0 for success, -1 for failure.
446 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
448 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
450 if (val
== NULL
) /* Paranoia. */
456 if (rn
== ZERO_REGNUM
)
457 *val
= X (OP_IMM
, SP
);
459 *val
= X (OP_REG
, SP
);
462 *val
= X (OP_MEM
, SP
);
465 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
472 cmdline_location(void)
474 if (h8300smode
&& !h8300_normal_mode
)
476 else if (h8300hmode
&& !h8300_normal_mode
)
483 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
485 int cst
[3] = {0, 0, 0};
486 int reg
[3] = {0, 0, 0};
487 int rdisp
[3] = {0, 0, 0};
489 const struct h8_opcode
*q
;
494 /* Find the exact opcode/arg combo. */
495 for (q
= h8_opcodes
; q
->name
; q
++)
497 const op_type
*nib
= q
->data
.nib
;
498 unsigned int len
= 0;
500 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
501 (q
->available
== AV_H8S
&& !h8300smode
) ||
502 (q
->available
== AV_H8H
&& !h8300hmode
))
505 cst
[0] = cst
[1] = cst
[2] = 0;
506 reg
[0] = reg
[1] = reg
[2] = 0;
507 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
511 op_type looking_for
= *nib
;
512 int thisnib
= data
[len
/ 2];
514 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
515 opnum
= ((looking_for
& OP3
) ? 2 :
516 (looking_for
& DST
) ? 1 : 0);
518 if (looking_for
< 16 && looking_for
>= 0)
520 if (looking_for
!= thisnib
)
525 if (looking_for
& B31
)
527 if (!((thisnib
& 0x8) != 0))
530 looking_for
= (op_type
) (looking_for
& ~B31
);
533 else if (looking_for
& B30
)
535 if (!((thisnib
& 0x8) == 0))
538 looking_for
= (op_type
) (looking_for
& ~B30
);
541 if (looking_for
& B21
)
543 if (!((thisnib
& 0x4) != 0))
546 looking_for
= (op_type
) (looking_for
& ~B21
);
549 else if (looking_for
& B20
)
551 if (!((thisnib
& 0x4) == 0))
554 looking_for
= (op_type
) (looking_for
& ~B20
);
557 if (looking_for
& B11
)
559 if (!((thisnib
& 0x2) != 0))
562 looking_for
= (op_type
) (looking_for
& ~B11
);
565 else if (looking_for
& B10
)
567 if (!((thisnib
& 0x2) == 0))
570 looking_for
= (op_type
) (looking_for
& ~B10
);
573 if (looking_for
& B01
)
575 if (!((thisnib
& 0x1) != 0))
578 looking_for
= (op_type
) (looking_for
& ~B01
);
581 else if (looking_for
& B00
)
583 if (!((thisnib
& 0x1) == 0))
586 looking_for
= (op_type
) (looking_for
& ~B00
);
589 if (looking_for
& IGNORE
)
591 /* Hitachi has declared that IGNORE must be zero. */
595 else if ((looking_for
& MODE
) == DATA
)
597 ; /* Skip embedded data. */
599 else if ((looking_for
& MODE
) == DBIT
)
601 /* Exclude adds/subs by looking at bit 0 and 2, and
602 make sure the operand size, either w or l,
603 matches by looking at bit 1. */
604 if ((looking_for
& 7) != (thisnib
& 7))
607 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
609 else if ((looking_for
& MODE
) == REG
||
610 (looking_for
& MODE
) == LOWREG
||
611 (looking_for
& MODE
) == IND
||
612 (looking_for
& MODE
) == PREINC
||
613 (looking_for
& MODE
) == POSTINC
||
614 (looking_for
& MODE
) == PREDEC
||
615 (looking_for
& MODE
) == POSTDEC
)
617 reg
[opnum
] = thisnib
;
619 else if (looking_for
& CTRL
)
622 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
623 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
624 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
625 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
626 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
627 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
629 if (((looking_for
& MODE
) == CCR_EXR
&&
630 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
631 ((looking_for
& MODE
) == VBR_SBR
&&
632 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
633 ((looking_for
& MODE
) == MACREG
&&
634 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
636 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
637 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
638 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
641 reg
[opnum
] = thisnib
;
643 else if ((looking_for
& MODE
) == ABS
)
645 /* Absolute addresses are unsigned. */
646 switch (looking_for
& SIZE
)
649 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
653 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
657 (data
[len
/ 2 + 0] << 24) +
658 (data
[len
/ 2 + 1] << 16) +
659 (data
[len
/ 2 + 2] << 8) +
663 printf ("decode: bad size ABS: %d\n",
664 (looking_for
& SIZE
));
668 else if ((looking_for
& MODE
) == DISP
||
669 (looking_for
& MODE
) == PCREL
||
670 (looking_for
& MODE
) == INDEXB
||
671 (looking_for
& MODE
) == INDEXW
||
672 (looking_for
& MODE
) == INDEXL
)
674 switch (looking_for
& SIZE
)
677 cst
[opnum
] = thisnib
& 3;
680 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
683 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
684 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
687 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
691 (data
[len
/ 2 + 0] << 24) +
692 (data
[len
/ 2 + 1] << 16) +
693 (data
[len
/ 2 + 2] << 8) +
697 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
698 (looking_for
& SIZE
));
702 else if ((looking_for
& SIZE
) == L_16
||
703 (looking_for
& SIZE
) == L_16U
)
705 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
706 /* Immediates are always unsigned. */
707 if ((looking_for
& SIZE
) != L_16U
&&
708 (looking_for
& MODE
) != IMM
)
709 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
711 else if (looking_for
& ABSJMP
)
713 switch (looking_for
& SIZE
) {
715 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
719 (data
[len
/ 2 + 0] << 24) +
720 (data
[len
/ 2 + 1] << 16) +
721 (data
[len
/ 2 + 2] << 8) +
725 printf ("decode: bad size ABSJMP: %d\n",
726 (looking_for
& SIZE
));
730 else if ((looking_for
& MODE
) == MEMIND
)
732 cst
[opnum
] = data
[1];
734 else if ((looking_for
& MODE
) == VECIND
)
736 if(h8300_normal_mode
)
737 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
739 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
740 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
742 else if ((looking_for
& SIZE
) == L_32
)
747 (data
[i
+ 0] << 24) |
748 (data
[i
+ 1] << 16) |
752 else if ((looking_for
& SIZE
) == L_24
)
757 (data
[i
+ 0] << 16) |
761 else if (looking_for
& DISPREG
)
763 rdisp
[opnum
] = thisnib
& 0x7;
765 else if ((looking_for
& MODE
) == KBIT
)
782 else if ((looking_for
& SIZE
) == L_8
)
784 if ((looking_for
& MODE
) == ABS
)
786 /* Will be combined with contents of SBR_REGNUM
787 by fetch (). For all modes except h8sx, this
788 will always contain the value 0xFFFFFF00. */
789 cst
[opnum
] = data
[len
/ 2] & 0xff;
793 cst
[opnum
] = data
[len
/ 2] & 0xff;
796 else if ((looking_for
& SIZE
) == L_2
)
798 cst
[opnum
] = thisnib
& 3;
800 else if ((looking_for
& SIZE
) == L_3
||
801 (looking_for
& SIZE
) == L_3NZ
)
803 cst
[opnum
] = thisnib
& 7;
804 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
807 else if ((looking_for
& SIZE
) == L_4
)
809 cst
[opnum
] = thisnib
& 15;
811 else if ((looking_for
& SIZE
) == L_5
)
813 cst
[opnum
] = data
[len
/ 2] & 0x1f;
815 else if (looking_for
== E
)
820 /* Fill in the args. */
822 const op_type
*args
= q
->args
.nib
;
827 nargs
< 3 && *args
!= E
;
833 opnum
= ((x
& OP3
) ? 2 :
842 if ((x
& MODE
) == IMM
||
843 (x
& MODE
) == KBIT
||
846 /* Use the instruction to determine
848 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
849 p
->literal
= cst
[opnum
];
851 else if ((x
& MODE
) == CONST_2
||
852 (x
& MODE
) == CONST_4
||
853 (x
& MODE
) == CONST_8
||
854 (x
& MODE
) == CONST_16
)
856 /* Use the instruction to determine
858 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
860 case CONST_2
: p
->literal
= 2; break;
861 case CONST_4
: p
->literal
= 4; break;
862 case CONST_8
: p
->literal
= 8; break;
863 case CONST_16
: p
->literal
= 16; break;
866 else if ((x
& MODE
) == REG
)
868 p
->type
= X (OP_REG
, bitfrom (x
));
871 else if ((x
& MODE
) == LOWREG
)
873 p
->type
= X (OP_LOWREG
, bitfrom (x
));
876 else if ((x
& MODE
) == PREINC
)
878 /* Use the instruction to determine
880 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
881 p
->reg
= reg
[opnum
] & 0x7;
883 else if ((x
& MODE
) == POSTINC
)
885 /* Use the instruction to determine
887 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
888 p
->reg
= reg
[opnum
] & 0x7;
890 else if ((x
& MODE
) == PREDEC
)
892 /* Use the instruction to determine
894 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
895 p
->reg
= reg
[opnum
] & 0x7;
897 else if ((x
& MODE
) == POSTDEC
)
899 /* Use the instruction to determine
901 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
902 p
->reg
= reg
[opnum
] & 0x7;
904 else if ((x
& MODE
) == IND
)
906 /* Note: an indirect is transformed into
907 a displacement of zero.
909 /* Use the instruction to determine
911 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
912 p
->reg
= reg
[opnum
] & 0x7;
914 if (OP_KIND (q
->how
) == O_JSR
||
915 OP_KIND (q
->how
) == O_JMP
)
916 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
919 else if ((x
& MODE
) == ABS
)
921 /* Note: a 16 or 32 bit ABS is transformed into a
922 displacement from pseudo-register ZERO_REGNUM,
923 which is always zero. An 8 bit ABS becomes
924 a displacement from SBR_REGNUM.
926 /* Use the instruction to determine
928 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
929 p
->literal
= cst
[opnum
];
931 /* 8-bit ABS is displacement from SBR.
932 16 and 32-bit ABS are displacement from ZERO.
933 (SBR will always be zero except for h8/sx)
935 if ((x
& SIZE
) == L_8
)
938 p
->reg
= ZERO_REGNUM
;;
940 else if ((x
& MODE
) == MEMIND
||
941 (x
& MODE
) == VECIND
)
943 /* Size doesn't matter. */
944 p
->type
= X (OP_MEM
, SB
);
945 p
->literal
= cst
[opnum
];
946 if (OP_KIND (q
->how
) == O_JSR
||
947 OP_KIND (q
->how
) == O_JMP
)
948 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
951 else if ((x
& MODE
) == PCREL
)
953 /* Size doesn't matter. */
954 p
->type
= X (OP_PCREL
, SB
);
955 p
->literal
= cst
[opnum
];
959 p
->type
= X (OP_IMM
, SP
);
960 p
->literal
= cst
[opnum
];
962 else if ((x
& MODE
) == INDEXB
)
964 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
965 p
->literal
= cst
[opnum
];
966 p
->reg
= rdisp
[opnum
];
968 else if ((x
& MODE
) == INDEXW
)
970 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
971 p
->literal
= cst
[opnum
];
972 p
->reg
= rdisp
[opnum
];
974 else if ((x
& MODE
) == INDEXL
)
976 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
977 p
->literal
= cst
[opnum
];
978 p
->reg
= rdisp
[opnum
];
980 else if ((x
& MODE
) == DISP
)
982 /* Yuck -- special for mova args. */
983 if (strncmp (q
->name
, "mova", 4) == 0 &&
986 /* Mova can have a DISP2 dest, with an
987 INDEXB or INDEXW src. The multiplier
988 for the displacement value is determined
989 by the src operand, not by the insn. */
991 switch (OP_KIND (dst
->src
.type
))
994 p
->type
= X (OP_DISP
, SB
);
995 p
->literal
= cst
[opnum
];
998 p
->type
= X (OP_DISP
, SW
);
999 p
->literal
= cst
[opnum
] * 2;
1007 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1008 p
->literal
= cst
[opnum
];
1009 /* DISP2 is special. */
1010 if ((x
& SIZE
) == L_2
)
1011 switch (OP_SIZE (q
->how
))
1014 case SW
: p
->literal
*= 2; break;
1015 case SL
: p
->literal
*= 4; break;
1018 p
->reg
= rdisp
[opnum
];
1025 p
->type
= X (OP_CCR
, SB
);
1028 p
->type
= X (OP_EXR
, SB
);
1031 p
->type
= X (OP_MACH
, SL
);
1034 p
->type
= X (OP_MACL
, SL
);
1037 p
->type
= X (OP_VBR
, SL
);
1040 p
->type
= X (OP_SBR
, SL
);
1044 else if ((x
& MODE
) == CCR
)
1048 else if ((x
& MODE
) == EXR
)
1053 printf ("Hmmmm 0x%x...\n", x
);
1059 /* Unary operators: treat src and dst as equivalent. */
1060 if (dst
->dst
.type
== -1)
1061 dst
->dst
= dst
->src
;
1062 if (dst
->src
.type
== -1)
1063 dst
->src
= dst
->dst
;
1065 dst
->opcode
= q
->how
;
1066 dst
->cycles
= q
->time
;
1068 /* And jsr's to these locations are turned into
1071 if (OP_KIND (dst
->opcode
) == O_JSR
)
1073 switch (dst
->src
.literal
)
1076 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1079 dst
->opcode
= O (O_SYS_READ
, SB
);
1082 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1085 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1088 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1091 dst
->opcode
= O (O_SYS_STAT
, SB
);
1094 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1097 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1100 /* End of Processing for system calls. */
1103 dst
->next_pc
= addr
+ len
/ 2;
1107 printf ("Don't understand 0x%x \n", looking_for
);
1118 /* Fell off the end. */
1119 dst
->opcode
= O (O_ILL
, SB
);
1122 static unsigned char *breg
[32];
1123 static unsigned short *wreg
[16];
1125 #define GET_B_REG(X) *(breg[X])
1126 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1127 #define GET_W_REG(X) *(wreg[X])
1128 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1129 #define GET_L_REG(X) h8_get_reg (sd, X)
1130 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1132 #define GET_MEMORY_L(X) \
1133 ((X) < memory_size \
1134 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1135 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1138 #define GET_MEMORY_W(X) \
1139 ((X) < memory_size \
1140 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1143 #define GET_MEMORY_B(X) \
1144 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1146 #define SET_MEMORY_L(X, Y) \
1147 { register unsigned char *_p; register int __y = (Y); \
1148 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1149 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1150 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1153 #define SET_MEMORY_W(X, Y) \
1154 { register unsigned char *_p; register int __y = (Y); \
1155 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1156 _p[0] = __y >> 8; _p[1] = __y; \
1159 #define SET_MEMORY_B(X, Y) \
1160 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1162 /* Simulate a memory fetch.
1163 Return 0 for success, -1 for failure.
1167 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1169 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1171 int abs
= arg
->literal
;
1176 return -1; /* Paranoia. */
1180 /* Indexed register plus displacement mode:
1182 This new family of addressing modes are similar to OP_DISP
1183 (register plus displacement), with two differences:
1184 1) INDEXB uses only the least significant byte of the register,
1185 INDEXW uses only the least significant word, and
1186 INDEXL uses the entire register (just like OP_DISP).
1188 2) The displacement value in abs is multiplied by two
1189 for SW-sized operations, and by four for SL-size.
1191 This gives nine possible variations.
1194 case X (OP_INDEXB
, SB
):
1195 case X (OP_INDEXB
, SW
):
1196 case X (OP_INDEXB
, SL
):
1197 case X (OP_INDEXW
, SB
):
1198 case X (OP_INDEXW
, SW
):
1199 case X (OP_INDEXW
, SL
):
1200 case X (OP_INDEXL
, SB
):
1201 case X (OP_INDEXL
, SW
):
1202 case X (OP_INDEXL
, SL
):
1204 switch (OP_KIND (arg
->type
)) {
1205 case OP_INDEXB
: t
&= 0xff; break;
1206 case OP_INDEXW
: t
&= 0xffff; break;
1210 switch (OP_SIZE (arg
->type
)) {
1212 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1215 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1218 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1223 case X (OP_LOWREG
, SB
):
1224 *val
= GET_L_REG (rn
) & 0xff;
1226 case X (OP_LOWREG
, SW
):
1227 *val
= GET_L_REG (rn
) & 0xffff;
1230 case X (OP_REG
, SB
): /* Register direct, byte. */
1231 *val
= GET_B_REG (rn
);
1233 case X (OP_REG
, SW
): /* Register direct, word. */
1234 *val
= GET_W_REG (rn
);
1236 case X (OP_REG
, SL
): /* Register direct, long. */
1237 *val
= GET_L_REG (rn
);
1239 case X (OP_IMM
, SB
): /* Immediate, byte. */
1240 case X (OP_IMM
, SW
): /* Immediate, word. */
1241 case X (OP_IMM
, SL
): /* Immediate, long. */
1244 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1246 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1252 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1254 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1260 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1262 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1269 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1271 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1277 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1279 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1285 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1287 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1294 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1295 t
= GET_L_REG (rn
) - 1;
1297 t
&= h8_get_mask (sd
);
1298 *val
= GET_MEMORY_B (t
);
1301 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1302 t
= GET_L_REG (rn
) - 2;
1304 t
&= h8_get_mask (sd
);
1305 *val
= GET_MEMORY_W (t
);
1308 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1309 t
= GET_L_REG (rn
) - 4;
1311 t
&= h8_get_mask (sd
);
1312 *val
= GET_MEMORY_L (t
);
1315 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1316 t
= GET_L_REG (rn
) + 1;
1318 t
&= h8_get_mask (sd
);
1319 *val
= GET_MEMORY_B (t
);
1322 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1323 t
= GET_L_REG (rn
) + 2;
1325 t
&= h8_get_mask (sd
);
1326 *val
= GET_MEMORY_W (t
);
1329 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1330 t
= GET_L_REG (rn
) + 4;
1332 t
&= h8_get_mask (sd
);
1333 *val
= GET_MEMORY_L (t
);
1336 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1337 t
= GET_L_REG (rn
) + abs
;
1338 t
&= h8_get_mask (sd
);
1339 *val
= GET_MEMORY_B (t
);
1342 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1343 t
= GET_L_REG (rn
) + abs
;
1344 t
&= h8_get_mask (sd
);
1345 *val
= GET_MEMORY_W (t
);
1348 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1349 t
= GET_L_REG (rn
) + abs
;
1350 t
&= h8_get_mask (sd
);
1351 *val
=GET_MEMORY_L (t
);
1354 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1355 t
= GET_MEMORY_L (abs
);
1356 t
&= h8_get_mask (sd
);
1360 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1361 t
= GET_MEMORY_W (abs
);
1362 t
&= h8_get_mask (sd
);
1366 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1367 case X (OP_PCREL
, SW
):
1368 case X (OP_PCREL
, SL
):
1369 case X (OP_PCREL
, SN
):
1373 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1375 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1378 return 0; /* Success. */
1384 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1386 return fetch_1 (sd
, arg
, val
, 0);
1389 /* Fetch which will be followed by a store to the same location.
1390 The difference being that we don't want to do a post-increment
1391 or post-decrement at this time: we'll do it when we store. */
1394 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1396 return fetch_1 (sd
, arg
, val
, 1);
1399 /* Simulate a memory store.
1400 Return 0 for success, -1 for failure.
1404 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1406 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1408 int abs
= arg
->literal
;
1413 /* Indexed register plus displacement mode:
1415 This new family of addressing modes are similar to OP_DISP
1416 (register plus displacement), with two differences:
1417 1) INDEXB uses only the least significant byte of the register,
1418 INDEXW uses only the least significant word, and
1419 INDEXL uses the entire register (just like OP_DISP).
1421 2) The displacement value in abs is multiplied by two
1422 for SW-sized operations, and by four for SL-size.
1424 This gives nine possible variations.
1427 case X (OP_INDEXB
, SB
):
1428 case X (OP_INDEXB
, SW
):
1429 case X (OP_INDEXB
, SL
):
1430 case X (OP_INDEXW
, SB
):
1431 case X (OP_INDEXW
, SW
):
1432 case X (OP_INDEXW
, SL
):
1433 case X (OP_INDEXL
, SB
):
1434 case X (OP_INDEXL
, SW
):
1435 case X (OP_INDEXL
, SL
):
1437 switch (OP_KIND (arg
->type
)) {
1438 case OP_INDEXB
: t
&= 0xff; break;
1439 case OP_INDEXW
: t
&= 0xffff; break;
1443 switch (OP_SIZE (arg
->type
)) {
1445 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1448 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1451 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1456 case X (OP_REG
, SB
): /* Register direct, byte. */
1459 case X (OP_REG
, SW
): /* Register direct, word. */
1462 case X (OP_REG
, SL
): /* Register direct, long. */
1466 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1471 t
&= h8_get_mask (sd
);
1472 SET_MEMORY_B (t
, n
);
1475 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1480 t
&= h8_get_mask (sd
);
1481 SET_MEMORY_W (t
, n
);
1484 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1489 t
&= h8_get_mask (sd
);
1490 SET_MEMORY_L (t
, n
);
1493 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1498 t
&= h8_get_mask (sd
);
1499 SET_MEMORY_B (t
, n
);
1502 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1507 t
&= h8_get_mask (sd
);
1508 SET_MEMORY_W (t
, n
);
1511 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1516 t
&= h8_get_mask (sd
);
1517 SET_MEMORY_L (t
, n
);
1520 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1522 SET_L_REG (rn
, t
- 1);
1523 t
&= h8_get_mask (sd
);
1524 SET_MEMORY_B (t
, n
);
1527 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1529 SET_L_REG (rn
, t
- 2);
1530 t
&= h8_get_mask (sd
);
1531 SET_MEMORY_W (t
, n
);
1534 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1536 SET_L_REG (rn
, t
- 4);
1537 t
&= h8_get_mask (sd
);
1538 SET_MEMORY_L (t
, n
);
1541 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1543 SET_L_REG (rn
, t
+ 1);
1544 t
&= h8_get_mask (sd
);
1545 SET_MEMORY_B (t
, n
);
1548 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1550 SET_L_REG (rn
, t
+ 2);
1551 t
&= h8_get_mask (sd
);
1552 SET_MEMORY_W (t
, n
);
1555 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1557 SET_L_REG (rn
, t
+ 4);
1558 t
&= h8_get_mask (sd
);
1559 SET_MEMORY_L (t
, n
);
1562 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1563 t
= GET_L_REG (rn
) + abs
;
1564 t
&= h8_get_mask (sd
);
1565 SET_MEMORY_B (t
, n
);
1568 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1569 t
= GET_L_REG (rn
) + abs
;
1570 t
&= h8_get_mask (sd
);
1571 SET_MEMORY_W (t
, n
);
1574 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1575 t
= GET_L_REG (rn
) + abs
;
1576 t
&= h8_get_mask (sd
);
1577 SET_MEMORY_L (t
, n
);
1581 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1582 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1583 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1585 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1594 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1596 return store_1 (sd
, arg
, n
, 0);
1599 /* Store which follows a fetch from the same location.
1600 The difference being that we don't want to do a pre-increment
1601 or pre-decrement at this time: it was already done when we fetched. */
1604 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1606 return store_1 (sd
, arg
, n
, 1);
1609 /* Flag to be set whenever a new SIM_DESC object is created. */
1610 static int init_pointers_needed
= 1;
1613 init_pointers (SIM_DESC sd
)
1615 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1617 if (init_pointers_needed
)
1621 if (h8300smode
&& !h8300_normal_mode
)
1622 memory_size
= H8300S_MSIZE
;
1623 else if (h8300hmode
&& !h8300_normal_mode
)
1624 memory_size
= H8300H_MSIZE
;
1626 memory_size
= H8300_MSIZE
;
1627 /* `msize' must be a power of two. */
1628 if ((memory_size
& (memory_size
- 1)) != 0)
1632 "init_pointers: bad memory size %d, defaulting to %d.\n",
1633 memory_size
, H8300S_MSIZE
);
1634 memory_size
= H8300S_MSIZE
;
1637 if (h8_get_memory_buf (sd
))
1638 free (h8_get_memory_buf (sd
));
1640 h8_set_memory_buf (sd
, (unsigned char *)
1641 calloc (sizeof (char), memory_size
));
1642 state
->memory_size
= memory_size
;
1644 h8_set_mask (sd
, memory_size
- 1);
1646 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1648 for (i
= 0; i
< 8; i
++)
1650 /* FIXME: rewrite using local buffer. */
1651 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1652 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1653 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1654 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1655 h8_set_reg (sd
, i
, 0x00112233);
1670 wreg
[i
] = wreg
[i
+ 8] = 0;
1684 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1685 sim_io_printf (sd
, "init_pointers: internal error.\n");
1687 h8_set_reg (sd
, i
, 0);
1690 init_pointers_needed
= 0;
1694 #define OBITOP(name, f, s, op) \
1695 case O (name, SB): \
1700 if (fetch (sd, &code->dst, &ea)) \
1702 if (fetch (sd, &code->src, &tmp)) \
1704 m = 1 << (tmp & 7); \
1707 if (store (sd, &code->dst,ea)) \
1713 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1717 int tick_start
= get_now ();
1724 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1728 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
1729 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1733 pc
= h8_get_pc (sd
);
1735 /* The PC should never be odd. */
1738 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1742 /* Get Status Register (flags). */
1745 if (h8300smode
) /* Get exr. */
1747 trace
= (h8_get_exr (sd
) >> 7) & 1;
1748 intMask
= h8_get_exr (sd
) & 7;
1751 oldmask
= h8_get_mask (sd
);
1752 if (!h8300hmode
|| h8300_normal_mode
)
1753 h8_set_mask (sd
, 0xffff);
1756 decoded_inst _code
, *code
= &_code
;
1757 memset (code
, 0, sizeof (*code
));
1758 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1764 printf ("%x %d %s\n", pc
, code
->opcode
,
1765 code
->op
? code
->op
->name
: "**");
1767 h8_increment_stats (sd
, code
->opcode
);
1772 cycles
+= code
->cycles
;
1776 switch (code
->opcode
)
1778 case O (O_MOVAB
, SL
):
1779 case O (O_MOVAW
, SL
):
1780 case O (O_MOVAL
, SL
):
1781 /* 1) Evaluate 2nd argument (dst).
1782 2) Mask / zero extend according to whether 1st argument (src)
1783 is INDEXB, INDEXW, or INDEXL.
1784 3) Left-shift the result by 0, 1 or 2, according to size of mova
1785 (mova/b, mova/w, mova/l).
1786 4) Add literal value of 1st argument (src).
1787 5) Store result in 3rd argument (op3).
1790 /* Alas, since this is the only instruction with 3 arguments,
1791 decode doesn't handle them very well. Some fix-up is required.
1793 a) The size of dst is determined by whether src is
1794 INDEXB or INDEXW. */
1796 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1797 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1798 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1799 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1801 /* b) If op3 == null, then this is the short form of the insn.
1802 Dst is the dispreg of src, and op3 is the 32-bit form
1803 of the same register.
1806 if (code
->op3
.type
== 0)
1808 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1809 We get to compose dst and op3 as follows:
1811 op3 is a 32-bit register, ID == src.reg.
1812 dst is the same register, but 8 or 16 bits
1813 depending on whether src is INDEXB or INDEXW.
1816 code
->op3
.type
= X (OP_REG
, SL
);
1817 code
->op3
.reg
= code
->src
.reg
;
1818 code
->op3
.literal
= 0;
1820 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1822 code
->dst
.type
= X (OP_REG
, SB
);
1823 code
->dst
.reg
= code
->op3
.reg
+ 8;
1826 code
->dst
.type
= X (OP_REG
, SW
);
1829 if (fetch (sd
, &code
->dst
, &ea
))
1832 switch (OP_KIND (code
->src
.type
)) {
1833 case OP_INDEXB
: ea
= ea
& 0xff; break;
1834 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1835 case OP_INDEXL
: break;
1836 default: goto illegal
;
1839 switch (code
->opcode
) {
1840 case O (O_MOVAB
, SL
): break;
1841 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1842 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1843 default: goto illegal
;
1846 ea
= ea
+ code
->src
.literal
;
1848 if (store (sd
, &code
->op3
, ea
))
1853 case O (O_SUBX
, SB
): /* subx, extended sub */
1854 if (fetch2 (sd
, &code
->dst
, &rd
))
1856 if (fetch (sd
, &code
->src
, &ea
))
1862 case O (O_SUBX
, SW
): /* subx, extended sub */
1863 if (fetch2 (sd
, &code
->dst
, &rd
))
1865 if (fetch (sd
, &code
->src
, &ea
))
1871 case O (O_SUBX
, SL
): /* subx, extended sub */
1872 if (fetch2 (sd
, &code
->dst
, &rd
))
1874 if (fetch (sd
, &code
->src
, &ea
))
1880 case O (O_ADDX
, SB
): /* addx, extended add */
1881 if (fetch2 (sd
, &code
->dst
, &rd
))
1883 if (fetch (sd
, &code
->src
, &ea
))
1889 case O (O_ADDX
, SW
): /* addx, extended add */
1890 if (fetch2 (sd
, &code
->dst
, &rd
))
1892 if (fetch (sd
, &code
->src
, &ea
))
1898 case O (O_ADDX
, SL
): /* addx, extended add */
1899 if (fetch2 (sd
, &code
->dst
, &rd
))
1901 if (fetch (sd
, &code
->src
, &ea
))
1907 case O (O_SUB
, SB
): /* sub.b */
1908 /* Fetch rd and ea. */
1909 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1915 case O (O_SUB
, SW
): /* sub.w */
1916 /* Fetch rd and ea. */
1917 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1923 case O (O_SUB
, SL
): /* sub.l */
1924 /* Fetch rd and ea. */
1925 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1931 case O (O_NEG
, SB
): /* neg.b */
1933 if (fetch2 (sd
, &code
->src
, &ea
))
1940 case O (O_NEG
, SW
): /* neg.w */
1942 if (fetch2 (sd
, &code
->src
, &ea
))
1949 case O (O_NEG
, SL
): /* neg.l */
1951 if (fetch2 (sd
, &code
->src
, &ea
))
1958 case O (O_ADD
, SB
): /* add.b */
1959 if (fetch2 (sd
, &code
->dst
, &rd
))
1961 if (fetch (sd
, &code
->src
, &ea
))
1966 case O (O_ADD
, SW
): /* add.w */
1967 if (fetch2 (sd
, &code
->dst
, &rd
))
1969 if (fetch (sd
, &code
->src
, &ea
))
1974 case O (O_ADD
, SL
): /* add.l */
1975 if (fetch2 (sd
, &code
->dst
, &rd
))
1977 if (fetch (sd
, &code
->src
, &ea
))
1982 case O (O_AND
, SB
): /* and.b */
1983 /* Fetch rd and ea. */
1984 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1989 case O (O_AND
, SW
): /* and.w */
1990 /* Fetch rd and ea. */
1991 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1996 case O (O_AND
, SL
): /* and.l */
1997 /* Fetch rd and ea. */
1998 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2003 case O (O_OR
, SB
): /* or.b */
2004 /* Fetch rd and ea. */
2005 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2010 case O (O_OR
, SW
): /* or.w */
2011 /* Fetch rd and ea. */
2012 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2017 case O (O_OR
, SL
): /* or.l */
2018 /* Fetch rd and ea. */
2019 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2024 case O (O_XOR
, SB
): /* xor.b */
2025 /* Fetch rd and ea. */
2026 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2031 case O (O_XOR
, SW
): /* xor.w */
2032 /* Fetch rd and ea. */
2033 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2038 case O (O_XOR
, SL
): /* xor.l */
2039 /* Fetch rd and ea. */
2040 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2046 if (fetch (sd
, &code
->src
, &res
))
2048 if (store (sd
, &code
->dst
, res
))
2050 goto just_flags_log8
;
2052 if (fetch (sd
, &code
->src
, &res
))
2054 if (store (sd
, &code
->dst
, res
))
2056 goto just_flags_log16
;
2058 if (fetch (sd
, &code
->src
, &res
))
2060 if (store (sd
, &code
->dst
, res
))
2062 goto just_flags_log32
;
2064 case O (O_MOVMD
, SB
): /* movmd.b */
2071 rd
= GET_MEMORY_B (GET_L_REG (5));
2072 SET_MEMORY_B (GET_L_REG (6), rd
);
2073 SET_L_REG (5, GET_L_REG (5) + 1);
2074 SET_L_REG (6, GET_L_REG (6) + 1);
2079 case O (O_MOVMD
, SW
): /* movmd.w */
2086 rd
= GET_MEMORY_W (GET_L_REG (5));
2087 SET_MEMORY_W (GET_L_REG (6), rd
);
2088 SET_L_REG (5, GET_L_REG (5) + 2);
2089 SET_L_REG (6, GET_L_REG (6) + 2);
2094 case O (O_MOVMD
, SL
): /* movmd.l */
2101 rd
= GET_MEMORY_L (GET_L_REG (5));
2102 SET_MEMORY_L (GET_L_REG (6), rd
);
2103 SET_L_REG (5, GET_L_REG (5) + 4);
2104 SET_L_REG (6, GET_L_REG (6) + 4);
2109 case O (O_MOVSD
, SB
): /* movsd.b */
2110 /* This instruction implements strncpy, with a conditional branch.
2111 r4 contains n, r5 contains src, and r6 contains dst.
2112 The 16-bit displacement operand is added to the pc
2113 if and only if the end of string is reached before
2114 n bytes are transferred. */
2116 ea
= GET_L_REG (4) & 0xffff;
2122 rd
= GET_MEMORY_B (GET_L_REG (5));
2123 SET_MEMORY_B (GET_L_REG (6), rd
);
2124 SET_L_REG (5, GET_L_REG (5) + 1);
2125 SET_L_REG (6, GET_L_REG (6) + 1);
2132 case O (O_EEPMOV
, SB
): /* eepmov.b */
2133 case O (O_EEPMOV
, SW
): /* eepmov.w */
2134 if (h8300hmode
|| h8300smode
)
2136 register unsigned char *_src
, *_dst
;
2137 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2138 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2139 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2141 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2142 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2144 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2145 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2147 memcpy (_dst
, _src
, count
);
2149 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2150 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2151 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2152 ((code
->opcode
== O (O_EEPMOV
, SW
))
2153 ? (~0xffff) : (~0xff)));
2154 cycles
+= 2 * count
;
2159 case O (O_ADDS
, SL
): /* adds (.l) */
2161 * This insn only uses register operands, but still
2162 * it would be cleaner to use fetch and store... */
2163 SET_L_REG (code
->dst
.reg
,
2164 GET_L_REG (code
->dst
.reg
)
2165 + code
->src
.literal
);
2169 case O (O_SUBS
, SL
): /* subs (.l) */
2171 * This insn only uses register operands, but still
2172 * it would be cleaner to use fetch and store... */
2173 SET_L_REG (code
->dst
.reg
,
2174 GET_L_REG (code
->dst
.reg
)
2175 - code
->src
.literal
);
2178 case O (O_CMP
, SB
): /* cmp.b */
2179 if (fetch (sd
, &code
->dst
, &rd
))
2181 if (fetch (sd
, &code
->src
, &ea
))
2185 goto just_flags_alu8
;
2187 case O (O_CMP
, SW
): /* cmp.w */
2188 if (fetch (sd
, &code
->dst
, &rd
))
2190 if (fetch (sd
, &code
->src
, &ea
))
2194 goto just_flags_alu16
;
2196 case O (O_CMP
, SL
): /* cmp.l */
2197 if (fetch (sd
, &code
->dst
, &rd
))
2199 if (fetch (sd
, &code
->src
, &ea
))
2203 goto just_flags_alu32
;
2205 case O (O_DEC
, SB
): /* dec.b */
2207 * This insn only uses register operands, but still
2208 * it would be cleaner to use fetch and store... */
2209 rd
= GET_B_REG (code
->src
.reg
);
2212 SET_B_REG (code
->src
.reg
, res
);
2213 goto just_flags_inc8
;
2215 case O (O_DEC
, SW
): /* dec.w */
2217 * This insn only uses register operands, but still
2218 * it would be cleaner to use fetch and store... */
2219 rd
= GET_W_REG (code
->dst
.reg
);
2220 ea
= -code
->src
.literal
;
2222 SET_W_REG (code
->dst
.reg
, res
);
2223 goto just_flags_inc16
;
2225 case O (O_DEC
, SL
): /* dec.l */
2227 * This insn only uses register operands, but still
2228 * it would be cleaner to use fetch and store... */
2229 rd
= GET_L_REG (code
->dst
.reg
);
2230 ea
= -code
->src
.literal
;
2232 SET_L_REG (code
->dst
.reg
, res
);
2233 goto just_flags_inc32
;
2235 case O (O_INC
, SB
): /* inc.b */
2237 * This insn only uses register operands, but still
2238 * it would be cleaner to use fetch and store... */
2239 rd
= GET_B_REG (code
->src
.reg
);
2242 SET_B_REG (code
->src
.reg
, res
);
2243 goto just_flags_inc8
;
2245 case O (O_INC
, SW
): /* inc.w */
2247 * This insn only uses register operands, but still
2248 * it would be cleaner to use fetch and store... */
2249 rd
= GET_W_REG (code
->dst
.reg
);
2250 ea
= code
->src
.literal
;
2252 SET_W_REG (code
->dst
.reg
, res
);
2253 goto just_flags_inc16
;
2255 case O (O_INC
, SL
): /* inc.l */
2257 * This insn only uses register operands, but still
2258 * it would be cleaner to use fetch and store... */
2259 rd
= GET_L_REG (code
->dst
.reg
);
2260 ea
= code
->src
.literal
;
2262 SET_L_REG (code
->dst
.reg
, res
);
2263 goto just_flags_inc32
;
2265 case O (O_LDC
, SB
): /* ldc.b */
2266 if (fetch (sd
, &code
->src
, &res
))
2270 case O (O_LDC
, SW
): /* ldc.w */
2271 if (fetch (sd
, &code
->src
, &res
))
2274 /* Word operand, value from MSB, must be shifted. */
2278 case O (O_LDC
, SL
): /* ldc.l */
2279 if (fetch (sd
, &code
->src
, &res
))
2281 switch (code
->dst
.type
) {
2282 case X (OP_SBR
, SL
):
2283 h8_set_sbr (sd
, res
);
2285 case X (OP_VBR
, SL
):
2286 h8_set_vbr (sd
, res
);
2293 case O (O_STC
, SW
): /* stc.w */
2294 case O (O_STC
, SB
): /* stc.b */
2295 if (code
->src
.type
== X (OP_CCR
, SB
))
2298 res
= h8_get_ccr (sd
);
2300 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2303 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2304 res
= h8_get_exr (sd
);
2309 /* Word operand, value to MSB, must be shifted. */
2310 if (code
->opcode
== X (O_STC
, SW
))
2312 if (store (sd
, &code
->dst
, res
))
2315 case O (O_STC
, SL
): /* stc.l */
2316 switch (code
->src
.type
) {
2317 case X (OP_SBR
, SL
):
2318 res
= h8_get_sbr (sd
);
2320 case X (OP_VBR
, SL
):
2321 res
= h8_get_vbr (sd
);
2326 if (store (sd
, &code
->dst
, res
))
2330 case O (O_ANDC
, SB
): /* andc.b */
2331 if (code
->dst
.type
== X (OP_CCR
, SB
))
2334 rd
= h8_get_ccr (sd
);
2336 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2339 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2340 rd
= h8_get_exr (sd
);
2344 ea
= code
->src
.literal
;
2348 case O (O_ORC
, SB
): /* orc.b */
2349 if (code
->dst
.type
== X (OP_CCR
, SB
))
2352 rd
= h8_get_ccr (sd
);
2354 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2357 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2358 rd
= h8_get_exr (sd
);
2362 ea
= code
->src
.literal
;
2366 case O (O_XORC
, SB
): /* xorc.b */
2367 if (code
->dst
.type
== X (OP_CCR
, SB
))
2370 rd
= h8_get_ccr (sd
);
2372 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2375 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2376 rd
= h8_get_exr (sd
);
2380 ea
= code
->src
.literal
;
2384 case O (O_BRAS
, SB
): /* bra/s */
2385 /* This is basically an ordinary branch, with a delay slot. */
2386 if (fetch (sd
, &code
->src
, &res
))
2394 /* Execution continues at next instruction, but
2395 delayed_branch is set up for next cycle. */
2396 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2400 case O (O_BRAB
, SB
): /* bra rd.b */
2401 case O (O_BRAW
, SW
): /* bra rd.w */
2402 case O (O_BRAL
, SL
): /* bra erd.l */
2403 if (fetch (sd
, &code
->src
, &rd
))
2405 switch (OP_SIZE (code
->opcode
)) {
2406 case SB
: rd
&= 0xff; break;
2407 case SW
: rd
&= 0xffff; break;
2408 case SL
: rd
&= 0xffffffff; break;
2410 pc
= code
->next_pc
+ rd
;
2413 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2414 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2415 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2416 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2417 if (fetch (sd
, &code
->dst
, &rd
) ||
2418 fetch (sd
, &code
->src
, &bit
))
2421 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2422 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2424 if ((rd
& (1 << bit
))) /* no branch */
2427 else /* branch/call if set */
2429 if (!(rd
& (1 << bit
))) /* no branch */
2433 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2435 pc
= code
->next_pc
+ res
;
2437 if (code
->opcode
== O (O_BRABC
, SB
) ||
2438 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2446 case O (O_BRA
, SB
): /* bra, branch always */
2451 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2456 case O (O_BHI
, SB
): /* bhi */
2462 case O (O_BLS
, SB
): /* bls */
2467 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2472 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2477 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2481 case O (O_BGT
, SB
): /* bgt */
2482 if (((Z
|| (N
^ V
)) == 0))
2486 case O (O_BLE
, SB
): /* ble */
2487 if (((Z
|| (N
^ V
)) == 1))
2491 case O (O_BGE
, SB
): /* bge */
2495 case O (O_BLT
, SB
): /* blt */
2499 case O (O_BMI
, SB
): /* bmi */
2503 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2508 case O (O_BPL
, SB
): /* bpl */
2512 case O (O_BVC
, SB
): /* bvc */
2516 case O (O_BVS
, SB
): /* bvs */
2521 /* Trap for Command Line setup. */
2522 case O (O_SYS_CMDLINE
, SB
):
2524 int i
= 0; /* Loop counter. */
2525 int j
= 0; /* Loop counter. */
2526 int ind_arg_len
= 0; /* Length of each argument. */
2527 int no_of_args
= 0; /* The no. or cmdline args. */
2528 int current_location
= 0; /* Location of string. */
2529 int old_sp
= 0; /* The Initial Stack Pointer. */
2530 int no_of_slots
= 0; /* No. of slots required on the stack
2531 for storing cmdline args. */
2532 int sp_move
= 0; /* No. of locations by which the stack needs
2534 int new_sp
= 0; /* The final stack pointer location passed
2536 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2537 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2538 args on the stack. */
2539 int char_ptr_size
= 0; /* Size of a character pointer on
2541 int addr_cmdline
= 0; /* Memory location where cmdline has
2543 int size_cmdline
= 0; /* Size of cmdline. */
2545 /* Set the address of 256 free locations where command line is
2547 addr_cmdline
= cmdline_location();
2548 h8_set_reg (sd
, 0, addr_cmdline
);
2550 /* Counting the no. of commandline arguments. */
2551 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2554 /* No. of arguments in the command line. */
2557 /* Current location is just a temporary variable,which we are
2558 setting to the point to the start of our commandline string. */
2559 current_location
= addr_cmdline
;
2561 /* Allocating space for storing pointers of the command line
2563 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2565 /* Setting char_ptr_size to the sizeof (char *) on the different
2567 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2576 for (i
= 0; i
< no_of_args
; i
++)
2580 /* The size of the commandline argument. */
2581 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2583 /* The total size of the command line string. */
2584 size_cmdline
+= ind_arg_len
;
2586 /* As we have only 256 bytes, we need to provide a graceful
2587 exit. Anyways, a program using command line arguments
2588 where we cannot store all the command line arguments
2589 given may behave unpredictably. */
2590 if (size_cmdline
>= 256)
2592 h8_set_reg (sd
, 0, 0);
2597 /* current_location points to the memory where the next
2598 commandline argument is stored. */
2599 argv_ptrs
[i
] = current_location
;
2600 for (j
= 0; j
< ind_arg_len
; j
++)
2602 SET_MEMORY_B ((current_location
+
2603 (sizeof (char) * j
)),
2604 *(h8_get_cmdline_arg (sd
, i
) +
2605 sizeof (char) * j
));
2608 /* Setting current_location to the starting of next
2610 current_location
+= ind_arg_len
;
2614 /* This is the original position of the stack pointer. */
2615 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2617 /* We need space from the stack to store the pointers to argvs. */
2618 /* As we will infringe on the stack, we need to shift the stack
2619 pointer so that the data is not overwritten. We calculate how
2620 much space is required. */
2621 sp_move
= (no_of_args
) * (char_ptr_size
);
2623 /* The final position of stack pointer, we have thus taken some
2624 space from the stack. */
2625 new_sp
= old_sp
- sp_move
;
2627 /* Temporary variable holding value where the argv pointers need
2629 argv_ptrs_location
= new_sp
;
2631 /* The argv pointers are stored at sequential locations. As per
2633 for (i
= 0; i
< no_of_args
; i
++)
2635 /* Saving the argv pointer. */
2636 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2638 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2642 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2645 /* The next location where the pointer to the next argv
2646 string has to be stored. */
2647 argv_ptrs_location
+= char_ptr_size
;
2650 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2652 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2654 SET_MEMORY_L (old_sp
, 0x0);
2658 SET_MEMORY_W (old_sp
, 0x0);
2661 /* Freeing allocated memory. */
2663 for (i
= 0; i
<= no_of_args
; i
++)
2665 free (h8_get_cmdline_arg (sd
, i
));
2667 free (h8_get_command_line (sd
));
2669 /* The no. of argv arguments are returned in Reg 0. */
2670 h8_set_reg (sd
, 0, no_of_args
);
2671 /* The Pointer to argv in Register 1. */
2672 h8_set_reg (sd
, 1, new_sp
);
2673 /* Setting the stack pointer to the new value. */
2674 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2678 /* System call processing starts. */
2679 case O (O_SYS_OPEN
, SB
):
2681 int len
= 0; /* Length of filename. */
2682 char *filename
; /* Filename would go here. */
2683 char temp_char
; /* Temporary character */
2684 int mode
= 0; /* Mode bits for the file. */
2685 int open_return
; /* Return value of open, file descriptor. */
2686 int i
; /* Loop counter */
2687 int filename_ptr
; /* Pointer to filename in cpu memory. */
2689 /* Setting filename_ptr to first argument of open, */
2690 /* and trying to get mode. */
2691 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2693 filename_ptr
= GET_L_REG (0);
2694 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2698 filename_ptr
= GET_W_REG (0);
2699 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2702 /* Trying to find the length of the filename. */
2703 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2706 while (temp_char
!= '\0')
2708 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2712 /* Allocating space for the filename. */
2713 filename
= (char *) malloc (sizeof (char) * len
);
2715 /* String copying the filename from memory. */
2716 for (i
= 0; i
< len
; i
++)
2718 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2719 filename
[i
] = temp_char
;
2722 /* Callback to open and return the file descriptor. */
2723 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2725 /* Return value in register 0. */
2726 h8_set_reg (sd
, 0, open_return
);
2728 /* Freeing memory used for filename. */
2733 case O (O_SYS_READ
, SB
):
2735 char *char_ptr
; /* Where characters read would be stored. */
2736 int fd
; /* File descriptor */
2737 int buf_size
; /* BUF_SIZE parameter in read. */
2738 int i
= 0; /* Temporary Loop counter */
2739 int read_return
= 0; /* Return value from callback to
2742 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2743 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2745 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2747 /* Callback to read and return the no. of characters read. */
2749 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2751 /* The characters read are stored in cpu memory. */
2752 for (i
= 0; i
< buf_size
; i
++)
2754 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2755 *(char_ptr
+ (sizeof (char) * i
)));
2758 /* Return value in Register 0. */
2759 h8_set_reg (sd
, 0, read_return
);
2761 /* Freeing memory used as buffer. */
2766 case O (O_SYS_WRITE
, SB
):
2768 int fd
; /* File descriptor */
2769 char temp_char
; /* Temporary character */
2770 int len
; /* Length of write, Parameter II to write. */
2771 int char_ptr
; /* Character Pointer, Parameter I of write. */
2772 char *ptr
; /* Where characters to be written are stored.
2774 int write_return
; /* Return value from callback to write. */
2775 int i
= 0; /* Loop counter */
2777 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2778 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2779 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2781 /* Allocating space for the characters to be written. */
2782 ptr
= (char *) malloc (sizeof (char) * len
);
2784 /* Fetching the characters from cpu memory. */
2785 for (i
= 0; i
< len
; i
++)
2787 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2791 /* Callback write and return the no. of characters written. */
2792 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2794 /* Return value in Register 0. */
2795 h8_set_reg (sd
, 0, write_return
);
2797 /* Freeing memory used as buffer. */
2802 case O (O_SYS_LSEEK
, SB
):
2804 int fd
; /* File descriptor */
2805 int offset
; /* Offset */
2806 int origin
; /* Origin */
2807 int lseek_return
; /* Return value from callback to lseek. */
2809 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2810 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2811 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2813 /* Callback lseek and return offset. */
2815 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2817 /* Return value in register 0. */
2818 h8_set_reg (sd
, 0, lseek_return
);
2822 case O (O_SYS_CLOSE
, SB
):
2824 int fd
; /* File descriptor */
2825 int close_return
; /* Return value from callback to close. */
2827 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2829 /* Callback close and return. */
2830 close_return
= sim_callback
->close (sim_callback
, fd
);
2832 /* Return value in register 0. */
2833 h8_set_reg (sd
, 0, close_return
);
2837 case O (O_SYS_FSTAT
, SB
):
2839 int fd
; /* File descriptor */
2840 struct stat stat_rec
; /* Stat record */
2841 int fstat_return
; /* Return value from callback to stat. */
2842 int stat_ptr
; /* Pointer to stat record. */
2843 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2845 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2847 /* Setting stat_ptr to second argument of stat. */
2848 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2850 /* Callback stat and return. */
2851 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2854 /* Have stat_ptr point to starting of stat_rec. */
2855 temp_stat_ptr
= (char *) (&stat_rec
);
2857 /* Setting up the stat structure returned. */
2858 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2860 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2862 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2864 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2866 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2868 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2870 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2872 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2874 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2876 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2878 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2880 /* Return value in register 0. */
2881 h8_set_reg (sd
, 0, fstat_return
);
2885 case O (O_SYS_STAT
, SB
):
2887 int len
= 0; /* Length of filename. */
2888 char *filename
; /* Filename would go here. */
2889 char temp_char
; /* Temporary character */
2890 int filename_ptr
; /* Pointer to filename in cpu memory. */
2891 struct stat stat_rec
; /* Stat record */
2892 int stat_return
; /* Return value from callback to stat */
2893 int stat_ptr
; /* Pointer to stat record. */
2894 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2895 int i
= 0; /* Loop Counter */
2897 /* Setting filename_ptr to first argument of open. */
2898 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2900 /* Trying to find the length of the filename. */
2901 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2904 while (temp_char
!= '\0')
2906 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2910 /* Allocating space for the filename. */
2911 filename
= (char *) malloc (sizeof (char) * len
);
2913 /* String copying the filename from memory. */
2914 for (i
= 0; i
< len
; i
++)
2916 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2917 filename
[i
] = temp_char
;
2920 /* Setting stat_ptr to second argument of stat. */
2921 /* stat_ptr = h8_get_reg (sd, 1); */
2922 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2924 /* Callback stat and return. */
2926 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2928 /* Have stat_ptr point to starting of stat_rec. */
2929 temp_stat_ptr
= (char *) (&stat_rec
);
2931 /* Freeing memory used for filename. */
2934 /* Setting up the stat structure returned. */
2935 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2937 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2939 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2941 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2943 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2945 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2947 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2949 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2951 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2953 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2955 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2957 /* Return value in register 0. */
2958 h8_set_reg (sd
, 0, stat_return
);
2961 /* End of system call processing. */
2963 case O (O_NOT
, SB
): /* not.b */
2964 if (fetch2 (sd
, &code
->src
, &rd
))
2970 case O (O_NOT
, SW
): /* not.w */
2971 if (fetch2 (sd
, &code
->src
, &rd
))
2977 case O (O_NOT
, SL
): /* not.l */
2978 if (fetch2 (sd
, &code
->src
, &rd
))
2984 case O (O_SHLL
, SB
): /* shll.b */
2985 case O (O_SHLR
, SB
): /* shlr.b */
2986 if (fetch2 (sd
, &code
->dst
, &rd
))
2989 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2990 ea
= 1; /* unary op */
2991 else /* binary op */
2992 fetch (sd
, &code
->src
, &ea
);
2994 if (code
->opcode
== O (O_SHLL
, SB
))
2997 c
= rd
& (0x80 >> (ea
- 1));
3003 c
= rd
& (1 << (ea
- 1));
3004 rd
= (unsigned char) rd
>> ea
;
3008 case O (O_SHLL
, SW
): /* shll.w */
3009 case O (O_SHLR
, SW
): /* shlr.w */
3010 if (fetch2 (sd
, &code
->dst
, &rd
))
3013 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3014 ea
= 1; /* unary op */
3016 fetch (sd
, &code
->src
, &ea
);
3018 if (code
->opcode
== O (O_SHLL
, SW
))
3021 c
= rd
& (0x8000 >> (ea
- 1));
3027 c
= rd
& (1 << (ea
- 1));
3028 rd
= (unsigned short) rd
>> ea
;
3032 case O (O_SHLL
, SL
): /* shll.l */
3033 case O (O_SHLR
, SL
): /* shlr.l */
3034 if (fetch2 (sd
, &code
->dst
, &rd
))
3037 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3038 ea
= 1; /* unary op */
3040 fetch (sd
, &code
->src
, &ea
);
3042 if (code
->opcode
== O (O_SHLL
, SL
))
3045 c
= rd
& (0x80000000 >> (ea
- 1));
3051 c
= rd
& (1 << (ea
- 1));
3052 rd
= (unsigned int) rd
>> ea
;
3056 case O (O_SHAL
, SB
):
3057 case O (O_SHAR
, SB
):
3058 if (fetch2 (sd
, &code
->dst
, &rd
))
3061 if (code
->src
.type
== X (OP_IMM
, SB
))
3062 fetch (sd
, &code
->src
, &ea
);
3066 if (code
->opcode
== O (O_SHAL
, SB
))
3068 c
= rd
& (0x80 >> (ea
- 1));
3069 res
= rd
>> (7 - ea
);
3070 v
= ((res
& 1) && !(res
& 2))
3071 || (!(res
& 1) && (res
& 2));
3076 c
= rd
& (1 << (ea
- 1));
3078 rd
= ((signed char) rd
) >> ea
;
3082 case O (O_SHAL
, SW
):
3083 case O (O_SHAR
, SW
):
3084 if (fetch2 (sd
, &code
->dst
, &rd
))
3087 if (code
->src
.type
== X (OP_IMM
, SW
))
3088 fetch (sd
, &code
->src
, &ea
);
3092 if (code
->opcode
== O (O_SHAL
, SW
))
3094 c
= rd
& (0x8000 >> (ea
- 1));
3095 res
= rd
>> (15 - ea
);
3096 v
= ((res
& 1) && !(res
& 2))
3097 || (!(res
& 1) && (res
& 2));
3102 c
= rd
& (1 << (ea
- 1));
3104 rd
= ((signed short) rd
) >> ea
;
3108 case O (O_SHAL
, SL
):
3109 case O (O_SHAR
, SL
):
3110 if (fetch2 (sd
, &code
->dst
, &rd
))
3113 if (code
->src
.type
== X (OP_IMM
, SL
))
3114 fetch (sd
, &code
->src
, &ea
);
3118 if (code
->opcode
== O (O_SHAL
, SL
))
3120 c
= rd
& (0x80000000 >> (ea
- 1));
3121 res
= rd
>> (31 - ea
);
3122 v
= ((res
& 1) && !(res
& 2))
3123 || (!(res
& 1) && (res
& 2));
3128 c
= rd
& (1 << (ea
- 1));
3130 rd
= ((signed int) rd
) >> ea
;
3134 case O (O_ROTL
, SB
):
3135 case O (O_ROTR
, SB
):
3136 if (fetch2 (sd
, &code
->dst
, &rd
))
3139 if (code
->src
.type
== X (OP_IMM
, SB
))
3140 fetch (sd
, &code
->src
, &ea
);
3145 if (code
->opcode
== O (O_ROTL
, SB
))
3155 rd
= ((unsigned char) rd
) >> 1;
3163 case O (O_ROTL
, SW
):
3164 case O (O_ROTR
, SW
):
3165 if (fetch2 (sd
, &code
->dst
, &rd
))
3168 if (code
->src
.type
== X (OP_IMM
, SW
))
3169 fetch (sd
, &code
->src
, &ea
);
3174 if (code
->opcode
== O (O_ROTL
, SW
))
3184 rd
= ((unsigned short) rd
) >> 1;
3192 case O (O_ROTL
, SL
):
3193 case O (O_ROTR
, SL
):
3194 if (fetch2 (sd
, &code
->dst
, &rd
))
3197 if (code
->src
.type
== X (OP_IMM
, SL
))
3198 fetch (sd
, &code
->src
, &ea
);
3203 if (code
->opcode
== O (O_ROTL
, SL
))
3205 c
= rd
& 0x80000000;
3213 rd
= ((unsigned int) rd
) >> 1;
3221 case O (O_ROTXL
, SB
):
3222 case O (O_ROTXR
, SB
):
3223 if (fetch2 (sd
, &code
->dst
, &rd
))
3226 if (code
->src
.type
== X (OP_IMM
, SB
))
3227 fetch (sd
, &code
->src
, &ea
);
3232 if (code
->opcode
== O (O_ROTXL
, SB
))
3243 rd
= ((unsigned char) rd
) >> 1;
3252 case O (O_ROTXL
, SW
):
3253 case O (O_ROTXR
, SW
):
3254 if (fetch2 (sd
, &code
->dst
, &rd
))
3257 if (code
->src
.type
== X (OP_IMM
, SW
))
3258 fetch (sd
, &code
->src
, &ea
);
3263 if (code
->opcode
== O (O_ROTXL
, SW
))
3274 rd
= ((unsigned short) rd
) >> 1;
3283 case O (O_ROTXL
, SL
):
3284 case O (O_ROTXR
, SL
):
3285 if (fetch2 (sd
, &code
->dst
, &rd
))
3288 if (code
->src
.type
== X (OP_IMM
, SL
))
3289 fetch (sd
, &code
->src
, &ea
);
3294 if (code
->opcode
== O (O_ROTXL
, SL
))
3296 res
= rd
& 0x80000000;
3305 rd
= ((unsigned int) rd
) >> 1;
3316 case O (O_JMP
, SB
): /* jmp */
3318 fetch (sd
, &code
->src
, &pc
);
3323 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3325 if (fetch (sd
, &code
->src
, &pc
))
3328 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3330 if (h8300hmode
&& !h8300_normal_mode
)
3333 SET_MEMORY_L (tmp
, code
->next_pc
);
3338 SET_MEMORY_W (tmp
, code
->next_pc
);
3340 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3346 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3347 if (fetch (sd
, &code
->src
, &res
))
3349 pc
= code
->next_pc
+ res
;
3352 case O (O_RTE
, SN
): /* rte, return from exception */
3354 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3355 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3357 if (h8300smode
) /* pop exr */
3359 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3362 if (h8300hmode
&& !h8300_normal_mode
)
3364 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3366 pc
= GET_MEMORY_L (tmp
);
3371 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3373 pc
= GET_MEMORY_W (tmp
);
3378 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3381 case O (O_RTS
, SN
): /* rts, return from subroutine */
3383 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3385 if (h8300hmode
&& !h8300_normal_mode
)
3387 pc
= GET_MEMORY_L (tmp
);
3392 pc
= GET_MEMORY_W (tmp
);
3396 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3399 case O (O_ILL
, SB
): /* illegal */
3400 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3403 case O (O_SLEEP
, SN
): /* sleep */
3404 /* Check for magic numbers in r1 and r2. */
3405 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3406 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3407 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3409 /* This trap comes from _exit, not from gdb. */
3410 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3411 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3414 /* Unfortunately this won't really work, because
3415 when we take a breakpoint trap, R0 has a "random",
3416 user-defined value. Don't see any immediate solution. */
3417 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3419 /* Pass the stop signal up to gdb. */
3420 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3421 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3426 /* Treat it as a sigtrap. */
3427 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3431 case O (O_TRAPA
, SB
): /* trapa */
3432 if (fetch (sd
, &code
->src
, &res
))
3433 goto end
; /* res is vector number. */
3435 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3436 if(h8300_normal_mode
)
3439 SET_MEMORY_W (tmp
, code
->next_pc
);
3441 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3446 SET_MEMORY_L (tmp
, code
->next_pc
);
3448 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3456 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3459 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3461 if(h8300_normal_mode
)
3462 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3464 pc
= GET_MEMORY_L (0x20 + res
* 4);
3468 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3471 case O (O_BSETEQ
, SB
):
3476 case O (O_BSETNE
, SB
):
3481 case O (O_BCLREQ
, SB
):
3486 case O (O_BCLRNE
, SB
):
3491 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3492 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3494 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3496 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3497 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3498 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3499 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3500 if (C
) ea
|= m
); /* bst */
3501 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3502 if (!C
) ea
|= m
); /* bist */
3503 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3504 if (Z
) ea
|= m
); /* bstz */
3505 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3506 if (!Z
) ea
|= m
); /* bistz */
3507 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3508 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3509 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3510 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3511 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3512 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3514 case O (O_BFLD
, SB
): /* bfld */
3517 if (fetch (sd
, &code
->src
, &bit
))
3522 if (fetch (sd
, &code
->dst
, &ea
))
3532 if (store (sd
, &code
->op3
, ea
))
3537 case O(O_BFST
, SB
): /* bfst */
3538 /* bitfield store */
3539 /* NOTE: the imm8 value is in dst, and the ea value
3540 (which is actually the destination) is in op3.
3541 It has to be that way, to avoid breaking the assembler. */
3543 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3545 if (bit
== 0) /* noop -- nothing to do. */
3548 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3551 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3554 /* Left-shift the register data into position. */
3555 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3558 /* Combine it with the neighboring bits. */
3559 ea
= (ea
& ~bit
) | (rd
& bit
);
3562 if (store2 (sd
, &code
->op3
, ea
))
3566 case O (O_CLRMAC
, SN
): /* clrmac */
3567 h8_set_mach (sd
, 0);
3568 h8_set_macl (sd
, 0);
3569 h8_set_macZ (sd
, 1);
3570 h8_set_macV (sd
, 0);
3571 h8_set_macN (sd
, 0);
3574 case O (O_STMAC
, SL
): /* stmac, 260 */
3575 switch (code
->src
.type
) {
3576 case X (OP_MACH
, SL
):
3577 res
= h8_get_mach (sd
);
3578 if (res
& 0x200) /* sign extend */
3581 case X (OP_MACL
, SL
):
3582 res
= h8_get_macl (sd
);
3584 default: goto illegal
;
3586 nz
= !h8_get_macZ (sd
);
3587 n
= h8_get_macN (sd
);
3588 v
= h8_get_macV (sd
);
3590 if (store (sd
, &code
->dst
, res
))
3595 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3596 if (fetch (sd
, &code
->src
, &rd
))
3599 switch (code
->dst
.type
) {
3600 case X (OP_MACH
, SL
):
3601 rd
&= 0x3ff; /* Truncate to 10 bits */
3602 h8_set_mach (sd
, rd
);
3604 case X (OP_MACL
, SL
):
3605 h8_set_macl (sd
, rd
);
3607 default: goto illegal
;
3609 h8_set_macV (sd
, 0);
3613 if (fetch (sd
, &code
->src
, &rd
) ||
3614 fetch (sd
, &code
->dst
, &res
))
3617 /* Ye gods, this is non-portable!
3618 However, the existing mul/div code is similar. */
3619 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3621 if (h8_get_macS (sd
)) /* Saturating mode */
3623 long long mac
= h8_get_macl (sd
);
3625 if (mac
& 0x80000000) /* sign extend */
3626 mac
|= 0xffffffff00000000LL
;
3629 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3630 h8_set_macV (sd
, 1);
3631 h8_set_macZ (sd
, (mac
== 0));
3632 h8_set_macN (sd
, (mac
< 0));
3633 h8_set_macl (sd
, (int) mac
);
3635 else /* "Less Saturating" mode */
3637 long long mac
= h8_get_mach (sd
);
3639 mac
+= h8_get_macl (sd
);
3641 if (mac
& 0x20000000000LL
) /* sign extend */
3642 mac
|= 0xfffffc0000000000LL
;
3645 if (mac
> 0x1ffffffffffLL
||
3646 mac
< (long long) 0xfffffe0000000000LL
)
3647 h8_set_macV (sd
, 1);
3648 h8_set_macZ (sd
, (mac
== 0));
3649 h8_set_macN (sd
, (mac
< 0));
3650 h8_set_macl (sd
, (int) mac
);
3652 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3656 case O (O_MULS
, SW
): /* muls.w */
3657 if (fetch (sd
, &code
->src
, &ea
) ||
3658 fetch (sd
, &code
->dst
, &rd
))
3661 ea
= SEXTSHORT (ea
);
3662 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3666 if (store (sd
, &code
->dst
, res
))
3671 case O (O_MULS
, SL
): /* muls.l */
3672 if (fetch (sd
, &code
->src
, &ea
) ||
3673 fetch (sd
, &code
->dst
, &rd
))
3678 n
= res
& 0x80000000;
3679 nz
= res
& 0xffffffff;
3680 if (store (sd
, &code
->dst
, res
))
3684 case O (O_MULSU
, SL
): /* muls/u.l */
3685 if (fetch (sd
, &code
->src
, &ea
) ||
3686 fetch (sd
, &code
->dst
, &rd
))
3689 /* Compute upper 32 bits of the 64-bit result. */
3690 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3692 n
= res
& 0x80000000;
3693 nz
= res
& 0xffffffff;
3694 if (store (sd
, &code
->dst
, res
))
3698 case O (O_MULU
, SW
): /* mulu.w */
3699 if (fetch (sd
, &code
->src
, &ea
) ||
3700 fetch (sd
, &code
->dst
, &rd
))
3703 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3705 /* Don't set Z or N. */
3706 if (store (sd
, &code
->dst
, res
))
3711 case O (O_MULU
, SL
): /* mulu.l */
3712 if (fetch (sd
, &code
->src
, &ea
) ||
3713 fetch (sd
, &code
->dst
, &rd
))
3718 /* Don't set Z or N. */
3719 if (store (sd
, &code
->dst
, res
))
3724 case O (O_MULUU
, SL
): /* mulu/u.l */
3725 if (fetch (sd
, &code
->src
, &ea
) ||
3726 fetch (sd
, &code
->dst
, &rd
))
3729 /* Compute upper 32 bits of the 64-bit result. */
3730 res
= (((unsigned long long) (unsigned) ea
) *
3731 ((unsigned long long) (unsigned) rd
)) >> 32;
3733 /* Don't set Z or N. */
3734 if (store (sd
, &code
->dst
, res
))
3739 case O (O_MULXS
, SB
): /* mulxs.b */
3740 if (fetch (sd
, &code
->src
, &ea
) ||
3741 fetch (sd
, &code
->dst
, &rd
))
3745 res
= ea
* SEXTCHAR (rd
);
3749 if (store (sd
, &code
->dst
, res
))
3754 case O (O_MULXS
, SW
): /* mulxs.w */
3755 if (fetch (sd
, &code
->src
, &ea
) ||
3756 fetch (sd
, &code
->dst
, &rd
))
3759 ea
= SEXTSHORT (ea
);
3760 res
= ea
* SEXTSHORT (rd
& 0xffff);
3762 n
= res
& 0x80000000;
3763 nz
= res
& 0xffffffff;
3764 if (store (sd
, &code
->dst
, res
))
3769 case O (O_MULXU
, SB
): /* mulxu.b */
3770 if (fetch (sd
, &code
->src
, &ea
) ||
3771 fetch (sd
, &code
->dst
, &rd
))
3774 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3776 if (store (sd
, &code
->dst
, res
))
3781 case O (O_MULXU
, SW
): /* mulxu.w */
3782 if (fetch (sd
, &code
->src
, &ea
) ||
3783 fetch (sd
, &code
->dst
, &rd
))
3786 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3788 if (store (sd
, &code
->dst
, res
))
3793 case O (O_TAS
, SB
): /* tas (test and set) */
3794 if (!h8300sxmode
) /* h8sx can use any register. */
3795 switch (code
->src
.reg
)
3806 if (fetch (sd
, &code
->src
, &res
))
3808 if (store (sd
, &code
->src
, res
| 0x80))
3811 goto just_flags_log8
;
3813 case O (O_DIVU
, SW
): /* divu.w */
3814 if (fetch (sd
, &code
->src
, &ea
) ||
3815 fetch (sd
, &code
->dst
, &rd
))
3821 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3825 if (store (sd
, &code
->dst
, res
))
3829 case O (O_DIVU
, SL
): /* divu.l */
3830 if (fetch (sd
, &code
->src
, &ea
) ||
3831 fetch (sd
, &code
->dst
, &rd
))
3834 n
= ea
& 0x80000000;
3835 nz
= ea
& 0xffffffff;
3837 res
= (unsigned) rd
/ ea
;
3841 if (store (sd
, &code
->dst
, res
))
3845 case O (O_DIVS
, SW
): /* divs.w */
3846 if (fetch (sd
, &code
->src
, &ea
) ||
3847 fetch (sd
, &code
->dst
, &rd
))
3852 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3862 if (store (sd
, &code
->dst
, res
))
3866 case O (O_DIVS
, SL
): /* divs.l */
3867 if (fetch (sd
, &code
->src
, &ea
) ||
3868 fetch (sd
, &code
->dst
, &rd
))
3882 n
= res
& 0x80000000;
3883 if (store (sd
, &code
->dst
, res
))
3887 case O (O_DIVXU
, SB
): /* divxu.b */
3888 if (fetch (sd
, &code
->src
, &ea
) ||
3889 fetch (sd
, &code
->dst
, &rd
))
3892 rd
= UEXTSHORT (rd
);
3899 tmp
= (unsigned) rd
% ea
;
3900 res
= (unsigned) rd
/ ea
;
3908 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3912 case O (O_DIVXU
, SW
): /* divxu.w */
3913 if (fetch (sd
, &code
->src
, &ea
) ||
3914 fetch (sd
, &code
->dst
, &rd
))
3917 ea
= UEXTSHORT (ea
);
3923 tmp
= (unsigned) rd
% ea
;
3924 res
= (unsigned) rd
/ ea
;
3932 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3936 case O (O_DIVXS
, SB
): /* divxs.b */
3937 if (fetch (sd
, &code
->src
, &ea
) ||
3938 fetch (sd
, &code
->dst
, &rd
))
3941 rd
= SEXTSHORT (rd
);
3946 tmp
= (int) rd
% (int) ea
;
3947 res
= (int) rd
/ (int) ea
;
3958 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3962 case O (O_DIVXS
, SW
): /* divxs.w */
3963 if (fetch (sd
, &code
->src
, &ea
) ||
3964 fetch (sd
, &code
->dst
, &rd
))
3967 ea
= SEXTSHORT (ea
);
3971 tmp
= (int) rd
% (int) ea
;
3972 res
= (int) rd
/ (int) ea
;
3982 n
= res
& 0x80000000;
3983 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3987 case O (O_EXTS
, SW
): /* exts.w, signed extend */
3988 if (fetch2 (sd
, &code
->dst
, &rd
))
3990 ea
= rd
& 0x80 ? -256 : 0;
3991 res
= (rd
& 0xff) + ea
;
3994 case O (O_EXTS
, SL
): /* exts.l, signed extend */
3995 if (fetch2 (sd
, &code
->dst
, &rd
))
3997 if (code
->src
.type
== X (OP_IMM
, SL
))
3999 if (fetch (sd
, &code
->src
, &ea
))
4002 if (ea
== 2) /* exts.l #2, nn */
4004 /* Sign-extend from 8-bit to 32-bit. */
4005 ea
= rd
& 0x80 ? -256 : 0;
4006 res
= (rd
& 0xff) + ea
;
4010 /* Sign-extend from 16-bit to 32-bit. */
4011 ea
= rd
& 0x8000 ? -65536 : 0;
4012 res
= (rd
& 0xffff) + ea
;
4015 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4016 if (fetch2 (sd
, &code
->dst
, &rd
))
4019 res
= (rd
& 0xff) + ea
;
4022 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4023 if (fetch2 (sd
, &code
->dst
, &rd
))
4025 if (code
->src
.type
== X (OP_IMM
, SL
))
4027 if (fetch (sd
, &code
->src
, &ea
))
4030 if (ea
== 2) /* extu.l #2, nn */
4032 /* Zero-extend from 8-bit to 32-bit. */
4034 res
= (rd
& 0xff) + ea
;
4038 /* Zero-extend from 16-bit to 32-bit. */
4040 res
= (rd
& 0xffff) + ea
;
4043 case O (O_NOP
, SN
): /* nop */
4046 case O (O_STM
, SL
): /* stm, store to memory */
4048 int nregs
, firstreg
, i
;
4050 nregs
= GET_MEMORY_B (pc
+ 1);
4053 firstreg
= code
->src
.reg
;
4055 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4057 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4058 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4063 case O (O_LDM
, SL
): /* ldm, load from memory */
4064 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4065 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4067 int nregs
, firstreg
, i
;
4069 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4070 firstreg
= code
->dst
.reg
& 0xf;
4071 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4073 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4074 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4077 switch (code
->opcode
) {
4078 case O (O_RTEL
, SN
):
4080 case O (O_RTSL
, SN
):
4089 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4090 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4091 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4092 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4093 res
= res
; /* Value added == 0. */
4094 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4095 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4096 res
= res
+ 0x6; /* Value added == 6. */
4097 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4098 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4099 res
= res
+ 0x6; /* Value added == 6. */
4100 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4101 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4102 res
= res
+ 0x60; /* Value added == 60. */
4103 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4104 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4105 res
= res
+ 0x66; /* Value added == 66. */
4106 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4107 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4108 res
= res
+ 0x66; /* Value added == 66. */
4109 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4110 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4111 res
= res
+ 0x60; /* Value added == 60. */
4112 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4113 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4114 res
= res
+ 0x66; /* Value added == 66. */
4115 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4116 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4117 res
= res
+ 0x66; /* Value added == 66. */
4122 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4123 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4124 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4125 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4126 res
= res
; /* Value added == 0. */
4127 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4128 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4129 res
= res
+ 0xfa; /* Value added == 0xfa. */
4130 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4131 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4132 res
= res
+ 0xa0; /* Value added == 0xa0. */
4133 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4134 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4135 res
= res
+ 0x9a; /* Value added == 0x9a. */
4141 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4146 sim_io_printf (sd
, "sim_resume: internal error.\n");
4147 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4151 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4152 code
->dst
.type
== X (OP_CCR
, SW
))
4154 h8_set_ccr (sd
, res
);
4157 else if (h8300smode
&&
4158 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4159 code
->dst
.type
== X (OP_EXR
, SW
)))
4161 h8_set_exr (sd
, res
);
4162 if (h8300smode
) /* Get exr. */
4164 trace
= (h8_get_exr (sd
) >> 7) & 1;
4165 intMask
= h8_get_exr (sd
) & 7;
4174 /* When a branch works */
4175 if (fetch (sd
, &code
->src
, &res
))
4177 if (res
& 1) /* bad address */
4179 pc
= code
->next_pc
+ res
;
4182 /* Set the cond codes from res */
4185 /* Set the flags after an 8 bit inc/dec operation */
4189 v
= (rd
& 0x7f) == 0x7f;
4192 /* Set the flags after an 16 bit inc/dec operation */
4196 v
= (rd
& 0x7fff) == 0x7fff;
4199 /* Set the flags after an 32 bit inc/dec operation */
4201 n
= res
& 0x80000000;
4202 nz
= res
& 0xffffffff;
4203 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4207 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4210 if (store2 (sd
, &code
->dst
, rd
))
4215 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4218 if (store2 (sd
, &code
->dst
, rd
))
4223 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4224 n
= (rd
& 0x80000000);
4225 nz
= rd
& 0xffffffff;
4226 if (store2 (sd
, &code
->dst
, rd
))
4231 if (store2 (sd
, &code
->dst
, res
))
4235 /* flags after a 32bit logical operation */
4236 n
= res
& 0x80000000;
4237 nz
= res
& 0xffffffff;
4242 if (store2 (sd
, &code
->dst
, res
))
4246 /* flags after a 16bit logical operation */
4253 if (store2 (sd
, &code
->dst
, res
))
4263 if (store2 (sd
, &code
->dst
, res
))
4270 switch (code
->opcode
/ 4)
4274 v
= ((rd
& 0x80) == (ea
& 0x80)
4275 && (rd
& 0x80) != (res
& 0x80));
4280 v
= ((rd
& 0x80) != (-ea
& 0x80)
4281 && (rd
& 0x80) != (res
& 0x80));
4288 break; /* No effect on v flag. */
4293 if (store2 (sd
, &code
->dst
, res
))
4299 c
= (res
& 0x10000);
4300 switch (code
->opcode
/ 4)
4304 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4305 && (rd
& 0x8000) != (res
& 0x8000));
4310 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4311 && (rd
& 0x8000) != (res
& 0x8000));
4320 if (store2 (sd
, &code
->dst
, res
))
4324 n
= res
& 0x80000000;
4325 nz
= res
& 0xffffffff;
4326 switch (code
->opcode
/ 4)
4330 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4331 && (rd
& 0x80000000) != (res
& 0x80000000));
4332 c
= ((unsigned) res
< (unsigned) rd
) ||
4333 ((unsigned) res
< (unsigned) ea
);
4338 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4339 && (rd
& 0x80000000) != (res
& 0x80000000));
4340 c
= (unsigned) rd
< (unsigned) -ea
;
4343 v
= (rd
== 0x80000000);
4350 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4353 h8_set_delayed_branch (sd
, 0);
4361 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4362 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4363 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4368 h8_set_exr (sd
, (trace
<<7) | intMask
);
4370 h8_set_mask (sd
, oldmask
);
4374 sim_engine_run (SIM_DESC sd
,
4375 int next_cpu_nr
, /* ignore */
4376 int nr_cpus
, /* ignore */
4381 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4383 cpu
= STATE_CPU (sd
, 0);
4387 step_once (sd
, cpu
);
4388 if (sim_events_tick (sd
))
4389 sim_events_process (sd
);
4394 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4401 for (i
= 0; i
< size
; i
++)
4403 if (addr
< memory_size
)
4405 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4414 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4419 if (addr
+ size
< memory_size
)
4420 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4427 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4432 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4433 shortval
= (value
[0] << 8) | (value
[1]);
4434 intval
= h8300hmode
? longval
: shortval
;
4436 init_pointers (CPU_STATE (cpu
));
4440 if(h8300_normal_mode
)
4441 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4461 cpu
->regs
[rn
] = intval
;
4466 cpu
->regs
[rn
] = longval
;
4473 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4478 init_pointers (CPU_STATE (cpu
));
4480 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4515 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4516 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4533 sim_info (SIM_DESC sd
, int verbose
)
4535 const struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4536 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4537 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4539 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4540 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4541 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4542 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4543 if (timetaken
!= 0.0)
4544 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4547 /* This to be conditional on `what' (aka `verbose'),
4548 however it was never passed as non-zero. */
4552 for (i
= 0; i
< O_LAST
; i
++)
4554 if (h8_get_stats (sd
, i
))
4555 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4561 /* Indicate whether the cpu is an H8/300 or H8/300H.
4562 FLAG is non-zero for the H8/300H. */
4565 set_h8300h (unsigned long machine
)
4567 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4568 This function being replaced by a sim_open:ARGV configuration
4571 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4573 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4576 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4579 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4582 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4583 h8300_normal_mode
= 1;
4586 /* H8300-specific options.
4587 TODO: These really should be merged into the common model modules. */
4595 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4596 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4598 switch ((H8300_OPTIONS
) opt
)
4601 set_h8300h (bfd_mach_h8300h
);
4604 set_h8300h (bfd_mach_h8300s
);
4606 case OPTION_H8300SX
:
4607 set_h8300h (bfd_mach_h8300sx
);
4611 /* We'll actually never get here; the caller handles the error
4613 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4620 static const OPTION h8300_options
[] =
4622 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4623 'h', NULL
, "Indicate the CPU is H8/300H",
4624 h8300_option_handler
},
4625 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4626 'S', NULL
, "Indicate the CPU is H8S",
4627 h8300_option_handler
},
4628 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4629 'x', NULL
, "Indicate the CPU is H8SX",
4630 h8300_option_handler
},
4631 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4635 h8300_pc_get (sim_cpu
*cpu
)
4641 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4646 /* Cover function of sim_state_free to free the cpu buffers as well. */
4649 free_state (SIM_DESC sd
)
4651 if (STATE_MODULES (sd
) != NULL
)
4652 sim_module_uninstall (sd
);
4654 /* Fixme: free buffers in _sim_cpu. */
4655 sim_state_free (sd
);
4659 sim_open (SIM_OPEN_KIND kind
,
4660 struct host_callback_struct
*callback
,
4668 sd
= sim_state_alloc_extra (kind
, callback
, sizeof (struct h8300_sim_state
));
4670 /* The cpu data is kept in a separately allocated chunk of memory. */
4671 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4677 cpu
= STATE_CPU (sd
, 0);
4678 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4679 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4680 /* sim_cpu object is new, so some initialization is needed. */
4681 init_pointers_needed
= 1;
4683 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4689 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4695 /* The parser will print an error message for us, so we silently return. */
4696 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4698 /* Uninstall the modules to avoid memory leaks,
4699 file descriptor leaks, etc. */
4704 /* Check for/establish the a reference program image. */
4705 if (sim_analyze_program (sd
,
4706 (STATE_PROG_ARGV (sd
) != NULL
4707 ? *STATE_PROG_ARGV (sd
)
4708 : NULL
), abfd
) != SIM_RC_OK
)
4714 /* Establish any remaining configuration options. */
4715 if (sim_config (sd
) != SIM_RC_OK
)
4721 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4723 /* Uninstall the modules to avoid memory leaks,
4724 file descriptor leaks, etc. */
4729 /* CPU specific initialization. */
4730 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4732 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4734 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4735 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4736 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4737 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4740 /* sim_hw_configure (sd); */
4742 /* FIXME: Much of the code in sim_load can be moved here. */
4747 /* Called by gdb to load a program into memory. */
4750 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4752 struct h8300_sim_state
*state
= H8300_SIM_STATE (sd
);
4755 /* FIXME: The code below that sets a specific variant of the H8/300
4756 being simulated should be moved to sim_open(). */
4758 /* See if the file is for the H8/300 or H8/300H. */
4759 /* ??? This may not be the most efficient way. The z8k simulator
4760 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4764 prog_bfd
= bfd_openr (prog
, NULL
);
4765 if (prog_bfd
!= NULL
)
4767 /* Set the cpu type. We ignore failure from bfd_check_format
4768 and bfd_openr as sim_load_file checks too. */
4769 if (bfd_check_format (prog_bfd
, bfd_object
))
4771 set_h8300h (bfd_get_mach (prog_bfd
));
4775 /* If we're using gdb attached to the simulator, then we have to
4776 reallocate memory for the simulator.
4778 When gdb first starts, it calls fetch_registers (among other
4779 functions), which in turn calls init_pointers, which allocates
4782 The problem is when we do that, we don't know whether we're
4783 debugging an H8/300 or H8/300H program.
4785 This is the first point at which we can make that determination,
4786 so we just reallocate memory now; this will also allow us to handle
4787 switching between H8/300 and H8/300H programs without exiting
4790 if (h8300smode
&& !h8300_normal_mode
)
4791 memory_size
= H8300S_MSIZE
;
4792 else if (h8300hmode
&& !h8300_normal_mode
)
4793 memory_size
= H8300H_MSIZE
;
4795 memory_size
= H8300_MSIZE
;
4797 if (h8_get_memory_buf (sd
))
4798 free (h8_get_memory_buf (sd
));
4800 h8_set_memory_buf (sd
, (unsigned char *)
4801 calloc (sizeof (char), memory_size
));
4802 state
->memory_size
= memory_size
;
4804 /* `msize' must be a power of two. */
4805 if ((memory_size
& (memory_size
- 1)) != 0)
4807 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4810 h8_set_mask (sd
, memory_size
- 1);
4812 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4813 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4817 /* Close the bfd if we opened it. */
4818 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4819 bfd_close (prog_bfd
);
4823 /* Close the bfd if we opened it. */
4824 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4825 bfd_close (prog_bfd
);
4830 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4831 char * const *argv
, char * const *env
)
4838 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4842 /* Command Line support. */
4845 /* Counting the no. of commandline arguments. */
4846 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4849 /* Allocating memory for the argv pointers. */
4850 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4851 * (no_of_args
+ 1)));
4853 for (i
= 0; i
< no_of_args
; i
++)
4855 /* Copying the argument string. */
4856 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4858 h8_set_cmdline_arg (sd
, i
, NULL
);