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[binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Hitachi H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21
22 #include <stdio.h>
23 #include <signal.h>
24 #ifdef HAVE_TIME_H
25 #include <time.h>
26 #endif
27 #ifdef HAVE_STDLIB_H
28 #include <stdlib.h>
29 #endif
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
32 #endif
33 #include "ansidecl.h"
34 #include "bfd.h"
35 #include "gdb/callback.h"
36 #include "gdb/remote-sim.h"
37 #include "gdb/sim-h8300.h"
38
39 #ifndef SIGTRAP
40 # define SIGTRAP 5
41 #endif
42
43 int debug;
44
45 host_callback *sim_callback;
46
47 static SIM_OPEN_KIND sim_kind;
48 static char *myname;
49
50 /* FIXME: Needs to live in header file.
51 This header should also include the things in remote-sim.h.
52 One could move this to remote-sim.h but this function isn't needed
53 by gdb. */
54 void sim_set_simcache_size PARAMS ((int));
55
56 #define X(op, size) op * 4 + size
57
58 #define SP (h8300hmode ? SL : SW)
59 #define SB 0
60 #define SW 1
61 #define SL 2
62 #define OP_REG 1
63 #define OP_DEC 2
64 #define OP_DISP 3
65 #define OP_INC 4
66 #define OP_PCREL 5
67 #define OP_MEM 6
68 #define OP_CCR 7
69 #define OP_IMM 8
70 #define OP_ABS 10
71 #define OP_EXR 11
72 #define h8_opcodes ops
73 #define DEFINE_TABLE
74 #include "opcode/h8300.h"
75
76 #include "inst.h"
77
78 /* The rate at which to call the host's poll_quit callback. */
79
80 #define POLL_QUIT_INTERVAL 0x80000
81
82 #define LOW_BYTE(x) ((x) & 0xff)
83 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
84 #define P(X,Y) ((X << 8) | Y)
85
86 #define BUILDSR() \
87 cpu.ccr = ((I << 7) | (UI << 6) | (H << 5) | (U << 4) \
88 | (N << 3) | (Z << 2) | (V << 1) | C);
89
90 #define BUILDEXR() \
91 if (h8300smode) cpu.exr = (trace<<7) | intMask;
92
93 #define GETSR() \
94 c = (cpu.ccr >> 0) & 1;\
95 v = (cpu.ccr >> 1) & 1;\
96 nz = !((cpu.ccr >> 2) & 1);\
97 n = (cpu.ccr >> 3) & 1;\
98 u = (cpu.ccr >> 4) & 1;\
99 h = (cpu.ccr >> 5) & 1;\
100 ui = ((cpu.ccr >> 6) & 1);\
101 intMaskBit = (cpu.ccr >> 7) & 1;
102
103 #define GETEXR() \
104 if (h8300smode) \
105 { \
106 trace = (cpu.exr >> 7) & 1; \
107 intMask = cpu.exr & 7; \
108 }
109
110 #ifdef __CHAR_IS_SIGNED__
111 #define SEXTCHAR(x) ((char) (x))
112 #endif
113
114 #ifndef SEXTCHAR
115 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
116 #endif
117
118 #define UEXTCHAR(x) ((x) & 0xff)
119 #define UEXTSHORT(x) ((x) & 0xffff)
120 #define SEXTSHORT(x) ((short) (x))
121
122 static cpu_state_type cpu;
123
124 int h8300hmode = 0;
125 int h8300smode = 0;
126
127 static int memory_size;
128
129 static int
130 get_now (void)
131 {
132 return time (0); /* WinXX HAS UNIX like 'time', so why not using it? */
133 }
134
135 static int
136 now_persec (void)
137 {
138 return 1;
139 }
140
141 static int
142 bitfrom (int x)
143 {
144 switch (x & SIZE)
145 {
146 case L_8:
147 return SB;
148 case L_16:
149 return SW;
150 case L_32:
151 return SL;
152 case L_P:
153 return h8300hmode ? SL : SW;
154 }
155 }
156
157 static unsigned int
158 lvalue (int x, int rn)
159 {
160 switch (x / 4)
161 {
162 case OP_DISP:
163 if (rn == 8)
164 {
165 return X (OP_IMM, SP);
166 }
167 return X (OP_REG, SP);
168
169 case OP_MEM:
170 return X (OP_MEM, SP);
171
172 default:
173 abort (); /* ?? May be something more usefull? */
174 }
175 }
176
177 static unsigned int
178 decode (int addr, unsigned char *data, decoded_inst *dst)
179 {
180 int rs = 0;
181 int rd = 0;
182 int rdisp = 0;
183 int abs = 0;
184 int bit = 0;
185 int plen = 0;
186 struct h8_opcode *q;
187 int size = 0;
188
189 dst->dst.type = -1;
190 dst->src.type = -1;
191
192 /* Find the exact opcode/arg combo. */
193 for (q = h8_opcodes; q->name; q++)
194 {
195 op_type *nib = q->data.nib;
196 unsigned int len = 0;
197
198 while (1)
199 {
200 op_type looking_for = *nib;
201 int thisnib = data[len >> 1];
202
203 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
204
205 if (looking_for < 16 && looking_for >= 0)
206 {
207 if (looking_for != thisnib)
208 goto fail;
209 }
210 else
211 {
212 if ((int) looking_for & (int) B31)
213 {
214 if (!(((int) thisnib & 0x8) != 0))
215 goto fail;
216
217 looking_for = (op_type) ((int) looking_for & ~(int) B31);
218 thisnib &= 0x7;
219 }
220
221 if ((int) looking_for & (int) B30)
222 {
223 if (!(((int) thisnib & 0x8) == 0))
224 goto fail;
225
226 looking_for = (op_type) ((int) looking_for & ~(int) B30);
227 }
228
229 if (looking_for & DBIT)
230 {
231 /* Exclude adds/subs by looking at bit 0 and 2, and
232 make sure the operand size, either w or l,
233 matches by looking at bit 1. */
234 if ((looking_for & 7) != (thisnib & 7))
235 goto fail;
236
237 abs = (thisnib & 0x8) ? 2 : 1;
238 }
239 else if (looking_for & (REG | IND | INC | DEC))
240 {
241 if (looking_for & REG)
242 {
243 /* Can work out size from the register. */
244 size = bitfrom (looking_for);
245 }
246 if (looking_for & SRC)
247 rs = thisnib;
248 else
249 rd = thisnib;
250 }
251 else if (looking_for & L_16)
252 {
253 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
254 plen = 16;
255 if (looking_for & (PCREL | DISP))
256 {
257 abs = (short) (abs);
258 }
259 }
260 else if (looking_for & ABSJMP)
261 {
262 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
263 }
264 else if (looking_for & MEMIND)
265 {
266 abs = data[1];
267 }
268 else if (looking_for & L_32)
269 {
270 int i = len >> 1;
271
272 abs = (data[i] << 24)
273 | (data[i + 1] << 16)
274 | (data[i + 2] << 8)
275 | (data[i + 3]);
276
277 plen = 32;
278 }
279 else if (looking_for & L_24)
280 {
281 int i = len >> 1;
282
283 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
284 plen = 24;
285 }
286 else if (looking_for & IGNORE)
287 {
288 ;
289 }
290 else if (looking_for & DISPREG)
291 {
292 rdisp = thisnib & 0x7;
293 }
294 else if (looking_for & KBIT)
295 {
296 switch (thisnib)
297 {
298 case 9:
299 abs = 4;
300 break;
301 case 8:
302 abs = 2;
303 break;
304 case 0:
305 abs = 1;
306 break;
307 default:
308 goto fail;
309 }
310 }
311 else if (looking_for & L_8)
312 {
313 plen = 8;
314
315 if (looking_for & PCREL)
316 {
317 abs = SEXTCHAR (data[len >> 1]);
318 }
319 else if (looking_for & ABS8MEM)
320 {
321 plen = 8;
322 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
323 abs |= data[len >> 1] & 0xff;
324 }
325 else
326 {
327 abs = data[len >> 1] & 0xff;
328 }
329 }
330 else if (looking_for & L_3)
331 {
332 plen = 3;
333
334 bit = thisnib;
335 }
336 else if (looking_for == E)
337 {
338 dst->op = q;
339
340 /* Fill in the args. */
341 {
342 op_type *args = q->args.nib;
343 int hadone = 0;
344
345 while (*args != E)
346 {
347 int x = *args;
348 int rn = (x & DST) ? rd : rs;
349 ea_type *p;
350
351 if (x & DST)
352 p = &(dst->dst);
353 else
354 p = &(dst->src);
355
356 if (x & L_3)
357 {
358 p->type = X (OP_IMM, size);
359 p->literal = bit;
360 }
361 else if (x & (IMM | KBIT | DBIT))
362 {
363 p->type = X (OP_IMM, size);
364 p->literal = abs;
365 }
366 else if (x & REG)
367 {
368 /* Reset the size.
369 Some ops (like mul) have two sizes. */
370
371 size = bitfrom (x);
372 p->type = X (OP_REG, size);
373 p->reg = rn;
374 }
375 else if (x & INC)
376 {
377 p->type = X (OP_INC, size);
378 p->reg = rn & 0x7;
379 }
380 else if (x & DEC)
381 {
382 p->type = X (OP_DEC, size);
383 p->reg = rn & 0x7;
384 }
385 else if (x & IND)
386 {
387 p->type = X (OP_DISP, size);
388 p->reg = rn & 0x7;
389 p->literal = 0;
390 }
391 else if (x & (ABS | ABSJMP | ABS8MEM))
392 {
393 p->type = X (OP_DISP, size);
394 p->literal = abs;
395 p->reg = 8;
396 }
397 else if (x & MEMIND)
398 {
399 p->type = X (OP_MEM, size);
400 p->literal = abs;
401 }
402 else if (x & PCREL)
403 {
404 p->type = X (OP_PCREL, size);
405 p->literal = abs + addr + 2;
406 if (x & L_16)
407 p->literal += 2;
408 }
409 else if (x & ABSJMP)
410 {
411 p->type = X (OP_IMM, SP);
412 p->literal = abs;
413 }
414 else if (x & DISP)
415 {
416 p->type = X (OP_DISP, size);
417 p->literal = abs;
418 p->reg = rdisp & 0x7;
419 }
420 else if (x & CCR)
421 {
422 p->type = OP_CCR;
423 }
424 else if (x & EXR)
425 {
426 p->type = OP_EXR;
427 }
428 else
429 printf ("Hmmmm %x", x);
430
431 args++;
432 }
433 }
434
435 /* But a jmp or a jsr gets automagically lvalued,
436 since we branch to their address not their
437 contents. */
438 if (q->how == O (O_JSR, SB)
439 || q->how == O (O_JMP, SB))
440 {
441 dst->src.type = lvalue (dst->src.type, dst->src.reg);
442 }
443
444 if (dst->dst.type == -1)
445 dst->dst = dst->src;
446
447 dst->opcode = q->how;
448 dst->cycles = q->time;
449
450 /* And a jsr to 0xc4 is turned into a magic trap. */
451
452 if (dst->opcode == O (O_JSR, SB))
453 {
454 if (dst->src.literal == 0xc4)
455 {
456 dst->opcode = O (O_SYSCALL, SB);
457 }
458 }
459
460 dst->next_pc = addr + len / 2;
461 return;
462 }
463 else
464 printf ("Don't understand %x \n", looking_for);
465 }
466
467 len++;
468 nib++;
469 }
470
471 fail:
472 ;
473 }
474
475 /* Fell off the end. */
476 dst->opcode = O (O_ILL, SB);
477 }
478
479 static void
480 compile (int pc)
481 {
482 int idx;
483
484 /* Find the next cache entry to use. */
485 idx = cpu.cache_top + 1;
486 cpu.compiles++;
487 if (idx >= cpu.csize)
488 {
489 idx = 1;
490 }
491 cpu.cache_top = idx;
492
493 /* Throw away its old meaning. */
494 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
495
496 /* Set to new address. */
497 cpu.cache[idx].oldpc = pc;
498
499 /* Fill in instruction info. */
500 decode (pc, cpu.memory + pc, cpu.cache + idx);
501
502 /* Point to new cache entry. */
503 cpu.cache_idx[pc] = idx;
504 }
505
506
507 static unsigned char *breg[18];
508 static unsigned short *wreg[18];
509 static unsigned int *lreg[18];
510
511 #define GET_B_REG(x) *(breg[x])
512 #define SET_B_REG(x,y) (*(breg[x])) = (y)
513 #define GET_W_REG(x) *(wreg[x])
514 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
515
516 #define GET_L_REG(x) *(lreg[x])
517 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
518
519 #define GET_MEMORY_L(x) \
520 (x < memory_size \
521 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
522 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
523 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
524 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
525
526 #define GET_MEMORY_W(x) \
527 (x < memory_size \
528 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
529 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
530
531
532 #define GET_MEMORY_B(x) \
533 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
534
535 #define SET_MEMORY_L(x,y) \
536 { register unsigned char *_p; register int __y = y; \
537 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
538 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
539 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
540
541 #define SET_MEMORY_W(x,y) \
542 { register unsigned char *_p; register int __y = y; \
543 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
544 _p[0] = (__y)>>8; _p[1] =(__y);}
545
546 #define SET_MEMORY_B(x,y) \
547 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
548
549 static int
550 fetch (ea_type *arg)
551 {
552 int rn = arg->reg;
553 int abs = arg->literal;
554 int r;
555 int t;
556
557 switch (arg->type)
558 {
559 case X (OP_REG, SB):
560 return GET_B_REG (rn);
561 case X (OP_REG, SW):
562 return GET_W_REG (rn);
563 case X (OP_REG, SL):
564 return GET_L_REG (rn);
565 case X (OP_IMM, SB):
566 case X (OP_IMM, SW):
567 case X (OP_IMM, SL):
568 return abs;
569 case X (OP_DEC, SB):
570 abort ();
571
572 case X (OP_INC, SB):
573 t = GET_L_REG (rn);
574 t &= cpu.mask;
575 r = GET_MEMORY_B (t);
576 t++;
577 t = t & cpu.mask;
578 SET_L_REG (rn, t);
579 return r;
580 break;
581 case X (OP_INC, SW):
582 t = GET_L_REG (rn);
583 t &= cpu.mask;
584 r = GET_MEMORY_W (t);
585 t += 2;
586 t = t & cpu.mask;
587 SET_L_REG (rn, t);
588 return r;
589 case X (OP_INC, SL):
590 t = GET_L_REG (rn);
591 t &= cpu.mask;
592 r = GET_MEMORY_L (t);
593
594 t += 4;
595 t = t & cpu.mask;
596 SET_L_REG (rn, t);
597 return r;
598
599 case X (OP_DISP, SB):
600 t = GET_L_REG (rn) + abs;
601 t &= cpu.mask;
602 return GET_MEMORY_B (t);
603
604 case X (OP_DISP, SW):
605 t = GET_L_REG (rn) + abs;
606 t &= cpu.mask;
607 return GET_MEMORY_W (t);
608
609 case X (OP_DISP, SL):
610 t = GET_L_REG (rn) + abs;
611 t &= cpu.mask;
612 return GET_MEMORY_L (t);
613
614 case X (OP_MEM, SL):
615 t = GET_MEMORY_L (abs);
616 t &= cpu.mask;
617 return t;
618
619 case X (OP_MEM, SW):
620 t = GET_MEMORY_W (abs);
621 t &= cpu.mask;
622 return t;
623
624 default:
625 abort (); /* ?? May be something more usefull? */
626
627 }
628 }
629
630
631 static void
632 store (ea_type *arg, int n)
633 {
634 int rn = arg->reg;
635 int abs = arg->literal;
636 int t;
637
638 switch (arg->type)
639 {
640 case X (OP_REG, SB):
641 SET_B_REG (rn, n);
642 break;
643 case X (OP_REG, SW):
644 SET_W_REG (rn, n);
645 break;
646 case X (OP_REG, SL):
647 SET_L_REG (rn, n);
648 break;
649
650 case X (OP_DEC, SB):
651 t = GET_L_REG (rn) - 1;
652 t &= cpu.mask;
653 SET_L_REG (rn, t);
654 SET_MEMORY_B (t, n);
655
656 break;
657 case X (OP_DEC, SW):
658 t = (GET_L_REG (rn) - 2) & cpu.mask;
659 SET_L_REG (rn, t);
660 SET_MEMORY_W (t, n);
661 break;
662
663 case X (OP_DEC, SL):
664 t = (GET_L_REG (rn) - 4) & cpu.mask;
665 SET_L_REG (rn, t);
666 SET_MEMORY_L (t, n);
667 break;
668
669 case X (OP_DISP, SB):
670 t = GET_L_REG (rn) + abs;
671 t &= cpu.mask;
672 SET_MEMORY_B (t, n);
673 break;
674
675 case X (OP_DISP, SW):
676 t = GET_L_REG (rn) + abs;
677 t &= cpu.mask;
678 SET_MEMORY_W (t, n);
679 break;
680
681 case X (OP_DISP, SL):
682 t = GET_L_REG (rn) + abs;
683 t &= cpu.mask;
684 SET_MEMORY_L (t, n);
685 break;
686 default:
687 abort ();
688 }
689 }
690
691
692 static union
693 {
694 short int i;
695 struct
696 {
697 char low;
698 char high;
699 }
700 u;
701 }
702
703 littleendian;
704
705 static void
706 init_pointers (void)
707 {
708 static int init;
709
710 if (!init)
711 {
712 int i;
713
714 init = 1;
715 littleendian.i = 1;
716
717 if (h8300smode)
718 memory_size = H8300S_MSIZE;
719 else if (h8300hmode)
720 memory_size = H8300H_MSIZE;
721 else
722 memory_size = H8300_MSIZE;
723 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
724 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
725 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
726
727 /* `msize' must be a power of two. */
728 if ((memory_size & (memory_size - 1)) != 0)
729 abort ();
730 cpu.mask = memory_size - 1;
731
732 for (i = 0; i < 9; i++)
733 {
734 cpu.regs[i] = 0;
735 }
736
737 for (i = 0; i < 8; i++)
738 {
739 unsigned char *p = (unsigned char *) (cpu.regs + i);
740 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
741 unsigned short *q = (unsigned short *) (cpu.regs + i);
742 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
743 cpu.regs[i] = 0x00112233;
744 while (p < e)
745 {
746 if (*p == 0x22)
747 {
748 breg[i] = p;
749 }
750 if (*p == 0x33)
751 {
752 breg[i + 8] = p;
753 }
754 p++;
755 }
756 while (q < u)
757 {
758 if (*q == 0x2233)
759 {
760 wreg[i] = q;
761 }
762 if (*q == 0x0011)
763 {
764 wreg[i + 8] = q;
765 }
766 q++;
767 }
768 cpu.regs[i] = 0;
769 lreg[i] = &cpu.regs[i];
770 }
771
772 lreg[8] = &cpu.regs[8];
773
774 /* Initialize the seg registers. */
775 if (!cpu.cache)
776 sim_set_simcache_size (CSIZE);
777 }
778 }
779
780 static void
781 control_c (int sig)
782 {
783 cpu.state = SIM_STATE_STOPPED;
784 cpu.exception = SIGINT;
785 }
786
787 #define C (c != 0)
788 #define Z (nz == 0)
789 #define V (v != 0)
790 #define N (n != 0)
791 #define U (u != 0)
792 #define H (h != 0)
793 #define UI (ui != 0)
794 #define I (intMaskBit != 0)
795
796 static int
797 mop (decoded_inst *code, int bsize, int sign)
798 {
799 int multiplier;
800 int multiplicand;
801 int result;
802 int n, nz;
803
804 if (sign)
805 {
806 multiplicand =
807 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
808 SEXTSHORT (GET_W_REG (code->dst.reg));
809 multiplier =
810 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
811 SEXTSHORT (GET_W_REG (code->src.reg));
812 }
813 else
814 {
815 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
816 UEXTSHORT (GET_W_REG (code->dst.reg));
817 multiplier =
818 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
819 UEXTSHORT (GET_W_REG (code->src.reg));
820
821 }
822 result = multiplier * multiplicand;
823
824 if (sign)
825 {
826 n = result & (bsize ? 0x8000 : 0x80000000);
827 nz = result & (bsize ? 0xffff : 0xffffffff);
828 }
829 if (bsize)
830 {
831 SET_W_REG (code->dst.reg, result);
832 }
833 else
834 {
835 SET_L_REG (code->dst.reg, result);
836 }
837 #if 0
838 return ((n == 1) << 1) | (nz == 1);
839 #endif
840 }
841
842 #define ONOT(name, how) \
843 case O (name, SB): \
844 { \
845 int t; \
846 int hm = 0x80; \
847 rd = GET_B_REG (code->src.reg); \
848 how; \
849 goto shift8; \
850 } \
851 case O (name, SW): \
852 { \
853 int t; \
854 int hm = 0x8000; \
855 rd = GET_W_REG (code->src.reg); \
856 how; \
857 goto shift16; \
858 } \
859 case O (name, SL): \
860 { \
861 int t; \
862 int hm = 0x80000000; \
863 rd = GET_L_REG (code->src.reg); \
864 how; \
865 goto shift32; \
866 }
867
868 #define OSHIFTS(name, how1, how2) \
869 case O (name, SB): \
870 { \
871 int t; \
872 int hm = 0x80; \
873 rd = GET_B_REG (code->src.reg); \
874 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
875 { \
876 how1; \
877 } \
878 else \
879 { \
880 how2; \
881 } \
882 goto shift8; \
883 } \
884 case O (name, SW): \
885 { \
886 int t; \
887 int hm = 0x8000; \
888 rd = GET_W_REG (code->src.reg); \
889 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
890 { \
891 how1; \
892 } \
893 else \
894 { \
895 how2; \
896 } \
897 goto shift16; \
898 } \
899 case O (name, SL): \
900 { \
901 int t; \
902 int hm = 0x80000000; \
903 rd = GET_L_REG (code->src.reg); \
904 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
905 { \
906 how1; \
907 } \
908 else \
909 { \
910 how2; \
911 } \
912 goto shift32; \
913 }
914
915 #define OBITOP(name,f, s, op) \
916 case O (name, SB): \
917 { \
918 int m; \
919 int b; \
920 if (f) ea = fetch (&code->dst); \
921 m=1<< fetch (&code->src); \
922 op; \
923 if (s) store (&code->dst,ea); goto next; \
924 }
925
926 int
927 sim_stop (sd)
928 SIM_DESC sd;
929 {
930 cpu.state = SIM_STATE_STOPPED;
931 cpu.exception = SIGINT;
932 return 1;
933 }
934
935 #define R0_REGNUM 0
936 #define R1_REGNUM 1
937 #define R2_REGNUM 2
938 #define R3_REGNUM 3
939 #define R4_REGNUM 4
940 #define R5_REGNUM 5
941 #define R6_REGNUM 6
942 #define R7_REGNUM 7
943
944 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
945 #define FP_REGNUM R6_REGNUM /* Contains address of executing
946 * stack frame */
947
948 #define CCR_REGNUM 8 /* Contains processor status */
949 #define PC_REGNUM 9 /* Contains program counter */
950
951 #define CYCLE_REGNUM 10
952
953 #define EXR_REGNUM 11
954 #define INST_REGNUM 12
955 #define TICK_REGNUM 13
956
957 void
958 sim_resume (SIM_DESC sd, int step, int siggnal)
959 {
960 static int init1;
961 int cycles = 0;
962 int insts = 0;
963 int tick_start = get_now ();
964 void (*prev) ();
965 int poll_count = 0;
966 int res;
967 int tmp;
968 int rd;
969 int ea;
970 int bit;
971 int pc;
972 int c, nz, v, n, u, h, ui, intMaskBit;
973 int trace, intMask;
974 int oldmask;
975 init_pointers ();
976
977 prev = signal (SIGINT, control_c);
978
979 if (step)
980 {
981 cpu.state = SIM_STATE_STOPPED;
982 cpu.exception = SIGTRAP;
983 }
984 else
985 {
986 cpu.state = SIM_STATE_RUNNING;
987 cpu.exception = 0;
988 }
989
990 pc = cpu.pc;
991
992 /* The PC should never be odd. */
993 if (pc & 0x1)
994 abort ();
995
996 GETSR ();
997 GETEXR ();
998
999 oldmask = cpu.mask;
1000 if (!h8300hmode)
1001 cpu.mask = 0xffff;
1002 do
1003 {
1004 int cidx;
1005 decoded_inst *code;
1006
1007 top:
1008 cidx = cpu.cache_idx[pc];
1009 code = cpu.cache + cidx;
1010
1011
1012 #define ALUOP(STORE, NAME, HOW) \
1013 case O (NAME, SB): HOW; if (STORE) goto alu8; else goto just_flags_alu8; \
1014 case O (NAME, SW): HOW; if (STORE) goto alu16; else goto just_flags_alu16; \
1015 case O (NAME, SL): HOW; if (STORE) goto alu32; else goto just_flags_alu32;
1016
1017
1018 #define LOGOP(NAME, HOW) \
1019 case O (NAME, SB): HOW; goto log8; \
1020 case O (NAME, SW): HOW; goto log16; \
1021 case O (NAME, SL): HOW; goto log32;
1022
1023
1024
1025 #if ADEBUG
1026 if (debug)
1027 {
1028 printf ("%x %d %s\n", pc, code->opcode,
1029 code->op ? code->op->name : "**");
1030 }
1031 cpu.stats[code->opcode]++;
1032
1033 #endif
1034
1035 if (code->opcode)
1036 {
1037 cycles += code->cycles;
1038 insts++;
1039 }
1040
1041 switch (code->opcode)
1042 {
1043 case 0:
1044 /*
1045 * This opcode is a fake for when we get to an
1046 * instruction which hasnt been compiled
1047 */
1048 compile (pc);
1049 goto top;
1050 break;
1051
1052
1053 case O (O_SUBX, SB):
1054 rd = fetch (&code->dst);
1055 ea = fetch (&code->src);
1056 ea = -(ea + C);
1057 res = rd + ea;
1058 goto alu8;
1059
1060 case O (O_ADDX, SB):
1061 rd = fetch (&code->dst);
1062 ea = fetch (&code->src);
1063 ea = C + ea;
1064 res = rd + ea;
1065 goto alu8;
1066
1067 #define EA ea = fetch (&code->src);
1068 #define RD_EA ea = fetch (&code->src); rd = fetch (&code->dst);
1069
1070 ALUOP (1, O_SUB, RD_EA;
1071 ea = -ea;
1072 res = rd + ea);
1073 ALUOP (1, O_NEG, EA;
1074 ea = -ea;
1075 rd = 0;
1076 res = rd + ea);
1077
1078 case O (O_ADD, SB):
1079 rd = GET_B_REG (code->dst.reg);
1080 ea = fetch (&code->src);
1081 res = rd + ea;
1082 goto alu8;
1083 case O (O_ADD, SW):
1084 rd = GET_W_REG (code->dst.reg);
1085 ea = fetch (&code->src);
1086 res = rd + ea;
1087 goto alu16;
1088 case O (O_ADD, SL):
1089 rd = GET_L_REG (code->dst.reg);
1090 ea = fetch (&code->src);
1091 res = rd + ea;
1092 goto alu32;
1093
1094
1095 LOGOP (O_AND, RD_EA;
1096 res = rd & ea);
1097
1098 LOGOP (O_OR, RD_EA;
1099 res = rd | ea);
1100
1101 LOGOP (O_XOR, RD_EA;
1102 res = rd ^ ea);
1103
1104
1105 case O (O_MOV_TO_MEM, SB):
1106 res = GET_B_REG (code->src.reg);
1107 goto log8;
1108 case O (O_MOV_TO_MEM, SW):
1109 res = GET_W_REG (code->src.reg);
1110 goto log16;
1111 case O (O_MOV_TO_MEM, SL):
1112 res = GET_L_REG (code->src.reg);
1113 goto log32;
1114
1115
1116 case O (O_MOV_TO_REG, SB):
1117 res = fetch (&code->src);
1118 SET_B_REG (code->dst.reg, res);
1119 goto just_flags_log8;
1120 case O (O_MOV_TO_REG, SW):
1121 res = fetch (&code->src);
1122 SET_W_REG (code->dst.reg, res);
1123 goto just_flags_log16;
1124 case O (O_MOV_TO_REG, SL):
1125 res = fetch (&code->src);
1126 SET_L_REG (code->dst.reg, res);
1127 goto just_flags_log32;
1128
1129 case O (O_EEPMOV, SB):
1130 case O (O_EEPMOV, SW):
1131 if (h8300hmode || h8300smode)
1132 {
1133 register unsigned char *_src, *_dst;
1134 unsigned int count = ((code->opcode == O (O_EEPMOV, SW))
1135 ? cpu.regs[R4_REGNUM] & 0xffff
1136 : cpu.regs[R4_REGNUM] & 0xff);
1137
1138 _src = (cpu.regs[R5_REGNUM] < memory_size
1139 ? cpu.memory + cpu.regs[R5_REGNUM]
1140 : cpu.eightbit + (cpu.regs[R5_REGNUM] & 0xff));
1141 if ((_src + count) >= (cpu.memory + memory_size))
1142 {
1143 if ((_src + count) >= (cpu.eightbit + 0x100))
1144 goto illegal;
1145 }
1146 _dst = (cpu.regs[R6_REGNUM] < memory_size
1147 ? cpu.memory + cpu.regs[R6_REGNUM]
1148 : cpu.eightbit + (cpu.regs[R6_REGNUM] & 0xff));
1149 if ((_dst + count) >= (cpu.memory + memory_size))
1150 {
1151 if ((_dst + count) >= (cpu.eightbit + 0x100))
1152 goto illegal;
1153 }
1154 memcpy (_dst, _src, count);
1155
1156 cpu.regs[R5_REGNUM] += count;
1157 cpu.regs[R6_REGNUM] += count;
1158 cpu.regs[R4_REGNUM] &= ((code->opcode == O (O_EEPMOV, SW))
1159 ? (~0xffff) : (~0xff));
1160 cycles += 2 * count;
1161 goto next;
1162 }
1163 goto illegal;
1164
1165 case O (O_ADDS, SL):
1166 SET_L_REG (code->dst.reg,
1167 GET_L_REG (code->dst.reg)
1168 + code->src.literal);
1169
1170 goto next;
1171
1172 case O (O_SUBS, SL):
1173 SET_L_REG (code->dst.reg,
1174 GET_L_REG (code->dst.reg)
1175 - code->src.literal);
1176 goto next;
1177
1178 case O (O_CMP, SB):
1179 rd = fetch (&code->dst);
1180 ea = fetch (&code->src);
1181 ea = -ea;
1182 res = rd + ea;
1183 goto just_flags_alu8;
1184
1185 case O (O_CMP, SW):
1186 rd = fetch (&code->dst);
1187 ea = fetch (&code->src);
1188 ea = -ea;
1189 res = rd + ea;
1190 goto just_flags_alu16;
1191
1192 case O (O_CMP, SL):
1193 rd = fetch (&code->dst);
1194 ea = fetch (&code->src);
1195 ea = -ea;
1196 res = rd + ea;
1197 goto just_flags_alu32;
1198
1199
1200 case O (O_DEC, SB):
1201 rd = GET_B_REG (code->src.reg);
1202 ea = -1;
1203 res = rd + ea;
1204 SET_B_REG (code->src.reg, res);
1205 goto just_flags_inc8;
1206
1207 case O (O_DEC, SW):
1208 rd = GET_W_REG (code->dst.reg);
1209 ea = -code->src.literal;
1210 res = rd + ea;
1211 SET_W_REG (code->dst.reg, res);
1212 goto just_flags_inc16;
1213
1214 case O (O_DEC, SL):
1215 rd = GET_L_REG (code->dst.reg);
1216 ea = -code->src.literal;
1217 res = rd + ea;
1218 SET_L_REG (code->dst.reg, res);
1219 goto just_flags_inc32;
1220
1221
1222 case O (O_INC, SB):
1223 rd = GET_B_REG (code->src.reg);
1224 ea = 1;
1225 res = rd + ea;
1226 SET_B_REG (code->src.reg, res);
1227 goto just_flags_inc8;
1228
1229 case O (O_INC, SW):
1230 rd = GET_W_REG (code->dst.reg);
1231 ea = code->src.literal;
1232 res = rd + ea;
1233 SET_W_REG (code->dst.reg, res);
1234 goto just_flags_inc16;
1235
1236 case O (O_INC, SL):
1237 rd = GET_L_REG (code->dst.reg);
1238 ea = code->src.literal;
1239 res = rd + ea;
1240 SET_L_REG (code->dst.reg, res);
1241 goto just_flags_inc32;
1242
1243 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1244 #define GET_EXR(x) BUILDEXR ();x = cpu.exr
1245
1246 case O (O_LDC, SB):
1247 case O (O_LDC, SW):
1248 res = fetch (&code->src);
1249 goto setc;
1250 case O (O_STC, SB):
1251 case O (O_STC, SW):
1252 if (code->src.type == OP_CCR)
1253 {
1254 GET_CCR (res);
1255 }
1256 else if (code->src.type == OP_EXR && h8300smode)
1257 {
1258 GET_EXR (res);
1259 }
1260 else
1261 goto illegal;
1262 store (&code->dst, res);
1263 goto next;
1264
1265 case O (O_ANDC, SB):
1266 if (code->dst.type == OP_CCR)
1267 {
1268 GET_CCR (rd);
1269 }
1270 else if (code->dst.type == OP_EXR && h8300smode)
1271 {
1272 GET_EXR (rd);
1273 }
1274 else
1275 goto illegal;
1276 ea = code->src.literal;
1277 res = rd & ea;
1278 goto setc;
1279
1280 case O (O_ORC, SB):
1281 if (code->dst.type == OP_CCR)
1282 {
1283 GET_CCR (rd);
1284 }
1285 else if (code->dst.type == OP_EXR && h8300smode)
1286 {
1287 GET_EXR (rd);
1288 }
1289 else
1290 goto illegal;
1291 ea = code->src.literal;
1292 res = rd | ea;
1293 goto setc;
1294
1295 case O (O_XORC, SB):
1296 if (code->dst.type == OP_CCR)
1297 {
1298 GET_CCR (rd);
1299 }
1300 else if (code->dst.type == OP_EXR && h8300smode)
1301 {
1302 GET_EXR (rd);
1303 }
1304 else
1305 goto illegal;
1306 ea = code->src.literal;
1307 res = rd ^ ea;
1308 goto setc;
1309
1310
1311 case O (O_BRA, SB):
1312 if (1)
1313 goto condtrue;
1314 goto next;
1315
1316 case O (O_BRN, SB):
1317 if (0)
1318 goto condtrue;
1319 goto next;
1320
1321 case O (O_BHI, SB):
1322 if ((C || Z) == 0)
1323 goto condtrue;
1324 goto next;
1325
1326
1327 case O (O_BLS, SB):
1328 if ((C || Z))
1329 goto condtrue;
1330 goto next;
1331
1332 case O (O_BCS, SB):
1333 if ((C == 1))
1334 goto condtrue;
1335 goto next;
1336
1337 case O (O_BCC, SB):
1338 if ((C == 0))
1339 goto condtrue;
1340 goto next;
1341
1342 case O (O_BEQ, SB):
1343 if (Z)
1344 goto condtrue;
1345 goto next;
1346 case O (O_BGT, SB):
1347 if (((Z || (N ^ V)) == 0))
1348 goto condtrue;
1349 goto next;
1350
1351
1352 case O (O_BLE, SB):
1353 if (((Z || (N ^ V)) == 1))
1354 goto condtrue;
1355 goto next;
1356
1357 case O (O_BGE, SB):
1358 if ((N ^ V) == 0)
1359 goto condtrue;
1360 goto next;
1361 case O (O_BLT, SB):
1362 if ((N ^ V))
1363 goto condtrue;
1364 goto next;
1365 case O (O_BMI, SB):
1366 if ((N))
1367 goto condtrue;
1368 goto next;
1369 case O (O_BNE, SB):
1370 if ((Z == 0))
1371 goto condtrue;
1372 goto next;
1373
1374 case O (O_BPL, SB):
1375 if (N == 0)
1376 goto condtrue;
1377 goto next;
1378 case O (O_BVC, SB):
1379 if ((V == 0))
1380 goto condtrue;
1381 goto next;
1382 case O (O_BVS, SB):
1383 if ((V == 1))
1384 goto condtrue;
1385 goto next;
1386
1387 case O (O_SYSCALL, SB):
1388 {
1389 char c = cpu.regs[2];
1390 sim_callback->write_stdout (sim_callback, &c, 1);
1391 }
1392 goto next;
1393
1394 ONOT (O_NOT, rd = ~rd; v = 0;);
1395 OSHIFTS (O_SHLL,
1396 c = rd & hm; v = 0; rd <<= 1,
1397 c = rd & (hm >> 1); v = 0; rd <<= 2);
1398 OSHIFTS (O_SHLR,
1399 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1400 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1401 OSHIFTS (O_SHAL,
1402 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1403 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1404 OSHIFTS (O_SHAR,
1405 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1406 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1);
1407 OSHIFTS (O_ROTL,
1408 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1409 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1410 OSHIFTS (O_ROTR,
1411 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1412 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1413 OSHIFTS (O_ROTXL,
1414 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1415 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1416 OSHIFTS (O_ROTXR,
1417 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1418 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1419
1420 case O (O_JMP, SB):
1421 {
1422 pc = fetch (&code->src);
1423 goto end;
1424
1425 }
1426
1427 case O (O_JSR, SB):
1428 {
1429 int tmp;
1430 pc = fetch (&code->src);
1431 call:
1432 tmp = cpu.regs[7];
1433
1434 if (h8300hmode)
1435 {
1436 tmp -= 4;
1437 SET_MEMORY_L (tmp, code->next_pc);
1438 }
1439 else
1440 {
1441 tmp -= 2;
1442 SET_MEMORY_W (tmp, code->next_pc);
1443 }
1444 cpu.regs[7] = tmp;
1445
1446 goto end;
1447 }
1448 case O (O_BSR, SB):
1449 pc = code->src.literal;
1450 goto call;
1451
1452 case O (O_RTS, SN):
1453 {
1454 int tmp;
1455
1456 tmp = cpu.regs[7];
1457
1458 if (h8300hmode)
1459 {
1460 pc = GET_MEMORY_L (tmp);
1461 tmp += 4;
1462 }
1463 else
1464 {
1465 pc = GET_MEMORY_W (tmp);
1466 tmp += 2;
1467 }
1468
1469 cpu.regs[7] = tmp;
1470 goto end;
1471 }
1472
1473 case O (O_ILL, SB):
1474 cpu.state = SIM_STATE_STOPPED;
1475 cpu.exception = SIGILL;
1476 goto end;
1477 case O (O_SLEEP, SN):
1478 /* FIXME: Doesn't this break for breakpoints when r0
1479 contains just the right (er, wrong) value? */
1480 cpu.state = SIM_STATE_STOPPED;
1481 /* The format of r0 is defined by target newlib. Expand
1482 the macros here instead of looking for .../sys/wait.h. */
1483 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1484 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1485 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1486 cpu.exception = SIGILL;
1487 else
1488 cpu.exception = SIGTRAP;
1489 goto end;
1490 case O (O_BPT, SN):
1491 cpu.state = SIM_STATE_STOPPED;
1492 cpu.exception = SIGTRAP;
1493 goto end;
1494
1495 OBITOP (O_BNOT, 1, 1, ea ^= m);
1496 OBITOP (O_BTST, 1, 0, nz = ea & m);
1497 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1498 OBITOP (O_BSET, 1, 1, ea |= m);
1499 OBITOP (O_BLD, 1, 0, c = ea & m);
1500 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1501 OBITOP (O_BST, 1, 1, ea &= ~m;
1502 if (C) ea |= m);
1503 OBITOP (O_BIST, 1, 1, ea &= ~m;
1504 if (!C) ea |= m);
1505 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1506 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1507 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1508 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1509 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1510 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1511
1512 #define MOP(bsize, signed) \
1513 mop (code, bsize, signed); \
1514 goto next;
1515
1516 case O (O_MULS, SB):
1517 MOP (1, 1);
1518 break;
1519 case O (O_MULS, SW):
1520 MOP (0, 1);
1521 break;
1522 case O (O_MULU, SB):
1523 MOP (1, 0);
1524 break;
1525 case O (O_MULU, SW):
1526 MOP (0, 0);
1527 break;
1528
1529 case O (O_TAS, SB):
1530 if (!h8300smode || code->src.type != X (OP_REG, SL))
1531 goto illegal;
1532 switch (code->src.reg)
1533 {
1534 case R0_REGNUM:
1535 case R1_REGNUM:
1536 case R4_REGNUM:
1537 case R5_REGNUM:
1538 break;
1539 default:
1540 goto illegal;
1541 }
1542 res = fetch (&code->src);
1543 store (&code->src, res | 0x80);
1544 goto just_flags_log8;
1545
1546 case O (O_DIVU, SB):
1547 {
1548 rd = GET_W_REG (code->dst.reg);
1549 ea = GET_B_REG (code->src.reg);
1550 if (ea)
1551 {
1552 tmp = (unsigned) rd % ea;
1553 rd = (unsigned) rd / ea;
1554 }
1555 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1556 n = ea & 0x80;
1557 nz = ea & 0xff;
1558
1559 goto next;
1560 }
1561 case O (O_DIVU, SW):
1562 {
1563 rd = GET_L_REG (code->dst.reg);
1564 ea = GET_W_REG (code->src.reg);
1565 n = ea & 0x8000;
1566 nz = ea & 0xffff;
1567 if (ea)
1568 {
1569 tmp = (unsigned) rd % ea;
1570 rd = (unsigned) rd / ea;
1571 }
1572 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1573 goto next;
1574 }
1575
1576 case O (O_DIVS, SB):
1577 {
1578
1579 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1580 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1581 if (ea)
1582 {
1583 tmp = (int) rd % (int) ea;
1584 rd = (int) rd / (int) ea;
1585 n = rd & 0x8000;
1586 nz = 1;
1587 }
1588 else
1589 nz = 0;
1590 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1591 goto next;
1592 }
1593 case O (O_DIVS, SW):
1594 {
1595 rd = GET_L_REG (code->dst.reg);
1596 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1597 if (ea)
1598 {
1599 tmp = (int) rd % (int) ea;
1600 rd = (int) rd / (int) ea;
1601 n = rd & 0x80000000;
1602 nz = 1;
1603 }
1604 else
1605 nz = 0;
1606 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1607 goto next;
1608 }
1609 case O (O_EXTS, SW):
1610 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1611 ea = rd & 0x80 ? -256 : 0;
1612 res = rd + ea;
1613 goto log16;
1614 case O (O_EXTS, SL):
1615 rd = GET_W_REG (code->src.reg) & 0xffff;
1616 ea = rd & 0x8000 ? -65536 : 0;
1617 res = rd + ea;
1618 goto log32;
1619 case O (O_EXTU, SW):
1620 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1621 ea = 0;
1622 res = rd + ea;
1623 goto log16;
1624 case O (O_EXTU, SL):
1625 rd = GET_W_REG (code->src.reg) & 0xffff;
1626 ea = 0;
1627 res = rd + ea;
1628 goto log32;
1629
1630 case O (O_NOP, SN):
1631 goto next;
1632
1633 case O (O_STM, SL):
1634 {
1635 int nregs, firstreg, i;
1636
1637 nregs = GET_MEMORY_B (pc + 1);
1638 nregs >>= 4;
1639 nregs &= 0xf;
1640 firstreg = GET_MEMORY_B (pc + 3);
1641 firstreg &= 0xf;
1642 for (i = firstreg; i <= firstreg + nregs; i++)
1643 {
1644 cpu.regs[7] -= 4;
1645 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1646 }
1647 }
1648 goto next;
1649
1650 case O (O_LDM, SL):
1651 {
1652 int nregs, firstreg, i;
1653
1654 nregs = GET_MEMORY_B (pc + 1);
1655 nregs >>= 4;
1656 nregs &= 0xf;
1657 firstreg = GET_MEMORY_B (pc + 3);
1658 firstreg &= 0xf;
1659 for (i = firstreg; i >= firstreg - nregs; i--)
1660 {
1661 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1662 cpu.regs[7] += 4;
1663 }
1664 }
1665 goto next;
1666
1667 default:
1668 illegal:
1669 cpu.state = SIM_STATE_STOPPED;
1670 cpu.exception = SIGILL;
1671 goto end;
1672
1673 }
1674 abort ();
1675
1676 setc:
1677 if (code->dst.type == OP_CCR)
1678 {
1679 cpu.ccr = res;
1680 GETSR ();
1681 }
1682 else if (code->dst.type == OP_EXR && h8300smode)
1683 {
1684 cpu.exr = res;
1685 GETEXR ();
1686 }
1687 else
1688 goto illegal;
1689
1690 goto next;
1691
1692 condtrue:
1693 /* When a branch works */
1694 pc = code->src.literal;
1695 goto end;
1696
1697 /* Set the cond codes from res */
1698 bitop:
1699
1700 /* Set the flags after an 8 bit inc/dec operation */
1701 just_flags_inc8:
1702 n = res & 0x80;
1703 nz = res & 0xff;
1704 v = (rd & 0x7f) == 0x7f;
1705 goto next;
1706
1707
1708 /* Set the flags after an 16 bit inc/dec operation */
1709 just_flags_inc16:
1710 n = res & 0x8000;
1711 nz = res & 0xffff;
1712 v = (rd & 0x7fff) == 0x7fff;
1713 goto next;
1714
1715
1716 /* Set the flags after an 32 bit inc/dec operation */
1717 just_flags_inc32:
1718 n = res & 0x80000000;
1719 nz = res & 0xffffffff;
1720 v = (rd & 0x7fffffff) == 0x7fffffff;
1721 goto next;
1722
1723
1724 shift8:
1725 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1726 n = (rd & 0x80);
1727 nz = rd & 0xff;
1728 SET_B_REG (code->src.reg, rd);
1729 goto next;
1730
1731 shift16:
1732 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1733 n = (rd & 0x8000);
1734 nz = rd & 0xffff;
1735 SET_W_REG (code->src.reg, rd);
1736 goto next;
1737
1738 shift32:
1739 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1740 n = (rd & 0x80000000);
1741 nz = rd & 0xffffffff;
1742 SET_L_REG (code->src.reg, rd);
1743 goto next;
1744
1745 log32:
1746 store (&code->dst, res);
1747 just_flags_log32:
1748 /* flags after a 32bit logical operation */
1749 n = res & 0x80000000;
1750 nz = res & 0xffffffff;
1751 v = 0;
1752 goto next;
1753
1754 log16:
1755 store (&code->dst, res);
1756 just_flags_log16:
1757 /* flags after a 16bit logical operation */
1758 n = res & 0x8000;
1759 nz = res & 0xffff;
1760 v = 0;
1761 goto next;
1762
1763
1764 log8:
1765 store (&code->dst, res);
1766 just_flags_log8:
1767 n = res & 0x80;
1768 nz = res & 0xff;
1769 v = 0;
1770 goto next;
1771
1772 alu8:
1773 SET_B_REG (code->dst.reg, res);
1774 just_flags_alu8:
1775 n = res & 0x80;
1776 nz = res & 0xff;
1777 c = (res & 0x100);
1778 switch (code->opcode / 4)
1779 {
1780 case O_ADD:
1781 v = ((rd & 0x80) == (ea & 0x80)
1782 && (rd & 0x80) != (res & 0x80));
1783 break;
1784 case O_SUB:
1785 case O_CMP:
1786 v = ((rd & 0x80) != (-ea & 0x80)
1787 && (rd & 0x80) != (res & 0x80));
1788 break;
1789 case O_NEG:
1790 v = (rd == 0x80);
1791 break;
1792 }
1793 goto next;
1794
1795 alu16:
1796 SET_W_REG (code->dst.reg, res);
1797 just_flags_alu16:
1798 n = res & 0x8000;
1799 nz = res & 0xffff;
1800 c = (res & 0x10000);
1801 switch (code->opcode / 4)
1802 {
1803 case O_ADD:
1804 v = ((rd & 0x8000) == (ea & 0x8000)
1805 && (rd & 0x8000) != (res & 0x8000));
1806 break;
1807 case O_SUB:
1808 case O_CMP:
1809 v = ((rd & 0x8000) != (-ea & 0x8000)
1810 && (rd & 0x8000) != (res & 0x8000));
1811 break;
1812 case O_NEG:
1813 v = (rd == 0x8000);
1814 break;
1815 }
1816 goto next;
1817
1818 alu32:
1819 SET_L_REG (code->dst.reg, res);
1820 just_flags_alu32:
1821 n = res & 0x80000000;
1822 nz = res & 0xffffffff;
1823 switch (code->opcode / 4)
1824 {
1825 case O_ADD:
1826 v = ((rd & 0x80000000) == (ea & 0x80000000)
1827 && (rd & 0x80000000) != (res & 0x80000000));
1828 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1829 break;
1830 case O_SUB:
1831 case O_CMP:
1832 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1833 && (rd & 0x80000000) != (res & 0x80000000));
1834 c = (unsigned) rd < (unsigned) -ea;
1835 break;
1836 case O_NEG:
1837 v = (rd == 0x80000000);
1838 c = res != 0;
1839 break;
1840 }
1841 goto next;
1842
1843 next:;
1844 pc = code->next_pc;
1845
1846 end:
1847 ;
1848 #if 0
1849 if (cpu.regs[8])
1850 abort ();
1851 #endif
1852
1853 if (--poll_count < 0)
1854 {
1855 poll_count = POLL_QUIT_INTERVAL;
1856 if ((*sim_callback->poll_quit) != NULL
1857 && (*sim_callback->poll_quit) (sim_callback))
1858 sim_stop (sd);
1859 }
1860
1861 }
1862 while (cpu.state == SIM_STATE_RUNNING);
1863 cpu.ticks += get_now () - tick_start;
1864 cpu.cycles += cycles;
1865 cpu.insts += insts;
1866
1867 cpu.pc = pc;
1868 BUILDSR ();
1869 BUILDEXR ();
1870 cpu.mask = oldmask;
1871 signal (SIGINT, prev);
1872 }
1873
1874 int
1875 sim_trace (SIM_DESC sd)
1876 {
1877 /* FIXME: Unfinished. */
1878 abort ();
1879 }
1880
1881 int
1882 sim_write (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1883 {
1884 int i;
1885
1886 init_pointers ();
1887 if (addr < 0)
1888 return 0;
1889 for (i = 0; i < size; i++)
1890 {
1891 if (addr < memory_size)
1892 {
1893 cpu.memory[addr + i] = buffer[i];
1894 cpu.cache_idx[addr + i] = 0;
1895 }
1896 else
1897 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1898 }
1899 return size;
1900 }
1901
1902 int
1903 sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
1904 {
1905 init_pointers ();
1906 if (addr < 0)
1907 return 0;
1908 if (addr < memory_size)
1909 memcpy (buffer, cpu.memory + addr, size);
1910 else
1911 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1912 return size;
1913 }
1914
1915
1916 int
1917 sim_store_register (SIM_DESC sd, int rn, unsigned char *value, int length)
1918 {
1919 int longval;
1920 int shortval;
1921 int intval;
1922 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1923 shortval = (value[0] << 8) | (value[1]);
1924 intval = h8300hmode ? longval : shortval;
1925
1926 init_pointers ();
1927 switch (rn)
1928 {
1929 case PC_REGNUM:
1930 cpu.pc = intval;
1931 break;
1932 default:
1933 abort ();
1934 case R0_REGNUM:
1935 case R1_REGNUM:
1936 case R2_REGNUM:
1937 case R3_REGNUM:
1938 case R4_REGNUM:
1939 case R5_REGNUM:
1940 case R6_REGNUM:
1941 case R7_REGNUM:
1942 cpu.regs[rn] = intval;
1943 break;
1944 case CCR_REGNUM:
1945 cpu.ccr = intval;
1946 break;
1947 case EXR_REGNUM:
1948 cpu.exr = intval;
1949 break;
1950 case CYCLE_REGNUM:
1951 cpu.cycles = longval;
1952 break;
1953
1954 case INST_REGNUM:
1955 cpu.insts = longval;
1956 break;
1957
1958 case TICK_REGNUM:
1959 cpu.ticks = longval;
1960 break;
1961 }
1962 return -1;
1963 }
1964
1965 int
1966 sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length)
1967 {
1968 int v;
1969 int longreg = 0;
1970
1971 init_pointers ();
1972
1973 if (!h8300smode && rn >= EXR_REGNUM)
1974 rn++;
1975 switch (rn)
1976 {
1977 default:
1978 abort ();
1979 case CCR_REGNUM:
1980 v = cpu.ccr;
1981 break;
1982 case EXR_REGNUM:
1983 v = cpu.exr;
1984 break;
1985 case PC_REGNUM:
1986 v = cpu.pc;
1987 break;
1988 case R0_REGNUM:
1989 case R1_REGNUM:
1990 case R2_REGNUM:
1991 case R3_REGNUM:
1992 case R4_REGNUM:
1993 case R5_REGNUM:
1994 case R6_REGNUM:
1995 case R7_REGNUM:
1996 v = cpu.regs[rn];
1997 break;
1998 case CYCLE_REGNUM:
1999 v = cpu.cycles;
2000 longreg = 1;
2001 break;
2002 case TICK_REGNUM:
2003 v = cpu.ticks;
2004 longreg = 1;
2005 break;
2006 case INST_REGNUM:
2007 v = cpu.insts;
2008 longreg = 1;
2009 break;
2010 }
2011 if (h8300hmode || longreg)
2012 {
2013 buf[0] = v >> 24;
2014 buf[1] = v >> 16;
2015 buf[2] = v >> 8;
2016 buf[3] = v >> 0;
2017 }
2018 else
2019 {
2020 buf[0] = v >> 8;
2021 buf[1] = v;
2022 }
2023 return -1;
2024 }
2025
2026 void
2027 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
2028 {
2029 #if 0 /* FIXME: This should work but we can't use it.
2030 grep for SLEEP above. */
2031 switch (cpu.state)
2032 {
2033 case SIM_STATE_EXITED : *reason = sim_exited; break;
2034 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
2035 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
2036 default : abort ();
2037 }
2038 #else
2039 *reason = sim_stopped;
2040 #endif
2041 *sigrc = cpu.exception;
2042 }
2043
2044 /* FIXME: Rename to sim_set_mem_size. */
2045
2046 void
2047 sim_size (int n)
2048 {
2049 /* Memory size is fixed. */
2050 }
2051
2052 void
2053 sim_set_simcache_size (int n)
2054 {
2055 if (cpu.cache)
2056 free (cpu.cache);
2057 if (n < 2)
2058 n = 2;
2059 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
2060 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
2061 cpu.csize = n;
2062 }
2063
2064
2065 void
2066 sim_info (SIM_DESC sd, int verbose)
2067 {
2068 double timetaken = (double) cpu.ticks / (double) now_persec ();
2069 double virttime = cpu.cycles / 10.0e6;
2070
2071 (*sim_callback->printf_filtered) (sim_callback,
2072 "\n\n#instructions executed %10d\n",
2073 cpu.insts);
2074 (*sim_callback->printf_filtered) (sim_callback,
2075 "#cycles (v approximate) %10d\n",
2076 cpu.cycles);
2077 (*sim_callback->printf_filtered) (sim_callback,
2078 "#real time taken %10.4f\n",
2079 timetaken);
2080 (*sim_callback->printf_filtered) (sim_callback,
2081 "#virtual time taked %10.4f\n",
2082 virttime);
2083 if (timetaken != 0.0)
2084 (*sim_callback->printf_filtered) (sim_callback,
2085 "#simulation ratio %10.4f\n",
2086 virttime / timetaken);
2087 (*sim_callback->printf_filtered) (sim_callback,
2088 "#compiles %10d\n",
2089 cpu.compiles);
2090 (*sim_callback->printf_filtered) (sim_callback,
2091 "#cache size %10d\n",
2092 cpu.csize);
2093
2094 #ifdef ADEBUG
2095 /* This to be conditional on `what' (aka `verbose'),
2096 however it was never passed as non-zero. */
2097 if (1)
2098 {
2099 int i;
2100 for (i = 0; i < O_LAST; i++)
2101 {
2102 if (cpu.stats[i])
2103 (*sim_callback->printf_filtered) (sim_callback,
2104 "%d: %d\n", i, cpu.stats[i]);
2105 }
2106 }
2107 #endif
2108 }
2109
2110 /* Indicate whether the cpu is an H8/300 or H8/300H.
2111 FLAG is non-zero for the H8/300H. */
2112
2113 void
2114 set_h8300h (int h_flag, int s_flag)
2115 {
2116 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2117 This function being replaced by a sim_open:ARGV configuration
2118 option. */
2119 h8300hmode = h_flag;
2120 h8300smode = s_flag;
2121 }
2122
2123 SIM_DESC
2124 sim_open (SIM_OPEN_KIND kind,
2125 struct host_callback_struct *ptr,
2126 struct _bfd *abfd,
2127 char **argv)
2128 {
2129 /* FIXME: Much of the code in sim_load can be moved here. */
2130
2131 sim_kind = kind;
2132 myname = argv[0];
2133 sim_callback = ptr;
2134 /* Fudge our descriptor. */
2135 return (SIM_DESC) 1;
2136 }
2137
2138 void
2139 sim_close (SIM_DESC sd, int quitting)
2140 {
2141 /* Nothing to do. */
2142 }
2143
2144 /* Called by gdb to load a program into memory. */
2145
2146 SIM_RC
2147 sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty)
2148 {
2149 bfd *prog_bfd;
2150
2151 /* FIXME: The code below that sets a specific variant of the H8/300
2152 being simulated should be moved to sim_open(). */
2153
2154 /* See if the file is for the H8/300 or H8/300H. */
2155 /* ??? This may not be the most efficient way. The z8k simulator
2156 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2157 if (abfd != NULL)
2158 prog_bfd = abfd;
2159 else
2160 prog_bfd = bfd_openr (prog, "coff-h8300");
2161 if (prog_bfd != NULL)
2162 {
2163 /* Set the cpu type. We ignore failure from bfd_check_format
2164 and bfd_openr as sim_load_file checks too. */
2165 if (bfd_check_format (prog_bfd, bfd_object))
2166 {
2167 unsigned long mach = bfd_get_mach (prog_bfd);
2168 set_h8300h (mach == bfd_mach_h8300h || mach == bfd_mach_h8300s,
2169 mach == bfd_mach_h8300s);
2170 }
2171 }
2172
2173 /* If we're using gdb attached to the simulator, then we have to
2174 reallocate memory for the simulator.
2175
2176 When gdb first starts, it calls fetch_registers (among other
2177 functions), which in turn calls init_pointers, which allocates
2178 simulator memory.
2179
2180 The problem is when we do that, we don't know whether we're
2181 debugging an H8/300 or H8/300H program.
2182
2183 This is the first point at which we can make that determination,
2184 so we just reallocate memory now; this will also allow us to handle
2185 switching between H8/300 and H8/300H programs without exiting
2186 gdb. */
2187
2188 if (h8300smode)
2189 memory_size = H8300S_MSIZE;
2190 else if (h8300hmode)
2191 memory_size = H8300H_MSIZE;
2192 else
2193 memory_size = H8300_MSIZE;
2194
2195 if (cpu.memory)
2196 free (cpu.memory);
2197 if (cpu.cache_idx)
2198 free (cpu.cache_idx);
2199 if (cpu.eightbit)
2200 free (cpu.eightbit);
2201
2202 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2203 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2204 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2205
2206 /* `msize' must be a power of two. */
2207 if ((memory_size & (memory_size - 1)) != 0)
2208 abort ();
2209 cpu.mask = memory_size - 1;
2210
2211 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2212 sim_kind == SIM_OPEN_DEBUG,
2213 0, sim_write)
2214 == NULL)
2215 {
2216 /* Close the bfd if we opened it. */
2217 if (abfd == NULL && prog_bfd != NULL)
2218 bfd_close (prog_bfd);
2219 return SIM_RC_FAIL;
2220 }
2221
2222 /* Close the bfd if we opened it. */
2223 if (abfd == NULL && prog_bfd != NULL)
2224 bfd_close (prog_bfd);
2225 return SIM_RC_OK;
2226 }
2227
2228 SIM_RC
2229 sim_create_inferior (SIM_DESC sd, struct _bfd *abfd, char **argv, char **env)
2230 {
2231 if (abfd != NULL)
2232 cpu.pc = bfd_get_start_address (abfd);
2233 else
2234 cpu.pc = 0;
2235 return SIM_RC_OK;
2236 }
2237
2238 void
2239 sim_do_command (SIM_DESC sd, char *cmd)
2240 {
2241 (*sim_callback->printf_filtered) (sim_callback,
2242 "This simulator does not accept any commands.\n");
2243 }
2244
2245 void
2246 sim_set_callbacks (struct host_callback_struct *ptr)
2247 {
2248 sim_callback = ptr;
2249 }