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* compile.c: Fix comment typos.
[binutils-gdb.git] / sim / h8300 / compile.c
1 /*
2 * Simulator for the Hitachi H8/300 architecture.
3 *
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
5 *
6 * This file is part of H8/300 sim
7 *
8 *
9 * THIS SOFTWARE IS NOT COPYRIGHTED
10 *
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
14 *
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
18 */
19
20 #include "config.h"
21
22 #include <stdio.h>
23 #include <signal.h>
24 #ifdef HAVE_TIME_H
25 #include <time.h>
26 #endif
27 #ifdef HAVE_STDLIB_H
28 #include <stdlib.h>
29 #endif
30 #ifdef HAVE_SYS_PARAM_H
31 #include <sys/param.h>
32 #endif
33 #include "ansidecl.h"
34 #include "bfd.h"
35 #include "callback.h"
36 #include "remote-sim.h"
37
38 #ifndef SIGTRAP
39 # define SIGTRAP 5
40 #endif
41
42 int debug;
43
44 host_callback *sim_callback;
45
46 static SIM_OPEN_KIND sim_kind;
47 static char *myname;
48
49 /* FIXME: Needs to live in header file.
50 This header should also include the things in remote-sim.h.
51 One could move this to remote-sim.h but this function isn't needed
52 by gdb. */
53 void sim_set_simcache_size PARAMS ((int));
54
55 #define X(op, size) op*4+size
56
57 #define SP (h8300hmode ? SL:SW)
58 #define SB 0
59 #define SW 1
60 #define SL 2
61 #define OP_REG 1
62 #define OP_DEC 2
63 #define OP_DISP 3
64 #define OP_INC 4
65 #define OP_PCREL 5
66 #define OP_MEM 6
67 #define OP_CCR 7
68 #define OP_IMM 8
69 #define OP_ABS 10
70 #define h8_opcodes ops
71 #define DEFINE_TABLE
72 #include "opcode/h8300.h"
73
74 #include "inst.h"
75
76 /* The rate at which to call the host's poll_quit callback. */
77
78 #define POLL_QUIT_INTERVAL 0x80000
79
80 #define LOW_BYTE(x) ((x) & 0xff)
81 #define HIGH_BYTE(x) (((x)>>8) & 0xff)
82 #define P(X,Y) ((X<<8) | Y)
83
84 #define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C;
85
86 #define GETSR() \
87 c = (cpu.ccr >> 0) & 1;\
88 v = (cpu.ccr >> 1) & 1;\
89 nz = !((cpu.ccr >> 2) & 1);\
90 n = (cpu.ccr >> 3) & 1;
91
92 #ifdef __CHAR_IS_SIGNED__
93 #define SEXTCHAR(x) ((char)(x))
94 #endif
95
96 #ifndef SEXTCHAR
97 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff)
98 #endif
99
100 #define UEXTCHAR(x) ((x) & 0xff)
101 #define UEXTSHORT(x) ((x) & 0xffff)
102 #define SEXTSHORT(x) ((short)(x))
103
104 static cpu_state_type cpu;
105
106 int h8300hmode = 0;
107 int h8300smode = 0;
108
109 static int memory_size;
110
111 static int
112 get_now ()
113 {
114 #ifndef WIN32
115 return time (0);
116 #endif
117 return 0;
118 }
119
120 static int
121 now_persec ()
122 {
123 return 1;
124 }
125
126 static int
127 bitfrom (x)
128 {
129 switch (x & SIZE)
130 {
131 case L_8:
132 return SB;
133 case L_16:
134 return SW;
135 case L_32:
136 return SL;
137 case L_P:
138 return h8300hmode ? SL : SW;
139 }
140 }
141
142 static unsigned int
143 lvalue (x, rn)
144 {
145 switch (x / 4)
146 {
147 case OP_DISP:
148 if (rn == 8)
149 {
150 return X (OP_IMM, SP);
151 }
152 return X (OP_REG, SP);
153
154 case OP_MEM:
155 return X (OP_MEM, SP);
156
157 default:
158 abort ();
159 }
160 }
161
162 static unsigned int
163 decode (addr, data, dst)
164 int addr;
165 unsigned char *data;
166 decoded_inst *dst;
167
168 {
169 int rs = 0;
170 int rd = 0;
171 int rdisp = 0;
172 int abs = 0;
173 int bit = 0;
174 int plen = 0;
175 struct h8_opcode *q;
176 int size = 0;
177
178 dst->dst.type = -1;
179 dst->src.type = -1;
180
181 /* Find the exact opcode/arg combo. */
182 for (q = h8_opcodes; q->name; q++)
183 {
184 op_type *nib = q->data.nib;
185 unsigned int len = 0;
186
187 while (1)
188 {
189 op_type looking_for = *nib;
190 int thisnib = data[len >> 1];
191
192 thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf);
193
194 if (looking_for < 16 && looking_for >= 0)
195 {
196 if (looking_for != thisnib)
197 goto fail;
198 }
199 else
200 {
201 if ((int) looking_for & (int) B31)
202 {
203 if (!(((int) thisnib & 0x8) != 0))
204 goto fail;
205
206 looking_for = (op_type) ((int) looking_for & ~(int) B31);
207 thisnib &= 0x7;
208 }
209
210 if ((int) looking_for & (int) B30)
211 {
212 if (!(((int) thisnib & 0x8) == 0))
213 goto fail;
214
215 looking_for = (op_type) ((int) looking_for & ~(int) B30);
216 }
217
218 if (looking_for & DBIT)
219 {
220 /* Exclude adds/subs by looking at bit 0 and 2, and
221 make sure the operand size, either w or l,
222 matches by looking at bit 1. */
223 if ((looking_for & 7) != (thisnib & 7))
224 goto fail;
225
226 abs = (thisnib & 0x8) ? 2 : 1;
227 }
228 else if (looking_for & (REG | IND | INC | DEC))
229 {
230 if (looking_for & REG)
231 {
232 /* Can work out size from the register. */
233 size = bitfrom (looking_for);
234 }
235 if (looking_for & SRC)
236 rs = thisnib;
237 else
238 rd = thisnib;
239 }
240 else if (looking_for & L_16)
241 {
242 abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1];
243 plen = 16;
244 if (looking_for & (PCREL | DISP))
245 {
246 abs = (short) (abs);
247 }
248 }
249 else if (looking_for & ABSJMP)
250 {
251 abs = (data[1] << 16) | (data[2] << 8) | (data[3]);
252 }
253 else if (looking_for & MEMIND)
254 {
255 abs = data[1];
256 }
257 else if (looking_for & L_32)
258 {
259 int i = len >> 1;
260
261 abs = (data[i] << 24)
262 | (data[i + 1] << 16)
263 | (data[i + 2] << 8)
264 | (data[i + 3]);
265
266 plen = 32;
267 }
268 else if (looking_for & L_24)
269 {
270 int i = len >> 1;
271
272 abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
273 plen = 24;
274 }
275 else if (looking_for & IGNORE)
276 {
277 ;
278 }
279 else if (looking_for & DISPREG)
280 {
281 rdisp = thisnib & 0x7;
282 }
283 else if (looking_for & KBIT)
284 {
285 switch (thisnib)
286 {
287 case 9:
288 abs = 4;
289 break;
290 case 8:
291 abs = 2;
292 break;
293 case 0:
294 abs = 1;
295 break;
296 default:
297 goto fail;
298 }
299 }
300 else if (looking_for & L_8)
301 {
302 plen = 8;
303
304 if (looking_for & PCREL)
305 {
306 abs = SEXTCHAR (data[len >> 1]);
307 }
308 else if (looking_for & ABS8MEM)
309 {
310 plen = 8;
311 abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff;
312 abs |= data[len >> 1] & 0xff;
313 }
314 else
315 {
316 abs = data[len >> 1] & 0xff;
317 }
318 }
319 else if (looking_for & L_3)
320 {
321 plen = 3;
322
323 bit = thisnib;
324 }
325 else if (looking_for == E)
326 {
327 dst->op = q;
328
329 /* Fill in the args. */
330 {
331 op_type *args = q->args.nib;
332 int hadone = 0;
333
334 while (*args != E)
335 {
336 int x = *args;
337 int rn = (x & DST) ? rd : rs;
338 ea_type *p;
339
340 if (x & DST)
341 p = &(dst->dst);
342 else
343 p = &(dst->src);
344
345 if (x & L_3)
346 {
347 p->type = X (OP_IMM, size);
348 p->literal = bit;
349 }
350 else if (x & (IMM | KBIT | DBIT))
351 {
352 p->type = X (OP_IMM, size);
353 p->literal = abs;
354 }
355 else if (x & REG)
356 {
357 /* Reset the size.
358 Some ops (like mul) have two sizes. */
359
360 size = bitfrom (x);
361 p->type = X (OP_REG, size);
362 p->reg = rn;
363 }
364 else if (x & INC)
365 {
366 p->type = X (OP_INC, size);
367 p->reg = rn & 0x7;
368 }
369 else if (x & DEC)
370 {
371 p->type = X (OP_DEC, size);
372 p->reg = rn & 0x7;
373 }
374 else if (x & IND)
375 {
376 p->type = X (OP_DISP, size);
377 p->reg = rn & 0x7;
378 p->literal = 0;
379 }
380 else if (x & (ABS | ABSJMP | ABS8MEM))
381 {
382 p->type = X (OP_DISP, size);
383 p->literal = abs;
384 p->reg = 8;
385 }
386 else if (x & MEMIND)
387 {
388 p->type = X (OP_MEM, size);
389 p->literal = abs;
390 }
391 else if (x & PCREL)
392 {
393 p->type = X (OP_PCREL, size);
394 p->literal = abs + addr + 2;
395 if (x & L_16)
396 p->literal += 2;
397 }
398 else if (x & ABSJMP)
399 {
400 p->type = X (OP_IMM, SP);
401 p->literal = abs;
402 }
403 else if (x & DISP)
404 {
405 p->type = X (OP_DISP, size);
406 p->literal = abs;
407 p->reg = rdisp & 0x7;
408 }
409 else if (x & CCR)
410 {
411 p->type = OP_CCR;
412 }
413 else
414 printf ("Hmmmm %x", x);
415
416 args++;
417 }
418 }
419
420 /* But a jmp or a jsr gets automagically lvalued,
421 since we branch to their address not their
422 contents. */
423 if (q->how == O (O_JSR, SB)
424 || q->how == O (O_JMP, SB))
425 {
426 dst->src.type = lvalue (dst->src.type, dst->src.reg);
427 }
428
429 if (dst->dst.type == -1)
430 dst->dst = dst->src;
431
432 dst->opcode = q->how;
433 dst->cycles = q->time;
434
435 /* And a jsr to 0xc4 is turned into a magic trap. */
436
437 if (dst->opcode == O (O_JSR, SB))
438 {
439 if (dst->src.literal == 0xc4)
440 {
441 dst->opcode = O (O_SYSCALL, SB);
442 }
443 }
444
445 dst->next_pc = addr + len / 2;
446 return;
447 }
448 else
449 printf ("Don't understand %x \n", looking_for);
450 }
451
452 len++;
453 nib++;
454 }
455
456 fail:
457 ;
458 }
459
460 /* Fell off the end. */
461 dst->opcode = O (O_ILL, SB);
462 }
463
464 static void
465 compile (pc)
466 {
467 int idx;
468
469 /* Find the next cache entry to use. */
470 idx = cpu.cache_top + 1;
471 cpu.compiles++;
472 if (idx >= cpu.csize)
473 {
474 idx = 1;
475 }
476 cpu.cache_top = idx;
477
478 /* Throw away its old meaning. */
479 cpu.cache_idx[cpu.cache[idx].oldpc] = 0;
480
481 /* Set to new address. */
482 cpu.cache[idx].oldpc = pc;
483
484 /* Fill in instruction info. */
485 decode (pc, cpu.memory + pc, cpu.cache + idx);
486
487 /* Point to new cache entry. */
488 cpu.cache_idx[pc] = idx;
489 }
490
491
492 static unsigned char *breg[18];
493 static unsigned short *wreg[18];
494 static unsigned int *lreg[18];
495
496 #define GET_B_REG(x) *(breg[x])
497 #define SET_B_REG(x,y) (*(breg[x])) = (y)
498 #define GET_W_REG(x) *(wreg[x])
499 #define SET_W_REG(x,y) (*(wreg[x])) = (y)
500
501 #define GET_L_REG(x) *(lreg[x])
502 #define SET_L_REG(x,y) (*(lreg[x])) = (y)
503
504 #define GET_MEMORY_L(x) \
505 (x < memory_size \
506 ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \
507 | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \
508 : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \
509 | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff]))
510
511 #define GET_MEMORY_W(x) \
512 (x < memory_size \
513 ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \
514 : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0)))
515
516
517 #define GET_MEMORY_B(x) \
518 (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff]))
519
520 #define SET_MEMORY_L(x,y) \
521 { register unsigned char *_p; register int __y = y; \
522 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
523 _p[0] = (__y)>>24; _p[1] = (__y)>>16; \
524 _p[2] = (__y)>>8; _p[3] = (__y)>>0;}
525
526 #define SET_MEMORY_W(x,y) \
527 { register unsigned char *_p; register int __y = y; \
528 _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \
529 _p[0] = (__y)>>8; _p[1] =(__y);}
530
531 #define SET_MEMORY_B(x,y) \
532 (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y))
533
534 int
535 fetch (arg, n)
536 ea_type *arg;
537 {
538 int rn = arg->reg;
539 int abs = arg->literal;
540 int r;
541 int t;
542
543 switch (arg->type)
544 {
545 case X (OP_REG, SB):
546 return GET_B_REG (rn);
547 case X (OP_REG, SW):
548 return GET_W_REG (rn);
549 case X (OP_REG, SL):
550 return GET_L_REG (rn);
551 case X (OP_IMM, SB):
552 case X (OP_IMM, SW):
553 case X (OP_IMM, SL):
554 return abs;
555 case X (OP_DEC, SB):
556 abort ();
557
558 case X (OP_INC, SB):
559 t = GET_L_REG (rn);
560 t &= cpu.mask;
561 r = GET_MEMORY_B (t);
562 t++;
563 t = t & cpu.mask;
564 SET_L_REG (rn, t);
565 return r;
566 break;
567 case X (OP_INC, SW):
568 t = GET_L_REG (rn);
569 t &= cpu.mask;
570 r = GET_MEMORY_W (t);
571 t += 2;
572 t = t & cpu.mask;
573 SET_L_REG (rn, t);
574 return r;
575 case X (OP_INC, SL):
576 t = GET_L_REG (rn);
577 t &= cpu.mask;
578 r = GET_MEMORY_L (t);
579
580 t += 4;
581 t = t & cpu.mask;
582 SET_L_REG (rn, t);
583 return r;
584
585 case X (OP_DISP, SB):
586 t = GET_L_REG (rn) + abs;
587 t &= cpu.mask;
588 return GET_MEMORY_B (t);
589
590 case X (OP_DISP, SW):
591 t = GET_L_REG (rn) + abs;
592 t &= cpu.mask;
593 return GET_MEMORY_W (t);
594
595 case X (OP_DISP, SL):
596 t = GET_L_REG (rn) + abs;
597 t &= cpu.mask;
598 return GET_MEMORY_L (t);
599
600 case X (OP_MEM, SL):
601 t = GET_MEMORY_L (abs);
602 t &= cpu.mask;
603 return t;
604
605 case X (OP_MEM, SW):
606 t = GET_MEMORY_W (abs);
607 t &= cpu.mask;
608 return t;
609
610 default:
611 abort ();
612
613 }
614 }
615
616
617 static
618 void
619 store (arg, n)
620 ea_type *arg;
621 int n;
622 {
623 int rn = arg->reg;
624 int abs = arg->literal;
625 int t;
626
627 switch (arg->type)
628 {
629 case X (OP_REG, SB):
630 SET_B_REG (rn, n);
631 break;
632 case X (OP_REG, SW):
633 SET_W_REG (rn, n);
634 break;
635 case X (OP_REG, SL):
636 SET_L_REG (rn, n);
637 break;
638
639 case X (OP_DEC, SB):
640 t = GET_L_REG (rn) - 1;
641 t &= cpu.mask;
642 SET_L_REG (rn, t);
643 SET_MEMORY_B (t, n);
644
645 break;
646 case X (OP_DEC, SW):
647 t = (GET_L_REG (rn) - 2) & cpu.mask;
648 SET_L_REG (rn, t);
649 SET_MEMORY_W (t, n);
650 break;
651
652 case X (OP_DEC, SL):
653 t = (GET_L_REG (rn) - 4) & cpu.mask;
654 SET_L_REG (rn, t);
655 SET_MEMORY_L (t, n);
656 break;
657
658 case X (OP_DISP, SB):
659 t = GET_L_REG (rn) + abs;
660 t &= cpu.mask;
661 SET_MEMORY_B (t, n);
662 break;
663
664 case X (OP_DISP, SW):
665 t = GET_L_REG (rn) + abs;
666 t &= cpu.mask;
667 SET_MEMORY_W (t, n);
668 break;
669
670 case X (OP_DISP, SL):
671 t = GET_L_REG (rn) + abs;
672 t &= cpu.mask;
673 SET_MEMORY_L (t, n);
674 break;
675 default:
676 abort ();
677 }
678 }
679
680
681 static union
682 {
683 short int i;
684 struct
685 {
686 char low;
687 char high;
688 }
689 u;
690 }
691
692 littleendian;
693
694 static
695 void
696 init_pointers ()
697 {
698 static int init;
699
700 if (!init)
701 {
702 int i;
703
704 init = 1;
705 littleendian.i = 1;
706
707 if (h8300hmode)
708 memory_size = H8300H_MSIZE;
709 else
710 memory_size = H8300_MSIZE;
711 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
712 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
713 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
714
715 /* `msize' must be a power of two. */
716 if ((memory_size & (memory_size - 1)) != 0)
717 abort ();
718 cpu.mask = memory_size - 1;
719
720 for (i = 0; i < 9; i++)
721 {
722 cpu.regs[i] = 0;
723 }
724
725 for (i = 0; i < 8; i++)
726 {
727 unsigned char *p = (unsigned char *) (cpu.regs + i);
728 unsigned char *e = (unsigned char *) (cpu.regs + i + 1);
729 unsigned short *q = (unsigned short *) (cpu.regs + i);
730 unsigned short *u = (unsigned short *) (cpu.regs + i + 1);
731 cpu.regs[i] = 0x00112233;
732 while (p < e)
733 {
734 if (*p == 0x22)
735 {
736 breg[i] = p;
737 }
738 if (*p == 0x33)
739 {
740 breg[i + 8] = p;
741 }
742 p++;
743 }
744 while (q < u)
745 {
746 if (*q == 0x2233)
747 {
748 wreg[i] = q;
749 }
750 if (*q == 0x0011)
751 {
752 wreg[i + 8] = q;
753 }
754 q++;
755 }
756 cpu.regs[i] = 0;
757 lreg[i] = &cpu.regs[i];
758 }
759
760 lreg[8] = &cpu.regs[8];
761
762 /* Initialize the seg registers. */
763 if (!cpu.cache)
764 sim_set_simcache_size (CSIZE);
765 }
766 }
767
768 static void
769 control_c (sig, code, scp, addr)
770 int sig;
771 int code;
772 char *scp;
773 char *addr;
774 {
775 cpu.state = SIM_STATE_STOPPED;
776 cpu.exception = SIGINT;
777 }
778
779 #define C (c != 0)
780 #define Z (nz == 0)
781 #define V (v != 0)
782 #define N (n != 0)
783
784 static int
785 mop (code, bsize, sign)
786 decoded_inst *code;
787 int bsize;
788 int sign;
789 {
790 int multiplier;
791 int multiplicand;
792 int result;
793 int n, nz;
794
795 if (sign)
796 {
797 multiplicand =
798 bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) :
799 SEXTSHORT (GET_W_REG (code->dst.reg));
800 multiplier =
801 bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) :
802 SEXTSHORT (GET_W_REG (code->src.reg));
803 }
804 else
805 {
806 multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) :
807 UEXTSHORT (GET_W_REG (code->dst.reg));
808 multiplier =
809 bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) :
810 UEXTSHORT (GET_W_REG (code->src.reg));
811
812 }
813 result = multiplier * multiplicand;
814
815 if (sign)
816 {
817 n = result & (bsize ? 0x8000 : 0x80000000);
818 nz = result & (bsize ? 0xffff : 0xffffffff);
819 }
820 if (bsize)
821 {
822 SET_W_REG (code->dst.reg, result);
823 }
824 else
825 {
826 SET_L_REG (code->dst.reg, result);
827 }
828 /* return ((n==1) << 1) | (nz==1); */
829
830 }
831
832 #define ONOT(name, how) \
833 case O(name, SB): \
834 { \
835 int t; \
836 int hm = 0x80; \
837 rd = GET_B_REG (code->src.reg); \
838 how; \
839 goto shift8; \
840 } \
841 case O(name, SW): \
842 { \
843 int t; \
844 int hm = 0x8000; \
845 rd = GET_W_REG (code->src.reg); \
846 how; \
847 goto shift16; \
848 } \
849 case O(name, SL): \
850 { \
851 int t; \
852 int hm = 0x80000000; \
853 rd = GET_L_REG (code->src.reg); \
854 how; \
855 goto shift32; \
856 }
857
858 #define OSHIFTS(name, how1, how2) \
859 case O(name, SB): \
860 { \
861 int t; \
862 int hm = 0x80; \
863 rd = GET_B_REG (code->src.reg); \
864 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
865 { \
866 how1; \
867 } \
868 else \
869 { \
870 how2; \
871 } \
872 goto shift8; \
873 } \
874 case O(name, SW): \
875 { \
876 int t; \
877 int hm = 0x8000; \
878 rd = GET_W_REG (code->src.reg); \
879 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
880 { \
881 how1; \
882 } \
883 else \
884 { \
885 how2; \
886 } \
887 goto shift16; \
888 } \
889 case O(name, SL): \
890 { \
891 int t; \
892 int hm = 0x80000000; \
893 rd = GET_L_REG (code->src.reg); \
894 if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \
895 { \
896 how1; \
897 } \
898 else \
899 { \
900 how2; \
901 } \
902 goto shift32; \
903 }
904
905 #define OBITOP(name,f, s, op) \
906 case O(name, SB): \
907 { \
908 int m; \
909 int b; \
910 if (f) ea = fetch (&code->dst); \
911 m=1<< fetch(&code->src); \
912 op; \
913 if(s) store (&code->dst,ea); goto next; \
914 }
915
916 int
917 sim_stop (sd)
918 SIM_DESC sd;
919 {
920 cpu.state = SIM_STATE_STOPPED;
921 cpu.exception = SIGINT;
922 return 1;
923 }
924
925 void
926 sim_resume (sd, step, siggnal)
927 SIM_DESC sd;
928 {
929 static int init1;
930 int cycles = 0;
931 int insts = 0;
932 int tick_start = get_now ();
933 void (*prev) ();
934 int poll_count = 0;
935 int res;
936 int tmp;
937 int rd;
938 int ea;
939 int bit;
940 int pc;
941 int c, nz, v, n;
942 int oldmask;
943 init_pointers ();
944
945 prev = signal (SIGINT, control_c);
946
947 if (step)
948 {
949 cpu.state = SIM_STATE_STOPPED;
950 cpu.exception = SIGTRAP;
951 }
952 else
953 {
954 cpu.state = SIM_STATE_RUNNING;
955 cpu.exception = 0;
956 }
957
958 pc = cpu.pc;
959
960 /* The PC should never be odd. */
961 if (pc & 0x1)
962 abort ();
963
964 GETSR ();
965 oldmask = cpu.mask;
966 if (!h8300hmode)
967 cpu.mask = 0xffff;
968 do
969 {
970 int cidx;
971 decoded_inst *code;
972
973 top:
974 cidx = cpu.cache_idx[pc];
975 code = cpu.cache + cidx;
976
977
978 #define ALUOP(STORE, NAME, HOW) \
979 case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \
980 case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \
981 case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32;
982
983
984 #define LOGOP(NAME, HOW) \
985 case O(NAME,SB): HOW; goto log8;\
986 case O(NAME, SW): HOW; goto log16;\
987 case O(NAME,SL): HOW; goto log32;
988
989
990
991 #if ADEBUG
992 if (debug)
993 {
994 printf ("%x %d %s\n", pc, code->opcode,
995 code->op ? code->op->name : "**");
996 }
997 cpu.stats[code->opcode]++;
998
999 #endif
1000
1001 cycles += code->cycles;
1002 insts++;
1003 switch (code->opcode)
1004 {
1005 case 0:
1006 /*
1007 * This opcode is a fake for when we get to an
1008 * instruction which hasnt been compiled
1009 */
1010 compile (pc);
1011 goto top;
1012 break;
1013
1014
1015 case O (O_SUBX, SB):
1016 rd = fetch (&code->dst);
1017 ea = fetch (&code->src);
1018 ea = -(ea + C);
1019 res = rd + ea;
1020 goto alu8;
1021
1022 case O (O_ADDX, SB):
1023 rd = fetch (&code->dst);
1024 ea = fetch (&code->src);
1025 ea = C + ea;
1026 res = rd + ea;
1027 goto alu8;
1028
1029 #define EA ea = fetch(&code->src);
1030 #define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst);
1031
1032 ALUOP (1, O_SUB, RD_EA;
1033 ea = -ea;
1034 res = rd + ea);
1035 ALUOP (1, O_NEG, EA;
1036 ea = -ea;
1037 rd = 0;
1038 res = rd + ea);
1039
1040 case O (O_ADD, SB):
1041 rd = GET_B_REG (code->dst.reg);
1042 ea = fetch (&code->src);
1043 res = rd + ea;
1044 goto alu8;
1045 case O (O_ADD, SW):
1046 rd = GET_W_REG (code->dst.reg);
1047 ea = fetch (&code->src);
1048 res = rd + ea;
1049 goto alu16;
1050 case O (O_ADD, SL):
1051 rd = GET_L_REG (code->dst.reg);
1052 ea = fetch (&code->src);
1053 res = rd + ea;
1054 goto alu32;
1055
1056
1057 LOGOP (O_AND, RD_EA;
1058 res = rd & ea);
1059
1060 LOGOP (O_OR, RD_EA;
1061 res = rd | ea);
1062
1063 LOGOP (O_XOR, RD_EA;
1064 res = rd ^ ea);
1065
1066
1067 case O (O_MOV_TO_MEM, SB):
1068 res = GET_B_REG (code->src.reg);
1069 goto log8;
1070 case O (O_MOV_TO_MEM, SW):
1071 res = GET_W_REG (code->src.reg);
1072 goto log16;
1073 case O (O_MOV_TO_MEM, SL):
1074 res = GET_L_REG (code->src.reg);
1075 goto log32;
1076
1077
1078 case O (O_MOV_TO_REG, SB):
1079 res = fetch (&code->src);
1080 SET_B_REG (code->dst.reg, res);
1081 goto just_flags_log8;
1082 case O (O_MOV_TO_REG, SW):
1083 res = fetch (&code->src);
1084 SET_W_REG (code->dst.reg, res);
1085 goto just_flags_log16;
1086 case O (O_MOV_TO_REG, SL):
1087 res = fetch (&code->src);
1088 SET_L_REG (code->dst.reg, res);
1089 goto just_flags_log32;
1090
1091
1092 case O (O_ADDS, SL):
1093 SET_L_REG (code->dst.reg,
1094 GET_L_REG (code->dst.reg)
1095 + code->src.literal);
1096
1097 goto next;
1098
1099 case O (O_SUBS, SL):
1100 SET_L_REG (code->dst.reg,
1101 GET_L_REG (code->dst.reg)
1102 - code->src.literal);
1103 goto next;
1104
1105 case O (O_CMP, SB):
1106 rd = fetch (&code->dst);
1107 ea = fetch (&code->src);
1108 ea = -ea;
1109 res = rd + ea;
1110 goto just_flags_alu8;
1111
1112 case O (O_CMP, SW):
1113 rd = fetch (&code->dst);
1114 ea = fetch (&code->src);
1115 ea = -ea;
1116 res = rd + ea;
1117 goto just_flags_alu16;
1118
1119 case O (O_CMP, SL):
1120 rd = fetch (&code->dst);
1121 ea = fetch (&code->src);
1122 ea = -ea;
1123 res = rd + ea;
1124 goto just_flags_alu32;
1125
1126
1127 case O (O_DEC, SB):
1128 rd = GET_B_REG (code->src.reg);
1129 ea = -1;
1130 res = rd + ea;
1131 SET_B_REG (code->src.reg, res);
1132 goto just_flags_inc8;
1133
1134 case O (O_DEC, SW):
1135 rd = GET_W_REG (code->dst.reg);
1136 ea = -code->src.literal;
1137 res = rd + ea;
1138 SET_W_REG (code->dst.reg, res);
1139 goto just_flags_inc16;
1140
1141 case O (O_DEC, SL):
1142 rd = GET_L_REG (code->dst.reg);
1143 ea = -code->src.literal;
1144 res = rd + ea;
1145 SET_L_REG (code->dst.reg, res);
1146 goto just_flags_inc32;
1147
1148
1149 case O (O_INC, SB):
1150 rd = GET_B_REG (code->src.reg);
1151 ea = 1;
1152 res = rd + ea;
1153 SET_B_REG (code->src.reg, res);
1154 goto just_flags_inc8;
1155
1156 case O (O_INC, SW):
1157 rd = GET_W_REG (code->dst.reg);
1158 ea = code->src.literal;
1159 res = rd + ea;
1160 SET_W_REG (code->dst.reg, res);
1161 goto just_flags_inc16;
1162
1163 case O (O_INC, SL):
1164 rd = GET_L_REG (code->dst.reg);
1165 ea = code->src.literal;
1166 res = rd + ea;
1167 SET_L_REG (code->dst.reg, res);
1168 goto just_flags_inc32;
1169
1170
1171 #define GET_CCR(x) BUILDSR();x = cpu.ccr
1172
1173 case O (O_ANDC, SB):
1174 GET_CCR (rd);
1175 ea = code->src.literal;
1176 res = rd & ea;
1177 goto setc;
1178
1179 case O (O_ORC, SB):
1180 GET_CCR (rd);
1181 ea = code->src.literal;
1182 res = rd | ea;
1183 goto setc;
1184
1185 case O (O_XORC, SB):
1186 GET_CCR (rd);
1187 ea = code->src.literal;
1188 res = rd ^ ea;
1189 goto setc;
1190
1191
1192 case O (O_BRA, SB):
1193 if (1)
1194 goto condtrue;
1195 goto next;
1196
1197 case O (O_BRN, SB):
1198 if (0)
1199 goto condtrue;
1200 goto next;
1201
1202 case O (O_BHI, SB):
1203 if ((C || Z) == 0)
1204 goto condtrue;
1205 goto next;
1206
1207
1208 case O (O_BLS, SB):
1209 if ((C || Z))
1210 goto condtrue;
1211 goto next;
1212
1213 case O (O_BCS, SB):
1214 if ((C == 1))
1215 goto condtrue;
1216 goto next;
1217
1218 case O (O_BCC, SB):
1219 if ((C == 0))
1220 goto condtrue;
1221 goto next;
1222
1223 case O (O_BEQ, SB):
1224 if (Z)
1225 goto condtrue;
1226 goto next;
1227 case O (O_BGT, SB):
1228 if (((Z || (N ^ V)) == 0))
1229 goto condtrue;
1230 goto next;
1231
1232
1233 case O (O_BLE, SB):
1234 if (((Z || (N ^ V)) == 1))
1235 goto condtrue;
1236 goto next;
1237
1238 case O (O_BGE, SB):
1239 if ((N ^ V) == 0)
1240 goto condtrue;
1241 goto next;
1242 case O (O_BLT, SB):
1243 if ((N ^ V))
1244 goto condtrue;
1245 goto next;
1246 case O (O_BMI, SB):
1247 if ((N))
1248 goto condtrue;
1249 goto next;
1250 case O (O_BNE, SB):
1251 if ((Z == 0))
1252 goto condtrue;
1253 goto next;
1254
1255 case O (O_BPL, SB):
1256 if (N == 0)
1257 goto condtrue;
1258 goto next;
1259 case O (O_BVC, SB):
1260 if ((V == 0))
1261 goto condtrue;
1262 goto next;
1263 case O (O_BVS, SB):
1264 if ((V == 1))
1265 goto condtrue;
1266 goto next;
1267
1268 case O (O_SYSCALL, SB):
1269 {
1270 char c = cpu.regs[2];
1271 sim_callback->write_stdout (sim_callback, &c, 1);
1272 }
1273 goto next;
1274
1275 ONOT (O_NOT, rd = ~rd; v = 0;);
1276 OSHIFTS (O_SHLL,
1277 c = rd & hm; v = 0; rd <<= 1,
1278 c = rd & (hm >> 1); v = 0; rd <<= 2);
1279 OSHIFTS (O_SHLR,
1280 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1,
1281 c = rd & 2; v = 0; rd = (unsigned int) rd >> 2);
1282 OSHIFTS (O_SHAL,
1283 c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1,
1284 c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2);
1285 OSHIFTS (O_SHAR,
1286 t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t,
1287 t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 );
1288 OSHIFTS (O_ROTL,
1289 c = rd & hm; v = 0; rd <<= 1; rd |= C,
1290 c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C);
1291 OSHIFTS (O_ROTR,
1292 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm,
1293 c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm);
1294 OSHIFTS (O_ROTXL,
1295 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0,
1296 t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t);
1297 OSHIFTS (O_ROTXR,
1298 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0,
1299 t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t);
1300
1301 case O (O_JMP, SB):
1302 {
1303 pc = fetch (&code->src);
1304 goto end;
1305
1306 }
1307
1308 case O (O_JSR, SB):
1309 {
1310 int tmp;
1311 pc = fetch (&code->src);
1312 call:
1313 tmp = cpu.regs[7];
1314
1315 if (h8300hmode)
1316 {
1317 tmp -= 4;
1318 SET_MEMORY_L (tmp, code->next_pc);
1319 }
1320 else
1321 {
1322 tmp -= 2;
1323 SET_MEMORY_W (tmp, code->next_pc);
1324 }
1325 cpu.regs[7] = tmp;
1326
1327 goto end;
1328 }
1329 case O (O_BSR, SB):
1330 pc = code->src.literal;
1331 goto call;
1332
1333 case O (O_RTS, SN):
1334 {
1335 int tmp;
1336
1337 tmp = cpu.regs[7];
1338
1339 if (h8300hmode)
1340 {
1341 pc = GET_MEMORY_L (tmp);
1342 tmp += 4;
1343 }
1344 else
1345 {
1346 pc = GET_MEMORY_W (tmp);
1347 tmp += 2;
1348 }
1349
1350 cpu.regs[7] = tmp;
1351 goto end;
1352 }
1353
1354 case O (O_ILL, SB):
1355 cpu.state = SIM_STATE_STOPPED;
1356 cpu.exception = SIGILL;
1357 goto end;
1358 case O (O_SLEEP, SN):
1359 /* FIXME: Doesn't this break for breakpoints when r0
1360 contains just the right (er, wrong) value? */
1361 cpu.state = SIM_STATE_STOPPED;
1362 /* The format of r0 is defined by target newlib. Expand
1363 the macros here instead of looking for .../sys/wait.h. */
1364 #define SIM_WIFEXITED(v) (((v) & 0xff) == 0)
1365 #define SIM_WIFSIGNALED(v) (((v) & 0x7f) > 0 && (((v) & 0x7f) < 0x7f))
1366 if (! SIM_WIFEXITED (cpu.regs[0]) && SIM_WIFSIGNALED (cpu.regs[0]))
1367 cpu.exception = SIGILL;
1368 else
1369 cpu.exception = SIGTRAP;
1370 goto end;
1371 case O (O_BPT, SN):
1372 cpu.state = SIM_STATE_STOPPED;
1373 cpu.exception = SIGTRAP;
1374 goto end;
1375
1376 OBITOP (O_BNOT, 1, 1, ea ^= m);
1377 OBITOP (O_BTST, 1, 0, nz = ea & m);
1378 OBITOP (O_BCLR, 1, 1, ea &= ~m);
1379 OBITOP (O_BSET, 1, 1, ea |= m);
1380 OBITOP (O_BLD, 1, 0, c = ea & m);
1381 OBITOP (O_BILD, 1, 0, c = !(ea & m));
1382 OBITOP (O_BST, 1, 1, ea &= ~m;
1383 if (C) ea |= m);
1384 OBITOP (O_BIST, 1, 1, ea &= ~m;
1385 if (!C) ea |= m);
1386 OBITOP (O_BAND, 1, 0, c = (ea & m) && C);
1387 OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C);
1388 OBITOP (O_BOR, 1, 0, c = (ea & m) || C);
1389 OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C);
1390 OBITOP (O_BXOR, 1, 0, c = (ea & m) != C);
1391 OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C);
1392
1393
1394 #define MOP(bsize, signed) mop(code, bsize,signed); goto next;
1395
1396 case O (O_MULS, SB):
1397 MOP (1, 1);
1398 break;
1399 case O (O_MULS, SW):
1400 MOP (0, 1);
1401 break;
1402 case O (O_MULU, SB):
1403 MOP (1, 0);
1404 break;
1405 case O (O_MULU, SW):
1406 MOP (0, 0);
1407 break;
1408
1409
1410 case O (O_DIVU, SB):
1411 {
1412 rd = GET_W_REG (code->dst.reg);
1413 ea = GET_B_REG (code->src.reg);
1414 if (ea)
1415 {
1416 tmp = (unsigned)rd % ea;
1417 rd = (unsigned)rd / ea;
1418 }
1419 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1420 n = ea & 0x80;
1421 nz = ea & 0xff;
1422
1423 goto next;
1424 }
1425 case O (O_DIVU, SW):
1426 {
1427 rd = GET_L_REG (code->dst.reg);
1428 ea = GET_W_REG (code->src.reg);
1429 n = ea & 0x8000;
1430 nz = ea & 0xffff;
1431 if (ea)
1432 {
1433 tmp = (unsigned)rd % ea;
1434 rd = (unsigned)rd / ea;
1435 }
1436 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1437 goto next;
1438 }
1439
1440 case O (O_DIVS, SB):
1441 {
1442
1443 rd = SEXTSHORT (GET_W_REG (code->dst.reg));
1444 ea = SEXTCHAR (GET_B_REG (code->src.reg));
1445 if (ea)
1446 {
1447 tmp = (int) rd % (int) ea;
1448 rd = (int) rd / (int) ea;
1449 n = rd & 0x8000;
1450 nz = 1;
1451 }
1452 else
1453 nz = 0;
1454 SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8));
1455 goto next;
1456 }
1457 case O (O_DIVS, SW):
1458 {
1459 rd = GET_L_REG (code->dst.reg);
1460 ea = SEXTSHORT (GET_W_REG (code->src.reg));
1461 if (ea)
1462 {
1463 tmp = (int) rd % (int) ea;
1464 rd = (int) rd / (int) ea;
1465 n = rd & 0x80000000;
1466 nz = 1;
1467 }
1468 else
1469 nz = 0;
1470 SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16));
1471 goto next;
1472 }
1473 case O (O_EXTS, SW):
1474 rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */
1475 ea = rd & 0x80 ? -256 : 0;
1476 res = rd + ea;
1477 goto log16;
1478 case O (O_EXTS, SL):
1479 rd = GET_W_REG (code->src.reg) & 0xffff;
1480 ea = rd & 0x8000 ? -65536 : 0;
1481 res = rd + ea;
1482 goto log32;
1483 case O (O_EXTU, SW):
1484 rd = GET_B_REG (code->src.reg + 8) & 0xff;
1485 ea = 0;
1486 res = rd + ea;
1487 goto log16;
1488 case O (O_EXTU, SL):
1489 rd = GET_W_REG (code->src.reg) & 0xffff;
1490 ea = 0;
1491 res = rd + ea;
1492 goto log32;
1493
1494 case O (O_NOP, SN):
1495 goto next;
1496
1497 case O (O_STM, SL):
1498 {
1499 int nregs, firstreg, i;
1500
1501 nregs = GET_MEMORY_B (pc + 1);
1502 nregs >>= 4;
1503 nregs &= 0xf;
1504 firstreg = GET_MEMORY_B (pc + 3);
1505 firstreg &= 0xf;
1506 for (i = firstreg; i <= firstreg + nregs; i++)
1507 {
1508 cpu.regs[7] -= 4;
1509 SET_MEMORY_L (cpu.regs[7], cpu.regs[i]);
1510 }
1511 }
1512 goto next;
1513
1514 case O (O_LDM, SL):
1515 {
1516 int nregs, firstreg, i;
1517
1518 nregs = GET_MEMORY_B (pc + 1);
1519 nregs >>= 4;
1520 nregs &= 0xf;
1521 firstreg = GET_MEMORY_B (pc + 3);
1522 firstreg &= 0xf;
1523 for (i = firstreg; i >= firstreg - nregs; i--)
1524 {
1525 cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]);
1526 cpu.regs[7] += 4;
1527 }
1528 }
1529 goto next;
1530
1531 default:
1532 cpu.state = SIM_STATE_STOPPED;
1533 cpu.exception = SIGILL;
1534 goto end;
1535
1536 }
1537 abort ();
1538
1539 setc:
1540 cpu.ccr = res;
1541 GETSR ();
1542 goto next;
1543
1544 condtrue:
1545 /* When a branch works */
1546 pc = code->src.literal;
1547 goto end;
1548
1549 /* Set the cond codes from res */
1550 bitop:
1551
1552 /* Set the flags after an 8 bit inc/dec operation */
1553 just_flags_inc8:
1554 n = res & 0x80;
1555 nz = res & 0xff;
1556 v = (rd & 0x7f) == 0x7f;
1557 goto next;
1558
1559
1560 /* Set the flags after an 16 bit inc/dec operation */
1561 just_flags_inc16:
1562 n = res & 0x8000;
1563 nz = res & 0xffff;
1564 v = (rd & 0x7fff) == 0x7fff;
1565 goto next;
1566
1567
1568 /* Set the flags after an 32 bit inc/dec operation */
1569 just_flags_inc32:
1570 n = res & 0x80000000;
1571 nz = res & 0xffffffff;
1572 v = (rd & 0x7fffffff) == 0x7fffffff;
1573 goto next;
1574
1575
1576 shift8:
1577 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
1578 n = (rd & 0x80);
1579 nz = rd & 0xff;
1580 SET_B_REG (code->src.reg, rd);
1581 goto next;
1582
1583 shift16:
1584 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
1585 n = (rd & 0x8000);
1586 nz = rd & 0xffff;
1587 SET_W_REG (code->src.reg, rd);
1588 goto next;
1589
1590 shift32:
1591 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
1592 n = (rd & 0x80000000);
1593 nz = rd & 0xffffffff;
1594 SET_L_REG (code->src.reg, rd);
1595 goto next;
1596
1597 log32:
1598 store (&code->dst, res);
1599 just_flags_log32:
1600 /* flags after a 32bit logical operation */
1601 n = res & 0x80000000;
1602 nz = res & 0xffffffff;
1603 v = 0;
1604 goto next;
1605
1606 log16:
1607 store (&code->dst, res);
1608 just_flags_log16:
1609 /* flags after a 16bit logical operation */
1610 n = res & 0x8000;
1611 nz = res & 0xffff;
1612 v = 0;
1613 goto next;
1614
1615
1616 log8:
1617 store (&code->dst, res);
1618 just_flags_log8:
1619 n = res & 0x80;
1620 nz = res & 0xff;
1621 v = 0;
1622 goto next;
1623
1624 alu8:
1625 SET_B_REG (code->dst.reg, res);
1626 just_flags_alu8:
1627 n = res & 0x80;
1628 nz = res & 0xff;
1629 c = (res & 0x100);
1630 switch (code->opcode / 4)
1631 {
1632 case O_ADD:
1633 v = ((rd & 0x80) == (ea & 0x80)
1634 && (rd & 0x80) != (res & 0x80));
1635 break;
1636 case O_SUB:
1637 case O_CMP:
1638 v = ((rd & 0x80) != (-ea & 0x80)
1639 && (rd & 0x80) != (res & 0x80));
1640 break;
1641 case O_NEG:
1642 v = (rd == 0x80);
1643 break;
1644 }
1645 goto next;
1646
1647 alu16:
1648 SET_W_REG (code->dst.reg, res);
1649 just_flags_alu16:
1650 n = res & 0x8000;
1651 nz = res & 0xffff;
1652 c = (res & 0x10000);
1653 switch (code->opcode / 4)
1654 {
1655 case O_ADD:
1656 v = ((rd & 0x8000) == (ea & 0x8000)
1657 && (rd & 0x8000) != (res & 0x8000));
1658 break;
1659 case O_SUB:
1660 case O_CMP:
1661 v = ((rd & 0x8000) != (-ea & 0x8000)
1662 && (rd & 0x8000) != (res & 0x8000));
1663 break;
1664 case O_NEG:
1665 v = (rd == 0x8000);
1666 break;
1667 }
1668 goto next;
1669
1670 alu32:
1671 SET_L_REG (code->dst.reg, res);
1672 just_flags_alu32:
1673 n = res & 0x80000000;
1674 nz = res & 0xffffffff;
1675 switch (code->opcode / 4)
1676 {
1677 case O_ADD:
1678 v = ((rd & 0x80000000) == (ea & 0x80000000)
1679 && (rd & 0x80000000) != (res & 0x80000000));
1680 c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea);
1681 break;
1682 case O_SUB:
1683 case O_CMP:
1684 v = ((rd & 0x80000000) != (-ea & 0x80000000)
1685 && (rd & 0x80000000) != (res & 0x80000000));
1686 c = (unsigned) rd < (unsigned) -ea;
1687 break;
1688 case O_NEG:
1689 v = (rd == 0x80000000);
1690 c = res != 0;
1691 break;
1692 }
1693 goto next;
1694
1695 next:;
1696 pc = code->next_pc;
1697
1698 end:
1699 ;
1700 /* if (cpu.regs[8] ) abort(); */
1701
1702 if (--poll_count < 0)
1703 {
1704 poll_count = POLL_QUIT_INTERVAL;
1705 if ((*sim_callback->poll_quit) != NULL
1706 && (*sim_callback->poll_quit) (sim_callback))
1707 sim_stop (sd);
1708 }
1709
1710 }
1711 while (cpu.state == SIM_STATE_RUNNING);
1712 cpu.ticks += get_now () - tick_start;
1713 cpu.cycles += cycles;
1714 cpu.insts += insts;
1715
1716 cpu.pc = pc;
1717 BUILDSR ();
1718 cpu.mask = oldmask;
1719 signal (SIGINT, prev);
1720 }
1721
1722 int
1723 sim_trace (sd)
1724 SIM_DESC sd;
1725 {
1726 /* FIXME: Unfinished. */
1727 abort ();
1728 }
1729
1730 int
1731 sim_write (sd, addr, buffer, size)
1732 SIM_DESC sd;
1733 SIM_ADDR addr;
1734 unsigned char *buffer;
1735 int size;
1736 {
1737 int i;
1738
1739 init_pointers ();
1740 if (addr < 0)
1741 return 0;
1742 for (i = 0; i < size; i++)
1743 {
1744 if (addr < memory_size)
1745 {
1746 cpu.memory[addr + i] = buffer[i];
1747 cpu.cache_idx[addr + i] = 0;
1748 }
1749 else
1750 cpu.eightbit[(addr + i) & 0xff] = buffer[i];
1751 }
1752 return size;
1753 }
1754
1755 int
1756 sim_read (sd, addr, buffer, size)
1757 SIM_DESC sd;
1758 SIM_ADDR addr;
1759 unsigned char *buffer;
1760 int size;
1761 {
1762 init_pointers ();
1763 if (addr < 0)
1764 return 0;
1765 if (addr < memory_size)
1766 memcpy (buffer, cpu.memory + addr, size);
1767 else
1768 memcpy (buffer, cpu.eightbit + (addr & 0xff), size);
1769 return size;
1770 }
1771
1772
1773 #define R0_REGNUM 0
1774 #define R1_REGNUM 1
1775 #define R2_REGNUM 2
1776 #define R3_REGNUM 3
1777 #define R4_REGNUM 4
1778 #define R5_REGNUM 5
1779 #define R6_REGNUM 6
1780 #define R7_REGNUM 7
1781
1782 #define SP_REGNUM R7_REGNUM /* Contains address of top of stack */
1783 #define FP_REGNUM R6_REGNUM /* Contains address of executing
1784 * stack frame */
1785
1786 #define CCR_REGNUM 8 /* Contains processor status */
1787 #define PC_REGNUM 9 /* Contains program counter */
1788
1789 #define CYCLE_REGNUM 10
1790 #define INST_REGNUM 11
1791 #define TICK_REGNUM 12
1792
1793
1794 int
1795 sim_store_register (sd, rn, value, length)
1796 SIM_DESC sd;
1797 int rn;
1798 unsigned char *value;
1799 int length;
1800 {
1801 int longval;
1802 int shortval;
1803 int intval;
1804 longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3];
1805 shortval = (value[0] << 8) | (value[1]);
1806 intval = h8300hmode ? longval : shortval;
1807
1808 init_pointers ();
1809 switch (rn)
1810 {
1811 case PC_REGNUM:
1812 cpu.pc = intval;
1813 break;
1814 default:
1815 abort ();
1816 case R0_REGNUM:
1817 case R1_REGNUM:
1818 case R2_REGNUM:
1819 case R3_REGNUM:
1820 case R4_REGNUM:
1821 case R5_REGNUM:
1822 case R6_REGNUM:
1823 case R7_REGNUM:
1824 cpu.regs[rn] = intval;
1825 break;
1826 case CCR_REGNUM:
1827 cpu.ccr = intval;
1828 break;
1829 case CYCLE_REGNUM:
1830 cpu.cycles = longval;
1831 break;
1832
1833 case INST_REGNUM:
1834 cpu.insts = longval;
1835 break;
1836
1837 case TICK_REGNUM:
1838 cpu.ticks = longval;
1839 break;
1840 }
1841 return -1;
1842 }
1843
1844 int
1845 sim_fetch_register (sd, rn, buf, length)
1846 SIM_DESC sd;
1847 int rn;
1848 unsigned char *buf;
1849 int length;
1850 {
1851 int v;
1852 int longreg = 0;
1853
1854 init_pointers ();
1855
1856 switch (rn)
1857 {
1858 default:
1859 abort ();
1860 case 8:
1861 v = cpu.ccr;
1862 break;
1863 case 9:
1864 v = cpu.pc;
1865 break;
1866 case R0_REGNUM:
1867 case R1_REGNUM:
1868 case R2_REGNUM:
1869 case R3_REGNUM:
1870 case R4_REGNUM:
1871 case R5_REGNUM:
1872 case R6_REGNUM:
1873 case R7_REGNUM:
1874 v = cpu.regs[rn];
1875 break;
1876 case 10:
1877 v = cpu.cycles;
1878 longreg = 1;
1879 break;
1880 case 11:
1881 v = cpu.ticks;
1882 longreg = 1;
1883 break;
1884 case 12:
1885 v = cpu.insts;
1886 longreg = 1;
1887 break;
1888 }
1889 if (h8300hmode || longreg)
1890 {
1891 buf[0] = v >> 24;
1892 buf[1] = v >> 16;
1893 buf[2] = v >> 8;
1894 buf[3] = v >> 0;
1895 }
1896 else
1897 {
1898 buf[0] = v >> 8;
1899 buf[1] = v;
1900 }
1901 return -1;
1902 }
1903
1904 void
1905 sim_stop_reason (sd, reason, sigrc)
1906 SIM_DESC sd;
1907 enum sim_stop *reason;
1908 int *sigrc;
1909 {
1910 #if 0 /* FIXME: This should work but we can't use it.
1911 grep for SLEEP above. */
1912 switch (cpu.state)
1913 {
1914 case SIM_STATE_EXITED : *reason = sim_exited; break;
1915 case SIM_STATE_SIGNALLED : *reason = sim_signalled; break;
1916 case SIM_STATE_STOPPED : *reason = sim_stopped; break;
1917 default : abort ();
1918 }
1919 #else
1920 *reason = sim_stopped;
1921 #endif
1922 *sigrc = cpu.exception;
1923 }
1924
1925 /* FIXME: Rename to sim_set_mem_size. */
1926
1927 void
1928 sim_size (n)
1929 int n;
1930 {
1931 /* Memory size is fixed. */
1932 }
1933
1934 void
1935 sim_set_simcache_size (n)
1936 {
1937 if (cpu.cache)
1938 free (cpu.cache);
1939 if (n < 2)
1940 n = 2;
1941 cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n);
1942 memset (cpu.cache, 0, sizeof (decoded_inst) * n);
1943 cpu.csize = n;
1944 }
1945
1946
1947 void
1948 sim_info (sd, verbose)
1949 SIM_DESC sd;
1950 int verbose;
1951 {
1952 double timetaken = (double) cpu.ticks / (double) now_persec ();
1953 double virttime = cpu.cycles / 10.0e6;
1954
1955 (*sim_callback->printf_filtered) (sim_callback,
1956 "\n\n#instructions executed %10d\n",
1957 cpu.insts);
1958 (*sim_callback->printf_filtered) (sim_callback,
1959 "#cycles (v approximate) %10d\n",
1960 cpu.cycles);
1961 (*sim_callback->printf_filtered) (sim_callback,
1962 "#real time taken %10.4f\n",
1963 timetaken);
1964 (*sim_callback->printf_filtered) (sim_callback,
1965 "#virtual time taked %10.4f\n",
1966 virttime);
1967 if (timetaken != 0.0)
1968 (*sim_callback->printf_filtered) (sim_callback,
1969 "#simulation ratio %10.4f\n",
1970 virttime / timetaken);
1971 (*sim_callback->printf_filtered) (sim_callback,
1972 "#compiles %10d\n",
1973 cpu.compiles);
1974 (*sim_callback->printf_filtered) (sim_callback,
1975 "#cache size %10d\n",
1976 cpu.csize);
1977
1978 #ifdef ADEBUG
1979 /* This to be conditional on `what' (aka `verbose'),
1980 however it was never passed as non-zero. */
1981 if (1)
1982 {
1983 int i;
1984 for (i = 0; i < O_LAST; i++)
1985 {
1986 if (cpu.stats[i])
1987 (*sim_callback->printf_filtered) (sim_callback,
1988 "%d: %d\n", i, cpu.stats[i]);
1989 }
1990 }
1991 #endif
1992 }
1993
1994 /* Indicate whether the cpu is an H8/300 or H8/300H.
1995 FLAG is non-zero for the H8/300H. */
1996
1997 void
1998 set_h8300h (flag)
1999 int flag;
2000 {
2001 /* FIXME: Much of the code in sim_load can be moved to sim_open.
2002 This function being replaced by a sim_open:ARGV configuration
2003 option. */
2004 h8300hmode = flag;
2005 }
2006
2007 SIM_DESC
2008 sim_open (kind, ptr, abfd, argv)
2009 SIM_OPEN_KIND kind;
2010 struct host_callback_struct *ptr;
2011 struct _bfd *abfd;
2012 char **argv;
2013 {
2014 /* FIXME: Much of the code in sim_load can be moved here. */
2015
2016 sim_kind = kind;
2017 myname = argv[0];
2018 sim_callback = ptr;
2019 /* Fudge our descriptor. */
2020 return (SIM_DESC) 1;
2021 }
2022
2023 void
2024 sim_close (sd, quitting)
2025 SIM_DESC sd;
2026 int quitting;
2027 {
2028 /* Nothing to do. */
2029 }
2030
2031 /* Called by gdb to load a program into memory. */
2032
2033 SIM_RC
2034 sim_load (sd, prog, abfd, from_tty)
2035 SIM_DESC sd;
2036 char *prog;
2037 bfd *abfd;
2038 int from_tty;
2039 {
2040 bfd *prog_bfd;
2041
2042 /* FIXME: The code below that sets a specific variant of the H8/300
2043 being simulated should be moved to sim_open(). */
2044
2045 /* See if the file is for the H8/300 or H8/300H. */
2046 /* ??? This may not be the most efficient way. The z8k simulator
2047 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
2048 if (abfd != NULL)
2049 prog_bfd = abfd;
2050 else
2051 prog_bfd = bfd_openr (prog, "coff-h8300");
2052 if (prog_bfd != NULL)
2053 {
2054 /* Set the cpu type. We ignore failure from bfd_check_format
2055 and bfd_openr as sim_load_file checks too. */
2056 if (bfd_check_format (prog_bfd, bfd_object))
2057 {
2058 unsigned long mach = bfd_get_mach (prog_bfd);
2059 set_h8300h (mach == bfd_mach_h8300h
2060 || mach == bfd_mach_h8300s);
2061 }
2062 }
2063
2064 /* If we're using gdb attached to the simulator, then we have to
2065 reallocate memory for the simulator.
2066
2067 When gdb first starts, it calls fetch_registers (among other
2068 functions), which in turn calls init_pointers, which allocates
2069 simulator memory.
2070
2071 The problem is when we do that, we don't know whether we're
2072 debugging an H8/300 or H8/300H program.
2073
2074 This is the first point at which we can make that determination,
2075 so we just reallocate memory now; this will also allow us to handle
2076 switching between H8/300 and H8/300H programs without exiting
2077 gdb. */
2078 if (h8300hmode)
2079 memory_size = H8300H_MSIZE;
2080 else
2081 memory_size = H8300_MSIZE;
2082
2083 if (cpu.memory)
2084 free (cpu.memory);
2085 if (cpu.cache_idx)
2086 free (cpu.cache_idx);
2087 if (cpu.eightbit)
2088 free (cpu.eightbit);
2089
2090 cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size);
2091 cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size);
2092 cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256);
2093
2094 /* `msize' must be a power of two. */
2095 if ((memory_size & (memory_size - 1)) != 0)
2096 abort ();
2097 cpu.mask = memory_size - 1;
2098
2099 if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd,
2100 sim_kind == SIM_OPEN_DEBUG,
2101 0, sim_write)
2102 == NULL)
2103 {
2104 /* Close the bfd if we opened it. */
2105 if (abfd == NULL && prog_bfd != NULL)
2106 bfd_close (prog_bfd);
2107 return SIM_RC_FAIL;
2108 }
2109
2110 /* Close the bfd if we opened it. */
2111 if (abfd == NULL && prog_bfd != NULL)
2112 bfd_close (prog_bfd);
2113 return SIM_RC_OK;
2114 }
2115
2116 SIM_RC
2117 sim_create_inferior (sd, abfd, argv, env)
2118 SIM_DESC sd;
2119 struct _bfd *abfd;
2120 char **argv;
2121 char **env;
2122 {
2123 if (abfd != NULL)
2124 cpu.pc = bfd_get_start_address (abfd);
2125 else
2126 cpu.pc = 0;
2127 return SIM_RC_OK;
2128 }
2129
2130 void
2131 sim_do_command (sd, cmd)
2132 SIM_DESC sd;
2133 char *cmd;
2134 {
2135 (*sim_callback->printf_filtered) (sim_callback,
2136 "This simulator does not accept any commands.\n");
2137 }
2138
2139 void
2140 sim_set_callbacks (ptr)
2141 struct host_callback_struct *ptr;
2142 {
2143 sim_callback = ptr;
2144 }