2 * Simulator for the Renesas (formerly Hitachi) H8/300 architecture.
4 * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com
6 * This file is part of H8/300 sim
9 * THIS SOFTWARE IS NOT COPYRIGHTED
11 * Cygnus offers the following for use in the public domain. Cygnus makes no
12 * warranty with regard to the software or its performance and the user
13 * accepts the software "AS IS" with all faults.
15 * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS
16 * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS FOR A PARTICULAR PURPOSE.
24 #ifdef HAVE_SYS_PARAM_H
25 #include <sys/param.h>
30 #include "gdb/sim-h8300.h"
32 #include "sys/types.h"
33 #include "sim-options.h"
41 static int memory_size
;
43 #define X(op, size) (op * 4 + size)
45 #define SP (h8300hmode && !h8300_normal_mode ? SL : SW)
47 #define h8_opcodes ops
49 #include "opcode/h8300.h"
51 /* CPU data object: */
54 h8_get_pc (SIM_DESC sd
)
56 return (STATE_CPU (sd
, 0)) -> pc
;
60 h8_set_pc (SIM_DESC sd
, unsigned int val
)
62 (STATE_CPU (sd
, 0)) -> pc
= val
;
66 h8_get_ccr (SIM_DESC sd
)
68 return (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
];
72 h8_set_ccr (SIM_DESC sd
, unsigned int val
)
74 (STATE_CPU (sd
, 0)) -> regs
[CCR_REGNUM
] = val
;
78 h8_get_exr (SIM_DESC sd
)
80 return (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
];
84 h8_set_exr (SIM_DESC sd
, unsigned int val
)
86 (STATE_CPU (sd
, 0)) -> regs
[EXR_REGNUM
] = val
;
90 h8_get_sbr (SIM_DESC sd
)
92 return (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
];
96 h8_set_sbr (SIM_DESC sd
, int val
)
98 (STATE_CPU (sd
, 0)) -> regs
[SBR_REGNUM
] = val
;
102 h8_get_vbr (SIM_DESC sd
)
104 return (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
];
108 h8_set_vbr (SIM_DESC sd
, int val
)
110 (STATE_CPU (sd
, 0)) -> regs
[VBR_REGNUM
] = val
;
114 h8_get_mask (SIM_DESC sd
)
116 return (STATE_CPU (sd
, 0)) -> mask
;
120 h8_set_mask (SIM_DESC sd
, int val
)
122 (STATE_CPU (sd
, 0)) -> mask
= val
;
126 h8_get_exception (SIM_DESC sd
)
128 return (STATE_CPU (sd
, 0)) -> exception
;
132 h8_set_exception (SIM_DESC sd
, int val
)
134 (STATE_CPU (sd
, 0)) -> exception
= val
;
137 static enum h8300_sim_state
138 h8_get_state (SIM_DESC sd
)
144 h8_set_state (SIM_DESC sd
, enum h8300_sim_state val
)
150 h8_get_cycles (SIM_DESC sd
)
152 return (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
];
156 h8_set_cycles (SIM_DESC sd
, unsigned int val
)
158 (STATE_CPU (sd
, 0)) -> regs
[CYCLE_REGNUM
] = val
;
162 h8_get_insts (SIM_DESC sd
)
164 return (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
];
168 h8_set_insts (SIM_DESC sd
, unsigned int val
)
170 (STATE_CPU (sd
, 0)) -> regs
[INST_REGNUM
] = val
;
174 h8_get_ticks (SIM_DESC sd
)
176 return (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
];
180 h8_set_ticks (SIM_DESC sd
, unsigned int val
)
182 (STATE_CPU (sd
, 0)) -> regs
[TICK_REGNUM
] = val
;
186 h8_get_mach (SIM_DESC sd
)
188 return (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
];
192 h8_set_mach (SIM_DESC sd
, unsigned int val
)
194 (STATE_CPU (sd
, 0)) -> regs
[MACH_REGNUM
] = val
;
198 h8_get_macl (SIM_DESC sd
)
200 return (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
];
204 h8_set_macl (SIM_DESC sd
, unsigned int val
)
206 (STATE_CPU (sd
, 0)) -> regs
[MACL_REGNUM
] = val
;
209 static unsigned int *
210 h8_get_reg_buf (SIM_DESC sd
)
212 return &(((STATE_CPU (sd
, 0)) -> regs
)[0]);
216 h8_get_reg (SIM_DESC sd
, int regnum
)
218 return (STATE_CPU (sd
, 0)) -> regs
[regnum
];
222 h8_set_reg (SIM_DESC sd
, int regnum
, int val
)
224 (STATE_CPU (sd
, 0)) -> regs
[regnum
] = val
;
229 h8_get_stats (SIM_DESC sd
, int idx
)
231 return sd
-> stats
[idx
];
235 h8_increment_stats (SIM_DESC sd
, int idx
)
241 static unsigned char *
242 h8_get_memory_buf (SIM_DESC sd
)
244 return (STATE_CPU (sd
, 0)) -> memory
;
248 h8_set_memory_buf (SIM_DESC sd
, unsigned char *ptr
)
250 (STATE_CPU (sd
, 0)) -> memory
= ptr
;
254 h8_get_memory (SIM_DESC sd
, int idx
)
256 ASSERT (idx
< memory_size
);
257 return (STATE_CPU (sd
, 0)) -> memory
[idx
];
261 h8_set_memory (SIM_DESC sd
, int idx
, unsigned int val
)
263 ASSERT (idx
< memory_size
);
264 (STATE_CPU (sd
, 0)) -> memory
[idx
] = (unsigned char) val
;
268 h8_get_delayed_branch (SIM_DESC sd
)
270 return (STATE_CPU (sd
, 0)) -> delayed_branch
;
274 h8_set_delayed_branch (SIM_DESC sd
, unsigned int dest
)
276 (STATE_CPU (sd
, 0)) -> delayed_branch
= dest
;
280 h8_get_command_line (SIM_DESC sd
)
282 return (STATE_CPU (sd
, 0)) -> command_line
;
286 h8_set_command_line (SIM_DESC sd
, char ** val
)
288 (STATE_CPU (sd
, 0)) -> command_line
= val
;
292 h8_get_cmdline_arg (SIM_DESC sd
, int index
)
294 return (STATE_CPU (sd
, 0)) -> command_line
[index
];
298 h8_set_cmdline_arg (SIM_DESC sd
, int index
, char * val
)
300 (STATE_CPU (sd
, 0)) -> command_line
[index
] = val
;
303 /* MAC Saturation Mode */
305 h8_get_macS (SIM_DESC sd
)
307 return (STATE_CPU (sd
, 0)) -> macS
;
311 h8_set_macS (SIM_DESC sd
, int val
)
313 (STATE_CPU (sd
, 0)) -> macS
= (val
!= 0);
318 h8_get_macZ (SIM_DESC sd
)
320 return (STATE_CPU (sd
, 0)) -> macZ
;
324 h8_set_macZ (SIM_DESC sd
, int val
)
326 (STATE_CPU (sd
, 0)) -> macZ
= (val
!= 0);
329 /* MAC Negative Flag */
331 h8_get_macN (SIM_DESC sd
)
333 return (STATE_CPU (sd
, 0)) -> macN
;
337 h8_set_macN (SIM_DESC sd
, int val
)
339 (STATE_CPU (sd
, 0)) -> macN
= (val
!= 0);
342 /* MAC Overflow Flag */
344 h8_get_macV (SIM_DESC sd
)
346 return (STATE_CPU (sd
, 0)) -> macV
;
350 h8_set_macV (SIM_DESC sd
, int val
)
352 (STATE_CPU (sd
, 0)) -> macV
= (val
!= 0);
355 /* End CPU data object. */
357 /* The rate at which to call the host's poll_quit callback. */
359 enum { POLL_QUIT_INTERVAL
= 0x80000 };
361 #define LOW_BYTE(x) ((x) & 0xff)
362 #define HIGH_BYTE(x) (((x) >> 8) & 0xff)
363 #define P(X, Y) ((X << 8) | Y)
372 #define I (intMaskBit != 0)
374 #define BUILDSR(SD) \
375 h8_set_ccr (SD, (I << 7) | (UI << 6) | (H << 5) | (U << 4) \
376 | (N << 3) | (Z << 2) | (V << 1) | C)
379 /* Get Status Register (flags). */ \
380 c = (h8_get_ccr (sd) >> 0) & 1; \
381 v = (h8_get_ccr (sd) >> 1) & 1; \
382 nz = !((h8_get_ccr (sd) >> 2) & 1); \
383 n = (h8_get_ccr (sd) >> 3) & 1; \
384 u = (h8_get_ccr (sd) >> 4) & 1; \
385 h = (h8_get_ccr (sd) >> 5) & 1; \
386 ui = ((h8_get_ccr (sd) >> 6) & 1); \
387 intMaskBit = (h8_get_ccr (sd) >> 7) & 1
390 #ifdef __CHAR_IS_SIGNED__
391 #define SEXTCHAR(x) ((char) (x))
395 #define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff) : x & 0xff)
398 #define UEXTCHAR(x) ((x) & 0xff)
399 #define UEXTSHORT(x) ((x) & 0xffff)
400 #define SEXTSHORT(x) ((short) (x))
404 int h8300_normal_mode
= 0;
410 return time (0); /* WinXX HAS UNIX like 'time', so why not use it? */
432 return (h8300hmode
&& !h8300_normal_mode
)? SL
: SW
;
437 /* Simulate an indirection / dereference.
438 return 0 for success, -1 for failure.
442 lvalue (SIM_DESC sd
, int x
, int rn
, unsigned int *val
)
444 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
446 if (val
== NULL
) /* Paranoia. */
452 if (rn
== ZERO_REGNUM
)
453 *val
= X (OP_IMM
, SP
);
455 *val
= X (OP_REG
, SP
);
458 *val
= X (OP_MEM
, SP
);
461 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
468 cmdline_location(void)
470 if (h8300smode
&& !h8300_normal_mode
)
472 else if (h8300hmode
&& !h8300_normal_mode
)
479 decode (SIM_DESC sd
, int addr
, unsigned char *data
, decoded_inst
*dst
)
481 int cst
[3] = {0, 0, 0};
482 int reg
[3] = {0, 0, 0};
483 int rdisp
[3] = {0, 0, 0};
485 const struct h8_opcode
*q
;
490 /* Find the exact opcode/arg combo. */
491 for (q
= h8_opcodes
; q
->name
; q
++)
493 const op_type
*nib
= q
->data
.nib
;
494 unsigned int len
= 0;
496 if ((q
->available
== AV_H8SX
&& !h8300sxmode
) ||
497 (q
->available
== AV_H8S
&& !h8300smode
) ||
498 (q
->available
== AV_H8H
&& !h8300hmode
))
501 cst
[0] = cst
[1] = cst
[2] = 0;
502 reg
[0] = reg
[1] = reg
[2] = 0;
503 rdisp
[0] = rdisp
[1] = rdisp
[2] = 0;
507 op_type looking_for
= *nib
;
508 int thisnib
= data
[len
/ 2];
510 thisnib
= (len
& 1) ? (thisnib
& 0xf) : ((thisnib
>> 4) & 0xf);
511 opnum
= ((looking_for
& OP3
) ? 2 :
512 (looking_for
& DST
) ? 1 : 0);
514 if (looking_for
< 16 && looking_for
>= 0)
516 if (looking_for
!= thisnib
)
521 if (looking_for
& B31
)
523 if (!((thisnib
& 0x8) != 0))
526 looking_for
= (op_type
) (looking_for
& ~B31
);
529 else if (looking_for
& B30
)
531 if (!((thisnib
& 0x8) == 0))
534 looking_for
= (op_type
) (looking_for
& ~B30
);
537 if (looking_for
& B21
)
539 if (!((thisnib
& 0x4) != 0))
542 looking_for
= (op_type
) (looking_for
& ~B21
);
545 else if (looking_for
& B20
)
547 if (!((thisnib
& 0x4) == 0))
550 looking_for
= (op_type
) (looking_for
& ~B20
);
553 if (looking_for
& B11
)
555 if (!((thisnib
& 0x2) != 0))
558 looking_for
= (op_type
) (looking_for
& ~B11
);
561 else if (looking_for
& B10
)
563 if (!((thisnib
& 0x2) == 0))
566 looking_for
= (op_type
) (looking_for
& ~B10
);
569 if (looking_for
& B01
)
571 if (!((thisnib
& 0x1) != 0))
574 looking_for
= (op_type
) (looking_for
& ~B01
);
577 else if (looking_for
& B00
)
579 if (!((thisnib
& 0x1) == 0))
582 looking_for
= (op_type
) (looking_for
& ~B00
);
585 if (looking_for
& IGNORE
)
587 /* Hitachi has declared that IGNORE must be zero. */
591 else if ((looking_for
& MODE
) == DATA
)
593 ; /* Skip embedded data. */
595 else if ((looking_for
& MODE
) == DBIT
)
597 /* Exclude adds/subs by looking at bit 0 and 2, and
598 make sure the operand size, either w or l,
599 matches by looking at bit 1. */
600 if ((looking_for
& 7) != (thisnib
& 7))
603 cst
[opnum
] = (thisnib
& 0x8) ? 2 : 1;
605 else if ((looking_for
& MODE
) == REG
||
606 (looking_for
& MODE
) == LOWREG
||
607 (looking_for
& MODE
) == IND
||
608 (looking_for
& MODE
) == PREINC
||
609 (looking_for
& MODE
) == POSTINC
||
610 (looking_for
& MODE
) == PREDEC
||
611 (looking_for
& MODE
) == POSTDEC
)
613 reg
[opnum
] = thisnib
;
615 else if (looking_for
& CTRL
)
618 if (((looking_for
& MODE
) == CCR
&& (thisnib
!= C_CCR
)) ||
619 ((looking_for
& MODE
) == EXR
&& (thisnib
!= C_EXR
)) ||
620 ((looking_for
& MODE
) == MACH
&& (thisnib
!= C_MACH
)) ||
621 ((looking_for
& MODE
) == MACL
&& (thisnib
!= C_MACL
)) ||
622 ((looking_for
& MODE
) == VBR
&& (thisnib
!= C_VBR
)) ||
623 ((looking_for
& MODE
) == SBR
&& (thisnib
!= C_SBR
)))
625 if (((looking_for
& MODE
) == CCR_EXR
&&
626 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
)) ||
627 ((looking_for
& MODE
) == VBR_SBR
&&
628 (thisnib
!= C_VBR
&& thisnib
!= C_SBR
)) ||
629 ((looking_for
& MODE
) == MACREG
&&
630 (thisnib
!= C_MACH
&& thisnib
!= C_MACL
)))
632 if (((looking_for
& MODE
) == CC_EX_VB_SB
&&
633 (thisnib
!= C_CCR
&& thisnib
!= C_EXR
&&
634 thisnib
!= C_VBR
&& thisnib
!= C_SBR
)))
637 reg
[opnum
] = thisnib
;
639 else if ((looking_for
& MODE
) == ABS
)
641 /* Absolute addresses are unsigned. */
642 switch (looking_for
& SIZE
)
645 cst
[opnum
] = UEXTCHAR (data
[len
/ 2]);
649 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
653 (data
[len
/ 2 + 0] << 24) +
654 (data
[len
/ 2 + 1] << 16) +
655 (data
[len
/ 2 + 2] << 8) +
659 printf ("decode: bad size ABS: %d\n",
660 (looking_for
& SIZE
));
664 else if ((looking_for
& MODE
) == DISP
||
665 (looking_for
& MODE
) == PCREL
||
666 (looking_for
& MODE
) == INDEXB
||
667 (looking_for
& MODE
) == INDEXW
||
668 (looking_for
& MODE
) == INDEXL
)
670 switch (looking_for
& SIZE
)
673 cst
[opnum
] = thisnib
& 3;
676 cst
[opnum
] = SEXTCHAR (data
[len
/ 2]);
679 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
680 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
683 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
687 (data
[len
/ 2 + 0] << 24) +
688 (data
[len
/ 2 + 1] << 16) +
689 (data
[len
/ 2 + 2] << 8) +
693 printf ("decode: bad size DISP/PCREL/INDEX: %d\n",
694 (looking_for
& SIZE
));
698 else if ((looking_for
& SIZE
) == L_16
||
699 (looking_for
& SIZE
) == L_16U
)
701 cst
[opnum
] = (data
[len
/ 2] << 8) + data
[len
/ 2 + 1];
702 /* Immediates are always unsigned. */
703 if ((looking_for
& SIZE
) != L_16U
&&
704 (looking_for
& MODE
) != IMM
)
705 cst
[opnum
] = (short) cst
[opnum
]; /* Sign extend. */
707 else if (looking_for
& ABSJMP
)
709 switch (looking_for
& SIZE
) {
711 cst
[opnum
] = (data
[1] << 16) | (data
[2] << 8) | (data
[3]);
715 (data
[len
/ 2 + 0] << 24) +
716 (data
[len
/ 2 + 1] << 16) +
717 (data
[len
/ 2 + 2] << 8) +
721 printf ("decode: bad size ABSJMP: %d\n",
722 (looking_for
& SIZE
));
726 else if ((looking_for
& MODE
) == MEMIND
)
728 cst
[opnum
] = data
[1];
730 else if ((looking_for
& MODE
) == VECIND
)
732 if(h8300_normal_mode
)
733 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 2;
735 cst
[opnum
] = ((data
[1] & 0x7f) + 0x80) * 4;
736 cst
[opnum
] += h8_get_vbr (sd
); /* Add vector base reg. */
738 else if ((looking_for
& SIZE
) == L_32
)
743 (data
[i
+ 0] << 24) |
744 (data
[i
+ 1] << 16) |
748 else if ((looking_for
& SIZE
) == L_24
)
753 (data
[i
+ 0] << 16) |
757 else if (looking_for
& DISPREG
)
759 rdisp
[opnum
] = thisnib
& 0x7;
761 else if ((looking_for
& MODE
) == KBIT
)
778 else if ((looking_for
& SIZE
) == L_8
)
780 if ((looking_for
& MODE
) == ABS
)
782 /* Will be combined with contents of SBR_REGNUM
783 by fetch (). For all modes except h8sx, this
784 will always contain the value 0xFFFFFF00. */
785 cst
[opnum
] = data
[len
/ 2] & 0xff;
789 cst
[opnum
] = data
[len
/ 2] & 0xff;
792 else if ((looking_for
& SIZE
) == L_2
)
794 cst
[opnum
] = thisnib
& 3;
796 else if ((looking_for
& SIZE
) == L_3
||
797 (looking_for
& SIZE
) == L_3NZ
)
799 cst
[opnum
] = thisnib
& 7;
800 if (cst
[opnum
] == 0 && (looking_for
& SIZE
) == L_3NZ
)
803 else if ((looking_for
& SIZE
) == L_4
)
805 cst
[opnum
] = thisnib
& 15;
807 else if ((looking_for
& SIZE
) == L_5
)
809 cst
[opnum
] = data
[len
/ 2] & 0x1f;
811 else if (looking_for
== E
)
816 /* Fill in the args. */
818 const op_type
*args
= q
->args
.nib
;
823 nargs
< 3 && *args
!= E
;
829 opnum
= ((x
& OP3
) ? 2 :
838 if ((x
& MODE
) == IMM
||
839 (x
& MODE
) == KBIT
||
842 /* Use the instruction to determine
844 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
845 p
->literal
= cst
[opnum
];
847 else if ((x
& MODE
) == CONST_2
||
848 (x
& MODE
) == CONST_4
||
849 (x
& MODE
) == CONST_8
||
850 (x
& MODE
) == CONST_16
)
852 /* Use the instruction to determine
854 p
->type
= X (OP_IMM
, OP_SIZE (q
->how
));
856 case CONST_2
: p
->literal
= 2; break;
857 case CONST_4
: p
->literal
= 4; break;
858 case CONST_8
: p
->literal
= 8; break;
859 case CONST_16
: p
->literal
= 16; break;
862 else if ((x
& MODE
) == REG
)
864 p
->type
= X (OP_REG
, bitfrom (x
));
867 else if ((x
& MODE
) == LOWREG
)
869 p
->type
= X (OP_LOWREG
, bitfrom (x
));
872 else if ((x
& MODE
) == PREINC
)
874 /* Use the instruction to determine
876 p
->type
= X (OP_PREINC
, OP_SIZE (q
->how
));
877 p
->reg
= reg
[opnum
] & 0x7;
879 else if ((x
& MODE
) == POSTINC
)
881 /* Use the instruction to determine
883 p
->type
= X (OP_POSTINC
, OP_SIZE (q
->how
));
884 p
->reg
= reg
[opnum
] & 0x7;
886 else if ((x
& MODE
) == PREDEC
)
888 /* Use the instruction to determine
890 p
->type
= X (OP_PREDEC
, OP_SIZE (q
->how
));
891 p
->reg
= reg
[opnum
] & 0x7;
893 else if ((x
& MODE
) == POSTDEC
)
895 /* Use the instruction to determine
897 p
->type
= X (OP_POSTDEC
, OP_SIZE (q
->how
));
898 p
->reg
= reg
[opnum
] & 0x7;
900 else if ((x
& MODE
) == IND
)
902 /* Note: an indirect is transformed into
903 a displacement of zero.
905 /* Use the instruction to determine
907 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
908 p
->reg
= reg
[opnum
] & 0x7;
910 if (OP_KIND (q
->how
) == O_JSR
||
911 OP_KIND (q
->how
) == O_JMP
)
912 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
915 else if ((x
& MODE
) == ABS
)
917 /* Note: a 16 or 32 bit ABS is transformed into a
918 displacement from pseudo-register ZERO_REGNUM,
919 which is always zero. An 8 bit ABS becomes
920 a displacement from SBR_REGNUM.
922 /* Use the instruction to determine
924 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
925 p
->literal
= cst
[opnum
];
927 /* 8-bit ABS is displacement from SBR.
928 16 and 32-bit ABS are displacement from ZERO.
929 (SBR will always be zero except for h8/sx)
931 if ((x
& SIZE
) == L_8
)
934 p
->reg
= ZERO_REGNUM
;;
936 else if ((x
& MODE
) == MEMIND
||
937 (x
& MODE
) == VECIND
)
939 /* Size doesn't matter. */
940 p
->type
= X (OP_MEM
, SB
);
941 p
->literal
= cst
[opnum
];
942 if (OP_KIND (q
->how
) == O_JSR
||
943 OP_KIND (q
->how
) == O_JMP
)
944 if (lvalue (sd
, p
->type
, p
->reg
, (unsigned int *)&p
->type
))
947 else if ((x
& MODE
) == PCREL
)
949 /* Size doesn't matter. */
950 p
->type
= X (OP_PCREL
, SB
);
951 p
->literal
= cst
[opnum
];
955 p
->type
= X (OP_IMM
, SP
);
956 p
->literal
= cst
[opnum
];
958 else if ((x
& MODE
) == INDEXB
)
960 p
->type
= X (OP_INDEXB
, OP_SIZE (q
->how
));
961 p
->literal
= cst
[opnum
];
962 p
->reg
= rdisp
[opnum
];
964 else if ((x
& MODE
) == INDEXW
)
966 p
->type
= X (OP_INDEXW
, OP_SIZE (q
->how
));
967 p
->literal
= cst
[opnum
];
968 p
->reg
= rdisp
[opnum
];
970 else if ((x
& MODE
) == INDEXL
)
972 p
->type
= X (OP_INDEXL
, OP_SIZE (q
->how
));
973 p
->literal
= cst
[opnum
];
974 p
->reg
= rdisp
[opnum
];
976 else if ((x
& MODE
) == DISP
)
978 /* Yuck -- special for mova args. */
979 if (strncmp (q
->name
, "mova", 4) == 0 &&
982 /* Mova can have a DISP2 dest, with an
983 INDEXB or INDEXW src. The multiplier
984 for the displacement value is determined
985 by the src operand, not by the insn. */
987 switch (OP_KIND (dst
->src
.type
))
990 p
->type
= X (OP_DISP
, SB
);
991 p
->literal
= cst
[opnum
];
994 p
->type
= X (OP_DISP
, SW
);
995 p
->literal
= cst
[opnum
] * 2;
1003 p
->type
= X (OP_DISP
, OP_SIZE (q
->how
));
1004 p
->literal
= cst
[opnum
];
1005 /* DISP2 is special. */
1006 if ((x
& SIZE
) == L_2
)
1007 switch (OP_SIZE (q
->how
))
1010 case SW
: p
->literal
*= 2; break;
1011 case SL
: p
->literal
*= 4; break;
1014 p
->reg
= rdisp
[opnum
];
1021 p
->type
= X (OP_CCR
, SB
);
1024 p
->type
= X (OP_EXR
, SB
);
1027 p
->type
= X (OP_MACH
, SL
);
1030 p
->type
= X (OP_MACL
, SL
);
1033 p
->type
= X (OP_VBR
, SL
);
1036 p
->type
= X (OP_SBR
, SL
);
1040 else if ((x
& MODE
) == CCR
)
1044 else if ((x
& MODE
) == EXR
)
1049 printf ("Hmmmm 0x%x...\n", x
);
1055 /* Unary operators: treat src and dst as equivalent. */
1056 if (dst
->dst
.type
== -1)
1057 dst
->dst
= dst
->src
;
1058 if (dst
->src
.type
== -1)
1059 dst
->src
= dst
->dst
;
1061 dst
->opcode
= q
->how
;
1062 dst
->cycles
= q
->time
;
1064 /* And jsr's to these locations are turned into
1067 if (OP_KIND (dst
->opcode
) == O_JSR
)
1069 switch (dst
->src
.literal
)
1072 dst
->opcode
= O (O_SYS_OPEN
, SB
);
1075 dst
->opcode
= O (O_SYS_READ
, SB
);
1078 dst
->opcode
= O (O_SYS_WRITE
, SB
);
1081 dst
->opcode
= O (O_SYS_LSEEK
, SB
);
1084 dst
->opcode
= O (O_SYS_CLOSE
, SB
);
1087 dst
->opcode
= O (O_SYS_STAT
, SB
);
1090 dst
->opcode
= O (O_SYS_FSTAT
, SB
);
1093 dst
->opcode
= O (O_SYS_CMDLINE
, SB
);
1096 /* End of Processing for system calls. */
1099 dst
->next_pc
= addr
+ len
/ 2;
1103 printf ("Don't understand 0x%x \n", looking_for
);
1114 /* Fell off the end. */
1115 dst
->opcode
= O (O_ILL
, SB
);
1118 static unsigned char *breg
[32];
1119 static unsigned short *wreg
[16];
1121 #define GET_B_REG(X) *(breg[X])
1122 #define SET_B_REG(X, Y) (*(breg[X])) = (Y)
1123 #define GET_W_REG(X) *(wreg[X])
1124 #define SET_W_REG(X, Y) (*(wreg[X])) = (Y)
1125 #define GET_L_REG(X) h8_get_reg (sd, X)
1126 #define SET_L_REG(X, Y) h8_set_reg (sd, X, Y)
1128 #define GET_MEMORY_L(X) \
1129 ((X) < memory_size \
1130 ? ((h8_get_memory (sd, (X)+0) << 24) | (h8_get_memory (sd, (X)+1) << 16) \
1131 | (h8_get_memory (sd, (X)+2) << 8) | (h8_get_memory (sd, (X)+3) << 0)) \
1134 #define GET_MEMORY_W(X) \
1135 ((X) < memory_size \
1136 ? ((h8_get_memory (sd, (X)+0) << 8) | (h8_get_memory (sd, (X)+1) << 0)) \
1139 #define GET_MEMORY_B(X) \
1140 ((X) < memory_size ? h8_get_memory (sd, (X)) : 0)
1142 #define SET_MEMORY_L(X, Y) \
1143 { register unsigned char *_p; register int __y = (Y); \
1144 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1145 _p[0] = __y >> 24; _p[1] = __y >> 16; \
1146 _p[2] = __y >> 8; _p[3] = __y >> 0; \
1149 #define SET_MEMORY_W(X, Y) \
1150 { register unsigned char *_p; register int __y = (Y); \
1151 _p = ((X) < memory_size ? h8_get_memory_buf (sd) + (X) : 0); \
1152 _p[0] = __y >> 8; _p[1] = __y; \
1155 #define SET_MEMORY_B(X, Y) \
1156 ((X) < memory_size ? h8_set_memory (sd, (X), (Y)) : 0)
1158 /* Simulate a memory fetch.
1159 Return 0 for success, -1 for failure.
1163 fetch_1 (SIM_DESC sd
, ea_type
*arg
, int *val
, int twice
)
1165 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1167 int abs
= arg
->literal
;
1172 return -1; /* Paranoia. */
1176 /* Indexed register plus displacement mode:
1178 This new family of addressing modes are similar to OP_DISP
1179 (register plus displacement), with two differences:
1180 1) INDEXB uses only the least significant byte of the register,
1181 INDEXW uses only the least significant word, and
1182 INDEXL uses the entire register (just like OP_DISP).
1184 2) The displacement value in abs is multiplied by two
1185 for SW-sized operations, and by four for SL-size.
1187 This gives nine possible variations.
1190 case X (OP_INDEXB
, SB
):
1191 case X (OP_INDEXB
, SW
):
1192 case X (OP_INDEXB
, SL
):
1193 case X (OP_INDEXW
, SB
):
1194 case X (OP_INDEXW
, SW
):
1195 case X (OP_INDEXW
, SL
):
1196 case X (OP_INDEXL
, SB
):
1197 case X (OP_INDEXL
, SW
):
1198 case X (OP_INDEXL
, SL
):
1200 switch (OP_KIND (arg
->type
)) {
1201 case OP_INDEXB
: t
&= 0xff; break;
1202 case OP_INDEXW
: t
&= 0xffff; break;
1206 switch (OP_SIZE (arg
->type
)) {
1208 *val
= GET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
));
1211 *val
= GET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
));
1214 *val
= GET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
));
1219 case X (OP_LOWREG
, SB
):
1220 *val
= GET_L_REG (rn
) & 0xff;
1222 case X (OP_LOWREG
, SW
):
1223 *val
= GET_L_REG (rn
) & 0xffff;
1226 case X (OP_REG
, SB
): /* Register direct, byte. */
1227 *val
= GET_B_REG (rn
);
1229 case X (OP_REG
, SW
): /* Register direct, word. */
1230 *val
= GET_W_REG (rn
);
1232 case X (OP_REG
, SL
): /* Register direct, long. */
1233 *val
= GET_L_REG (rn
);
1235 case X (OP_IMM
, SB
): /* Immediate, byte. */
1236 case X (OP_IMM
, SW
): /* Immediate, word. */
1237 case X (OP_IMM
, SL
): /* Immediate, long. */
1240 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr: byte. */
1242 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1248 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr: word. */
1250 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1256 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr: long. */
1258 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1265 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr: byte. */
1267 r
= GET_MEMORY_B (t
& h8_get_mask (sd
));
1273 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr: word. */
1275 r
= GET_MEMORY_W (t
& h8_get_mask (sd
));
1281 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr: long. */
1283 r
= GET_MEMORY_L (t
& h8_get_mask (sd
));
1290 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr: byte. */
1291 t
= GET_L_REG (rn
) - 1;
1293 t
&= h8_get_mask (sd
);
1294 *val
= GET_MEMORY_B (t
);
1297 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr: word. */
1298 t
= GET_L_REG (rn
) - 2;
1300 t
&= h8_get_mask (sd
);
1301 *val
= GET_MEMORY_W (t
);
1304 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr: long. */
1305 t
= GET_L_REG (rn
) - 4;
1307 t
&= h8_get_mask (sd
);
1308 *val
= GET_MEMORY_L (t
);
1311 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr: byte. */
1312 t
= GET_L_REG (rn
) + 1;
1314 t
&= h8_get_mask (sd
);
1315 *val
= GET_MEMORY_B (t
);
1318 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr: long. */
1319 t
= GET_L_REG (rn
) + 2;
1321 t
&= h8_get_mask (sd
);
1322 *val
= GET_MEMORY_W (t
);
1325 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr: long. */
1326 t
= GET_L_REG (rn
) + 4;
1328 t
&= h8_get_mask (sd
);
1329 *val
= GET_MEMORY_L (t
);
1332 case X (OP_DISP
, SB
): /* Register indirect w/displacement: byte. */
1333 t
= GET_L_REG (rn
) + abs
;
1334 t
&= h8_get_mask (sd
);
1335 *val
= GET_MEMORY_B (t
);
1338 case X (OP_DISP
, SW
): /* Register indirect w/displacement: word. */
1339 t
= GET_L_REG (rn
) + abs
;
1340 t
&= h8_get_mask (sd
);
1341 *val
= GET_MEMORY_W (t
);
1344 case X (OP_DISP
, SL
): /* Register indirect w/displacement: long. */
1345 t
= GET_L_REG (rn
) + abs
;
1346 t
&= h8_get_mask (sd
);
1347 *val
=GET_MEMORY_L (t
);
1350 case X (OP_MEM
, SL
): /* Absolute memory address, long. */
1351 t
= GET_MEMORY_L (abs
);
1352 t
&= h8_get_mask (sd
);
1356 case X (OP_MEM
, SW
): /* Absolute memory address, word. */
1357 t
= GET_MEMORY_W (abs
);
1358 t
&= h8_get_mask (sd
);
1362 case X (OP_PCREL
, SB
): /* PC relative (for jump, branch etc). */
1363 case X (OP_PCREL
, SW
):
1364 case X (OP_PCREL
, SL
):
1365 case X (OP_PCREL
, SN
):
1369 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1371 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1374 return 0; /* Success. */
1380 fetch (SIM_DESC sd
, ea_type
*arg
, int *val
)
1382 return fetch_1 (sd
, arg
, val
, 0);
1385 /* Fetch which will be followed by a store to the same location.
1386 The difference being that we don't want to do a post-increment
1387 or post-decrement at this time: we'll do it when we store. */
1390 fetch2 (SIM_DESC sd
, ea_type
*arg
, int *val
)
1392 return fetch_1 (sd
, arg
, val
, 1);
1395 /* Simulate a memory store.
1396 Return 0 for success, -1 for failure.
1400 store_1 (SIM_DESC sd
, ea_type
*arg
, int n
, int twice
)
1402 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1404 int abs
= arg
->literal
;
1409 /* Indexed register plus displacement mode:
1411 This new family of addressing modes are similar to OP_DISP
1412 (register plus displacement), with two differences:
1413 1) INDEXB uses only the least significant byte of the register,
1414 INDEXW uses only the least significant word, and
1415 INDEXL uses the entire register (just like OP_DISP).
1417 2) The displacement value in abs is multiplied by two
1418 for SW-sized operations, and by four for SL-size.
1420 This gives nine possible variations.
1423 case X (OP_INDEXB
, SB
):
1424 case X (OP_INDEXB
, SW
):
1425 case X (OP_INDEXB
, SL
):
1426 case X (OP_INDEXW
, SB
):
1427 case X (OP_INDEXW
, SW
):
1428 case X (OP_INDEXW
, SL
):
1429 case X (OP_INDEXL
, SB
):
1430 case X (OP_INDEXL
, SW
):
1431 case X (OP_INDEXL
, SL
):
1433 switch (OP_KIND (arg
->type
)) {
1434 case OP_INDEXB
: t
&= 0xff; break;
1435 case OP_INDEXW
: t
&= 0xffff; break;
1439 switch (OP_SIZE (arg
->type
)) {
1441 SET_MEMORY_B ((t
* 1 + abs
) & h8_get_mask (sd
), n
);
1444 SET_MEMORY_W ((t
* 2 + abs
) & h8_get_mask (sd
), n
);
1447 SET_MEMORY_L ((t
* 4 + abs
) & h8_get_mask (sd
), n
);
1452 case X (OP_REG
, SB
): /* Register direct, byte. */
1455 case X (OP_REG
, SW
): /* Register direct, word. */
1458 case X (OP_REG
, SL
): /* Register direct, long. */
1462 case X (OP_PREDEC
, SB
): /* Register indirect w/pre-decr, byte. */
1467 t
&= h8_get_mask (sd
);
1468 SET_MEMORY_B (t
, n
);
1471 case X (OP_PREDEC
, SW
): /* Register indirect w/pre-decr, word. */
1476 t
&= h8_get_mask (sd
);
1477 SET_MEMORY_W (t
, n
);
1480 case X (OP_PREDEC
, SL
): /* Register indirect w/pre-decr, long. */
1485 t
&= h8_get_mask (sd
);
1486 SET_MEMORY_L (t
, n
);
1489 case X (OP_PREINC
, SB
): /* Register indirect w/pre-incr, byte. */
1494 t
&= h8_get_mask (sd
);
1495 SET_MEMORY_B (t
, n
);
1498 case X (OP_PREINC
, SW
): /* Register indirect w/pre-incr, word. */
1503 t
&= h8_get_mask (sd
);
1504 SET_MEMORY_W (t
, n
);
1507 case X (OP_PREINC
, SL
): /* Register indirect w/pre-incr, long. */
1512 t
&= h8_get_mask (sd
);
1513 SET_MEMORY_L (t
, n
);
1516 case X (OP_POSTDEC
, SB
): /* Register indirect w/post-decr, byte. */
1518 SET_L_REG (rn
, t
- 1);
1519 t
&= h8_get_mask (sd
);
1520 SET_MEMORY_B (t
, n
);
1523 case X (OP_POSTDEC
, SW
): /* Register indirect w/post-decr, word. */
1525 SET_L_REG (rn
, t
- 2);
1526 t
&= h8_get_mask (sd
);
1527 SET_MEMORY_W (t
, n
);
1530 case X (OP_POSTDEC
, SL
): /* Register indirect w/post-decr, long. */
1532 SET_L_REG (rn
, t
- 4);
1533 t
&= h8_get_mask (sd
);
1534 SET_MEMORY_L (t
, n
);
1537 case X (OP_POSTINC
, SB
): /* Register indirect w/post-incr, byte. */
1539 SET_L_REG (rn
, t
+ 1);
1540 t
&= h8_get_mask (sd
);
1541 SET_MEMORY_B (t
, n
);
1544 case X (OP_POSTINC
, SW
): /* Register indirect w/post-incr, word. */
1546 SET_L_REG (rn
, t
+ 2);
1547 t
&= h8_get_mask (sd
);
1548 SET_MEMORY_W (t
, n
);
1551 case X (OP_POSTINC
, SL
): /* Register indirect w/post-incr, long. */
1553 SET_L_REG (rn
, t
+ 4);
1554 t
&= h8_get_mask (sd
);
1555 SET_MEMORY_L (t
, n
);
1558 case X (OP_DISP
, SB
): /* Register indirect w/displacement, byte. */
1559 t
= GET_L_REG (rn
) + abs
;
1560 t
&= h8_get_mask (sd
);
1561 SET_MEMORY_B (t
, n
);
1564 case X (OP_DISP
, SW
): /* Register indirect w/displacement, word. */
1565 t
= GET_L_REG (rn
) + abs
;
1566 t
&= h8_get_mask (sd
);
1567 SET_MEMORY_W (t
, n
);
1570 case X (OP_DISP
, SL
): /* Register indirect w/displacement, long. */
1571 t
= GET_L_REG (rn
) + abs
;
1572 t
&= h8_get_mask (sd
);
1573 SET_MEMORY_L (t
, n
);
1577 case X (OP_MEM
, SB
): /* Why isn't this implemented? */
1578 case X (OP_MEM
, SW
): /* Why isn't this implemented? */
1579 case X (OP_MEM
, SL
): /* Why isn't this implemented? */
1581 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGSEGV
);
1590 store (SIM_DESC sd
, ea_type
*arg
, int n
)
1592 return store_1 (sd
, arg
, n
, 0);
1595 /* Store which follows a fetch from the same location.
1596 The difference being that we don't want to do a pre-increment
1597 or pre-decrement at this time: it was already done when we fetched. */
1600 store2 (SIM_DESC sd
, ea_type
*arg
, int n
)
1602 return store_1 (sd
, arg
, n
, 1);
1605 /* Flag to be set whenever a new SIM_DESC object is created. */
1606 static int init_pointers_needed
= 1;
1609 init_pointers (SIM_DESC sd
)
1611 if (init_pointers_needed
)
1615 if (h8300smode
&& !h8300_normal_mode
)
1616 memory_size
= H8300S_MSIZE
;
1617 else if (h8300hmode
&& !h8300_normal_mode
)
1618 memory_size
= H8300H_MSIZE
;
1620 memory_size
= H8300_MSIZE
;
1621 /* `msize' must be a power of two. */
1622 if ((memory_size
& (memory_size
- 1)) != 0)
1626 "init_pointers: bad memory size %d, defaulting to %d.\n",
1627 memory_size
, H8300S_MSIZE
);
1628 memory_size
= H8300S_MSIZE
;
1631 if (h8_get_memory_buf (sd
))
1632 free (h8_get_memory_buf (sd
));
1634 h8_set_memory_buf (sd
, (unsigned char *)
1635 calloc (sizeof (char), memory_size
));
1636 sd
->memory_size
= memory_size
;
1638 h8_set_mask (sd
, memory_size
- 1);
1640 memset (h8_get_reg_buf (sd
), 0, sizeof (((STATE_CPU (sd
, 0))->regs
)));
1642 for (i
= 0; i
< 8; i
++)
1644 /* FIXME: rewrite using local buffer. */
1645 unsigned char *p
= (unsigned char *) (h8_get_reg_buf (sd
) + i
);
1646 unsigned char *e
= (unsigned char *) (h8_get_reg_buf (sd
) + i
+ 1);
1647 unsigned short *q
= (unsigned short *) (h8_get_reg_buf (sd
) + i
);
1648 unsigned short *u
= (unsigned short *) (h8_get_reg_buf (sd
) + i
+ 1);
1649 h8_set_reg (sd
, i
, 0x00112233);
1664 wreg
[i
] = wreg
[i
+ 8] = 0;
1678 if (wreg
[i
] == 0 || wreg
[i
+ 8] == 0)
1679 sim_io_printf (sd
, "init_pointers: internal error.\n");
1681 h8_set_reg (sd
, i
, 0);
1684 init_pointers_needed
= 0;
1688 #define OBITOP(name, f, s, op) \
1689 case O (name, SB): \
1694 if (fetch (sd, &code->dst, &ea)) \
1696 if (fetch (sd, &code->src, &tmp)) \
1698 m = 1 << (tmp & 7); \
1701 if (store (sd, &code->dst,ea)) \
1707 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
1711 int tick_start
= get_now ();
1718 int c
, nz
, v
, n
, u
, h
, ui
, intMaskBit
;
1721 host_callback
*sim_callback
= STATE_CALLBACK (sd
);
1725 pc
= h8_get_pc (sd
);
1727 /* The PC should never be odd. */
1730 sim_engine_halt (sd
, cpu
, NULL
, NULL_CIA
, sim_stopped
, SIM_SIGBUS
);
1734 /* Get Status Register (flags). */
1737 if (h8300smode
) /* Get exr. */
1739 trace
= (h8_get_exr (sd
) >> 7) & 1;
1740 intMask
= h8_get_exr (sd
) & 7;
1743 oldmask
= h8_get_mask (sd
);
1744 if (!h8300hmode
|| h8300_normal_mode
)
1745 h8_set_mask (sd
, 0xffff);
1748 decoded_inst _code
, *code
= &_code
;
1749 memset (code
, 0, sizeof (*code
));
1750 decode (sd
, pc
, h8_get_memory_buf (sd
) + pc
, code
);
1756 printf ("%x %d %s\n", pc
, code
->opcode
,
1757 code
->op
? code
->op
->name
: "**");
1759 h8_increment_stats (sd
, code
->opcode
);
1764 cycles
+= code
->cycles
;
1768 switch (code
->opcode
)
1770 case O (O_MOVAB
, SL
):
1771 case O (O_MOVAW
, SL
):
1772 case O (O_MOVAL
, SL
):
1773 /* 1) Evaluate 2nd argument (dst).
1774 2) Mask / zero extend according to whether 1st argument (src)
1775 is INDEXB, INDEXW, or INDEXL.
1776 3) Left-shift the result by 0, 1 or 2, according to size of mova
1777 (mova/b, mova/w, mova/l).
1778 4) Add literal value of 1st argument (src).
1779 5) Store result in 3rd argument (op3).
1782 /* Alas, since this is the only instruction with 3 arguments,
1783 decode doesn't handle them very well. Some fix-up is required.
1785 a) The size of dst is determined by whether src is
1786 INDEXB or INDEXW. */
1788 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1789 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SB
);
1790 else if (OP_KIND (code
->src
.type
) == OP_INDEXW
)
1791 code
->dst
.type
= X (OP_KIND (code
->dst
.type
), SW
);
1793 /* b) If op3 == null, then this is the short form of the insn.
1794 Dst is the dispreg of src, and op3 is the 32-bit form
1795 of the same register.
1798 if (code
->op3
.type
== 0)
1800 /* Short form: src == INDEXB/INDEXW, dst == op3 == 0.
1801 We get to compose dst and op3 as follows:
1803 op3 is a 32-bit register, ID == src.reg.
1804 dst is the same register, but 8 or 16 bits
1805 depending on whether src is INDEXB or INDEXW.
1808 code
->op3
.type
= X (OP_REG
, SL
);
1809 code
->op3
.reg
= code
->src
.reg
;
1810 code
->op3
.literal
= 0;
1812 if (OP_KIND (code
->src
.type
) == OP_INDEXB
)
1814 code
->dst
.type
= X (OP_REG
, SB
);
1815 code
->dst
.reg
= code
->op3
.reg
+ 8;
1818 code
->dst
.type
= X (OP_REG
, SW
);
1821 if (fetch (sd
, &code
->dst
, &ea
))
1824 switch (OP_KIND (code
->src
.type
)) {
1825 case OP_INDEXB
: ea
= ea
& 0xff; break;
1826 case OP_INDEXW
: ea
= ea
& 0xffff; break;
1827 case OP_INDEXL
: break;
1828 default: goto illegal
;
1831 switch (code
->opcode
) {
1832 case O (O_MOVAB
, SL
): break;
1833 case O (O_MOVAW
, SL
): ea
= ea
<< 1; break;
1834 case O (O_MOVAL
, SL
): ea
= ea
<< 2; break;
1835 default: goto illegal
;
1838 ea
= ea
+ code
->src
.literal
;
1840 if (store (sd
, &code
->op3
, ea
))
1845 case O (O_SUBX
, SB
): /* subx, extended sub */
1846 if (fetch2 (sd
, &code
->dst
, &rd
))
1848 if (fetch (sd
, &code
->src
, &ea
))
1854 case O (O_SUBX
, SW
): /* subx, extended sub */
1855 if (fetch2 (sd
, &code
->dst
, &rd
))
1857 if (fetch (sd
, &code
->src
, &ea
))
1863 case O (O_SUBX
, SL
): /* subx, extended sub */
1864 if (fetch2 (sd
, &code
->dst
, &rd
))
1866 if (fetch (sd
, &code
->src
, &ea
))
1872 case O (O_ADDX
, SB
): /* addx, extended add */
1873 if (fetch2 (sd
, &code
->dst
, &rd
))
1875 if (fetch (sd
, &code
->src
, &ea
))
1881 case O (O_ADDX
, SW
): /* addx, extended add */
1882 if (fetch2 (sd
, &code
->dst
, &rd
))
1884 if (fetch (sd
, &code
->src
, &ea
))
1890 case O (O_ADDX
, SL
): /* addx, extended add */
1891 if (fetch2 (sd
, &code
->dst
, &rd
))
1893 if (fetch (sd
, &code
->src
, &ea
))
1899 case O (O_SUB
, SB
): /* sub.b */
1900 /* Fetch rd and ea. */
1901 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1907 case O (O_SUB
, SW
): /* sub.w */
1908 /* Fetch rd and ea. */
1909 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1915 case O (O_SUB
, SL
): /* sub.l */
1916 /* Fetch rd and ea. */
1917 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1923 case O (O_NEG
, SB
): /* neg.b */
1925 if (fetch2 (sd
, &code
->src
, &ea
))
1932 case O (O_NEG
, SW
): /* neg.w */
1934 if (fetch2 (sd
, &code
->src
, &ea
))
1941 case O (O_NEG
, SL
): /* neg.l */
1943 if (fetch2 (sd
, &code
->src
, &ea
))
1950 case O (O_ADD
, SB
): /* add.b */
1951 if (fetch2 (sd
, &code
->dst
, &rd
))
1953 if (fetch (sd
, &code
->src
, &ea
))
1958 case O (O_ADD
, SW
): /* add.w */
1959 if (fetch2 (sd
, &code
->dst
, &rd
))
1961 if (fetch (sd
, &code
->src
, &ea
))
1966 case O (O_ADD
, SL
): /* add.l */
1967 if (fetch2 (sd
, &code
->dst
, &rd
))
1969 if (fetch (sd
, &code
->src
, &ea
))
1974 case O (O_AND
, SB
): /* and.b */
1975 /* Fetch rd and ea. */
1976 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1981 case O (O_AND
, SW
): /* and.w */
1982 /* Fetch rd and ea. */
1983 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1988 case O (O_AND
, SL
): /* and.l */
1989 /* Fetch rd and ea. */
1990 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
1995 case O (O_OR
, SB
): /* or.b */
1996 /* Fetch rd and ea. */
1997 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2002 case O (O_OR
, SW
): /* or.w */
2003 /* Fetch rd and ea. */
2004 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2009 case O (O_OR
, SL
): /* or.l */
2010 /* Fetch rd and ea. */
2011 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2016 case O (O_XOR
, SB
): /* xor.b */
2017 /* Fetch rd and ea. */
2018 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2023 case O (O_XOR
, SW
): /* xor.w */
2024 /* Fetch rd and ea. */
2025 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2030 case O (O_XOR
, SL
): /* xor.l */
2031 /* Fetch rd and ea. */
2032 if (fetch (sd
, &code
->src
, &ea
) || fetch2 (sd
, &code
->dst
, &rd
))
2038 if (fetch (sd
, &code
->src
, &res
))
2040 if (store (sd
, &code
->dst
, res
))
2042 goto just_flags_log8
;
2044 if (fetch (sd
, &code
->src
, &res
))
2046 if (store (sd
, &code
->dst
, res
))
2048 goto just_flags_log16
;
2050 if (fetch (sd
, &code
->src
, &res
))
2052 if (store (sd
, &code
->dst
, res
))
2054 goto just_flags_log32
;
2056 case O (O_MOVMD
, SB
): /* movmd.b */
2063 rd
= GET_MEMORY_B (GET_L_REG (5));
2064 SET_MEMORY_B (GET_L_REG (6), rd
);
2065 SET_L_REG (5, GET_L_REG (5) + 1);
2066 SET_L_REG (6, GET_L_REG (6) + 1);
2071 case O (O_MOVMD
, SW
): /* movmd.w */
2078 rd
= GET_MEMORY_W (GET_L_REG (5));
2079 SET_MEMORY_W (GET_L_REG (6), rd
);
2080 SET_L_REG (5, GET_L_REG (5) + 2);
2081 SET_L_REG (6, GET_L_REG (6) + 2);
2086 case O (O_MOVMD
, SL
): /* movmd.l */
2093 rd
= GET_MEMORY_L (GET_L_REG (5));
2094 SET_MEMORY_L (GET_L_REG (6), rd
);
2095 SET_L_REG (5, GET_L_REG (5) + 4);
2096 SET_L_REG (6, GET_L_REG (6) + 4);
2101 case O (O_MOVSD
, SB
): /* movsd.b */
2102 /* This instruction implements strncpy, with a conditional branch.
2103 r4 contains n, r5 contains src, and r6 contains dst.
2104 The 16-bit displacement operand is added to the pc
2105 if and only if the end of string is reached before
2106 n bytes are transferred. */
2108 ea
= GET_L_REG (4) & 0xffff;
2114 rd
= GET_MEMORY_B (GET_L_REG (5));
2115 SET_MEMORY_B (GET_L_REG (6), rd
);
2116 SET_L_REG (5, GET_L_REG (5) + 1);
2117 SET_L_REG (6, GET_L_REG (6) + 1);
2124 case O (O_EEPMOV
, SB
): /* eepmov.b */
2125 case O (O_EEPMOV
, SW
): /* eepmov.w */
2126 if (h8300hmode
|| h8300smode
)
2128 register unsigned char *_src
, *_dst
;
2129 unsigned int count
= ((code
->opcode
== O (O_EEPMOV
, SW
))
2130 ? h8_get_reg (sd
, R4_REGNUM
) & 0xffff
2131 : h8_get_reg (sd
, R4_REGNUM
) & 0xff);
2133 _src
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R5_REGNUM
);
2134 if ((_src
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2136 _dst
= h8_get_memory_buf (sd
) + h8_get_reg (sd
, R6_REGNUM
);
2137 if ((_dst
+ count
) >= (h8_get_memory_buf (sd
) + memory_size
))
2139 memcpy (_dst
, _src
, count
);
2141 h8_set_reg (sd
, R5_REGNUM
, h8_get_reg (sd
, R5_REGNUM
) + count
);
2142 h8_set_reg (sd
, R6_REGNUM
, h8_get_reg (sd
, R6_REGNUM
) + count
);
2143 h8_set_reg (sd
, R4_REGNUM
, h8_get_reg (sd
, R4_REGNUM
) &
2144 ((code
->opcode
== O (O_EEPMOV
, SW
))
2145 ? (~0xffff) : (~0xff)));
2146 cycles
+= 2 * count
;
2151 case O (O_ADDS
, SL
): /* adds (.l) */
2153 * This insn only uses register operands, but still
2154 * it would be cleaner to use fetch and store... */
2155 SET_L_REG (code
->dst
.reg
,
2156 GET_L_REG (code
->dst
.reg
)
2157 + code
->src
.literal
);
2161 case O (O_SUBS
, SL
): /* subs (.l) */
2163 * This insn only uses register operands, but still
2164 * it would be cleaner to use fetch and store... */
2165 SET_L_REG (code
->dst
.reg
,
2166 GET_L_REG (code
->dst
.reg
)
2167 - code
->src
.literal
);
2170 case O (O_CMP
, SB
): /* cmp.b */
2171 if (fetch (sd
, &code
->dst
, &rd
))
2173 if (fetch (sd
, &code
->src
, &ea
))
2177 goto just_flags_alu8
;
2179 case O (O_CMP
, SW
): /* cmp.w */
2180 if (fetch (sd
, &code
->dst
, &rd
))
2182 if (fetch (sd
, &code
->src
, &ea
))
2186 goto just_flags_alu16
;
2188 case O (O_CMP
, SL
): /* cmp.l */
2189 if (fetch (sd
, &code
->dst
, &rd
))
2191 if (fetch (sd
, &code
->src
, &ea
))
2195 goto just_flags_alu32
;
2197 case O (O_DEC
, SB
): /* dec.b */
2199 * This insn only uses register operands, but still
2200 * it would be cleaner to use fetch and store... */
2201 rd
= GET_B_REG (code
->src
.reg
);
2204 SET_B_REG (code
->src
.reg
, res
);
2205 goto just_flags_inc8
;
2207 case O (O_DEC
, SW
): /* dec.w */
2209 * This insn only uses register operands, but still
2210 * it would be cleaner to use fetch and store... */
2211 rd
= GET_W_REG (code
->dst
.reg
);
2212 ea
= -code
->src
.literal
;
2214 SET_W_REG (code
->dst
.reg
, res
);
2215 goto just_flags_inc16
;
2217 case O (O_DEC
, SL
): /* dec.l */
2219 * This insn only uses register operands, but still
2220 * it would be cleaner to use fetch and store... */
2221 rd
= GET_L_REG (code
->dst
.reg
);
2222 ea
= -code
->src
.literal
;
2224 SET_L_REG (code
->dst
.reg
, res
);
2225 goto just_flags_inc32
;
2227 case O (O_INC
, SB
): /* inc.b */
2229 * This insn only uses register operands, but still
2230 * it would be cleaner to use fetch and store... */
2231 rd
= GET_B_REG (code
->src
.reg
);
2234 SET_B_REG (code
->src
.reg
, res
);
2235 goto just_flags_inc8
;
2237 case O (O_INC
, SW
): /* inc.w */
2239 * This insn only uses register operands, but still
2240 * it would be cleaner to use fetch and store... */
2241 rd
= GET_W_REG (code
->dst
.reg
);
2242 ea
= code
->src
.literal
;
2244 SET_W_REG (code
->dst
.reg
, res
);
2245 goto just_flags_inc16
;
2247 case O (O_INC
, SL
): /* inc.l */
2249 * This insn only uses register operands, but still
2250 * it would be cleaner to use fetch and store... */
2251 rd
= GET_L_REG (code
->dst
.reg
);
2252 ea
= code
->src
.literal
;
2254 SET_L_REG (code
->dst
.reg
, res
);
2255 goto just_flags_inc32
;
2257 case O (O_LDC
, SB
): /* ldc.b */
2258 if (fetch (sd
, &code
->src
, &res
))
2262 case O (O_LDC
, SW
): /* ldc.w */
2263 if (fetch (sd
, &code
->src
, &res
))
2266 /* Word operand, value from MSB, must be shifted. */
2270 case O (O_LDC
, SL
): /* ldc.l */
2271 if (fetch (sd
, &code
->src
, &res
))
2273 switch (code
->dst
.type
) {
2274 case X (OP_SBR
, SL
):
2275 h8_set_sbr (sd
, res
);
2277 case X (OP_VBR
, SL
):
2278 h8_set_vbr (sd
, res
);
2285 case O (O_STC
, SW
): /* stc.w */
2286 case O (O_STC
, SB
): /* stc.b */
2287 if (code
->src
.type
== X (OP_CCR
, SB
))
2290 res
= h8_get_ccr (sd
);
2292 else if (code
->src
.type
== X (OP_EXR
, SB
) && h8300smode
)
2295 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2296 res
= h8_get_exr (sd
);
2301 /* Word operand, value to MSB, must be shifted. */
2302 if (code
->opcode
== X (O_STC
, SW
))
2304 if (store (sd
, &code
->dst
, res
))
2307 case O (O_STC
, SL
): /* stc.l */
2308 switch (code
->src
.type
) {
2309 case X (OP_SBR
, SL
):
2310 res
= h8_get_sbr (sd
);
2312 case X (OP_VBR
, SL
):
2313 res
= h8_get_vbr (sd
);
2318 if (store (sd
, &code
->dst
, res
))
2322 case O (O_ANDC
, SB
): /* andc.b */
2323 if (code
->dst
.type
== X (OP_CCR
, SB
))
2326 rd
= h8_get_ccr (sd
);
2328 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2331 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2332 rd
= h8_get_exr (sd
);
2336 ea
= code
->src
.literal
;
2340 case O (O_ORC
, SB
): /* orc.b */
2341 if (code
->dst
.type
== X (OP_CCR
, SB
))
2344 rd
= h8_get_ccr (sd
);
2346 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2349 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2350 rd
= h8_get_exr (sd
);
2354 ea
= code
->src
.literal
;
2358 case O (O_XORC
, SB
): /* xorc.b */
2359 if (code
->dst
.type
== X (OP_CCR
, SB
))
2362 rd
= h8_get_ccr (sd
);
2364 else if (code
->dst
.type
== X (OP_EXR
, SB
) && h8300smode
)
2367 h8_set_exr (sd
, (trace
<< 7) | intMask
);
2368 rd
= h8_get_exr (sd
);
2372 ea
= code
->src
.literal
;
2376 case O (O_BRAS
, SB
): /* bra/s */
2377 /* This is basically an ordinary branch, with a delay slot. */
2378 if (fetch (sd
, &code
->src
, &res
))
2386 /* Execution continues at next instruction, but
2387 delayed_branch is set up for next cycle. */
2388 h8_set_delayed_branch (sd
, code
->next_pc
+ res
);
2392 case O (O_BRAB
, SB
): /* bra rd.b */
2393 case O (O_BRAW
, SW
): /* bra rd.w */
2394 case O (O_BRAL
, SL
): /* bra erd.l */
2395 if (fetch (sd
, &code
->src
, &rd
))
2397 switch (OP_SIZE (code
->opcode
)) {
2398 case SB
: rd
&= 0xff; break;
2399 case SW
: rd
&= 0xffff; break;
2400 case SL
: rd
&= 0xffffffff; break;
2402 pc
= code
->next_pc
+ rd
;
2405 case O (O_BRABC
, SB
): /* bra/bc, branch if bit clear */
2406 case O (O_BRABS
, SB
): /* bra/bs, branch if bit set */
2407 case O (O_BSRBC
, SB
): /* bsr/bc, call if bit clear */
2408 case O (O_BSRBS
, SB
): /* bsr/bs, call if bit set */
2409 if (fetch (sd
, &code
->dst
, &rd
) ||
2410 fetch (sd
, &code
->src
, &bit
))
2413 if (code
->opcode
== O (O_BRABC
, SB
) || /* branch if clear */
2414 code
->opcode
== O (O_BSRBC
, SB
)) /* call if clear */
2416 if ((rd
& (1 << bit
))) /* no branch */
2419 else /* branch/call if set */
2421 if (!(rd
& (1 << bit
))) /* no branch */
2425 if (fetch (sd
, &code
->op3
, &res
)) /* branch */
2427 pc
= code
->next_pc
+ res
;
2429 if (code
->opcode
== O (O_BRABC
, SB
) ||
2430 code
->opcode
== O (O_BRABS
, SB
)) /* branch */
2438 case O (O_BRA
, SB
): /* bra, branch always */
2443 case O (O_BRN
, SB
): /* brn, ;-/ branch never? */
2448 case O (O_BHI
, SB
): /* bhi */
2454 case O (O_BLS
, SB
): /* bls */
2459 case O (O_BCS
, SB
): /* bcs, branch if carry set */
2464 case O (O_BCC
, SB
): /* bcc, branch if carry clear */
2469 case O (O_BEQ
, SB
): /* beq, branch if zero set */
2473 case O (O_BGT
, SB
): /* bgt */
2474 if (((Z
|| (N
^ V
)) == 0))
2478 case O (O_BLE
, SB
): /* ble */
2479 if (((Z
|| (N
^ V
)) == 1))
2483 case O (O_BGE
, SB
): /* bge */
2487 case O (O_BLT
, SB
): /* blt */
2491 case O (O_BMI
, SB
): /* bmi */
2495 case O (O_BNE
, SB
): /* bne, branch if zero clear */
2500 case O (O_BPL
, SB
): /* bpl */
2504 case O (O_BVC
, SB
): /* bvc */
2508 case O (O_BVS
, SB
): /* bvs */
2513 /* Trap for Command Line setup. */
2514 case O (O_SYS_CMDLINE
, SB
):
2516 int i
= 0; /* Loop counter. */
2517 int j
= 0; /* Loop counter. */
2518 int ind_arg_len
= 0; /* Length of each argument. */
2519 int no_of_args
= 0; /* The no. or cmdline args. */
2520 int current_location
= 0; /* Location of string. */
2521 int old_sp
= 0; /* The Initial Stack Pointer. */
2522 int no_of_slots
= 0; /* No. of slots required on the stack
2523 for storing cmdline args. */
2524 int sp_move
= 0; /* No. of locations by which the stack needs
2526 int new_sp
= 0; /* The final stack pointer location passed
2528 int *argv_ptrs
; /* Pointers of argv strings to be stored. */
2529 int argv_ptrs_location
= 0; /* Location of pointers to cmdline
2530 args on the stack. */
2531 int char_ptr_size
= 0; /* Size of a character pointer on
2533 int addr_cmdline
= 0; /* Memory location where cmdline has
2535 int size_cmdline
= 0; /* Size of cmdline. */
2537 /* Set the address of 256 free locations where command line is
2539 addr_cmdline
= cmdline_location();
2540 h8_set_reg (sd
, 0, addr_cmdline
);
2542 /* Counting the no. of commandline arguments. */
2543 for (i
= 0; h8_get_cmdline_arg (sd
, i
) != NULL
; i
++)
2546 /* No. of arguments in the command line. */
2549 /* Current location is just a temporary variable,which we are
2550 setting to the point to the start of our commandline string. */
2551 current_location
= addr_cmdline
;
2553 /* Allocating space for storing pointers of the command line
2555 argv_ptrs
= (int *) malloc (sizeof (int) * no_of_args
);
2557 /* Setting char_ptr_size to the sizeof (char *) on the different
2559 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2568 for (i
= 0; i
< no_of_args
; i
++)
2572 /* The size of the commandline argument. */
2573 ind_arg_len
= strlen (h8_get_cmdline_arg (sd
, i
)) + 1;
2575 /* The total size of the command line string. */
2576 size_cmdline
+= ind_arg_len
;
2578 /* As we have only 256 bytes, we need to provide a graceful
2579 exit. Anyways, a program using command line arguments
2580 where we cannot store all the command line arguments
2581 given may behave unpredictably. */
2582 if (size_cmdline
>= 256)
2584 h8_set_reg (sd
, 0, 0);
2589 /* current_location points to the memory where the next
2590 commandline argument is stored. */
2591 argv_ptrs
[i
] = current_location
;
2592 for (j
= 0; j
< ind_arg_len
; j
++)
2594 SET_MEMORY_B ((current_location
+
2595 (sizeof (char) * j
)),
2596 *(h8_get_cmdline_arg (sd
, i
) +
2597 sizeof (char) * j
));
2600 /* Setting current_location to the starting of next
2602 current_location
+= ind_arg_len
;
2606 /* This is the original position of the stack pointer. */
2607 old_sp
= h8_get_reg (sd
, SP_REGNUM
);
2609 /* We need space from the stack to store the pointers to argvs. */
2610 /* As we will infringe on the stack, we need to shift the stack
2611 pointer so that the data is not overwritten. We calculate how
2612 much space is required. */
2613 sp_move
= (no_of_args
) * (char_ptr_size
);
2615 /* The final position of stack pointer, we have thus taken some
2616 space from the stack. */
2617 new_sp
= old_sp
- sp_move
;
2619 /* Temporary variable holding value where the argv pointers need
2621 argv_ptrs_location
= new_sp
;
2623 /* The argv pointers are stored at sequential locations. As per
2625 for (i
= 0; i
< no_of_args
; i
++)
2627 /* Saving the argv pointer. */
2628 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2630 SET_MEMORY_L (argv_ptrs_location
, argv_ptrs
[i
]);
2634 SET_MEMORY_W (argv_ptrs_location
, argv_ptrs
[i
]);
2637 /* The next location where the pointer to the next argv
2638 string has to be stored. */
2639 argv_ptrs_location
+= char_ptr_size
;
2642 /* Required by POSIX, Setting 0x0 at the end of the list of argv
2644 if ((h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2646 SET_MEMORY_L (old_sp
, 0x0);
2650 SET_MEMORY_W (old_sp
, 0x0);
2653 /* Freeing allocated memory. */
2655 for (i
= 0; i
<= no_of_args
; i
++)
2657 free (h8_get_cmdline_arg (sd
, i
));
2659 free (h8_get_command_line (sd
));
2661 /* The no. of argv arguments are returned in Reg 0. */
2662 h8_set_reg (sd
, 0, no_of_args
);
2663 /* The Pointer to argv in Register 1. */
2664 h8_set_reg (sd
, 1, new_sp
);
2665 /* Setting the stack pointer to the new value. */
2666 h8_set_reg (sd
, SP_REGNUM
, new_sp
);
2670 /* System call processing starts. */
2671 case O (O_SYS_OPEN
, SB
):
2673 int len
= 0; /* Length of filename. */
2674 char *filename
; /* Filename would go here. */
2675 char temp_char
; /* Temporary character */
2676 int mode
= 0; /* Mode bits for the file. */
2677 int open_return
; /* Return value of open, file descriptor. */
2678 int i
; /* Loop counter */
2679 int filename_ptr
; /* Pointer to filename in cpu memory. */
2681 /* Setting filename_ptr to first argument of open, */
2682 /* and trying to get mode. */
2683 if ((h8300sxmode
|| h8300hmode
|| h8300smode
) && !h8300_normal_mode
)
2685 filename_ptr
= GET_L_REG (0);
2686 mode
= GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
) + 4);
2690 filename_ptr
= GET_W_REG (0);
2691 mode
= GET_MEMORY_W (h8_get_reg (sd
, SP_REGNUM
) + 2);
2694 /* Trying to find the length of the filename. */
2695 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2698 while (temp_char
!= '\0')
2700 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2704 /* Allocating space for the filename. */
2705 filename
= (char *) malloc (sizeof (char) * len
);
2707 /* String copying the filename from memory. */
2708 for (i
= 0; i
< len
; i
++)
2710 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2711 filename
[i
] = temp_char
;
2714 /* Callback to open and return the file descriptor. */
2715 open_return
= sim_callback
->open (sim_callback
, filename
, mode
);
2717 /* Return value in register 0. */
2718 h8_set_reg (sd
, 0, open_return
);
2720 /* Freeing memory used for filename. */
2725 case O (O_SYS_READ
, SB
):
2727 char *char_ptr
; /* Where characters read would be stored. */
2728 int fd
; /* File descriptor */
2729 int buf_size
; /* BUF_SIZE parameter in read. */
2730 int i
= 0; /* Temporary Loop counter */
2731 int read_return
= 0; /* Return value from callback to
2734 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2735 buf_size
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2737 char_ptr
= (char *) malloc (sizeof (char) * buf_size
);
2739 /* Callback to read and return the no. of characters read. */
2741 sim_callback
->read (sim_callback
, fd
, char_ptr
, buf_size
);
2743 /* The characters read are stored in cpu memory. */
2744 for (i
= 0; i
< buf_size
; i
++)
2746 SET_MEMORY_B ((h8_get_reg (sd
, 1) + (sizeof (char) * i
)),
2747 *(char_ptr
+ (sizeof (char) * i
)));
2750 /* Return value in Register 0. */
2751 h8_set_reg (sd
, 0, read_return
);
2753 /* Freeing memory used as buffer. */
2758 case O (O_SYS_WRITE
, SB
):
2760 int fd
; /* File descriptor */
2761 char temp_char
; /* Temporary character */
2762 int len
; /* Length of write, Parameter II to write. */
2763 int char_ptr
; /* Character Pointer, Parameter I of write. */
2764 char *ptr
; /* Where characters to be written are stored.
2766 int write_return
; /* Return value from callback to write. */
2767 int i
= 0; /* Loop counter */
2769 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2770 char_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2771 len
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2773 /* Allocating space for the characters to be written. */
2774 ptr
= (char *) malloc (sizeof (char) * len
);
2776 /* Fetching the characters from cpu memory. */
2777 for (i
= 0; i
< len
; i
++)
2779 temp_char
= GET_MEMORY_B (char_ptr
+ i
);
2783 /* Callback write and return the no. of characters written. */
2784 write_return
= sim_callback
->write (sim_callback
, fd
, ptr
, len
);
2786 /* Return value in Register 0. */
2787 h8_set_reg (sd
, 0, write_return
);
2789 /* Freeing memory used as buffer. */
2794 case O (O_SYS_LSEEK
, SB
):
2796 int fd
; /* File descriptor */
2797 int offset
; /* Offset */
2798 int origin
; /* Origin */
2799 int lseek_return
; /* Return value from callback to lseek. */
2801 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2802 offset
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2803 origin
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (2) : GET_W_REG (2);
2805 /* Callback lseek and return offset. */
2807 sim_callback
->lseek (sim_callback
, fd
, offset
, origin
);
2809 /* Return value in register 0. */
2810 h8_set_reg (sd
, 0, lseek_return
);
2814 case O (O_SYS_CLOSE
, SB
):
2816 int fd
; /* File descriptor */
2817 int close_return
; /* Return value from callback to close. */
2819 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2821 /* Callback close and return. */
2822 close_return
= sim_callback
->close (sim_callback
, fd
);
2824 /* Return value in register 0. */
2825 h8_set_reg (sd
, 0, close_return
);
2829 case O (O_SYS_FSTAT
, SB
):
2831 int fd
; /* File descriptor */
2832 struct stat stat_rec
; /* Stat record */
2833 int fstat_return
; /* Return value from callback to stat. */
2834 int stat_ptr
; /* Pointer to stat record. */
2835 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2837 fd
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2839 /* Setting stat_ptr to second argument of stat. */
2840 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2842 /* Callback stat and return. */
2843 fstat_return
= sim_callback
->to_fstat (sim_callback
, fd
,
2846 /* Have stat_ptr point to starting of stat_rec. */
2847 temp_stat_ptr
= (char *) (&stat_rec
);
2849 /* Setting up the stat structure returned. */
2850 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2852 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2854 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2856 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2858 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2860 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2862 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2864 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2866 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2868 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2870 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2872 /* Return value in register 0. */
2873 h8_set_reg (sd
, 0, fstat_return
);
2877 case O (O_SYS_STAT
, SB
):
2879 int len
= 0; /* Length of filename. */
2880 char *filename
; /* Filename would go here. */
2881 char temp_char
; /* Temporary character */
2882 int filename_ptr
; /* Pointer to filename in cpu memory. */
2883 struct stat stat_rec
; /* Stat record */
2884 int stat_return
; /* Return value from callback to stat */
2885 int stat_ptr
; /* Pointer to stat record. */
2886 char *temp_stat_ptr
; /* Temporary stat_rec pointer. */
2887 int i
= 0; /* Loop Counter */
2889 /* Setting filename_ptr to first argument of open. */
2890 filename_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (0) : GET_W_REG (0);
2892 /* Trying to find the length of the filename. */
2893 temp_char
= GET_MEMORY_B (h8_get_reg (sd
, 0));
2896 while (temp_char
!= '\0')
2898 temp_char
= GET_MEMORY_B (filename_ptr
+ len
);
2902 /* Allocating space for the filename. */
2903 filename
= (char *) malloc (sizeof (char) * len
);
2905 /* String copying the filename from memory. */
2906 for (i
= 0; i
< len
; i
++)
2908 temp_char
= GET_MEMORY_B (filename_ptr
+ i
);
2909 filename
[i
] = temp_char
;
2912 /* Setting stat_ptr to second argument of stat. */
2913 /* stat_ptr = h8_get_reg (sd, 1); */
2914 stat_ptr
= (h8300hmode
&& !h8300_normal_mode
) ? GET_L_REG (1) : GET_W_REG (1);
2916 /* Callback stat and return. */
2918 sim_callback
->to_stat (sim_callback
, filename
, &stat_rec
);
2920 /* Have stat_ptr point to starting of stat_rec. */
2921 temp_stat_ptr
= (char *) (&stat_rec
);
2923 /* Freeing memory used for filename. */
2926 /* Setting up the stat structure returned. */
2927 SET_MEMORY_W (stat_ptr
, stat_rec
.st_dev
);
2929 SET_MEMORY_W (stat_ptr
, stat_rec
.st_ino
);
2931 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mode
);
2933 SET_MEMORY_W (stat_ptr
, stat_rec
.st_nlink
);
2935 SET_MEMORY_W (stat_ptr
, stat_rec
.st_uid
);
2937 SET_MEMORY_W (stat_ptr
, stat_rec
.st_gid
);
2939 SET_MEMORY_W (stat_ptr
, stat_rec
.st_rdev
);
2941 SET_MEMORY_L (stat_ptr
, stat_rec
.st_size
);
2943 SET_MEMORY_L (stat_ptr
, stat_rec
.st_atime
);
2945 SET_MEMORY_L (stat_ptr
, stat_rec
.st_mtime
);
2947 SET_MEMORY_L (stat_ptr
, stat_rec
.st_ctime
);
2949 /* Return value in register 0. */
2950 h8_set_reg (sd
, 0, stat_return
);
2953 /* End of system call processing. */
2955 case O (O_NOT
, SB
): /* not.b */
2956 if (fetch2 (sd
, &code
->src
, &rd
))
2962 case O (O_NOT
, SW
): /* not.w */
2963 if (fetch2 (sd
, &code
->src
, &rd
))
2969 case O (O_NOT
, SL
): /* not.l */
2970 if (fetch2 (sd
, &code
->src
, &rd
))
2976 case O (O_SHLL
, SB
): /* shll.b */
2977 case O (O_SHLR
, SB
): /* shlr.b */
2978 if (fetch2 (sd
, &code
->dst
, &rd
))
2981 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
2982 ea
= 1; /* unary op */
2983 else /* binary op */
2984 fetch (sd
, &code
->src
, &ea
);
2986 if (code
->opcode
== O (O_SHLL
, SB
))
2989 c
= rd
& (0x80 >> (ea
- 1));
2995 c
= rd
& (1 << (ea
- 1));
2996 rd
= (unsigned char) rd
>> ea
;
3000 case O (O_SHLL
, SW
): /* shll.w */
3001 case O (O_SHLR
, SW
): /* shlr.w */
3002 if (fetch2 (sd
, &code
->dst
, &rd
))
3005 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3006 ea
= 1; /* unary op */
3008 fetch (sd
, &code
->src
, &ea
);
3010 if (code
->opcode
== O (O_SHLL
, SW
))
3013 c
= rd
& (0x8000 >> (ea
- 1));
3019 c
= rd
& (1 << (ea
- 1));
3020 rd
= (unsigned short) rd
>> ea
;
3024 case O (O_SHLL
, SL
): /* shll.l */
3025 case O (O_SHLR
, SL
): /* shlr.l */
3026 if (fetch2 (sd
, &code
->dst
, &rd
))
3029 if (memcmp (&code
->src
, &code
->dst
, sizeof (code
->src
)) == 0)
3030 ea
= 1; /* unary op */
3032 fetch (sd
, &code
->src
, &ea
);
3034 if (code
->opcode
== O (O_SHLL
, SL
))
3037 c
= rd
& (0x80000000 >> (ea
- 1));
3043 c
= rd
& (1 << (ea
- 1));
3044 rd
= (unsigned int) rd
>> ea
;
3048 case O (O_SHAL
, SB
):
3049 case O (O_SHAR
, SB
):
3050 if (fetch2 (sd
, &code
->dst
, &rd
))
3053 if (code
->src
.type
== X (OP_IMM
, SB
))
3054 fetch (sd
, &code
->src
, &ea
);
3058 if (code
->opcode
== O (O_SHAL
, SB
))
3060 c
= rd
& (0x80 >> (ea
- 1));
3061 res
= rd
>> (7 - ea
);
3062 v
= ((res
& 1) && !(res
& 2))
3063 || (!(res
& 1) && (res
& 2));
3068 c
= rd
& (1 << (ea
- 1));
3070 rd
= ((signed char) rd
) >> ea
;
3074 case O (O_SHAL
, SW
):
3075 case O (O_SHAR
, SW
):
3076 if (fetch2 (sd
, &code
->dst
, &rd
))
3079 if (code
->src
.type
== X (OP_IMM
, SW
))
3080 fetch (sd
, &code
->src
, &ea
);
3084 if (code
->opcode
== O (O_SHAL
, SW
))
3086 c
= rd
& (0x8000 >> (ea
- 1));
3087 res
= rd
>> (15 - ea
);
3088 v
= ((res
& 1) && !(res
& 2))
3089 || (!(res
& 1) && (res
& 2));
3094 c
= rd
& (1 << (ea
- 1));
3096 rd
= ((signed short) rd
) >> ea
;
3100 case O (O_SHAL
, SL
):
3101 case O (O_SHAR
, SL
):
3102 if (fetch2 (sd
, &code
->dst
, &rd
))
3105 if (code
->src
.type
== X (OP_IMM
, SL
))
3106 fetch (sd
, &code
->src
, &ea
);
3110 if (code
->opcode
== O (O_SHAL
, SL
))
3112 c
= rd
& (0x80000000 >> (ea
- 1));
3113 res
= rd
>> (31 - ea
);
3114 v
= ((res
& 1) && !(res
& 2))
3115 || (!(res
& 1) && (res
& 2));
3120 c
= rd
& (1 << (ea
- 1));
3122 rd
= ((signed int) rd
) >> ea
;
3126 case O (O_ROTL
, SB
):
3127 case O (O_ROTR
, SB
):
3128 if (fetch2 (sd
, &code
->dst
, &rd
))
3131 if (code
->src
.type
== X (OP_IMM
, SB
))
3132 fetch (sd
, &code
->src
, &ea
);
3137 if (code
->opcode
== O (O_ROTL
, SB
))
3147 rd
= ((unsigned char) rd
) >> 1;
3155 case O (O_ROTL
, SW
):
3156 case O (O_ROTR
, SW
):
3157 if (fetch2 (sd
, &code
->dst
, &rd
))
3160 if (code
->src
.type
== X (OP_IMM
, SW
))
3161 fetch (sd
, &code
->src
, &ea
);
3166 if (code
->opcode
== O (O_ROTL
, SW
))
3176 rd
= ((unsigned short) rd
) >> 1;
3184 case O (O_ROTL
, SL
):
3185 case O (O_ROTR
, SL
):
3186 if (fetch2 (sd
, &code
->dst
, &rd
))
3189 if (code
->src
.type
== X (OP_IMM
, SL
))
3190 fetch (sd
, &code
->src
, &ea
);
3195 if (code
->opcode
== O (O_ROTL
, SL
))
3197 c
= rd
& 0x80000000;
3205 rd
= ((unsigned int) rd
) >> 1;
3213 case O (O_ROTXL
, SB
):
3214 case O (O_ROTXR
, SB
):
3215 if (fetch2 (sd
, &code
->dst
, &rd
))
3218 if (code
->src
.type
== X (OP_IMM
, SB
))
3219 fetch (sd
, &code
->src
, &ea
);
3224 if (code
->opcode
== O (O_ROTXL
, SB
))
3235 rd
= ((unsigned char) rd
) >> 1;
3244 case O (O_ROTXL
, SW
):
3245 case O (O_ROTXR
, SW
):
3246 if (fetch2 (sd
, &code
->dst
, &rd
))
3249 if (code
->src
.type
== X (OP_IMM
, SW
))
3250 fetch (sd
, &code
->src
, &ea
);
3255 if (code
->opcode
== O (O_ROTXL
, SW
))
3266 rd
= ((unsigned short) rd
) >> 1;
3275 case O (O_ROTXL
, SL
):
3276 case O (O_ROTXR
, SL
):
3277 if (fetch2 (sd
, &code
->dst
, &rd
))
3280 if (code
->src
.type
== X (OP_IMM
, SL
))
3281 fetch (sd
, &code
->src
, &ea
);
3286 if (code
->opcode
== O (O_ROTXL
, SL
))
3288 res
= rd
& 0x80000000;
3297 rd
= ((unsigned int) rd
) >> 1;
3308 case O (O_JMP
, SB
): /* jmp */
3310 fetch (sd
, &code
->src
, &pc
);
3315 case O (O_JSR
, SB
): /* jsr, jump to subroutine */
3317 if (fetch (sd
, &code
->src
, &pc
))
3320 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3322 if (h8300hmode
&& !h8300_normal_mode
)
3325 SET_MEMORY_L (tmp
, code
->next_pc
);
3330 SET_MEMORY_W (tmp
, code
->next_pc
);
3332 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3338 case O (O_BSR
, SB
): /* bsr, branch to subroutine */
3339 if (fetch (sd
, &code
->src
, &res
))
3341 pc
= code
->next_pc
+ res
;
3344 case O (O_RTE
, SN
): /* rte, return from exception */
3346 /* Pops exr and ccr before pc -- otherwise identical to rts. */
3347 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3349 if (h8300smode
) /* pop exr */
3351 h8_set_exr (sd
, GET_MEMORY_L (tmp
));
3354 if (h8300hmode
&& !h8300_normal_mode
)
3356 h8_set_ccr (sd
, GET_MEMORY_L (tmp
));
3358 pc
= GET_MEMORY_L (tmp
);
3363 h8_set_ccr (sd
, GET_MEMORY_W (tmp
));
3365 pc
= GET_MEMORY_W (tmp
);
3370 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3373 case O (O_RTS
, SN
): /* rts, return from subroutine */
3375 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3377 if (h8300hmode
&& !h8300_normal_mode
)
3379 pc
= GET_MEMORY_L (tmp
);
3384 pc
= GET_MEMORY_W (tmp
);
3388 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3391 case O (O_ILL
, SB
): /* illegal */
3392 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
3395 case O (O_SLEEP
, SN
): /* sleep */
3396 /* Check for magic numbers in r1 and r2. */
3397 if ((h8_get_reg (sd
, R1_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC1
&&
3398 (h8_get_reg (sd
, R2_REGNUM
) & 0xffff) == LIBC_EXIT_MAGIC2
&&
3399 SIM_WIFEXITED (h8_get_reg (sd
, 0)))
3401 /* This trap comes from _exit, not from gdb. */
3402 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_exited
,
3403 SIM_WEXITSTATUS (h8_get_reg (sd
, 0)));
3406 /* Unfortunately this won't really work, because
3407 when we take a breakpoint trap, R0 has a "random",
3408 user-defined value. Don't see any immediate solution. */
3409 else if (SIM_WIFSTOPPED (h8_get_reg (sd
, 0)))
3411 /* Pass the stop signal up to gdb. */
3412 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
,
3413 SIM_WSTOPSIG (h8_get_reg (sd
, 0)));
3418 /* Treat it as a sigtrap. */
3419 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3423 case O (O_TRAPA
, SB
): /* trapa */
3424 if (fetch (sd
, &code
->src
, &res
))
3425 goto end
; /* res is vector number. */
3427 tmp
= h8_get_reg (sd
, SP_REGNUM
);
3428 if(h8300_normal_mode
)
3431 SET_MEMORY_W (tmp
, code
->next_pc
);
3433 SET_MEMORY_W (tmp
, h8_get_ccr (sd
));
3438 SET_MEMORY_L (tmp
, code
->next_pc
);
3440 SET_MEMORY_L (tmp
, h8_get_ccr (sd
));
3448 SET_MEMORY_L (tmp
, h8_get_exr (sd
));
3451 h8_set_reg (sd
, SP_REGNUM
, tmp
);
3453 if(h8300_normal_mode
)
3454 pc
= GET_MEMORY_L (0x10 + res
* 2); /* Vector addresses are 0x10,0x12,0x14 and 0x16 */
3456 pc
= GET_MEMORY_L (0x20 + res
* 4);
3460 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
3463 case O (O_BSETEQ
, SB
):
3468 case O (O_BSETNE
, SB
):
3473 case O (O_BCLREQ
, SB
):
3478 case O (O_BCLRNE
, SB
):
3483 OBITOP (O_BNOT
, 1, 1, ea
^= m
); /* bnot */
3484 OBITOP (O_BTST
, 1, 0, nz
= ea
& m
); /* btst */
3486 OBITOP (O_BSET
, 1, 1, ea
|= m
); /* bset */
3488 OBITOP (O_BCLR
, 1, 1, ea
&= ~m
); /* bclr */
3489 OBITOP (O_BLD
, 1, 0, c
= ea
& m
); /* bld */
3490 OBITOP (O_BILD
, 1, 0, c
= !(ea
& m
)); /* bild */
3491 OBITOP (O_BST
, 1, 1, ea
&= ~m
;
3492 if (C
) ea
|= m
); /* bst */
3493 OBITOP (O_BIST
, 1, 1, ea
&= ~m
;
3494 if (!C
) ea
|= m
); /* bist */
3495 OBITOP (O_BSTZ
, 1, 1, ea
&= ~m
;
3496 if (Z
) ea
|= m
); /* bstz */
3497 OBITOP (O_BISTZ
, 1, 1, ea
&= ~m
;
3498 if (!Z
) ea
|= m
); /* bistz */
3499 OBITOP (O_BAND
, 1, 0, c
= (ea
& m
) && C
); /* band */
3500 OBITOP (O_BIAND
, 1, 0, c
= !(ea
& m
) && C
); /* biand */
3501 OBITOP (O_BOR
, 1, 0, c
= (ea
& m
) || C
); /* bor */
3502 OBITOP (O_BIOR
, 1, 0, c
= !(ea
& m
) || C
); /* bior */
3503 OBITOP (O_BXOR
, 1, 0, c
= ((ea
& m
) != 0)!= C
); /* bxor */
3504 OBITOP (O_BIXOR
, 1, 0, c
= !(ea
& m
) != C
); /* bixor */
3506 case O (O_BFLD
, SB
): /* bfld */
3509 if (fetch (sd
, &code
->src
, &bit
))
3514 if (fetch (sd
, &code
->dst
, &ea
))
3524 if (store (sd
, &code
->op3
, ea
))
3529 case O(O_BFST
, SB
): /* bfst */
3530 /* bitfield store */
3531 /* NOTE: the imm8 value is in dst, and the ea value
3532 (which is actually the destination) is in op3.
3533 It has to be that way, to avoid breaking the assembler. */
3535 if (fetch (sd
, &code
->dst
, &bit
)) /* imm8 */
3537 if (bit
== 0) /* noop -- nothing to do. */
3540 if (fetch (sd
, &code
->src
, &rd
)) /* reg8 src */
3543 if (fetch2 (sd
, &code
->op3
, &ea
)) /* ea dst */
3546 /* Left-shift the register data into position. */
3547 for (tmp
= bit
; !(tmp
& 1); tmp
>>= 1)
3550 /* Combine it with the neighboring bits. */
3551 ea
= (ea
& ~bit
) | (rd
& bit
);
3554 if (store2 (sd
, &code
->op3
, ea
))
3558 case O (O_CLRMAC
, SN
): /* clrmac */
3559 h8_set_mach (sd
, 0);
3560 h8_set_macl (sd
, 0);
3561 h8_set_macZ (sd
, 1);
3562 h8_set_macV (sd
, 0);
3563 h8_set_macN (sd
, 0);
3566 case O (O_STMAC
, SL
): /* stmac, 260 */
3567 switch (code
->src
.type
) {
3568 case X (OP_MACH
, SL
):
3569 res
= h8_get_mach (sd
);
3570 if (res
& 0x200) /* sign extend */
3573 case X (OP_MACL
, SL
):
3574 res
= h8_get_macl (sd
);
3576 default: goto illegal
;
3578 nz
= !h8_get_macZ (sd
);
3579 n
= h8_get_macN (sd
);
3580 v
= h8_get_macV (sd
);
3582 if (store (sd
, &code
->dst
, res
))
3587 case O (O_LDMAC
, SL
): /* ldmac, 179 */
3588 if (fetch (sd
, &code
->src
, &rd
))
3591 switch (code
->dst
.type
) {
3592 case X (OP_MACH
, SL
):
3593 rd
&= 0x3ff; /* Truncate to 10 bits */
3594 h8_set_mach (sd
, rd
);
3596 case X (OP_MACL
, SL
):
3597 h8_set_macl (sd
, rd
);
3599 default: goto illegal
;
3601 h8_set_macV (sd
, 0);
3605 if (fetch (sd
, &code
->src
, &rd
) ||
3606 fetch (sd
, &code
->dst
, &res
))
3609 /* Ye gods, this is non-portable!
3610 However, the existing mul/div code is similar. */
3611 res
= SEXTSHORT (res
) * SEXTSHORT (rd
);
3613 if (h8_get_macS (sd
)) /* Saturating mode */
3615 long long mac
= h8_get_macl (sd
);
3617 if (mac
& 0x80000000) /* sign extend */
3618 mac
|= 0xffffffff00000000LL
;
3621 if (mac
> 0x7fffffff || mac
< 0xffffffff80000000LL
)
3622 h8_set_macV (sd
, 1);
3623 h8_set_macZ (sd
, (mac
== 0));
3624 h8_set_macN (sd
, (mac
< 0));
3625 h8_set_macl (sd
, (int) mac
);
3627 else /* "Less Saturating" mode */
3629 long long mac
= h8_get_mach (sd
);
3631 mac
+= h8_get_macl (sd
);
3633 if (mac
& 0x20000000000LL
) /* sign extend */
3634 mac
|= 0xfffffc0000000000LL
;
3637 if (mac
> 0x1ffffffffffLL
||
3638 mac
< (long long) 0xfffffe0000000000LL
)
3639 h8_set_macV (sd
, 1);
3640 h8_set_macZ (sd
, (mac
== 0));
3641 h8_set_macN (sd
, (mac
< 0));
3642 h8_set_macl (sd
, (int) mac
);
3644 h8_set_mach (sd
, (int) (mac
& 0x3ff));
3648 case O (O_MULS
, SW
): /* muls.w */
3649 if (fetch (sd
, &code
->src
, &ea
) ||
3650 fetch (sd
, &code
->dst
, &rd
))
3653 ea
= SEXTSHORT (ea
);
3654 res
= SEXTSHORT (ea
* SEXTSHORT (rd
));
3658 if (store (sd
, &code
->dst
, res
))
3663 case O (O_MULS
, SL
): /* muls.l */
3664 if (fetch (sd
, &code
->src
, &ea
) ||
3665 fetch (sd
, &code
->dst
, &rd
))
3670 n
= res
& 0x80000000;
3671 nz
= res
& 0xffffffff;
3672 if (store (sd
, &code
->dst
, res
))
3676 case O (O_MULSU
, SL
): /* muls/u.l */
3677 if (fetch (sd
, &code
->src
, &ea
) ||
3678 fetch (sd
, &code
->dst
, &rd
))
3681 /* Compute upper 32 bits of the 64-bit result. */
3682 res
= (((long long) ea
) * ((long long) rd
)) >> 32;
3684 n
= res
& 0x80000000;
3685 nz
= res
& 0xffffffff;
3686 if (store (sd
, &code
->dst
, res
))
3690 case O (O_MULU
, SW
): /* mulu.w */
3691 if (fetch (sd
, &code
->src
, &ea
) ||
3692 fetch (sd
, &code
->dst
, &rd
))
3695 res
= UEXTSHORT ((UEXTSHORT (ea
) * UEXTSHORT (rd
)));
3697 /* Don't set Z or N. */
3698 if (store (sd
, &code
->dst
, res
))
3703 case O (O_MULU
, SL
): /* mulu.l */
3704 if (fetch (sd
, &code
->src
, &ea
) ||
3705 fetch (sd
, &code
->dst
, &rd
))
3710 /* Don't set Z or N. */
3711 if (store (sd
, &code
->dst
, res
))
3716 case O (O_MULUU
, SL
): /* mulu/u.l */
3717 if (fetch (sd
, &code
->src
, &ea
) ||
3718 fetch (sd
, &code
->dst
, &rd
))
3721 /* Compute upper 32 bits of the 64-bit result. */
3722 res
= (((unsigned long long) (unsigned) ea
) *
3723 ((unsigned long long) (unsigned) rd
)) >> 32;
3725 /* Don't set Z or N. */
3726 if (store (sd
, &code
->dst
, res
))
3731 case O (O_MULXS
, SB
): /* mulxs.b */
3732 if (fetch (sd
, &code
->src
, &ea
) ||
3733 fetch (sd
, &code
->dst
, &rd
))
3737 res
= ea
* SEXTCHAR (rd
);
3741 if (store (sd
, &code
->dst
, res
))
3746 case O (O_MULXS
, SW
): /* mulxs.w */
3747 if (fetch (sd
, &code
->src
, &ea
) ||
3748 fetch (sd
, &code
->dst
, &rd
))
3751 ea
= SEXTSHORT (ea
);
3752 res
= ea
* SEXTSHORT (rd
& 0xffff);
3754 n
= res
& 0x80000000;
3755 nz
= res
& 0xffffffff;
3756 if (store (sd
, &code
->dst
, res
))
3761 case O (O_MULXU
, SB
): /* mulxu.b */
3762 if (fetch (sd
, &code
->src
, &ea
) ||
3763 fetch (sd
, &code
->dst
, &rd
))
3766 res
= UEXTCHAR (ea
) * UEXTCHAR (rd
);
3768 if (store (sd
, &code
->dst
, res
))
3773 case O (O_MULXU
, SW
): /* mulxu.w */
3774 if (fetch (sd
, &code
->src
, &ea
) ||
3775 fetch (sd
, &code
->dst
, &rd
))
3778 res
= UEXTSHORT (ea
) * UEXTSHORT (rd
);
3780 if (store (sd
, &code
->dst
, res
))
3785 case O (O_TAS
, SB
): /* tas (test and set) */
3786 if (!h8300sxmode
) /* h8sx can use any register. */
3787 switch (code
->src
.reg
)
3798 if (fetch (sd
, &code
->src
, &res
))
3800 if (store (sd
, &code
->src
, res
| 0x80))
3803 goto just_flags_log8
;
3805 case O (O_DIVU
, SW
): /* divu.w */
3806 if (fetch (sd
, &code
->src
, &ea
) ||
3807 fetch (sd
, &code
->dst
, &rd
))
3813 res
= (unsigned) (UEXTSHORT (rd
) / UEXTSHORT (ea
));
3817 if (store (sd
, &code
->dst
, res
))
3821 case O (O_DIVU
, SL
): /* divu.l */
3822 if (fetch (sd
, &code
->src
, &ea
) ||
3823 fetch (sd
, &code
->dst
, &rd
))
3826 n
= ea
& 0x80000000;
3827 nz
= ea
& 0xffffffff;
3829 res
= (unsigned) rd
/ ea
;
3833 if (store (sd
, &code
->dst
, res
))
3837 case O (O_DIVS
, SW
): /* divs.w */
3838 if (fetch (sd
, &code
->src
, &ea
) ||
3839 fetch (sd
, &code
->dst
, &rd
))
3844 res
= SEXTSHORT (rd
) / SEXTSHORT (ea
);
3854 if (store (sd
, &code
->dst
, res
))
3858 case O (O_DIVS
, SL
): /* divs.l */
3859 if (fetch (sd
, &code
->src
, &ea
) ||
3860 fetch (sd
, &code
->dst
, &rd
))
3874 n
= res
& 0x80000000;
3875 if (store (sd
, &code
->dst
, res
))
3879 case O (O_DIVXU
, SB
): /* divxu.b */
3880 if (fetch (sd
, &code
->src
, &ea
) ||
3881 fetch (sd
, &code
->dst
, &rd
))
3884 rd
= UEXTSHORT (rd
);
3891 tmp
= (unsigned) rd
% ea
;
3892 res
= (unsigned) rd
/ ea
;
3900 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3904 case O (O_DIVXU
, SW
): /* divxu.w */
3905 if (fetch (sd
, &code
->src
, &ea
) ||
3906 fetch (sd
, &code
->dst
, &rd
))
3909 ea
= UEXTSHORT (ea
);
3915 tmp
= (unsigned) rd
% ea
;
3916 res
= (unsigned) rd
/ ea
;
3924 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3928 case O (O_DIVXS
, SB
): /* divxs.b */
3929 if (fetch (sd
, &code
->src
, &ea
) ||
3930 fetch (sd
, &code
->dst
, &rd
))
3933 rd
= SEXTSHORT (rd
);
3938 tmp
= (int) rd
% (int) ea
;
3939 res
= (int) rd
/ (int) ea
;
3950 if (store (sd
, &code
->dst
, (res
& 0xff) | (tmp
<< 8)))
3954 case O (O_DIVXS
, SW
): /* divxs.w */
3955 if (fetch (sd
, &code
->src
, &ea
) ||
3956 fetch (sd
, &code
->dst
, &rd
))
3959 ea
= SEXTSHORT (ea
);
3963 tmp
= (int) rd
% (int) ea
;
3964 res
= (int) rd
/ (int) ea
;
3974 n
= res
& 0x80000000;
3975 if (store (sd
, &code
->dst
, (res
& 0xffff) | (tmp
<< 16)))
3979 case O (O_EXTS
, SW
): /* exts.w, signed extend */
3980 if (fetch2 (sd
, &code
->dst
, &rd
))
3982 ea
= rd
& 0x80 ? -256 : 0;
3983 res
= (rd
& 0xff) + ea
;
3986 case O (O_EXTS
, SL
): /* exts.l, signed extend */
3987 if (fetch2 (sd
, &code
->dst
, &rd
))
3989 if (code
->src
.type
== X (OP_IMM
, SL
))
3991 if (fetch (sd
, &code
->src
, &ea
))
3994 if (ea
== 2) /* exts.l #2, nn */
3996 /* Sign-extend from 8-bit to 32-bit. */
3997 ea
= rd
& 0x80 ? -256 : 0;
3998 res
= (rd
& 0xff) + ea
;
4002 /* Sign-extend from 16-bit to 32-bit. */
4003 ea
= rd
& 0x8000 ? -65536 : 0;
4004 res
= (rd
& 0xffff) + ea
;
4007 case O (O_EXTU
, SW
): /* extu.w, unsigned extend */
4008 if (fetch2 (sd
, &code
->dst
, &rd
))
4011 res
= (rd
& 0xff) + ea
;
4014 case O (O_EXTU
, SL
): /* extu.l, unsigned extend */
4015 if (fetch2 (sd
, &code
->dst
, &rd
))
4017 if (code
->src
.type
== X (OP_IMM
, SL
))
4019 if (fetch (sd
, &code
->src
, &ea
))
4022 if (ea
== 2) /* extu.l #2, nn */
4024 /* Zero-extend from 8-bit to 32-bit. */
4026 res
= (rd
& 0xff) + ea
;
4030 /* Zero-extend from 16-bit to 32-bit. */
4032 res
= (rd
& 0xffff) + ea
;
4035 case O (O_NOP
, SN
): /* nop */
4038 case O (O_STM
, SL
): /* stm, store to memory */
4040 int nregs
, firstreg
, i
;
4042 nregs
= GET_MEMORY_B (pc
+ 1);
4045 firstreg
= code
->src
.reg
;
4047 for (i
= firstreg
; i
<= firstreg
+ nregs
; i
++)
4049 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) - 4);
4050 SET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
), h8_get_reg (sd
, i
));
4055 case O (O_LDM
, SL
): /* ldm, load from memory */
4056 case O (O_RTEL
, SN
): /* rte/l, ldm plus rte */
4057 case O (O_RTSL
, SN
): /* rts/l, ldm plus rts */
4059 int nregs
, firstreg
, i
;
4061 nregs
= ((GET_MEMORY_B (pc
+ 1) >> 4) & 0xf);
4062 firstreg
= code
->dst
.reg
& 0xf;
4063 for (i
= firstreg
; i
>= firstreg
- nregs
; i
--)
4065 h8_set_reg (sd
, i
, GET_MEMORY_L (h8_get_reg (sd
, SP_REGNUM
)));
4066 h8_set_reg (sd
, SP_REGNUM
, h8_get_reg (sd
, SP_REGNUM
) + 4);
4069 switch (code
->opcode
) {
4070 case O (O_RTEL
, SN
):
4072 case O (O_RTSL
, SN
):
4081 /* Decimal Adjust Addition. This is for BCD arithmetic. */
4082 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch? */
4083 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4084 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4085 res
= res
; /* Value added == 0. */
4086 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4087 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4088 res
= res
+ 0x6; /* Value added == 6. */
4089 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4090 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4091 res
= res
+ 0x6; /* Value added == 6. */
4092 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4093 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4094 res
= res
+ 0x60; /* Value added == 60. */
4095 else if (!c
&& (9 <= (res
>> 4) && (res
>> 4) <= 15) &&
4096 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4097 res
= res
+ 0x66; /* Value added == 66. */
4098 else if (!c
&& (10 <= (res
>> 4) && (res
>> 4) <= 15) &&
4099 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4100 res
= res
+ 0x66; /* Value added == 66. */
4101 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4102 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4103 res
= res
+ 0x60; /* Value added == 60. */
4104 else if ( c
&& (1 <= (res
>> 4) && (res
>> 4) <= 2) &&
4105 !h
&& (10 <= (res
& 0xf) && (res
& 0xf) <= 15))
4106 res
= res
+ 0x66; /* Value added == 66. */
4107 else if (c
&& (1 <= (res
>> 4) && (res
>> 4) <= 3) &&
4108 h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 3))
4109 res
= res
+ 0x66; /* Value added == 66. */
4114 /* Decimal Adjust Subtraction. This is for BCD arithmetic. */
4115 res
= GET_B_REG (code
->src
.reg
); /* FIXME fetch, fetch2... */
4116 if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 9) &&
4117 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4118 res
= res
; /* Value added == 0. */
4119 else if (!c
&& (0 <= (res
>> 4) && (res
>> 4) <= 8) &&
4120 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4121 res
= res
+ 0xfa; /* Value added == 0xfa. */
4122 else if ( c
&& (7 <= (res
>> 4) && (res
>> 4) <= 15) &&
4123 !h
&& (0 <= (res
& 0xf) && (res
& 0xf) <= 9))
4124 res
= res
+ 0xa0; /* Value added == 0xa0. */
4125 else if (c
&& (6 <= (res
>> 4) && (res
>> 4) <= 15) &&
4126 h
&& (6 <= (res
& 0xf) && (res
& 0xf) <= 15))
4127 res
= res
+ 0x9a; /* Value added == 0x9a. */
4133 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4138 sim_io_printf (sd
, "sim_resume: internal error.\n");
4139 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_stopped
, SIM_SIGILL
);
4143 if (code
->dst
.type
== X (OP_CCR
, SB
) ||
4144 code
->dst
.type
== X (OP_CCR
, SW
))
4146 h8_set_ccr (sd
, res
);
4149 else if (h8300smode
&&
4150 (code
->dst
.type
== X (OP_EXR
, SB
) ||
4151 code
->dst
.type
== X (OP_EXR
, SW
)))
4153 h8_set_exr (sd
, res
);
4154 if (h8300smode
) /* Get exr. */
4156 trace
= (h8_get_exr (sd
) >> 7) & 1;
4157 intMask
= h8_get_exr (sd
) & 7;
4166 /* When a branch works */
4167 if (fetch (sd
, &code
->src
, &res
))
4169 if (res
& 1) /* bad address */
4171 pc
= code
->next_pc
+ res
;
4174 /* Set the cond codes from res */
4177 /* Set the flags after an 8 bit inc/dec operation */
4181 v
= (rd
& 0x7f) == 0x7f;
4184 /* Set the flags after an 16 bit inc/dec operation */
4188 v
= (rd
& 0x7fff) == 0x7fff;
4191 /* Set the flags after an 32 bit inc/dec operation */
4193 n
= res
& 0x80000000;
4194 nz
= res
& 0xffffffff;
4195 v
= (rd
& 0x7fffffff) == 0x7fffffff;
4199 /* Set flags after an 8 bit shift op, carry,overflow set in insn */
4202 if (store2 (sd
, &code
->dst
, rd
))
4207 /* Set flags after an 16 bit shift op, carry,overflow set in insn */
4210 if (store2 (sd
, &code
->dst
, rd
))
4215 /* Set flags after an 32 bit shift op, carry,overflow set in insn */
4216 n
= (rd
& 0x80000000);
4217 nz
= rd
& 0xffffffff;
4218 if (store2 (sd
, &code
->dst
, rd
))
4223 if (store2 (sd
, &code
->dst
, res
))
4227 /* flags after a 32bit logical operation */
4228 n
= res
& 0x80000000;
4229 nz
= res
& 0xffffffff;
4234 if (store2 (sd
, &code
->dst
, res
))
4238 /* flags after a 16bit logical operation */
4245 if (store2 (sd
, &code
->dst
, res
))
4255 if (store2 (sd
, &code
->dst
, res
))
4262 switch (code
->opcode
/ 4)
4266 v
= ((rd
& 0x80) == (ea
& 0x80)
4267 && (rd
& 0x80) != (res
& 0x80));
4272 v
= ((rd
& 0x80) != (-ea
& 0x80)
4273 && (rd
& 0x80) != (res
& 0x80));
4280 break; /* No effect on v flag. */
4285 if (store2 (sd
, &code
->dst
, res
))
4291 c
= (res
& 0x10000);
4292 switch (code
->opcode
/ 4)
4296 v
= ((rd
& 0x8000) == (ea
& 0x8000)
4297 && (rd
& 0x8000) != (res
& 0x8000));
4302 v
= ((rd
& 0x8000) != (-ea
& 0x8000)
4303 && (rd
& 0x8000) != (res
& 0x8000));
4312 if (store2 (sd
, &code
->dst
, res
))
4316 n
= res
& 0x80000000;
4317 nz
= res
& 0xffffffff;
4318 switch (code
->opcode
/ 4)
4322 v
= ((rd
& 0x80000000) == (ea
& 0x80000000)
4323 && (rd
& 0x80000000) != (res
& 0x80000000));
4324 c
= ((unsigned) res
< (unsigned) rd
) ||
4325 ((unsigned) res
< (unsigned) ea
);
4330 v
= ((rd
& 0x80000000) != (-ea
& 0x80000000)
4331 && (rd
& 0x80000000) != (res
& 0x80000000));
4332 c
= (unsigned) rd
< (unsigned) -ea
;
4335 v
= (rd
== 0x80000000);
4342 if ((res
= h8_get_delayed_branch (sd
)) != 0)
4345 h8_set_delayed_branch (sd
, 0);
4353 h8_set_ticks (sd
, h8_get_ticks (sd
) + get_now () - tick_start
);
4354 h8_set_cycles (sd
, h8_get_cycles (sd
) + cycles
);
4355 h8_set_insts (sd
, h8_get_insts (sd
) + insts
);
4360 h8_set_exr (sd
, (trace
<<7) | intMask
);
4362 h8_set_mask (sd
, oldmask
);
4366 sim_engine_run (SIM_DESC sd
,
4367 int next_cpu_nr
, /* ignore */
4368 int nr_cpus
, /* ignore */
4373 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4375 cpu
= STATE_CPU (sd
, 0);
4379 step_once (sd
, cpu
);
4380 if (sim_events_tick (sd
))
4381 sim_events_process (sd
);
4386 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
4393 for (i
= 0; i
< size
; i
++)
4395 if (addr
< memory_size
)
4397 h8_set_memory (sd
, addr
+ i
, buffer
[i
]);
4406 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
4411 if (addr
+ size
< memory_size
)
4412 memcpy (buffer
, h8_get_memory_buf (sd
) + addr
, size
);
4419 h8300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *value
, int length
)
4424 longval
= (value
[0] << 24) | (value
[1] << 16) | (value
[2] << 8) | value
[3];
4425 shortval
= (value
[0] << 8) | (value
[1]);
4426 intval
= h8300hmode
? longval
: shortval
;
4428 init_pointers (CPU_STATE (cpu
));
4432 if(h8300_normal_mode
)
4433 cpu
->pc
= shortval
; /* PC for Normal mode is 2 bytes */
4453 cpu
->regs
[rn
] = intval
;
4458 cpu
->regs
[rn
] = longval
;
4465 h8300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *buf
, int length
)
4470 init_pointers (CPU_STATE (cpu
));
4472 if (!h8300smode
&& rn
>= EXR_REGNUM
)
4507 /* In Normal mode PC is 2 byte, but other registers are 4 byte */
4508 if ((h8300hmode
|| longreg
) && !(rn
== PC_REGNUM
&& h8300_normal_mode
))
4525 sim_info (SIM_DESC sd
, int verbose
)
4527 double timetaken
= (double) h8_get_ticks (sd
) / (double) now_persec ();
4528 double virttime
= h8_get_cycles (sd
) / 10.0e6
;
4530 sim_io_printf (sd
, "\n\n#instructions executed %10d\n", h8_get_insts (sd
));
4531 sim_io_printf (sd
, "#cycles (v approximate) %10d\n", h8_get_cycles (sd
));
4532 sim_io_printf (sd
, "#real time taken %10.4f\n", timetaken
);
4533 sim_io_printf (sd
, "#virtual time taken %10.4f\n", virttime
);
4534 if (timetaken
!= 0.0)
4535 sim_io_printf (sd
, "#simulation ratio %10.4f\n", virttime
/ timetaken
);
4538 /* This to be conditional on `what' (aka `verbose'),
4539 however it was never passed as non-zero. */
4543 for (i
= 0; i
< O_LAST
; i
++)
4545 if (h8_get_stats (sd
, i
))
4546 sim_io_printf (sd
, "%d: %d\n", i
, h8_get_stats (sd
, i
));
4552 /* Indicate whether the cpu is an H8/300 or H8/300H.
4553 FLAG is non-zero for the H8/300H. */
4556 set_h8300h (unsigned long machine
)
4558 /* FIXME: Much of the code in sim_load can be moved to sim_open.
4559 This function being replaced by a sim_open:ARGV configuration
4562 h8300hmode
= h8300smode
= h8300sxmode
= h8300_normal_mode
= 0;
4564 if (machine
== bfd_mach_h8300sx
|| machine
== bfd_mach_h8300sxn
)
4567 if (machine
== bfd_mach_h8300s
|| machine
== bfd_mach_h8300sn
|| h8300sxmode
)
4570 if (machine
== bfd_mach_h8300h
|| machine
== bfd_mach_h8300hn
|| h8300smode
)
4573 if(machine
== bfd_mach_h8300hn
|| machine
== bfd_mach_h8300sn
|| machine
== bfd_mach_h8300sxn
)
4574 h8300_normal_mode
= 1;
4577 /* H8300-specific options.
4578 TODO: These really should be merged into the common model modules. */
4586 h8300_option_handler (SIM_DESC sd
, sim_cpu
*cpu ATTRIBUTE_UNUSED
, int opt
,
4587 char *arg
, int is_command ATTRIBUTE_UNUSED
)
4589 switch ((H8300_OPTIONS
) opt
)
4592 set_h8300h (bfd_mach_h8300h
);
4595 set_h8300h (bfd_mach_h8300s
);
4597 case OPTION_H8300SX
:
4598 set_h8300h (bfd_mach_h8300sx
);
4602 /* We'll actually never get here; the caller handles the error
4604 sim_io_eprintf (sd
, "Unknown option `%s'\n", arg
);
4611 static const OPTION h8300_options
[] =
4613 { {"h8300h", no_argument
, NULL
, OPTION_H8300H
},
4614 'h', NULL
, "Indicate the CPU is H8/300H",
4615 h8300_option_handler
},
4616 { {"h8300s", no_argument
, NULL
, OPTION_H8300S
},
4617 'S', NULL
, "Indicate the CPU is H8S",
4618 h8300_option_handler
},
4619 { {"h8300sx", no_argument
, NULL
, OPTION_H8300SX
},
4620 'x', NULL
, "Indicate the CPU is H8SX",
4621 h8300_option_handler
},
4622 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
, NULL
}
4626 h8300_pc_get (sim_cpu
*cpu
)
4632 h8300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
4637 /* Cover function of sim_state_free to free the cpu buffers as well. */
4640 free_state (SIM_DESC sd
)
4642 if (STATE_MODULES (sd
) != NULL
)
4643 sim_module_uninstall (sd
);
4645 /* Fixme: free buffers in _sim_cpu. */
4646 sim_state_free (sd
);
4650 sim_open (SIM_OPEN_KIND kind
,
4651 struct host_callback_struct
*callback
,
4659 sd
= sim_state_alloc (kind
, callback
);
4661 /* The cpu data is kept in a separately allocated chunk of memory. */
4662 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
4668 cpu
= STATE_CPU (sd
, 0);
4669 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
4670 cpu
->regs
[SBR_REGNUM
] = 0xFFFFFF00;
4671 /* sim_cpu object is new, so some initialization is needed. */
4672 init_pointers_needed
= 1;
4674 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
4680 if (sim_add_option_table (sd
, NULL
, h8300_options
) != SIM_RC_OK
)
4686 /* The parser will print an error message for us, so we silently return. */
4687 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
4689 /* Uninstall the modules to avoid memory leaks,
4690 file descriptor leaks, etc. */
4695 /* Check for/establish the a reference program image. */
4696 if (sim_analyze_program (sd
,
4697 (STATE_PROG_ARGV (sd
) != NULL
4698 ? *STATE_PROG_ARGV (sd
)
4699 : NULL
), abfd
) != SIM_RC_OK
)
4705 /* Establish any remaining configuration options. */
4706 if (sim_config (sd
) != SIM_RC_OK
)
4712 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
4714 /* Uninstall the modules to avoid memory leaks,
4715 file descriptor leaks, etc. */
4720 /* CPU specific initialization. */
4721 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
4723 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
4725 CPU_REG_FETCH (cpu
) = h8300_reg_fetch
;
4726 CPU_REG_STORE (cpu
) = h8300_reg_store
;
4727 CPU_PC_FETCH (cpu
) = h8300_pc_get
;
4728 CPU_PC_STORE (cpu
) = h8300_pc_set
;
4731 /* sim_hw_configure (sd); */
4733 /* FIXME: Much of the code in sim_load can be moved here. */
4738 /* Called by gdb to load a program into memory. */
4741 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
4745 /* FIXME: The code below that sets a specific variant of the H8/300
4746 being simulated should be moved to sim_open(). */
4748 /* See if the file is for the H8/300 or H8/300H. */
4749 /* ??? This may not be the most efficient way. The z8k simulator
4750 does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */
4754 prog_bfd
= bfd_openr (prog
, NULL
);
4755 if (prog_bfd
!= NULL
)
4757 /* Set the cpu type. We ignore failure from bfd_check_format
4758 and bfd_openr as sim_load_file checks too. */
4759 if (bfd_check_format (prog_bfd
, bfd_object
))
4761 set_h8300h (bfd_get_mach (prog_bfd
));
4765 /* If we're using gdb attached to the simulator, then we have to
4766 reallocate memory for the simulator.
4768 When gdb first starts, it calls fetch_registers (among other
4769 functions), which in turn calls init_pointers, which allocates
4772 The problem is when we do that, we don't know whether we're
4773 debugging an H8/300 or H8/300H program.
4775 This is the first point at which we can make that determination,
4776 so we just reallocate memory now; this will also allow us to handle
4777 switching between H8/300 and H8/300H programs without exiting
4780 if (h8300smode
&& !h8300_normal_mode
)
4781 memory_size
= H8300S_MSIZE
;
4782 else if (h8300hmode
&& !h8300_normal_mode
)
4783 memory_size
= H8300H_MSIZE
;
4785 memory_size
= H8300_MSIZE
;
4787 if (h8_get_memory_buf (sd
))
4788 free (h8_get_memory_buf (sd
));
4790 h8_set_memory_buf (sd
, (unsigned char *)
4791 calloc (sizeof (char), memory_size
));
4792 sd
->memory_size
= memory_size
;
4794 /* `msize' must be a power of two. */
4795 if ((memory_size
& (memory_size
- 1)) != 0)
4797 sim_io_printf (sd
, "sim_load: bad memory size.\n");
4800 h8_set_mask (sd
, memory_size
- 1);
4802 if (sim_load_file (sd
, STATE_MY_NAME (sd
), STATE_CALLBACK (sd
), prog
,
4803 prog_bfd
, STATE_OPEN_KIND (sd
) == SIM_OPEN_DEBUG
,
4807 /* Close the bfd if we opened it. */
4808 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4809 bfd_close (prog_bfd
);
4813 /* Close the bfd if we opened it. */
4814 if (abfd
== NULL
&& prog_bfd
!= NULL
)
4815 bfd_close (prog_bfd
);
4820 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
4821 char * const *argv
, char * const *env
)
4828 h8_set_pc (sd
, bfd_get_start_address (abfd
));
4832 /* Command Line support. */
4835 /* Counting the no. of commandline arguments. */
4836 for (no_of_args
= 0; argv
[no_of_args
] != NULL
; no_of_args
++)
4839 /* Allocating memory for the argv pointers. */
4840 h8_set_command_line (sd
, (char **) malloc ((sizeof (char *))
4841 * (no_of_args
+ 1)));
4843 for (i
= 0; i
< no_of_args
; i
++)
4845 /* Copying the argument string. */
4846 h8_set_cmdline_arg (sd
, i
, (char *) strdup (argv
[i
]));
4848 h8_set_cmdline_arg (sd
, i
, NULL
);