* callback.c (os_stat): Make 3rd arg a host struct stat ptr.
[binutils-gdb.git] / sim / igen / igen.h
1 /* This file is part of the program psim.
2
3 Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18
19 */
20
21 /* code-generation options: */
22
23 typedef enum {
24
25 /* Transfer control to an instructions semantic code using the the
26 standard call/return mechanism */
27
28 generate_calls,
29
30 /* Transfer control to an instructions semantic code using
31 (computed) goto's instead of the more conventional call/return
32 mechanism */
33
34 generate_jumps,
35
36 } igen_code;
37
38 typedef enum {
39 nia_is_cia_plus_one,
40 nia_is_void,
41 nia_is_invalid,
42 } igen_nia;
43
44
45
46 typedef struct _igen_gen_options igen_gen_options;
47 struct _igen_gen_options {
48 int direct_access;
49 int semantic_icache;
50 int insn_in_icache;
51 int conditional_issue;
52 int slot_verification;
53 int delayed_branch;
54
55 /* If zeroing a register, which one? */
56 int zero_reg;
57 int zero_reg_nr;
58
59 /* should multiple simulators be generated? */
60 int multi_sim;
61
62 /* should the simulator support multi word instructions and if so,
63 what is the max nr of words. */
64 int multi_word;
65
66 /* SMP? Should the generated code include SMP support (>0) and if
67 so, for how many processors? */
68 int smp;
69
70 /* how should the next instruction address be computed? */
71 igen_nia nia;
72
73 /* nr of instructions in the decoded instruction cache */
74 int icache;
75 int icache_size;
76
77 /* see above */
78 igen_code code;
79 };
80
81
82 typedef struct _igen_trace_options igen_trace_options;
83 struct _igen_trace_options {
84 int rule_selection;
85 int rule_rejection;
86 int entries;
87 int combine;
88 };
89
90 typedef struct _igen_prefix_name {
91 char *name;
92 char *uname;
93 } igen_prefix_name;
94
95 typedef struct _igen_prefix_options {
96 igen_prefix_name global;
97 igen_prefix_name engine;
98 igen_prefix_name icache;
99 igen_prefix_name idecode;
100 igen_prefix_name itable;
101 igen_prefix_name semantics;
102 igen_prefix_name support;
103 } igen_prefix_options;
104
105 typedef struct _igen_decode_options igen_decode_options ;
106 struct _igen_decode_options {
107
108 /* Combine tables? Should the generator make a second pass through
109 each generated table looking for any sub-entries that contain the
110 same instructions. Those entries being merged into a single
111 table */
112 int combine;
113
114 /* Instruction expansion? Should the semantic code for each
115 instruction, when the oportunity arrises, be expanded according
116 to the variable opcode files that the instruction decode process
117 renders constant */
118 int duplicate;
119
120 /* Treat reserved fields as constant (zero) instead of ignoring
121 their value when determining decode tables */
122 int zero_reserved;
123
124 /* Convert any padded switch rules into goto_switch */
125 int switch_as_goto;
126
127 /* Force all tables to be generated with this lookup mechanism */
128 char *overriding_gen;
129 };
130
131
132 typedef struct _igen_warn_options igen_warn_options;
133 struct _igen_warn_options {
134 int discard;
135 };
136
137
138 typedef struct _igen_options igen_options;
139 struct _igen_options {
140
141 /* What does the instruction look like - bit ordering, size, widths or
142 offesets */
143 int hi_bit_nr;
144 int insn_bit_size;
145 int insn_specifying_widths;
146
147 /* what should global names be prefixed with? */
148 igen_prefix_options prefix;
149
150 /* See above for options and flags */
151 igen_gen_options gen;
152
153 /* See above for trace options */
154 igen_trace_options trace;
155
156 /* See above for decode options */
157 igen_decode_options decode;
158
159 /* Filter set to be used on the flag field of the instruction table */
160 filter *flags_filter;
161
162 /* See above for warn options */
163 igen_warn_options warn;
164
165 /* Be more picky about the input */
166 error_func (*warning);
167
168 /* Model (processor) set - like flags_filter. Used to select the
169 specific ISA within a processor family. */
170 filter *model_filter;
171
172 /* Format name set */
173 filter *format_name_filter;
174 };
175
176 extern igen_options options;
177
178 /* default options - hopefully backward compatible */ \
179 #define INIT_OPTIONS(OPTIONS) \
180 do { \
181 memset (&(OPTIONS), 0, sizeof (OPTIONS)); \
182 memset (&(OPTIONS).warn, -1, sizeof ((OPTIONS).warn)); \
183 (OPTIONS).hi_bit_nr = 0; \
184 (OPTIONS).insn_bit_size = default_insn_bit_size; \
185 (OPTIONS).insn_specifying_widths = 0; \
186 (OPTIONS).prefix.global.name = ""; \
187 (OPTIONS).prefix.global.uname = ""; \
188 (OPTIONS).prefix.engine = (OPTIONS).prefix.global; \
189 (OPTIONS).prefix.icache = (OPTIONS).prefix.global; \
190 (OPTIONS).prefix.idecode = (OPTIONS).prefix.global; \
191 (OPTIONS).prefix.itable = (OPTIONS).prefix.global; \
192 (OPTIONS).prefix.semantics = (OPTIONS).prefix.global; \
193 (OPTIONS).prefix.support = (OPTIONS).prefix.global; \
194 (OPTIONS).gen.code = generate_calls; \
195 (OPTIONS).gen.icache_size = 1024; \
196 (OPTIONS).warning = warning; \
197 } while (0)