1 /* Lattice Mico32 exception and system call support.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009-2022 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This must come before any other includes. */
24 #define WANT_CPU lm32bf
25 #define WANT_CPU_LM32BF
28 #include "sim-signal.h"
29 #include "sim-syscall.h"
31 #include "target-newlib-syscall.h"
33 /* Handle invalid instructions. */
36 sim_engine_invalid_insn (SIM_CPU
* current_cpu
, IADDR cia
, SEM_PC pc
)
38 SIM_DESC sd
= CPU_STATE (current_cpu
);
40 sim_engine_halt (sd
, current_cpu
, NULL
, cia
, sim_stopped
, SIM_SIGILL
);
45 /* Handle divide instructions. */
48 lm32bf_divu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
50 SIM_DESC sd
= CPU_STATE (current_cpu
);
51 host_callback
*cb
= STATE_CALLBACK (sd
);
53 /* Check for divide by zero */
54 if (GET_H_GR (r1
) == 0)
56 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
57 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
60 /* Save PC in exception address register. */
62 /* Save and clear interrupt enable. */
63 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
64 /* Branch to divide by zero exception handler. */
65 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
70 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) / (USI
) GET_H_GR (r1
));
76 lm32bf_modu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
78 SIM_DESC sd
= CPU_STATE (current_cpu
);
79 host_callback
*cb
= STATE_CALLBACK (sd
);
81 /* Check for divide by zero. */
82 if (GET_H_GR (r1
) == 0)
84 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
85 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
88 /* Save PC in exception address register. */
90 /* Save and clear interrupt enable. */
91 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
92 /* Branch to divide by zero exception handler. */
93 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
98 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) % (USI
) GET_H_GR (r1
));
103 /* Handle break instructions. */
106 lm32bf_break_insn (SIM_CPU
* current_cpu
, IADDR pc
)
108 SIM_DESC sd
= CPU_STATE (current_cpu
);
109 host_callback
*cb
= STATE_CALLBACK (sd
);
111 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
113 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
118 /* Save PC in breakpoint address register. */
120 /* Save and clear interrupt enable. */
121 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 2);
122 /* Branch to breakpoint exception handler. */
123 return GET_H_CSR (LM32_CSR_DEBA
) + LM32_EID_BREAKPOINT
* 32;
127 /* Handle scall instructions. */
130 lm32bf_scall_insn (SIM_CPU
* current_cpu
, IADDR pc
)
132 SIM_DESC sd
= CPU_STATE (current_cpu
);
133 host_callback
*cb
= STATE_CALLBACK (sd
);
135 if ((STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
136 || (GET_H_GR (8) == TARGET_NEWLIB_SYS_exit
))
138 /* Delegate system call to host O/S. */
139 long result
, result2
;
142 /* Perform the system call. */
143 sim_syscall_multi (current_cpu
, GET_H_GR (8), GET_H_GR (1), GET_H_GR (2),
144 GET_H_GR (3), GET_H_GR (4), &result
, &result2
,
146 /* Store the return value in the CPU's registers. */
147 SET_H_GR (1, result
);
148 SET_H_GR (2, result2
);
149 SET_H_GR (3, errcode
);
151 /* Skip over scall instruction. */
156 /* Save PC in exception address register. */
158 /* Save and clear interrupt enable */
159 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
160 /* Branch to system call exception handler. */
161 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_SYSTEM_CALL
* 32;
165 /* Handle b instructions. */
168 lm32bf_b_insn (SIM_CPU
* current_cpu
, USI r0
, USI f_r0
)
170 SIM_DESC sd
= CPU_STATE (current_cpu
);
171 host_callback
*cb
= STATE_CALLBACK (sd
);
173 /* Restore interrupt enable. */
175 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 2) >> 1);
177 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 4) >> 2);
181 /* Handle wcsr instructions. */
184 lm32bf_wcsr_insn (SIM_CPU
* current_cpu
, USI f_csr
, USI r1
)
186 SIM_DESC sd
= CPU_STATE (current_cpu
);
187 host_callback
*cb
= STATE_CALLBACK (sd
);
189 /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect. */
190 if (f_csr
== LM32_CSR_IP
)
191 SET_H_CSR (f_csr
, GET_H_CSR (f_csr
) & ~r1
);
193 SET_H_CSR (f_csr
, r1
);
196 /* Handle signals. */
199 lm32_core_signal (SIM_DESC sd
,
205 transfer_type transfer
, sim_core_signals sig
)
207 const char *copy
= (transfer
== read_transfer
? "read" : "write");
208 address_word ip
= CIA_ADDR (cia
);
209 SIM_CPU
*current_cpu
= cpu
;
213 case sim_core_unmapped_signal
:
215 "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
216 nr_bytes
, copy
, (unsigned long) addr
,
219 /* Save and clear interrupt enable. */
220 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
221 CPU_PC_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
222 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
223 sim_stopped
, SIM_SIGSEGV
);
225 case sim_core_unaligned_signal
:
227 "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
228 nr_bytes
, copy
, (unsigned long) addr
,
231 /* Save and clear interrupt enable. */
232 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
233 CPU_PC_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
234 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
235 sim_stopped
, SIM_SIGBUS
);
238 sim_engine_abort (sd
, cpu
, cia
,
239 "sim_core_signal - internal error - bad switch");