sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49   /* accumulator */
  50   DI h_accum;
  51 /* start-sanitize-m32rx */
  52   /* accumulators */
  53   DI h_accums[2];
  54 /* end-sanitize-m32rx */
  55   /* condition bit */
  56   BI h_cond;
  57 #define GET_H_COND() CPU (h_cond)
  58 #define SET_H_COND(x) (CPU (h_cond) = (x))
  59   /* psw part of psw */
  60   UQI h_psw;
  61   /* backup psw */
  62   UQI h_bpsw;
  63 #define GET_H_BPSW() CPU (h_bpsw)
  64 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  65   /* backup bpsw */
  66   UQI h_bbpsw;
  67 #define GET_H_BBPSW() CPU (h_bbpsw)
  68 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  69   /* lock */
  70   BI h_lock;
  71 #define GET_H_LOCK() CPU (h_lock)
  72 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  73   } hardware;
  74 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  75 } M32RBF_CPU_DATA;
  76
  77 /* Cover fns for register access.  */
  78 USI m32rbf_h_pc_get (SIM_CPU *);
  79 void m32rbf_h_pc_set (SIM_CPU *, USI);
  80 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  81 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  82 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  83 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  84 DI m32rbf_h_accum_get (SIM_CPU *);
  85 void m32rbf_h_accum_set (SIM_CPU *, DI);
  86 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  87 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  88 BI m32rbf_h_cond_get (SIM_CPU *);
  89 void m32rbf_h_cond_set (SIM_CPU *, BI);
  90 UQI m32rbf_h_psw_get (SIM_CPU *);
  91 void m32rbf_h_psw_set (SIM_CPU *, UQI);
  92 UQI m32rbf_h_bpsw_get (SIM_CPU *);
  93 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
  94 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
  95 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
  96 BI m32rbf_h_lock_get (SIM_CPU *);
  97 void m32rbf_h_lock_set (SIM_CPU *, BI);
  98
  99 /* These must be hand-written.  */
 100 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 101 extern CPUREG_STORE_FN m32rbf_store_register;
 102
 103 typedef struct {
 104   UINT h_gr;
 105 } MODEL_M32R_D_DATA;
 106
 107 typedef struct {
 108   int empty;
 109 } MODEL_TEST_DATA;
 110
 111 /* The ARGBUF struct.  */
 112 struct argbuf {
 113   /* These are the baseclass definitions.  */
 114   PCADDR addr;
 115   const IDESC *idesc;
 116   char trace_p;
 117   char profile_p;
 118   /* cpu specific data follows */
 119   union sem semantic;
 120   int written;
 121   union {
 122     struct { /* empty format for unspecified field list */
 123       int empty;
 124     } fmt_empty;
 125     struct { /* e.g. add $dr,$sr */
 126       SI * i_dr;
 127       SI * i_sr;
 128       unsigned char in_dr;
 129       unsigned char in_sr;
 130       unsigned char out_dr;
 131     } fmt_add;
 132     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 133       INT f_simm16;
 134       SI * i_sr;
 135       SI * i_dr;
 136       unsigned char in_sr;
 137       unsigned char out_dr;
 138     } fmt_add3;
 139     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 140       UINT f_uimm16;
 141       SI * i_sr;
 142       SI * i_dr;
 143       unsigned char in_sr;
 144       unsigned char out_dr;
 145     } fmt_and3;
 146     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 147       UINT f_uimm16;
 148       SI * i_sr;
 149       SI * i_dr;
 150       unsigned char in_sr;
 151       unsigned char out_dr;
 152     } fmt_or3;
 153     struct { /* e.g. addi $dr,$simm8 */
 154       INT f_simm8;
 155       SI * i_dr;
 156       unsigned char in_dr;
 157       unsigned char out_dr;
 158     } fmt_addi;
 159     struct { /* e.g. addv $dr,$sr */
 160       SI * i_dr;
 161       SI * i_sr;
 162       unsigned char in_dr;
 163       unsigned char in_sr;
 164       unsigned char out_dr;
 165     } fmt_addv;
 166     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 167       INT f_simm16;
 168       SI * i_sr;
 169       SI * i_dr;
 170       unsigned char in_sr;
 171       unsigned char out_dr;
 172     } fmt_addv3;
 173     struct { /* e.g. addx $dr,$sr */
 174       SI * i_dr;
 175       SI * i_sr;
 176       unsigned char in_dr;
 177       unsigned char in_sr;
 178       unsigned char out_dr;
 179     } fmt_addx;
 180     struct { /* e.g. cmp $src1,$src2 */
 181       SI * i_src1;
 182       SI * i_src2;
 183       unsigned char in_src1;
 184       unsigned char in_src2;
 185     } fmt_cmp;
 186     struct { /* e.g. cmpi $src2,$simm16 */
 187       INT f_simm16;
 188       SI * i_src2;
 189       unsigned char in_src2;
 190     } fmt_cmpi;
 191     struct { /* e.g. div $dr,$sr */
 192       SI * i_sr;
 193       SI * i_dr;
 194       unsigned char in_sr;
 195       unsigned char in_dr;
 196       unsigned char out_dr;
 197     } fmt_div;
 198     struct { /* e.g. ld $dr,@$sr */
 199       SI * i_sr;
 200       SI * i_dr;
 201       unsigned char in_sr;
 202       unsigned char out_dr;
 203     } fmt_ld;
 204     struct { /* e.g. ld $dr,@($slo16,$sr) */
 205       INT f_simm16;
 206       SI * i_sr;
 207       SI * i_dr;
 208       unsigned char in_sr;
 209       unsigned char out_dr;
 210     } fmt_ld_d;
 211     struct { /* e.g. ldb $dr,@$sr */
 212       SI * i_sr;
 213       SI * i_dr;
 214       unsigned char in_sr;
 215       unsigned char out_dr;
 216     } fmt_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       INT f_simm16;
 219       SI * i_sr;
 220       SI * i_dr;
 221       unsigned char in_sr;
 222       unsigned char out_dr;
 223     } fmt_ldb_d;
 224     struct { /* e.g. ldh $dr,@$sr */
 225       SI * i_sr;
 226       SI * i_dr;
 227       unsigned char in_sr;
 228       unsigned char out_dr;
 229     } fmt_ldh;
 230     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 231       INT f_simm16;
 232       SI * i_sr;
 233       SI * i_dr;
 234       unsigned char in_sr;
 235       unsigned char out_dr;
 236     } fmt_ldh_d;
 237     struct { /* e.g. ld $dr,@$sr+ */
 238       SI * i_sr;
 239       SI * i_dr;
 240       unsigned char in_sr;
 241       unsigned char out_dr;
 242       unsigned char out_sr;
 243     } fmt_ld_plus;
 244     struct { /* e.g. ld24 $dr,$uimm24 */
 245       ADDR i_uimm24;
 246       SI * i_dr;
 247       unsigned char out_dr;
 248     } fmt_ld24;
 249     struct { /* e.g. ldi8 $dr,$simm8 */
 250       INT f_simm8;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ldi8;
 254     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 255       INT f_simm16;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi16;
 259     struct { /* e.g. lock $dr,@$sr */
 260       SI * i_sr;
 261       SI * i_dr;
 262       unsigned char in_sr;
 263       unsigned char out_dr;
 264     } fmt_lock;
 265     struct { /* e.g. machi $src1,$src2 */
 266       SI * i_src1;
 267       SI * i_src2;
 268       unsigned char in_src1;
 269       unsigned char in_src2;
 270     } fmt_machi;
 271     struct { /* e.g. mulhi $src1,$src2 */
 272       SI * i_src1;
 273       SI * i_src2;
 274       unsigned char in_src1;
 275       unsigned char in_src2;
 276     } fmt_mulhi;
 277     struct { /* e.g. mv $dr,$sr */
 278       SI * i_sr;
 279       SI * i_dr;
 280       unsigned char in_sr;
 281       unsigned char out_dr;
 282     } fmt_mv;
 283     struct { /* e.g. mvfachi $dr */
 284       SI * i_dr;
 285       unsigned char out_dr;
 286     } fmt_mvfachi;
 287     struct { /* e.g. mvfc $dr,$scr */
 288       UINT f_r2;
 289       SI * i_dr;
 290       unsigned char out_dr;
 291     } fmt_mvfc;
 292     struct { /* e.g. mvtachi $src1 */
 293       SI * i_src1;
 294       unsigned char in_src1;
 295     } fmt_mvtachi;
 296     struct { /* e.g. mvtc $sr,$dcr */
 297       UINT f_r1;
 298       SI * i_sr;
 299       unsigned char in_sr;
 300     } fmt_mvtc;
 301     struct { /* e.g. nop */
 302       int empty;
 303     } fmt_nop;
 304     struct { /* e.g. rac */
 305       int empty;
 306     } fmt_rac;
 307     struct { /* e.g. seth $dr,$hash$hi16 */
 308       UINT f_hi16;
 309       SI * i_dr;
 310       unsigned char out_dr;
 311     } fmt_seth;
 312     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 313       INT f_simm16;
 314       SI * i_sr;
 315       SI * i_dr;
 316       unsigned char in_sr;
 317       unsigned char out_dr;
 318     } fmt_sll3;
 319     struct { /* e.g. slli $dr,$uimm5 */
 320       UINT f_uimm5;
 321       SI * i_dr;
 322       unsigned char in_dr;
 323       unsigned char out_dr;
 324     } fmt_slli;
 325     struct { /* e.g. st $src1,@$src2 */
 326       SI * i_src2;
 327       SI * i_src1;
 328       unsigned char in_src2;
 329       unsigned char in_src1;
 330     } fmt_st;
 331     struct { /* e.g. st $src1,@($slo16,$src2) */
 332       INT f_simm16;
 333       SI * i_src2;
 334       SI * i_src1;
 335       unsigned char in_src2;
 336       unsigned char in_src1;
 337     } fmt_st_d;
 338     struct { /* e.g. stb $src1,@$src2 */
 339       SI * i_src2;
 340       SI * i_src1;
 341       unsigned char in_src2;
 342       unsigned char in_src1;
 343     } fmt_stb;
 344     struct { /* e.g. stb $src1,@($slo16,$src2) */
 345       INT f_simm16;
 346       SI * i_src2;
 347       SI * i_src1;
 348       unsigned char in_src2;
 349       unsigned char in_src1;
 350     } fmt_stb_d;
 351     struct { /* e.g. sth $src1,@$src2 */
 352       SI * i_src2;
 353       SI * i_src1;
 354       unsigned char in_src2;
 355       unsigned char in_src1;
 356     } fmt_sth;
 357     struct { /* e.g. sth $src1,@($slo16,$src2) */
 358       INT f_simm16;
 359       SI * i_src2;
 360       SI * i_src1;
 361       unsigned char in_src2;
 362       unsigned char in_src1;
 363     } fmt_sth_d;
 364     struct { /* e.g. st $src1,@+$src2 */
 365       SI * i_src2;
 366       SI * i_src1;
 367       unsigned char in_src2;
 368       unsigned char in_src1;
 369       unsigned char out_src2;
 370     } fmt_st_plus;
 371     struct { /* e.g. unlock $src1,@$src2 */
 372       SI * i_src2;
 373       SI * i_src1;
 374       unsigned char in_src2;
 375       unsigned char in_src1;
 376     } fmt_unlock;
 377   /* cti insns, kept separately so addr_cache is in fixed place */
 378   struct {
 379     union {
 380     struct { /* e.g. bc.s $disp8 */
 381       IADDR i_disp8;
 382     } fmt_bc8;
 383     struct { /* e.g. bc.l $disp24 */
 384       IADDR i_disp24;
 385     } fmt_bc24;
 386     struct { /* e.g. beq $src1,$src2,$disp16 */
 387       SI * i_src1;
 388       SI * i_src2;
 389       IADDR i_disp16;
 390       unsigned char in_src1;
 391       unsigned char in_src2;
 392     } fmt_beq;
 393     struct { /* e.g. beqz $src2,$disp16 */
 394       SI * i_src2;
 395       IADDR i_disp16;
 396       unsigned char in_src2;
 397     } fmt_beqz;
 398     struct { /* e.g. bl.s $disp8 */
 399       IADDR i_disp8;
 400       unsigned char out_h_gr_14;
 401     } fmt_bl8;
 402     struct { /* e.g. bl.l $disp24 */
 403       IADDR i_disp24;
 404       unsigned char out_h_gr_14;
 405     } fmt_bl24;
 406     struct { /* e.g. bra.s $disp8 */
 407       IADDR i_disp8;
 408     } fmt_bra8;
 409     struct { /* e.g. bra.l $disp24 */
 410       IADDR i_disp24;
 411     } fmt_bra24;
 412     struct { /* e.g. jl $sr */
 413       SI * i_sr;
 414       unsigned char in_sr;
 415       unsigned char out_h_gr_14;
 416     } fmt_jl;
 417     struct { /* e.g. jmp $sr */
 418       SI * i_sr;
 419       unsigned char in_sr;
 420     } fmt_jmp;
 421     struct { /* e.g. rte */
 422       int empty;
 423     } fmt_rte;
 424     struct { /* e.g. trap $uimm4 */
 425       UINT f_uimm4;
 426     } fmt_trap;
 427     } fields;
 428 #if WITH_SCACHE_PBB
 429     SEM_PC addr_cache;
 430 #endif
 431   } cti;
 432 #if WITH_SCACHE_PBB
 433     /* Writeback handler.  */
 434     struct {
 435       /* Pointer to argbuf entry for insn whose results need writing back.  */
 436       const struct argbuf *abuf;
 437     } write;
 438     /* x-before handler */
 439     struct {
 440       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 441       int first_p;
 442     } before;
 443     /* x-after handler */
 444     struct {
 445       int empty;
 446     } after;
 447     /* This entry is used to terminate each pbb.  */
 448     struct {
 449       /* Number of insns in pbb.  */
 450       int insn_count;
 451       /* Next pbb to execute.  */
 452       SCACHE *next;
 453     } chain;
 454 #endif
 455   } fields;
 456 };
 457
 458 /* A cached insn.
 459
 460    ??? SCACHE used to contain more than just argbuf.  We could delete the
 461    type entirely and always just use ARGBUF, but for future concerns and as
 462    a level of abstraction it is left in.  */
 463
 464 struct scache {
 465   struct argbuf argbuf;
 466 };
 467
 468 /* Macros to simplify extraction, reading and semantic code.
 469    These define and assign the local vars that contain the insn's fields.  */
 470
 471 #define EXTRACT_FMT_EMPTY_VARS \
 472   /* Instruction fields.  */ \
 473   unsigned int length;
 474 #define EXTRACT_FMT_EMPTY_CODE \
 475   length = 0; \
 476
 477 #define EXTRACT_FMT_ADD_VARS \
 478   /* Instruction fields.  */ \
 479   UINT f_op1; \
 480   UINT f_r1; \
 481   UINT f_op2; \
 482   UINT f_r2; \
 483   unsigned int length;
 484 #define EXTRACT_FMT_ADD_CODE \
 485   length = 2; \
 486   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 487   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 488   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 489   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 490
 491 #define EXTRACT_FMT_ADD3_VARS \
 492   /* Instruction fields.  */ \
 493   UINT f_op1; \
 494   UINT f_r1; \
 495   UINT f_op2; \
 496   UINT f_r2; \
 497   INT f_simm16; \
 498   unsigned int length;
 499 #define EXTRACT_FMT_ADD3_CODE \
 500   length = 4; \
 501   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 502   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 503   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 504   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 505   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 506
 507 #define EXTRACT_FMT_AND3_VARS \
 508   /* Instruction fields.  */ \
 509   UINT f_op1; \
 510   UINT f_r1; \
 511   UINT f_op2; \
 512   UINT f_r2; \
 513   UINT f_uimm16; \
 514   unsigned int length;
 515 #define EXTRACT_FMT_AND3_CODE \
 516   length = 4; \
 517   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 518   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 519   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 520   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 521   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 522
 523 #define EXTRACT_FMT_OR3_VARS \
 524   /* Instruction fields.  */ \
 525   UINT f_op1; \
 526   UINT f_r1; \
 527   UINT f_op2; \
 528   UINT f_r2; \
 529   UINT f_uimm16; \
 530   unsigned int length;
 531 #define EXTRACT_FMT_OR3_CODE \
 532   length = 4; \
 533   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 534   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 535   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 536   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 537   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 538
 539 #define EXTRACT_FMT_ADDI_VARS \
 540   /* Instruction fields.  */ \
 541   UINT f_op1; \
 542   UINT f_r1; \
 543   INT f_simm8; \
 544   unsigned int length;
 545 #define EXTRACT_FMT_ADDI_CODE \
 546   length = 2; \
 547   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 548   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 549   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 550
 551 #define EXTRACT_FMT_ADDV_VARS \
 552   /* Instruction fields.  */ \
 553   UINT f_op1; \
 554   UINT f_r1; \
 555   UINT f_op2; \
 556   UINT f_r2; \
 557   unsigned int length;
 558 #define EXTRACT_FMT_ADDV_CODE \
 559   length = 2; \
 560   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 561   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 562   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 563   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 564
 565 #define EXTRACT_FMT_ADDV3_VARS \
 566   /* Instruction fields.  */ \
 567   UINT f_op1; \
 568   UINT f_r1; \
 569   UINT f_op2; \
 570   UINT f_r2; \
 571   INT f_simm16; \
 572   unsigned int length;
 573 #define EXTRACT_FMT_ADDV3_CODE \
 574   length = 4; \
 575   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 576   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 577   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 578   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 579   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 580
 581 #define EXTRACT_FMT_ADDX_VARS \
 582   /* Instruction fields.  */ \
 583   UINT f_op1; \
 584   UINT f_r1; \
 585   UINT f_op2; \
 586   UINT f_r2; \
 587   unsigned int length;
 588 #define EXTRACT_FMT_ADDX_CODE \
 589   length = 2; \
 590   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 591   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 592   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 593   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 594
 595 #define EXTRACT_FMT_BC8_VARS \
 596   /* Instruction fields.  */ \
 597   UINT f_op1; \
 598   UINT f_r1; \
 599   SI f_disp8; \
 600   unsigned int length;
 601 #define EXTRACT_FMT_BC8_CODE \
 602   length = 2; \
 603   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 604   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 605   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 606
 607 #define EXTRACT_FMT_BC24_VARS \
 608   /* Instruction fields.  */ \
 609   UINT f_op1; \
 610   UINT f_r1; \
 611   SI f_disp24; \
 612   unsigned int length;
 613 #define EXTRACT_FMT_BC24_CODE \
 614   length = 4; \
 615   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 616   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 617   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 618
 619 #define EXTRACT_FMT_BEQ_VARS \
 620   /* Instruction fields.  */ \
 621   UINT f_op1; \
 622   UINT f_r1; \
 623   UINT f_op2; \
 624   UINT f_r2; \
 625   SI f_disp16; \
 626   unsigned int length;
 627 #define EXTRACT_FMT_BEQ_CODE \
 628   length = 4; \
 629   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 630   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 631   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 632   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 633   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 634
 635 #define EXTRACT_FMT_BEQZ_VARS \
 636   /* Instruction fields.  */ \
 637   UINT f_op1; \
 638   UINT f_r1; \
 639   UINT f_op2; \
 640   UINT f_r2; \
 641   SI f_disp16; \
 642   unsigned int length;
 643 #define EXTRACT_FMT_BEQZ_CODE \
 644   length = 4; \
 645   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 646   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 647   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 648   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 649   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 650
 651 #define EXTRACT_FMT_BL8_VARS \
 652   /* Instruction fields.  */ \
 653   UINT f_op1; \
 654   UINT f_r1; \
 655   SI f_disp8; \
 656   unsigned int length;
 657 #define EXTRACT_FMT_BL8_CODE \
 658   length = 2; \
 659   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 660   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 661   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 662
 663 #define EXTRACT_FMT_BL24_VARS \
 664   /* Instruction fields.  */ \
 665   UINT f_op1; \
 666   UINT f_r1; \
 667   SI f_disp24; \
 668   unsigned int length;
 669 #define EXTRACT_FMT_BL24_CODE \
 670   length = 4; \
 671   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 672   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 673   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 674
 675 #define EXTRACT_FMT_BRA8_VARS \
 676   /* Instruction fields.  */ \
 677   UINT f_op1; \
 678   UINT f_r1; \
 679   SI f_disp8; \
 680   unsigned int length;
 681 #define EXTRACT_FMT_BRA8_CODE \
 682   length = 2; \
 683   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 684   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 685   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 686
 687 #define EXTRACT_FMT_BRA24_VARS \
 688   /* Instruction fields.  */ \
 689   UINT f_op1; \
 690   UINT f_r1; \
 691   SI f_disp24; \
 692   unsigned int length;
 693 #define EXTRACT_FMT_BRA24_CODE \
 694   length = 4; \
 695   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 696   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 697   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 698
 699 #define EXTRACT_FMT_CMP_VARS \
 700   /* Instruction fields.  */ \
 701   UINT f_op1; \
 702   UINT f_r1; \
 703   UINT f_op2; \
 704   UINT f_r2; \
 705   unsigned int length;
 706 #define EXTRACT_FMT_CMP_CODE \
 707   length = 2; \
 708   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 709   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 710   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 711   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 712
 713 #define EXTRACT_FMT_CMPI_VARS \
 714   /* Instruction fields.  */ \
 715   UINT f_op1; \
 716   UINT f_r1; \
 717   UINT f_op2; \
 718   UINT f_r2; \
 719   INT f_simm16; \
 720   unsigned int length;
 721 #define EXTRACT_FMT_CMPI_CODE \
 722   length = 4; \
 723   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 724   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 725   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 726   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 727   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 728
 729 #define EXTRACT_FMT_DIV_VARS \
 730   /* Instruction fields.  */ \
 731   UINT f_op1; \
 732   UINT f_r1; \
 733   UINT f_op2; \
 734   UINT f_r2; \
 735   INT f_simm16; \
 736   unsigned int length;
 737 #define EXTRACT_FMT_DIV_CODE \
 738   length = 4; \
 739   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 740   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 741   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 742   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 743   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 744
 745 #define EXTRACT_FMT_JL_VARS \
 746   /* Instruction fields.  */ \
 747   UINT f_op1; \
 748   UINT f_r1; \
 749   UINT f_op2; \
 750   UINT f_r2; \
 751   unsigned int length;
 752 #define EXTRACT_FMT_JL_CODE \
 753   length = 2; \
 754   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 755   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 756   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 757   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 758
 759 #define EXTRACT_FMT_JMP_VARS \
 760   /* Instruction fields.  */ \
 761   UINT f_op1; \
 762   UINT f_r1; \
 763   UINT f_op2; \
 764   UINT f_r2; \
 765   unsigned int length;
 766 #define EXTRACT_FMT_JMP_CODE \
 767   length = 2; \
 768   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 769   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 770   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 771   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 772
 773 #define EXTRACT_FMT_LD_VARS \
 774   /* Instruction fields.  */ \
 775   UINT f_op1; \
 776   UINT f_r1; \
 777   UINT f_op2; \
 778   UINT f_r2; \
 779   unsigned int length;
 780 #define EXTRACT_FMT_LD_CODE \
 781   length = 2; \
 782   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 783   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 784   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 785   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 786
 787 #define EXTRACT_FMT_LD_D_VARS \
 788   /* Instruction fields.  */ \
 789   UINT f_op1; \
 790   UINT f_r1; \
 791   UINT f_op2; \
 792   UINT f_r2; \
 793   INT f_simm16; \
 794   unsigned int length;
 795 #define EXTRACT_FMT_LD_D_CODE \
 796   length = 4; \
 797   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 798   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 799   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 800   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 801   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 802
 803 #define EXTRACT_FMT_LDB_VARS \
 804   /* Instruction fields.  */ \
 805   UINT f_op1; \
 806   UINT f_r1; \
 807   UINT f_op2; \
 808   UINT f_r2; \
 809   unsigned int length;
 810 #define EXTRACT_FMT_LDB_CODE \
 811   length = 2; \
 812   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 813   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 814   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 815   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 816
 817 #define EXTRACT_FMT_LDB_D_VARS \
 818   /* Instruction fields.  */ \
 819   UINT f_op1; \
 820   UINT f_r1; \
 821   UINT f_op2; \
 822   UINT f_r2; \
 823   INT f_simm16; \
 824   unsigned int length;
 825 #define EXTRACT_FMT_LDB_D_CODE \
 826   length = 4; \
 827   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 828   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 829   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 830   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 831   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 832
 833 #define EXTRACT_FMT_LDH_VARS \
 834   /* Instruction fields.  */ \
 835   UINT f_op1; \
 836   UINT f_r1; \
 837   UINT f_op2; \
 838   UINT f_r2; \
 839   unsigned int length;
 840 #define EXTRACT_FMT_LDH_CODE \
 841   length = 2; \
 842   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 843   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 844   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 845   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 846
 847 #define EXTRACT_FMT_LDH_D_VARS \
 848   /* Instruction fields.  */ \
 849   UINT f_op1; \
 850   UINT f_r1; \
 851   UINT f_op2; \
 852   UINT f_r2; \
 853   INT f_simm16; \
 854   unsigned int length;
 855 #define EXTRACT_FMT_LDH_D_CODE \
 856   length = 4; \
 857   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 858   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 859   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 860   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 861   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 862
 863 #define EXTRACT_FMT_LD_PLUS_VARS \
 864   /* Instruction fields.  */ \
 865   UINT f_op1; \
 866   UINT f_r1; \
 867   UINT f_op2; \
 868   UINT f_r2; \
 869   unsigned int length;
 870 #define EXTRACT_FMT_LD_PLUS_CODE \
 871   length = 2; \
 872   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 873   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 874   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 875   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 876
 877 #define EXTRACT_FMT_LD24_VARS \
 878   /* Instruction fields.  */ \
 879   UINT f_op1; \
 880   UINT f_r1; \
 881   UINT f_uimm24; \
 882   unsigned int length;
 883 #define EXTRACT_FMT_LD24_CODE \
 884   length = 4; \
 885   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 886   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 887   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 888
 889 #define EXTRACT_FMT_LDI8_VARS \
 890   /* Instruction fields.  */ \
 891   UINT f_op1; \
 892   UINT f_r1; \
 893   INT f_simm8; \
 894   unsigned int length;
 895 #define EXTRACT_FMT_LDI8_CODE \
 896   length = 2; \
 897   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 898   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 899   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 900
 901 #define EXTRACT_FMT_LDI16_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   UINT f_op2; \
 906   UINT f_r2; \
 907   INT f_simm16; \
 908   unsigned int length;
 909 #define EXTRACT_FMT_LDI16_CODE \
 910   length = 4; \
 911   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 912   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 913   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 914   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 915   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 916
 917 #define EXTRACT_FMT_LOCK_VARS \
 918   /* Instruction fields.  */ \
 919   UINT f_op1; \
 920   UINT f_r1; \
 921   UINT f_op2; \
 922   UINT f_r2; \
 923   unsigned int length;
 924 #define EXTRACT_FMT_LOCK_CODE \
 925   length = 2; \
 926   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 927   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 928   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 929   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 930
 931 #define EXTRACT_FMT_MACHI_VARS \
 932   /* Instruction fields.  */ \
 933   UINT f_op1; \
 934   UINT f_r1; \
 935   UINT f_op2; \
 936   UINT f_r2; \
 937   unsigned int length;
 938 #define EXTRACT_FMT_MACHI_CODE \
 939   length = 2; \
 940   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 941   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 942   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 943   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 944
 945 #define EXTRACT_FMT_MULHI_VARS \
 946   /* Instruction fields.  */ \
 947   UINT f_op1; \
 948   UINT f_r1; \
 949   UINT f_op2; \
 950   UINT f_r2; \
 951   unsigned int length;
 952 #define EXTRACT_FMT_MULHI_CODE \
 953   length = 2; \
 954   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 955   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 956   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 957   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 958
 959 #define EXTRACT_FMT_MV_VARS \
 960   /* Instruction fields.  */ \
 961   UINT f_op1; \
 962   UINT f_r1; \
 963   UINT f_op2; \
 964   UINT f_r2; \
 965   unsigned int length;
 966 #define EXTRACT_FMT_MV_CODE \
 967   length = 2; \
 968   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 969   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 970   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 971   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 972
 973 #define EXTRACT_FMT_MVFACHI_VARS \
 974   /* Instruction fields.  */ \
 975   UINT f_op1; \
 976   UINT f_r1; \
 977   UINT f_op2; \
 978   UINT f_r2; \
 979   unsigned int length;
 980 #define EXTRACT_FMT_MVFACHI_CODE \
 981   length = 2; \
 982   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 983   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 984   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 985   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 986
 987 #define EXTRACT_FMT_MVFC_VARS \
 988   /* Instruction fields.  */ \
 989   UINT f_op1; \
 990   UINT f_r1; \
 991   UINT f_op2; \
 992   UINT f_r2; \
 993   unsigned int length;
 994 #define EXTRACT_FMT_MVFC_CODE \
 995   length = 2; \
 996   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 997   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 998   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 999   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1000
1001 #define EXTRACT_FMT_MVTACHI_VARS \
1002   /* Instruction fields.  */ \
1003   UINT f_op1; \
1004   UINT f_r1; \
1005   UINT f_op2; \
1006   UINT f_r2; \
1007   unsigned int length;
1008 #define EXTRACT_FMT_MVTACHI_CODE \
1009   length = 2; \
1010   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1011   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1012   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1013   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1014
1015 #define EXTRACT_FMT_MVTC_VARS \
1016   /* Instruction fields.  */ \
1017   UINT f_op1; \
1018   UINT f_r1; \
1019   UINT f_op2; \
1020   UINT f_r2; \
1021   unsigned int length;
1022 #define EXTRACT_FMT_MVTC_CODE \
1023   length = 2; \
1024   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1025   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1026   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1027   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1028
1029 #define EXTRACT_FMT_NOP_VARS \
1030   /* Instruction fields.  */ \
1031   UINT f_op1; \
1032   UINT f_r1; \
1033   UINT f_op2; \
1034   UINT f_r2; \
1035   unsigned int length;
1036 #define EXTRACT_FMT_NOP_CODE \
1037   length = 2; \
1038   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1039   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1040   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1041   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1042
1043 #define EXTRACT_FMT_RAC_VARS \
1044   /* Instruction fields.  */ \
1045   UINT f_op1; \
1046   UINT f_r1; \
1047   UINT f_op2; \
1048   UINT f_r2; \
1049   unsigned int length;
1050 #define EXTRACT_FMT_RAC_CODE \
1051   length = 2; \
1052   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1053   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1054   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1055   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1056
1057 #define EXTRACT_FMT_RTE_VARS \
1058   /* Instruction fields.  */ \
1059   UINT f_op1; \
1060   UINT f_r1; \
1061   UINT f_op2; \
1062   UINT f_r2; \
1063   unsigned int length;
1064 #define EXTRACT_FMT_RTE_CODE \
1065   length = 2; \
1066   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1067   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1068   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1069   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1070
1071 #define EXTRACT_FMT_SETH_VARS \
1072   /* Instruction fields.  */ \
1073   UINT f_op1; \
1074   UINT f_r1; \
1075   UINT f_op2; \
1076   UINT f_r2; \
1077   UINT f_hi16; \
1078   unsigned int length;
1079 #define EXTRACT_FMT_SETH_CODE \
1080   length = 4; \
1081   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1082   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1083   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1084   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1085   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1086
1087 #define EXTRACT_FMT_SLL3_VARS \
1088   /* Instruction fields.  */ \
1089   UINT f_op1; \
1090   UINT f_r1; \
1091   UINT f_op2; \
1092   UINT f_r2; \
1093   INT f_simm16; \
1094   unsigned int length;
1095 #define EXTRACT_FMT_SLL3_CODE \
1096   length = 4; \
1097   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1098   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1099   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1100   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1101   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1102
1103 #define EXTRACT_FMT_SLLI_VARS \
1104   /* Instruction fields.  */ \
1105   UINT f_op1; \
1106   UINT f_r1; \
1107   UINT f_shift_op2; \
1108   UINT f_uimm5; \
1109   unsigned int length;
1110 #define EXTRACT_FMT_SLLI_CODE \
1111   length = 2; \
1112   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1113   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1114   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1115   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1116
1117 #define EXTRACT_FMT_ST_VARS \
1118   /* Instruction fields.  */ \
1119   UINT f_op1; \
1120   UINT f_r1; \
1121   UINT f_op2; \
1122   UINT f_r2; \
1123   unsigned int length;
1124 #define EXTRACT_FMT_ST_CODE \
1125   length = 2; \
1126   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1127   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1128   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1129   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1130
1131 #define EXTRACT_FMT_ST_D_VARS \
1132   /* Instruction fields.  */ \
1133   UINT f_op1; \
1134   UINT f_r1; \
1135   UINT f_op2; \
1136   UINT f_r2; \
1137   INT f_simm16; \
1138   unsigned int length;
1139 #define EXTRACT_FMT_ST_D_CODE \
1140   length = 4; \
1141   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1142   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1143   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1144   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1145   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1146
1147 #define EXTRACT_FMT_STB_VARS \
1148   /* Instruction fields.  */ \
1149   UINT f_op1; \
1150   UINT f_r1; \
1151   UINT f_op2; \
1152   UINT f_r2; \
1153   unsigned int length;
1154 #define EXTRACT_FMT_STB_CODE \
1155   length = 2; \
1156   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1157   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1158   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1159   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1160
1161 #define EXTRACT_FMT_STB_D_VARS \
1162   /* Instruction fields.  */ \
1163   UINT f_op1; \
1164   UINT f_r1; \
1165   UINT f_op2; \
1166   UINT f_r2; \
1167   INT f_simm16; \
1168   unsigned int length;
1169 #define EXTRACT_FMT_STB_D_CODE \
1170   length = 4; \
1171   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1172   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1173   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1174   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1175   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1176
1177 #define EXTRACT_FMT_STH_VARS \
1178   /* Instruction fields.  */ \
1179   UINT f_op1; \
1180   UINT f_r1; \
1181   UINT f_op2; \
1182   UINT f_r2; \
1183   unsigned int length;
1184 #define EXTRACT_FMT_STH_CODE \
1185   length = 2; \
1186   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1187   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1188   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1189   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1190
1191 #define EXTRACT_FMT_STH_D_VARS \
1192   /* Instruction fields.  */ \
1193   UINT f_op1; \
1194   UINT f_r1; \
1195   UINT f_op2; \
1196   UINT f_r2; \
1197   INT f_simm16; \
1198   unsigned int length;
1199 #define EXTRACT_FMT_STH_D_CODE \
1200   length = 4; \
1201   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1202   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1203   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1204   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1205   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1206
1207 #define EXTRACT_FMT_ST_PLUS_VARS \
1208   /* Instruction fields.  */ \
1209   UINT f_op1; \
1210   UINT f_r1; \
1211   UINT f_op2; \
1212   UINT f_r2; \
1213   unsigned int length;
1214 #define EXTRACT_FMT_ST_PLUS_CODE \
1215   length = 2; \
1216   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1217   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1218   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1219   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1220
1221 #define EXTRACT_FMT_TRAP_VARS \
1222   /* Instruction fields.  */ \
1223   UINT f_op1; \
1224   UINT f_r1; \
1225   UINT f_op2; \
1226   UINT f_uimm4; \
1227   unsigned int length;
1228 #define EXTRACT_FMT_TRAP_CODE \
1229   length = 2; \
1230   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1231   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1232   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1233   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1234
1235 #define EXTRACT_FMT_UNLOCK_VARS \
1236   /* Instruction fields.  */ \
1237   UINT f_op1; \
1238   UINT f_r1; \
1239   UINT f_op2; \
1240   UINT f_r2; \
1241   unsigned int length;
1242 #define EXTRACT_FMT_UNLOCK_CODE \
1243   length = 2; \
1244   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1245   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1246   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1247   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1248
1249 /* Collection of various things for the trace handler to use.  */
1250
1251 typedef struct trace_record {
1252   PCADDR pc;
1253   /* FIXME:wip */
1254 } TRACE_RECORD;
1255
1256 #endif /* CPU_M32RBF_H */