sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() CPU (h_psw)
  68 #define SET_H_PSW(x) (CPU (h_psw) = (x))
  69   /* backup psw */
  70   UQI h_bpsw;
  71 #define GET_H_BPSW() CPU (h_bpsw)
  72 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  73   /* backup bpsw */
  74   UQI h_bbpsw;
  75 #define GET_H_BBPSW() CPU (h_bbpsw)
  76 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  77   /* lock */
  78   BI h_lock;
  79 #define GET_H_LOCK() CPU (h_lock)
  80 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  81   } hardware;
  82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  83 } M32RBF_CPU_DATA;
  84
  85 /* Cover fns for register access.  */
  86 USI m32rbf_h_pc_get (SIM_CPU *);
  87 void m32rbf_h_pc_set (SIM_CPU *, USI);
  88 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  89 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  90 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  91 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  92 DI m32rbf_h_accum_get (SIM_CPU *);
  93 void m32rbf_h_accum_set (SIM_CPU *, DI);
  94 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  95 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  96 BI m32rbf_h_cond_get (SIM_CPU *);
  97 void m32rbf_h_cond_set (SIM_CPU *, BI);
  98 UQI m32rbf_h_psw_get (SIM_CPU *);
  99 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 100 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 101 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 102 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 103 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 104 BI m32rbf_h_lock_get (SIM_CPU *);
 105 void m32rbf_h_lock_set (SIM_CPU *, BI);
 106
 107 /* These must be hand-written.  */
 108 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 109 extern CPUREG_STORE_FN m32rbf_store_register;
 110
 111 typedef struct {
 112   UINT h_gr;
 113 } MODEL_M32R_D_DATA;
 114
 115 typedef struct {
 116   int empty;
 117 } MODEL_TEST_DATA;
 118
 119 /* The ARGBUF struct.  */
 120 struct argbuf {
 121   /* These are the baseclass definitions.  */
 122   PCADDR addr;
 123   const IDESC *idesc;
 124   /* cpu specific data follows */
 125   union sem semantic;
 126   int written;
 127   union {
 128     struct { /* e.g. add $dr,$sr */
 129       SI * i_dr;
 130       SI * i_sr;
 131       unsigned char in_dr;
 132       unsigned char in_sr;
 133       unsigned char out_dr;
 134     } fmt_add;
 135     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 136       SI * i_sr;
 137       HI f_simm16;
 138       SI * i_dr;
 139       unsigned char in_sr;
 140       unsigned char out_dr;
 141     } fmt_add3;
 142     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 143       SI * i_sr;
 144       USI f_uimm16;
 145       SI * i_dr;
 146       unsigned char in_sr;
 147       unsigned char out_dr;
 148     } fmt_and3;
 149     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 150       SI * i_sr;
 151       UHI f_uimm16;
 152       SI * i_dr;
 153       unsigned char in_sr;
 154       unsigned char out_dr;
 155     } fmt_or3;
 156     struct { /* e.g. addi $dr,$simm8 */
 157       SI * i_dr;
 158       SI f_simm8;
 159       unsigned char in_dr;
 160       unsigned char out_dr;
 161     } fmt_addi;
 162     struct { /* e.g. addv $dr,$sr */
 163       SI * i_dr;
 164       SI * i_sr;
 165       unsigned char in_dr;
 166       unsigned char in_sr;
 167       unsigned char out_dr;
 168     } fmt_addv;
 169     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 170       SI * i_sr;
 171       SI f_simm16;
 172       SI * i_dr;
 173       unsigned char in_sr;
 174       unsigned char out_dr;
 175     } fmt_addv3;
 176     struct { /* e.g. addx $dr,$sr */
 177       SI * i_dr;
 178       SI * i_sr;
 179       unsigned char in_dr;
 180       unsigned char in_sr;
 181       unsigned char out_dr;
 182     } fmt_addx;
 183     struct { /* e.g. cmp $src1,$src2 */
 184       SI * i_src1;
 185       SI * i_src2;
 186       unsigned char in_src1;
 187       unsigned char in_src2;
 188     } fmt_cmp;
 189     struct { /* e.g. cmpi $src2,$simm16 */
 190       SI * i_src2;
 191       SI f_simm16;
 192       unsigned char in_src2;
 193     } fmt_cmpi;
 194     struct { /* e.g. div $dr,$sr */
 195       SI * i_sr;
 196       SI * i_dr;
 197       unsigned char in_sr;
 198       unsigned char in_dr;
 199       unsigned char out_dr;
 200     } fmt_div;
 201     struct { /* e.g. ld $dr,@$sr */
 202       SI * i_sr;
 203       SI * i_dr;
 204       unsigned char in_sr;
 205       unsigned char out_dr;
 206     } fmt_ld;
 207     struct { /* e.g. ld $dr,@($slo16,$sr) */
 208       SI * i_sr;
 209       HI f_simm16;
 210       SI * i_dr;
 211       unsigned char in_sr;
 212       unsigned char out_dr;
 213     } fmt_ld_d;
 214     struct { /* e.g. ldb $dr,@$sr */
 215       SI * i_sr;
 216       SI * i_dr;
 217       unsigned char in_sr;
 218       unsigned char out_dr;
 219     } fmt_ldb;
 220     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 221       SI * i_sr;
 222       HI f_simm16;
 223       SI * i_dr;
 224       unsigned char in_sr;
 225       unsigned char out_dr;
 226     } fmt_ldb_d;
 227     struct { /* e.g. ldh $dr,@$sr */
 228       SI * i_sr;
 229       SI * i_dr;
 230       unsigned char in_sr;
 231       unsigned char out_dr;
 232     } fmt_ldh;
 233     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 234       SI * i_sr;
 235       HI f_simm16;
 236       SI * i_dr;
 237       unsigned char in_sr;
 238       unsigned char out_dr;
 239     } fmt_ldh_d;
 240     struct { /* e.g. ld $dr,@$sr+ */
 241       SI * i_sr;
 242       SI * i_dr;
 243       unsigned char in_sr;
 244       unsigned char out_dr;
 245       unsigned char out_sr;
 246     } fmt_ld_plus;
 247     struct { /* e.g. ld24 $dr,$uimm24 */
 248       ADDR f_uimm24;
 249       SI * i_dr;
 250       unsigned char out_dr;
 251     } fmt_ld24;
 252     struct { /* e.g. ldi8 $dr,$simm8 */
 253       SI f_simm8;
 254       SI * i_dr;
 255       unsigned char out_dr;
 256     } fmt_ldi8;
 257     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 258       HI f_simm16;
 259       SI * i_dr;
 260       unsigned char out_dr;
 261     } fmt_ldi16;
 262     struct { /* e.g. lock $dr,@$sr */
 263       SI * i_sr;
 264       SI * i_dr;
 265       unsigned char in_sr;
 266       unsigned char out_dr;
 267     } fmt_lock;
 268     struct { /* e.g. machi $src1,$src2 */
 269       SI * i_src1;
 270       SI * i_src2;
 271       unsigned char in_src1;
 272       unsigned char in_src2;
 273     } fmt_machi;
 274     struct { /* e.g. mulhi $src1,$src2 */
 275       SI * i_src1;
 276       SI * i_src2;
 277       unsigned char in_src1;
 278       unsigned char in_src2;
 279     } fmt_mulhi;
 280     struct { /* e.g. mv $dr,$sr */
 281       SI * i_sr;
 282       SI * i_dr;
 283       unsigned char in_sr;
 284       unsigned char out_dr;
 285     } fmt_mv;
 286     struct { /* e.g. mvfachi $dr */
 287       SI * i_dr;
 288       unsigned char out_dr;
 289     } fmt_mvfachi;
 290     struct { /* e.g. mvfc $dr,$scr */
 291       UINT f_r2;
 292       SI * i_dr;
 293       unsigned char out_dr;
 294     } fmt_mvfc;
 295     struct { /* e.g. mvtachi $src1 */
 296       SI * i_src1;
 297       unsigned char in_src1;
 298     } fmt_mvtachi;
 299     struct { /* e.g. mvtc $sr,$dcr */
 300       SI * i_sr;
 301       UINT f_r1;
 302       unsigned char in_sr;
 303     } fmt_mvtc;
 304     struct { /* e.g. nop */
 305       int empty;
 306     } fmt_nop;
 307     struct { /* e.g. rac */
 308       int empty;
 309     } fmt_rac;
 310     struct { /* e.g. seth $dr,$hash$hi16 */
 311       UHI f_hi16;
 312       SI * i_dr;
 313       unsigned char out_dr;
 314     } fmt_seth;
 315     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 316       SI * i_sr;
 317       SI f_simm16;
 318       SI * i_dr;
 319       unsigned char in_sr;
 320       unsigned char out_dr;
 321     } fmt_sll3;
 322     struct { /* e.g. slli $dr,$uimm5 */
 323       SI * i_dr;
 324       USI f_uimm5;
 325       unsigned char in_dr;
 326       unsigned char out_dr;
 327     } fmt_slli;
 328     struct { /* e.g. st $src1,@$src2 */
 329       SI * i_src2;
 330       SI * i_src1;
 331       unsigned char in_src2;
 332       unsigned char in_src1;
 333     } fmt_st;
 334     struct { /* e.g. st $src1,@($slo16,$src2) */
 335       SI * i_src2;
 336       HI f_simm16;
 337       SI * i_src1;
 338       unsigned char in_src2;
 339       unsigned char in_src1;
 340     } fmt_st_d;
 341     struct { /* e.g. stb $src1,@$src2 */
 342       SI * i_src2;
 343       SI * i_src1;
 344       unsigned char in_src2;
 345       unsigned char in_src1;
 346     } fmt_stb;
 347     struct { /* e.g. stb $src1,@($slo16,$src2) */
 348       SI * i_src2;
 349       HI f_simm16;
 350       SI * i_src1;
 351       unsigned char in_src2;
 352       unsigned char in_src1;
 353     } fmt_stb_d;
 354     struct { /* e.g. sth $src1,@$src2 */
 355       SI * i_src2;
 356       SI * i_src1;
 357       unsigned char in_src2;
 358       unsigned char in_src1;
 359     } fmt_sth;
 360     struct { /* e.g. sth $src1,@($slo16,$src2) */
 361       SI * i_src2;
 362       HI f_simm16;
 363       SI * i_src1;
 364       unsigned char in_src2;
 365       unsigned char in_src1;
 366     } fmt_sth_d;
 367     struct { /* e.g. st $src1,@+$src2 */
 368       SI * i_src2;
 369       SI * i_src1;
 370       unsigned char in_src2;
 371       unsigned char in_src1;
 372       unsigned char out_src2;
 373     } fmt_st_plus;
 374     struct { /* e.g. unlock $src1,@$src2 */
 375       SI * i_src2;
 376       SI * i_src1;
 377       unsigned char in_src2;
 378       unsigned char in_src1;
 379     } fmt_unlock;
 380   /* cti insns, kept separately so addr_cache is in fixed place */
 381   struct {
 382     union {
 383     struct { /* e.g. bc.s $disp8 */
 384       IADDR f_disp8;
 385     } fmt_bc8;
 386     struct { /* e.g. bc.l $disp24 */
 387       IADDR f_disp24;
 388     } fmt_bc24;
 389     struct { /* e.g. beq $src1,$src2,$disp16 */
 390       SI * i_src1;
 391       SI * i_src2;
 392       IADDR f_disp16;
 393       unsigned char in_src1;
 394       unsigned char in_src2;
 395     } fmt_beq;
 396     struct { /* e.g. beqz $src2,$disp16 */
 397       SI * i_src2;
 398       IADDR f_disp16;
 399       unsigned char in_src2;
 400     } fmt_beqz;
 401     struct { /* e.g. bl.s $disp8 */
 402       IADDR f_disp8;
 403       unsigned char out_h_gr_14;
 404     } fmt_bl8;
 405     struct { /* e.g. bl.l $disp24 */
 406       IADDR f_disp24;
 407       unsigned char out_h_gr_14;
 408     } fmt_bl24;
 409     struct { /* e.g. bra.s $disp8 */
 410       IADDR f_disp8;
 411     } fmt_bra8;
 412     struct { /* e.g. bra.l $disp24 */
 413       IADDR f_disp24;
 414     } fmt_bra24;
 415     struct { /* e.g. jl $sr */
 416       SI * i_sr;
 417       unsigned char in_sr;
 418       unsigned char out_h_gr_14;
 419     } fmt_jl;
 420     struct { /* e.g. jmp $sr */
 421       SI * i_sr;
 422       unsigned char in_sr;
 423     } fmt_jmp;
 424     struct { /* e.g. rte */
 425       int empty;
 426     } fmt_rte;
 427     struct { /* e.g. trap $uimm4 */
 428       USI f_uimm4;
 429     } fmt_trap;
 430     } fields;
 431 #if WITH_SCACHE_PBB_M32RBF
 432     SEM_PC addr_cache;
 433 #endif
 434   } cti;
 435 #if WITH_SCACHE_PBB_M32RBF
 436     /* Writeback handler.  */
 437     struct {
 438       /* Pointer to argbuf entry for insn whose results need writing back.  */
 439       const struct argbuf *abuf;
 440     } write;
 441     /* x-before handler */
 442     struct {
 443       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 444       int first_p;
 445     } before;
 446     /* x-after handler */
 447     struct {
 448       int empty;
 449     } after;
 450     /* This entry is used to terminate each pbb.  */
 451     struct {
 452       /* Number of insns in pbb.  */
 453       int insn_count;
 454       /* Next pbb to execute.  */
 455       SCACHE *next;
 456     } chain;
 457 #endif
 458   } fields;
 459 };
 460
 461 /* A cached insn.
 462
 463    ??? SCACHE used to contain more than just argbuf.  We could delete the
 464    type entirely and always just use ARGBUF, but for future concerns and as
 465    a level of abstraction it is left in.  */
 466
 467 struct scache {
 468   struct argbuf argbuf;
 469 };
 470
 471 /* Macros to simplify extraction, reading and semantic code.
 472    These define and assign the local vars that contain the insn's fields.  */
 473
 474 #define EXTRACT_FMT_ADD_VARS \
 475   /* Instruction fields.  */ \
 476   UINT f_op1; \
 477   UINT f_r1; \
 478   UINT f_op2; \
 479   UINT f_r2; \
 480   unsigned int length;
 481 #define EXTRACT_FMT_ADD_CODE \
 482   length = 2; \
 483   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 484   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 485   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 486   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 487
 488 #define EXTRACT_FMT_ADD3_VARS \
 489   /* Instruction fields.  */ \
 490   UINT f_op1; \
 491   UINT f_r1; \
 492   UINT f_op2; \
 493   UINT f_r2; \
 494   INT f_simm16; \
 495   unsigned int length;
 496 #define EXTRACT_FMT_ADD3_CODE \
 497   length = 4; \
 498   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 499   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 500   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 501   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 502   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 503
 504 #define EXTRACT_FMT_AND3_VARS \
 505   /* Instruction fields.  */ \
 506   UINT f_op1; \
 507   UINT f_r1; \
 508   UINT f_op2; \
 509   UINT f_r2; \
 510   UINT f_uimm16; \
 511   unsigned int length;
 512 #define EXTRACT_FMT_AND3_CODE \
 513   length = 4; \
 514   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 515   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 516   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 517   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 518   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 519
 520 #define EXTRACT_FMT_OR3_VARS \
 521   /* Instruction fields.  */ \
 522   UINT f_op1; \
 523   UINT f_r1; \
 524   UINT f_op2; \
 525   UINT f_r2; \
 526   UINT f_uimm16; \
 527   unsigned int length;
 528 #define EXTRACT_FMT_OR3_CODE \
 529   length = 4; \
 530   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 531   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 532   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 533   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 534   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 535
 536 #define EXTRACT_FMT_ADDI_VARS \
 537   /* Instruction fields.  */ \
 538   UINT f_op1; \
 539   UINT f_r1; \
 540   INT f_simm8; \
 541   unsigned int length;
 542 #define EXTRACT_FMT_ADDI_CODE \
 543   length = 2; \
 544   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 545   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 546   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 547
 548 #define EXTRACT_FMT_ADDV_VARS \
 549   /* Instruction fields.  */ \
 550   UINT f_op1; \
 551   UINT f_r1; \
 552   UINT f_op2; \
 553   UINT f_r2; \
 554   unsigned int length;
 555 #define EXTRACT_FMT_ADDV_CODE \
 556   length = 2; \
 557   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 558   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 559   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 560   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 561
 562 #define EXTRACT_FMT_ADDV3_VARS \
 563   /* Instruction fields.  */ \
 564   UINT f_op1; \
 565   UINT f_r1; \
 566   UINT f_op2; \
 567   UINT f_r2; \
 568   INT f_simm16; \
 569   unsigned int length;
 570 #define EXTRACT_FMT_ADDV3_CODE \
 571   length = 4; \
 572   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 573   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 574   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 575   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 576   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 577
 578 #define EXTRACT_FMT_ADDX_VARS \
 579   /* Instruction fields.  */ \
 580   UINT f_op1; \
 581   UINT f_r1; \
 582   UINT f_op2; \
 583   UINT f_r2; \
 584   unsigned int length;
 585 #define EXTRACT_FMT_ADDX_CODE \
 586   length = 2; \
 587   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 588   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 589   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 590   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 591
 592 #define EXTRACT_FMT_BC8_VARS \
 593   /* Instruction fields.  */ \
 594   UINT f_op1; \
 595   UINT f_r1; \
 596   INT f_disp8; \
 597   unsigned int length;
 598 #define EXTRACT_FMT_BC8_CODE \
 599   length = 2; \
 600   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 601   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 602   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 603
 604 #define EXTRACT_FMT_BC24_VARS \
 605   /* Instruction fields.  */ \
 606   UINT f_op1; \
 607   UINT f_r1; \
 608   INT f_disp24; \
 609   unsigned int length;
 610 #define EXTRACT_FMT_BC24_CODE \
 611   length = 4; \
 612   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 613   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 614   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 615
 616 #define EXTRACT_FMT_BEQ_VARS \
 617   /* Instruction fields.  */ \
 618   UINT f_op1; \
 619   UINT f_r1; \
 620   UINT f_op2; \
 621   UINT f_r2; \
 622   INT f_disp16; \
 623   unsigned int length;
 624 #define EXTRACT_FMT_BEQ_CODE \
 625   length = 4; \
 626   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 627   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 628   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 629   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 630   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 631
 632 #define EXTRACT_FMT_BEQZ_VARS \
 633   /* Instruction fields.  */ \
 634   UINT f_op1; \
 635   UINT f_r1; \
 636   UINT f_op2; \
 637   UINT f_r2; \
 638   INT f_disp16; \
 639   unsigned int length;
 640 #define EXTRACT_FMT_BEQZ_CODE \
 641   length = 4; \
 642   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 643   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 644   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 645   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 646   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 647
 648 #define EXTRACT_FMT_BL8_VARS \
 649   /* Instruction fields.  */ \
 650   UINT f_op1; \
 651   UINT f_r1; \
 652   INT f_disp8; \
 653   unsigned int length;
 654 #define EXTRACT_FMT_BL8_CODE \
 655   length = 2; \
 656   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 657   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 658   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 659
 660 #define EXTRACT_FMT_BL24_VARS \
 661   /* Instruction fields.  */ \
 662   UINT f_op1; \
 663   UINT f_r1; \
 664   INT f_disp24; \
 665   unsigned int length;
 666 #define EXTRACT_FMT_BL24_CODE \
 667   length = 4; \
 668   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 669   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 670   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 671
 672 #define EXTRACT_FMT_BRA8_VARS \
 673   /* Instruction fields.  */ \
 674   UINT f_op1; \
 675   UINT f_r1; \
 676   INT f_disp8; \
 677   unsigned int length;
 678 #define EXTRACT_FMT_BRA8_CODE \
 679   length = 2; \
 680   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 681   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 682   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 683
 684 #define EXTRACT_FMT_BRA24_VARS \
 685   /* Instruction fields.  */ \
 686   UINT f_op1; \
 687   UINT f_r1; \
 688   INT f_disp24; \
 689   unsigned int length;
 690 #define EXTRACT_FMT_BRA24_CODE \
 691   length = 4; \
 692   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 693   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 694   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 695
 696 #define EXTRACT_FMT_CMP_VARS \
 697   /* Instruction fields.  */ \
 698   UINT f_op1; \
 699   UINT f_r1; \
 700   UINT f_op2; \
 701   UINT f_r2; \
 702   unsigned int length;
 703 #define EXTRACT_FMT_CMP_CODE \
 704   length = 2; \
 705   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 706   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 707   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 708   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 709
 710 #define EXTRACT_FMT_CMPI_VARS \
 711   /* Instruction fields.  */ \
 712   UINT f_op1; \
 713   UINT f_r1; \
 714   UINT f_op2; \
 715   UINT f_r2; \
 716   INT f_simm16; \
 717   unsigned int length;
 718 #define EXTRACT_FMT_CMPI_CODE \
 719   length = 4; \
 720   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 721   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 722   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 723   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 724   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 725
 726 #define EXTRACT_FMT_DIV_VARS \
 727   /* Instruction fields.  */ \
 728   UINT f_op1; \
 729   UINT f_r1; \
 730   UINT f_op2; \
 731   UINT f_r2; \
 732   INT f_simm16; \
 733   unsigned int length;
 734 #define EXTRACT_FMT_DIV_CODE \
 735   length = 4; \
 736   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 737   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 738   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 739   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 740   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 741
 742 #define EXTRACT_FMT_JL_VARS \
 743   /* Instruction fields.  */ \
 744   UINT f_op1; \
 745   UINT f_r1; \
 746   UINT f_op2; \
 747   UINT f_r2; \
 748   unsigned int length;
 749 #define EXTRACT_FMT_JL_CODE \
 750   length = 2; \
 751   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 752   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 753   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 754   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 755
 756 #define EXTRACT_FMT_JMP_VARS \
 757   /* Instruction fields.  */ \
 758   UINT f_op1; \
 759   UINT f_r1; \
 760   UINT f_op2; \
 761   UINT f_r2; \
 762   unsigned int length;
 763 #define EXTRACT_FMT_JMP_CODE \
 764   length = 2; \
 765   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 766   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 767   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 768   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 769
 770 #define EXTRACT_FMT_LD_VARS \
 771   /* Instruction fields.  */ \
 772   UINT f_op1; \
 773   UINT f_r1; \
 774   UINT f_op2; \
 775   UINT f_r2; \
 776   unsigned int length;
 777 #define EXTRACT_FMT_LD_CODE \
 778   length = 2; \
 779   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 780   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 781   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 782   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 783
 784 #define EXTRACT_FMT_LD_D_VARS \
 785   /* Instruction fields.  */ \
 786   UINT f_op1; \
 787   UINT f_r1; \
 788   UINT f_op2; \
 789   UINT f_r2; \
 790   INT f_simm16; \
 791   unsigned int length;
 792 #define EXTRACT_FMT_LD_D_CODE \
 793   length = 4; \
 794   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 795   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 796   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 797   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 798   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 799
 800 #define EXTRACT_FMT_LDB_VARS \
 801   /* Instruction fields.  */ \
 802   UINT f_op1; \
 803   UINT f_r1; \
 804   UINT f_op2; \
 805   UINT f_r2; \
 806   unsigned int length;
 807 #define EXTRACT_FMT_LDB_CODE \
 808   length = 2; \
 809   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 810   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 811   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 812   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 813
 814 #define EXTRACT_FMT_LDB_D_VARS \
 815   /* Instruction fields.  */ \
 816   UINT f_op1; \
 817   UINT f_r1; \
 818   UINT f_op2; \
 819   UINT f_r2; \
 820   INT f_simm16; \
 821   unsigned int length;
 822 #define EXTRACT_FMT_LDB_D_CODE \
 823   length = 4; \
 824   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 825   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 826   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 827   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 828   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 829
 830 #define EXTRACT_FMT_LDH_VARS \
 831   /* Instruction fields.  */ \
 832   UINT f_op1; \
 833   UINT f_r1; \
 834   UINT f_op2; \
 835   UINT f_r2; \
 836   unsigned int length;
 837 #define EXTRACT_FMT_LDH_CODE \
 838   length = 2; \
 839   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 840   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 841   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 842   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 843
 844 #define EXTRACT_FMT_LDH_D_VARS \
 845   /* Instruction fields.  */ \
 846   UINT f_op1; \
 847   UINT f_r1; \
 848   UINT f_op2; \
 849   UINT f_r2; \
 850   INT f_simm16; \
 851   unsigned int length;
 852 #define EXTRACT_FMT_LDH_D_CODE \
 853   length = 4; \
 854   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 855   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 856   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 857   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 858   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 859
 860 #define EXTRACT_FMT_LD_PLUS_VARS \
 861   /* Instruction fields.  */ \
 862   UINT f_op1; \
 863   UINT f_r1; \
 864   UINT f_op2; \
 865   UINT f_r2; \
 866   unsigned int length;
 867 #define EXTRACT_FMT_LD_PLUS_CODE \
 868   length = 2; \
 869   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 870   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 871   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 872   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 873
 874 #define EXTRACT_FMT_LD24_VARS \
 875   /* Instruction fields.  */ \
 876   UINT f_op1; \
 877   UINT f_r1; \
 878   UINT f_uimm24; \
 879   unsigned int length;
 880 #define EXTRACT_FMT_LD24_CODE \
 881   length = 4; \
 882   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 883   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 884   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 885
 886 #define EXTRACT_FMT_LDI8_VARS \
 887   /* Instruction fields.  */ \
 888   UINT f_op1; \
 889   UINT f_r1; \
 890   INT f_simm8; \
 891   unsigned int length;
 892 #define EXTRACT_FMT_LDI8_CODE \
 893   length = 2; \
 894   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 895   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 896   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 897
 898 #define EXTRACT_FMT_LDI16_VARS \
 899   /* Instruction fields.  */ \
 900   UINT f_op1; \
 901   UINT f_r1; \
 902   UINT f_op2; \
 903   UINT f_r2; \
 904   INT f_simm16; \
 905   unsigned int length;
 906 #define EXTRACT_FMT_LDI16_CODE \
 907   length = 4; \
 908   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 909   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 910   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 911   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 912   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 913
 914 #define EXTRACT_FMT_LOCK_VARS \
 915   /* Instruction fields.  */ \
 916   UINT f_op1; \
 917   UINT f_r1; \
 918   UINT f_op2; \
 919   UINT f_r2; \
 920   unsigned int length;
 921 #define EXTRACT_FMT_LOCK_CODE \
 922   length = 2; \
 923   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 924   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 925   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 926   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 927
 928 #define EXTRACT_FMT_MACHI_VARS \
 929   /* Instruction fields.  */ \
 930   UINT f_op1; \
 931   UINT f_r1; \
 932   UINT f_op2; \
 933   UINT f_r2; \
 934   unsigned int length;
 935 #define EXTRACT_FMT_MACHI_CODE \
 936   length = 2; \
 937   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 938   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 939   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 940   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 941
 942 #define EXTRACT_FMT_MULHI_VARS \
 943   /* Instruction fields.  */ \
 944   UINT f_op1; \
 945   UINT f_r1; \
 946   UINT f_op2; \
 947   UINT f_r2; \
 948   unsigned int length;
 949 #define EXTRACT_FMT_MULHI_CODE \
 950   length = 2; \
 951   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 952   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 953   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 954   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 955
 956 #define EXTRACT_FMT_MV_VARS \
 957   /* Instruction fields.  */ \
 958   UINT f_op1; \
 959   UINT f_r1; \
 960   UINT f_op2; \
 961   UINT f_r2; \
 962   unsigned int length;
 963 #define EXTRACT_FMT_MV_CODE \
 964   length = 2; \
 965   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 966   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 967   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 968   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 969
 970 #define EXTRACT_FMT_MVFACHI_VARS \
 971   /* Instruction fields.  */ \
 972   UINT f_op1; \
 973   UINT f_r1; \
 974   UINT f_op2; \
 975   UINT f_r2; \
 976   unsigned int length;
 977 #define EXTRACT_FMT_MVFACHI_CODE \
 978   length = 2; \
 979   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 980   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 981   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 982   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 983
 984 #define EXTRACT_FMT_MVFC_VARS \
 985   /* Instruction fields.  */ \
 986   UINT f_op1; \
 987   UINT f_r1; \
 988   UINT f_op2; \
 989   UINT f_r2; \
 990   unsigned int length;
 991 #define EXTRACT_FMT_MVFC_CODE \
 992   length = 2; \
 993   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 994   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 995   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 996   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 997
 998 #define EXTRACT_FMT_MVTACHI_VARS \
 999   /* Instruction fields.  */ \
1000   UINT f_op1; \
1001   UINT f_r1; \
1002   UINT f_op2; \
1003   UINT f_r2; \
1004   unsigned int length;
1005 #define EXTRACT_FMT_MVTACHI_CODE \
1006   length = 2; \
1007   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1008   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1009   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1010   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1011
1012 #define EXTRACT_FMT_MVTC_VARS \
1013   /* Instruction fields.  */ \
1014   UINT f_op1; \
1015   UINT f_r1; \
1016   UINT f_op2; \
1017   UINT f_r2; \
1018   unsigned int length;
1019 #define EXTRACT_FMT_MVTC_CODE \
1020   length = 2; \
1021   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1022   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1023   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1024   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1025
1026 #define EXTRACT_FMT_NOP_VARS \
1027   /* Instruction fields.  */ \
1028   UINT f_op1; \
1029   UINT f_r1; \
1030   UINT f_op2; \
1031   UINT f_r2; \
1032   unsigned int length;
1033 #define EXTRACT_FMT_NOP_CODE \
1034   length = 2; \
1035   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1036   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1037   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1038   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1039
1040 #define EXTRACT_FMT_RAC_VARS \
1041   /* Instruction fields.  */ \
1042   UINT f_op1; \
1043   UINT f_r1; \
1044   UINT f_op2; \
1045   UINT f_r2; \
1046   unsigned int length;
1047 #define EXTRACT_FMT_RAC_CODE \
1048   length = 2; \
1049   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1050   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1051   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1052   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1053
1054 #define EXTRACT_FMT_RTE_VARS \
1055   /* Instruction fields.  */ \
1056   UINT f_op1; \
1057   UINT f_r1; \
1058   UINT f_op2; \
1059   UINT f_r2; \
1060   unsigned int length;
1061 #define EXTRACT_FMT_RTE_CODE \
1062   length = 2; \
1063   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1064   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1065   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1066   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1067
1068 #define EXTRACT_FMT_SETH_VARS \
1069   /* Instruction fields.  */ \
1070   UINT f_op1; \
1071   UINT f_r1; \
1072   UINT f_op2; \
1073   UINT f_r2; \
1074   UINT f_hi16; \
1075   unsigned int length;
1076 #define EXTRACT_FMT_SETH_CODE \
1077   length = 4; \
1078   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1079   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1080   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1081   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1082   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1083
1084 #define EXTRACT_FMT_SLL3_VARS \
1085   /* Instruction fields.  */ \
1086   UINT f_op1; \
1087   UINT f_r1; \
1088   UINT f_op2; \
1089   UINT f_r2; \
1090   INT f_simm16; \
1091   unsigned int length;
1092 #define EXTRACT_FMT_SLL3_CODE \
1093   length = 4; \
1094   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1095   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1096   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1097   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1098   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1099
1100 #define EXTRACT_FMT_SLLI_VARS \
1101   /* Instruction fields.  */ \
1102   UINT f_op1; \
1103   UINT f_r1; \
1104   UINT f_shift_op2; \
1105   UINT f_uimm5; \
1106   unsigned int length;
1107 #define EXTRACT_FMT_SLLI_CODE \
1108   length = 2; \
1109   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1110   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1111   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1112   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1113
1114 #define EXTRACT_FMT_ST_VARS \
1115   /* Instruction fields.  */ \
1116   UINT f_op1; \
1117   UINT f_r1; \
1118   UINT f_op2; \
1119   UINT f_r2; \
1120   unsigned int length;
1121 #define EXTRACT_FMT_ST_CODE \
1122   length = 2; \
1123   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1124   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1125   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1126   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1127
1128 #define EXTRACT_FMT_ST_D_VARS \
1129   /* Instruction fields.  */ \
1130   UINT f_op1; \
1131   UINT f_r1; \
1132   UINT f_op2; \
1133   UINT f_r2; \
1134   INT f_simm16; \
1135   unsigned int length;
1136 #define EXTRACT_FMT_ST_D_CODE \
1137   length = 4; \
1138   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1139   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1140   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1141   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1142   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1143
1144 #define EXTRACT_FMT_STB_VARS \
1145   /* Instruction fields.  */ \
1146   UINT f_op1; \
1147   UINT f_r1; \
1148   UINT f_op2; \
1149   UINT f_r2; \
1150   unsigned int length;
1151 #define EXTRACT_FMT_STB_CODE \
1152   length = 2; \
1153   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1154   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1155   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1156   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1157
1158 #define EXTRACT_FMT_STB_D_VARS \
1159   /* Instruction fields.  */ \
1160   UINT f_op1; \
1161   UINT f_r1; \
1162   UINT f_op2; \
1163   UINT f_r2; \
1164   INT f_simm16; \
1165   unsigned int length;
1166 #define EXTRACT_FMT_STB_D_CODE \
1167   length = 4; \
1168   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1169   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1170   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1171   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1172   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1173
1174 #define EXTRACT_FMT_STH_VARS \
1175   /* Instruction fields.  */ \
1176   UINT f_op1; \
1177   UINT f_r1; \
1178   UINT f_op2; \
1179   UINT f_r2; \
1180   unsigned int length;
1181 #define EXTRACT_FMT_STH_CODE \
1182   length = 2; \
1183   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1184   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1185   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1186   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1187
1188 #define EXTRACT_FMT_STH_D_VARS \
1189   /* Instruction fields.  */ \
1190   UINT f_op1; \
1191   UINT f_r1; \
1192   UINT f_op2; \
1193   UINT f_r2; \
1194   INT f_simm16; \
1195   unsigned int length;
1196 #define EXTRACT_FMT_STH_D_CODE \
1197   length = 4; \
1198   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1199   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1200   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1201   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1202   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1203
1204 #define EXTRACT_FMT_ST_PLUS_VARS \
1205   /* Instruction fields.  */ \
1206   UINT f_op1; \
1207   UINT f_r1; \
1208   UINT f_op2; \
1209   UINT f_r2; \
1210   unsigned int length;
1211 #define EXTRACT_FMT_ST_PLUS_CODE \
1212   length = 2; \
1213   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1214   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1215   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1216   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1217
1218 #define EXTRACT_FMT_TRAP_VARS \
1219   /* Instruction fields.  */ \
1220   UINT f_op1; \
1221   UINT f_r1; \
1222   UINT f_op2; \
1223   UINT f_uimm4; \
1224   unsigned int length;
1225 #define EXTRACT_FMT_TRAP_CODE \
1226   length = 2; \
1227   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1228   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1229   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1230   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1231
1232 #define EXTRACT_FMT_UNLOCK_VARS \
1233   /* Instruction fields.  */ \
1234   UINT f_op1; \
1235   UINT f_r1; \
1236   UINT f_op2; \
1237   UINT f_r2; \
1238   unsigned int length;
1239 #define EXTRACT_FMT_UNLOCK_CODE \
1240   length = 2; \
1241   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1242   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1243   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1244   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1245
1246 /* Collection of various things for the trace handler to use.  */
1247
1248 typedef struct trace_record {
1249   PCADDR pc;
1250   /* FIXME:wip */
1251 } TRACE_RECORD;
1252
1253 #endif /* CPU_M32RBF_H */