sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RBF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rbf_h_pc_get (SIM_CPU *);
  89 void m32rbf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rbf_h_accum_get (SIM_CPU *);
  95 void m32rbf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rbf_h_cond_get (SIM_CPU *);
  99 void m32rbf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rbf_h_psw_get (SIM_CPU *);
 101 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 103 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 105 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rbf_h_lock_get (SIM_CPU *);
 107 void m32rbf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 111 extern CPUREG_STORE_FN m32rbf_store_register;
 112
 113 typedef struct {
 114   UINT h_gr;
 115 } MODEL_M32R_D_DATA;
 116
 117 typedef struct {
 118   int empty;
 119 } MODEL_TEST_DATA;
 120
 121 union sem_fields {
 122     struct { /* empty format for unspecified field list */
 123       int empty;
 124     } fmt_empty;
 125     struct { /* e.g. add $dr,$sr */
 126       SI * i_dr;
 127       SI * i_sr;
 128       unsigned char in_dr;
 129       unsigned char in_sr;
 130       unsigned char out_dr;
 131     } fmt_add;
 132     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 133       INT f_simm16;
 134       SI * i_sr;
 135       SI * i_dr;
 136       unsigned char in_sr;
 137       unsigned char out_dr;
 138     } fmt_add3;
 139     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 140       UINT f_uimm16;
 141       SI * i_sr;
 142       SI * i_dr;
 143       unsigned char in_sr;
 144       unsigned char out_dr;
 145     } fmt_and3;
 146     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 147       UINT f_uimm16;
 148       SI * i_sr;
 149       SI * i_dr;
 150       unsigned char in_sr;
 151       unsigned char out_dr;
 152     } fmt_or3;
 153     struct { /* e.g. addi $dr,$simm8 */
 154       INT f_simm8;
 155       SI * i_dr;
 156       unsigned char in_dr;
 157       unsigned char out_dr;
 158     } fmt_addi;
 159     struct { /* e.g. addv $dr,$sr */
 160       SI * i_dr;
 161       SI * i_sr;
 162       unsigned char in_dr;
 163       unsigned char in_sr;
 164       unsigned char out_dr;
 165     } fmt_addv;
 166     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 167       INT f_simm16;
 168       SI * i_sr;
 169       SI * i_dr;
 170       unsigned char in_sr;
 171       unsigned char out_dr;
 172     } fmt_addv3;
 173     struct { /* e.g. addx $dr,$sr */
 174       SI * i_dr;
 175       SI * i_sr;
 176       unsigned char in_dr;
 177       unsigned char in_sr;
 178       unsigned char out_dr;
 179     } fmt_addx;
 180     struct { /* e.g. cmp $src1,$src2 */
 181       SI * i_src1;
 182       SI * i_src2;
 183       unsigned char in_src1;
 184       unsigned char in_src2;
 185     } fmt_cmp;
 186     struct { /* e.g. cmpi $src2,$simm16 */
 187       INT f_simm16;
 188       SI * i_src2;
 189       unsigned char in_src2;
 190     } fmt_cmpi;
 191     struct { /* e.g. div $dr,$sr */
 192       SI * i_sr;
 193       SI * i_dr;
 194       unsigned char in_sr;
 195       unsigned char in_dr;
 196       unsigned char out_dr;
 197     } fmt_div;
 198     struct { /* e.g. ld $dr,@$sr */
 199       SI * i_sr;
 200       SI * i_dr;
 201       unsigned char in_sr;
 202       unsigned char out_dr;
 203     } fmt_ld;
 204     struct { /* e.g. ld $dr,@($slo16,$sr) */
 205       INT f_simm16;
 206       SI * i_sr;
 207       SI * i_dr;
 208       unsigned char in_sr;
 209       unsigned char out_dr;
 210     } fmt_ld_d;
 211     struct { /* e.g. ldb $dr,@$sr */
 212       SI * i_sr;
 213       SI * i_dr;
 214       unsigned char in_sr;
 215       unsigned char out_dr;
 216     } fmt_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       INT f_simm16;
 219       SI * i_sr;
 220       SI * i_dr;
 221       unsigned char in_sr;
 222       unsigned char out_dr;
 223     } fmt_ldb_d;
 224     struct { /* e.g. ldh $dr,@$sr */
 225       SI * i_sr;
 226       SI * i_dr;
 227       unsigned char in_sr;
 228       unsigned char out_dr;
 229     } fmt_ldh;
 230     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 231       INT f_simm16;
 232       SI * i_sr;
 233       SI * i_dr;
 234       unsigned char in_sr;
 235       unsigned char out_dr;
 236     } fmt_ldh_d;
 237     struct { /* e.g. ld $dr,@$sr+ */
 238       SI * i_sr;
 239       SI * i_dr;
 240       unsigned char in_sr;
 241       unsigned char out_dr;
 242       unsigned char out_sr;
 243     } fmt_ld_plus;
 244     struct { /* e.g. ld24 $dr,$uimm24 */
 245       ADDR i_uimm24;
 246       SI * i_dr;
 247       unsigned char out_dr;
 248     } fmt_ld24;
 249     struct { /* e.g. ldi8 $dr,$simm8 */
 250       INT f_simm8;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ldi8;
 254     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 255       INT f_simm16;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi16;
 259     struct { /* e.g. lock $dr,@$sr */
 260       SI * i_sr;
 261       SI * i_dr;
 262       unsigned char in_sr;
 263       unsigned char out_dr;
 264     } fmt_lock;
 265     struct { /* e.g. machi $src1,$src2 */
 266       SI * i_src1;
 267       SI * i_src2;
 268       unsigned char in_src1;
 269       unsigned char in_src2;
 270     } fmt_machi;
 271     struct { /* e.g. mulhi $src1,$src2 */
 272       SI * i_src1;
 273       SI * i_src2;
 274       unsigned char in_src1;
 275       unsigned char in_src2;
 276     } fmt_mulhi;
 277     struct { /* e.g. mv $dr,$sr */
 278       SI * i_sr;
 279       SI * i_dr;
 280       unsigned char in_sr;
 281       unsigned char out_dr;
 282     } fmt_mv;
 283     struct { /* e.g. mvfachi $dr */
 284       SI * i_dr;
 285       unsigned char out_dr;
 286     } fmt_mvfachi;
 287     struct { /* e.g. mvfc $dr,$scr */
 288       UINT f_r2;
 289       SI * i_dr;
 290       unsigned char out_dr;
 291     } fmt_mvfc;
 292     struct { /* e.g. mvtachi $src1 */
 293       SI * i_src1;
 294       unsigned char in_src1;
 295     } fmt_mvtachi;
 296     struct { /* e.g. mvtc $sr,$dcr */
 297       UINT f_r1;
 298       SI * i_sr;
 299       unsigned char in_sr;
 300     } fmt_mvtc;
 301     struct { /* e.g. nop */
 302       int empty;
 303     } fmt_nop;
 304     struct { /* e.g. rac */
 305       int empty;
 306     } fmt_rac;
 307     struct { /* e.g. seth $dr,$hash$hi16 */
 308       UINT f_hi16;
 309       SI * i_dr;
 310       unsigned char out_dr;
 311     } fmt_seth;
 312     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 313       INT f_simm16;
 314       SI * i_sr;
 315       SI * i_dr;
 316       unsigned char in_sr;
 317       unsigned char out_dr;
 318     } fmt_sll3;
 319     struct { /* e.g. slli $dr,$uimm5 */
 320       UINT f_uimm5;
 321       SI * i_dr;
 322       unsigned char in_dr;
 323       unsigned char out_dr;
 324     } fmt_slli;
 325     struct { /* e.g. st $src1,@$src2 */
 326       SI * i_src2;
 327       SI * i_src1;
 328       unsigned char in_src2;
 329       unsigned char in_src1;
 330     } fmt_st;
 331     struct { /* e.g. st $src1,@($slo16,$src2) */
 332       INT f_simm16;
 333       SI * i_src2;
 334       SI * i_src1;
 335       unsigned char in_src2;
 336       unsigned char in_src1;
 337     } fmt_st_d;
 338     struct { /* e.g. stb $src1,@$src2 */
 339       SI * i_src2;
 340       SI * i_src1;
 341       unsigned char in_src2;
 342       unsigned char in_src1;
 343     } fmt_stb;
 344     struct { /* e.g. stb $src1,@($slo16,$src2) */
 345       INT f_simm16;
 346       SI * i_src2;
 347       SI * i_src1;
 348       unsigned char in_src2;
 349       unsigned char in_src1;
 350     } fmt_stb_d;
 351     struct { /* e.g. sth $src1,@$src2 */
 352       SI * i_src2;
 353       SI * i_src1;
 354       unsigned char in_src2;
 355       unsigned char in_src1;
 356     } fmt_sth;
 357     struct { /* e.g. sth $src1,@($slo16,$src2) */
 358       INT f_simm16;
 359       SI * i_src2;
 360       SI * i_src1;
 361       unsigned char in_src2;
 362       unsigned char in_src1;
 363     } fmt_sth_d;
 364     struct { /* e.g. st $src1,@+$src2 */
 365       SI * i_src2;
 366       SI * i_src1;
 367       unsigned char in_src2;
 368       unsigned char in_src1;
 369       unsigned char out_src2;
 370     } fmt_st_plus;
 371     struct { /* e.g. unlock $src1,@$src2 */
 372       SI * i_src2;
 373       SI * i_src1;
 374       unsigned char in_src2;
 375       unsigned char in_src1;
 376     } fmt_unlock;
 377   /* cti insns, kept separately so addr_cache is in fixed place */
 378   struct {
 379     union {
 380     struct { /* e.g. bc.s $disp8 */
 381       IADDR i_disp8;
 382     } fmt_bc8;
 383     struct { /* e.g. bc.l $disp24 */
 384       IADDR i_disp24;
 385     } fmt_bc24;
 386     struct { /* e.g. beq $src1,$src2,$disp16 */
 387       SI * i_src1;
 388       SI * i_src2;
 389       IADDR i_disp16;
 390       unsigned char in_src1;
 391       unsigned char in_src2;
 392     } fmt_beq;
 393     struct { /* e.g. beqz $src2,$disp16 */
 394       SI * i_src2;
 395       IADDR i_disp16;
 396       unsigned char in_src2;
 397     } fmt_beqz;
 398     struct { /* e.g. bl.s $disp8 */
 399       IADDR i_disp8;
 400       unsigned char out_h_gr_14;
 401     } fmt_bl8;
 402     struct { /* e.g. bl.l $disp24 */
 403       IADDR i_disp24;
 404       unsigned char out_h_gr_14;
 405     } fmt_bl24;
 406     struct { /* e.g. bra.s $disp8 */
 407       IADDR i_disp8;
 408     } fmt_bra8;
 409     struct { /* e.g. bra.l $disp24 */
 410       IADDR i_disp24;
 411     } fmt_bra24;
 412     struct { /* e.g. jl $sr */
 413       SI * i_sr;
 414       unsigned char in_sr;
 415       unsigned char out_h_gr_14;
 416     } fmt_jl;
 417     struct { /* e.g. jmp $sr */
 418       SI * i_sr;
 419       unsigned char in_sr;
 420     } fmt_jmp;
 421     struct { /* e.g. rte */
 422       int empty;
 423     } fmt_rte;
 424     struct { /* e.g. trap $uimm4 */
 425       UINT f_uimm4;
 426     } fmt_trap;
 427     } fields;
 428 #if WITH_SCACHE_PBB
 429     SEM_PC addr_cache;
 430 #endif
 431   } cti;
 432 #if WITH_SCACHE_PBB
 433   /* Writeback handler.  */
 434   struct {
 435     /* Pointer to argbuf entry for insn whose results need writing back.  */
 436     const struct argbuf *abuf;
 437   } write;
 438   /* x-before handler */
 439   struct {
 440     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 441     int first_p;
 442   } before;
 443   /* x-after handler */
 444   struct {
 445     int empty;
 446   } after;
 447   /* This entry is used to terminate each pbb.  */
 448   struct {
 449     /* Number of insns in pbb.  */
 450     int insn_count;
 451     /* Next pbb to execute.  */
 452     SCACHE *next;
 453   } chain;
 454 #endif
 455 };
 456
 457 /* The ARGBUF struct.  */
 458 struct argbuf {
 459   /* These are the baseclass definitions.  */
 460   PCADDR addr;
 461   const IDESC *idesc;
 462   char trace_p;
 463   char profile_p;
 464   /* cpu specific data follows */
 465   union sem semantic;
 466   int written;
 467   union sem_fields fields;
 468 };
 469
 470 /* A cached insn.
 471
 472    ??? SCACHE used to contain more than just argbuf.  We could delete the
 473    type entirely and always just use ARGBUF, but for future concerns and as
 474    a level of abstraction it is left in.  */
 475
 476 struct scache {
 477   struct argbuf argbuf;
 478 };
 479
 480 /* Macros to simplify extraction, reading and semantic code.
 481    These define and assign the local vars that contain the insn's fields.  */
 482
 483 #define EXTRACT_FMT_EMPTY_VARS \
 484   /* Instruction fields.  */ \
 485   unsigned int length;
 486 #define EXTRACT_FMT_EMPTY_CODE \
 487   length = 0; \
 488
 489 #define EXTRACT_FMT_ADD_VARS \
 490   /* Instruction fields.  */ \
 491   UINT f_op1; \
 492   UINT f_r1; \
 493   UINT f_op2; \
 494   UINT f_r2; \
 495   unsigned int length;
 496 #define EXTRACT_FMT_ADD_CODE \
 497   length = 2; \
 498   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 499   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 500   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 501   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 502
 503 #define EXTRACT_FMT_ADD3_VARS \
 504   /* Instruction fields.  */ \
 505   UINT f_op1; \
 506   UINT f_r1; \
 507   UINT f_op2; \
 508   UINT f_r2; \
 509   INT f_simm16; \
 510   unsigned int length;
 511 #define EXTRACT_FMT_ADD3_CODE \
 512   length = 4; \
 513   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 514   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 515   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 516   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 517   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 518
 519 #define EXTRACT_FMT_AND3_VARS \
 520   /* Instruction fields.  */ \
 521   UINT f_op1; \
 522   UINT f_r1; \
 523   UINT f_op2; \
 524   UINT f_r2; \
 525   UINT f_uimm16; \
 526   unsigned int length;
 527 #define EXTRACT_FMT_AND3_CODE \
 528   length = 4; \
 529   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 530   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 531   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 532   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 533   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 534
 535 #define EXTRACT_FMT_OR3_VARS \
 536   /* Instruction fields.  */ \
 537   UINT f_op1; \
 538   UINT f_r1; \
 539   UINT f_op2; \
 540   UINT f_r2; \
 541   UINT f_uimm16; \
 542   unsigned int length;
 543 #define EXTRACT_FMT_OR3_CODE \
 544   length = 4; \
 545   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 546   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 547   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 548   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 549   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 550
 551 #define EXTRACT_FMT_ADDI_VARS \
 552   /* Instruction fields.  */ \
 553   UINT f_op1; \
 554   UINT f_r1; \
 555   INT f_simm8; \
 556   unsigned int length;
 557 #define EXTRACT_FMT_ADDI_CODE \
 558   length = 2; \
 559   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 560   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 561   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 562
 563 #define EXTRACT_FMT_ADDV_VARS \
 564   /* Instruction fields.  */ \
 565   UINT f_op1; \
 566   UINT f_r1; \
 567   UINT f_op2; \
 568   UINT f_r2; \
 569   unsigned int length;
 570 #define EXTRACT_FMT_ADDV_CODE \
 571   length = 2; \
 572   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 573   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 574   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 575   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 576
 577 #define EXTRACT_FMT_ADDV3_VARS \
 578   /* Instruction fields.  */ \
 579   UINT f_op1; \
 580   UINT f_r1; \
 581   UINT f_op2; \
 582   UINT f_r2; \
 583   INT f_simm16; \
 584   unsigned int length;
 585 #define EXTRACT_FMT_ADDV3_CODE \
 586   length = 4; \
 587   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 588   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 589   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 590   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 591   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 592
 593 #define EXTRACT_FMT_ADDX_VARS \
 594   /* Instruction fields.  */ \
 595   UINT f_op1; \
 596   UINT f_r1; \
 597   UINT f_op2; \
 598   UINT f_r2; \
 599   unsigned int length;
 600 #define EXTRACT_FMT_ADDX_CODE \
 601   length = 2; \
 602   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 603   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 604   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 605   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 606
 607 #define EXTRACT_FMT_BC8_VARS \
 608   /* Instruction fields.  */ \
 609   UINT f_op1; \
 610   UINT f_r1; \
 611   SI f_disp8; \
 612   unsigned int length;
 613 #define EXTRACT_FMT_BC8_CODE \
 614   length = 2; \
 615   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 616   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 617   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 618
 619 #define EXTRACT_FMT_BC24_VARS \
 620   /* Instruction fields.  */ \
 621   UINT f_op1; \
 622   UINT f_r1; \
 623   SI f_disp24; \
 624   unsigned int length;
 625 #define EXTRACT_FMT_BC24_CODE \
 626   length = 4; \
 627   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 628   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 629   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 630
 631 #define EXTRACT_FMT_BEQ_VARS \
 632   /* Instruction fields.  */ \
 633   UINT f_op1; \
 634   UINT f_r1; \
 635   UINT f_op2; \
 636   UINT f_r2; \
 637   SI f_disp16; \
 638   unsigned int length;
 639 #define EXTRACT_FMT_BEQ_CODE \
 640   length = 4; \
 641   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 642   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 643   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 644   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 645   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 646
 647 #define EXTRACT_FMT_BEQZ_VARS \
 648   /* Instruction fields.  */ \
 649   UINT f_op1; \
 650   UINT f_r1; \
 651   UINT f_op2; \
 652   UINT f_r2; \
 653   SI f_disp16; \
 654   unsigned int length;
 655 #define EXTRACT_FMT_BEQZ_CODE \
 656   length = 4; \
 657   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 658   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 659   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 660   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 661   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 662
 663 #define EXTRACT_FMT_BL8_VARS \
 664   /* Instruction fields.  */ \
 665   UINT f_op1; \
 666   UINT f_r1; \
 667   SI f_disp8; \
 668   unsigned int length;
 669 #define EXTRACT_FMT_BL8_CODE \
 670   length = 2; \
 671   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 672   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 673   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 674
 675 #define EXTRACT_FMT_BL24_VARS \
 676   /* Instruction fields.  */ \
 677   UINT f_op1; \
 678   UINT f_r1; \
 679   SI f_disp24; \
 680   unsigned int length;
 681 #define EXTRACT_FMT_BL24_CODE \
 682   length = 4; \
 683   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 684   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 685   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 686
 687 #define EXTRACT_FMT_BRA8_VARS \
 688   /* Instruction fields.  */ \
 689   UINT f_op1; \
 690   UINT f_r1; \
 691   SI f_disp8; \
 692   unsigned int length;
 693 #define EXTRACT_FMT_BRA8_CODE \
 694   length = 2; \
 695   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 696   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 697   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 698
 699 #define EXTRACT_FMT_BRA24_VARS \
 700   /* Instruction fields.  */ \
 701   UINT f_op1; \
 702   UINT f_r1; \
 703   SI f_disp24; \
 704   unsigned int length;
 705 #define EXTRACT_FMT_BRA24_CODE \
 706   length = 4; \
 707   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 708   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 709   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 710
 711 #define EXTRACT_FMT_CMP_VARS \
 712   /* Instruction fields.  */ \
 713   UINT f_op1; \
 714   UINT f_r1; \
 715   UINT f_op2; \
 716   UINT f_r2; \
 717   unsigned int length;
 718 #define EXTRACT_FMT_CMP_CODE \
 719   length = 2; \
 720   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 721   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 722   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 723   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 724
 725 #define EXTRACT_FMT_CMPI_VARS \
 726   /* Instruction fields.  */ \
 727   UINT f_op1; \
 728   UINT f_r1; \
 729   UINT f_op2; \
 730   UINT f_r2; \
 731   INT f_simm16; \
 732   unsigned int length;
 733 #define EXTRACT_FMT_CMPI_CODE \
 734   length = 4; \
 735   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 736   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 737   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 738   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 739   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 740
 741 #define EXTRACT_FMT_DIV_VARS \
 742   /* Instruction fields.  */ \
 743   UINT f_op1; \
 744   UINT f_r1; \
 745   UINT f_op2; \
 746   UINT f_r2; \
 747   INT f_simm16; \
 748   unsigned int length;
 749 #define EXTRACT_FMT_DIV_CODE \
 750   length = 4; \
 751   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 752   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 753   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 754   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 755   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 756
 757 #define EXTRACT_FMT_JL_VARS \
 758   /* Instruction fields.  */ \
 759   UINT f_op1; \
 760   UINT f_r1; \
 761   UINT f_op2; \
 762   UINT f_r2; \
 763   unsigned int length;
 764 #define EXTRACT_FMT_JL_CODE \
 765   length = 2; \
 766   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 767   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 768   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 769   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 770
 771 #define EXTRACT_FMT_JMP_VARS \
 772   /* Instruction fields.  */ \
 773   UINT f_op1; \
 774   UINT f_r1; \
 775   UINT f_op2; \
 776   UINT f_r2; \
 777   unsigned int length;
 778 #define EXTRACT_FMT_JMP_CODE \
 779   length = 2; \
 780   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 781   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 782   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 783   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 784
 785 #define EXTRACT_FMT_LD_VARS \
 786   /* Instruction fields.  */ \
 787   UINT f_op1; \
 788   UINT f_r1; \
 789   UINT f_op2; \
 790   UINT f_r2; \
 791   unsigned int length;
 792 #define EXTRACT_FMT_LD_CODE \
 793   length = 2; \
 794   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 795   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 796   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 797   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 798
 799 #define EXTRACT_FMT_LD_D_VARS \
 800   /* Instruction fields.  */ \
 801   UINT f_op1; \
 802   UINT f_r1; \
 803   UINT f_op2; \
 804   UINT f_r2; \
 805   INT f_simm16; \
 806   unsigned int length;
 807 #define EXTRACT_FMT_LD_D_CODE \
 808   length = 4; \
 809   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 810   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 811   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 812   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 813   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 814
 815 #define EXTRACT_FMT_LDB_VARS \
 816   /* Instruction fields.  */ \
 817   UINT f_op1; \
 818   UINT f_r1; \
 819   UINT f_op2; \
 820   UINT f_r2; \
 821   unsigned int length;
 822 #define EXTRACT_FMT_LDB_CODE \
 823   length = 2; \
 824   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 825   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 826   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 827   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 828
 829 #define EXTRACT_FMT_LDB_D_VARS \
 830   /* Instruction fields.  */ \
 831   UINT f_op1; \
 832   UINT f_r1; \
 833   UINT f_op2; \
 834   UINT f_r2; \
 835   INT f_simm16; \
 836   unsigned int length;
 837 #define EXTRACT_FMT_LDB_D_CODE \
 838   length = 4; \
 839   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 840   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 841   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 842   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 843   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 844
 845 #define EXTRACT_FMT_LDH_VARS \
 846   /* Instruction fields.  */ \
 847   UINT f_op1; \
 848   UINT f_r1; \
 849   UINT f_op2; \
 850   UINT f_r2; \
 851   unsigned int length;
 852 #define EXTRACT_FMT_LDH_CODE \
 853   length = 2; \
 854   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 855   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 856   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 857   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 858
 859 #define EXTRACT_FMT_LDH_D_VARS \
 860   /* Instruction fields.  */ \
 861   UINT f_op1; \
 862   UINT f_r1; \
 863   UINT f_op2; \
 864   UINT f_r2; \
 865   INT f_simm16; \
 866   unsigned int length;
 867 #define EXTRACT_FMT_LDH_D_CODE \
 868   length = 4; \
 869   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 870   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 871   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 872   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 873   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 874
 875 #define EXTRACT_FMT_LD_PLUS_VARS \
 876   /* Instruction fields.  */ \
 877   UINT f_op1; \
 878   UINT f_r1; \
 879   UINT f_op2; \
 880   UINT f_r2; \
 881   unsigned int length;
 882 #define EXTRACT_FMT_LD_PLUS_CODE \
 883   length = 2; \
 884   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 885   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 886   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 887   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 888
 889 #define EXTRACT_FMT_LD24_VARS \
 890   /* Instruction fields.  */ \
 891   UINT f_op1; \
 892   UINT f_r1; \
 893   UINT f_uimm24; \
 894   unsigned int length;
 895 #define EXTRACT_FMT_LD24_CODE \
 896   length = 4; \
 897   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 898   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 899   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 900
 901 #define EXTRACT_FMT_LDI8_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   INT f_simm8; \
 906   unsigned int length;
 907 #define EXTRACT_FMT_LDI8_CODE \
 908   length = 2; \
 909   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 910   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 911   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 912
 913 #define EXTRACT_FMT_LDI16_VARS \
 914   /* Instruction fields.  */ \
 915   UINT f_op1; \
 916   UINT f_r1; \
 917   UINT f_op2; \
 918   UINT f_r2; \
 919   INT f_simm16; \
 920   unsigned int length;
 921 #define EXTRACT_FMT_LDI16_CODE \
 922   length = 4; \
 923   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 924   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 925   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 926   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 927   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 928
 929 #define EXTRACT_FMT_LOCK_VARS \
 930   /* Instruction fields.  */ \
 931   UINT f_op1; \
 932   UINT f_r1; \
 933   UINT f_op2; \
 934   UINT f_r2; \
 935   unsigned int length;
 936 #define EXTRACT_FMT_LOCK_CODE \
 937   length = 2; \
 938   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 939   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 940   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 941   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 942
 943 #define EXTRACT_FMT_MACHI_VARS \
 944   /* Instruction fields.  */ \
 945   UINT f_op1; \
 946   UINT f_r1; \
 947   UINT f_op2; \
 948   UINT f_r2; \
 949   unsigned int length;
 950 #define EXTRACT_FMT_MACHI_CODE \
 951   length = 2; \
 952   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 953   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 954   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 955   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 956
 957 #define EXTRACT_FMT_MULHI_VARS \
 958   /* Instruction fields.  */ \
 959   UINT f_op1; \
 960   UINT f_r1; \
 961   UINT f_op2; \
 962   UINT f_r2; \
 963   unsigned int length;
 964 #define EXTRACT_FMT_MULHI_CODE \
 965   length = 2; \
 966   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 967   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 968   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 969   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 970
 971 #define EXTRACT_FMT_MV_VARS \
 972   /* Instruction fields.  */ \
 973   UINT f_op1; \
 974   UINT f_r1; \
 975   UINT f_op2; \
 976   UINT f_r2; \
 977   unsigned int length;
 978 #define EXTRACT_FMT_MV_CODE \
 979   length = 2; \
 980   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 981   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 982   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 983   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 984
 985 #define EXTRACT_FMT_MVFACHI_VARS \
 986   /* Instruction fields.  */ \
 987   UINT f_op1; \
 988   UINT f_r1; \
 989   UINT f_op2; \
 990   UINT f_r2; \
 991   unsigned int length;
 992 #define EXTRACT_FMT_MVFACHI_CODE \
 993   length = 2; \
 994   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 995   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 996   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 997   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 998
 999 #define EXTRACT_FMT_MVFC_VARS \
1000   /* Instruction fields.  */ \
1001   UINT f_op1; \
1002   UINT f_r1; \
1003   UINT f_op2; \
1004   UINT f_r2; \
1005   unsigned int length;
1006 #define EXTRACT_FMT_MVFC_CODE \
1007   length = 2; \
1008   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1009   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1010   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1011   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1012
1013 #define EXTRACT_FMT_MVTACHI_VARS \
1014   /* Instruction fields.  */ \
1015   UINT f_op1; \
1016   UINT f_r1; \
1017   UINT f_op2; \
1018   UINT f_r2; \
1019   unsigned int length;
1020 #define EXTRACT_FMT_MVTACHI_CODE \
1021   length = 2; \
1022   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1023   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1024   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1025   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1026
1027 #define EXTRACT_FMT_MVTC_VARS \
1028   /* Instruction fields.  */ \
1029   UINT f_op1; \
1030   UINT f_r1; \
1031   UINT f_op2; \
1032   UINT f_r2; \
1033   unsigned int length;
1034 #define EXTRACT_FMT_MVTC_CODE \
1035   length = 2; \
1036   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1037   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1038   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1039   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1040
1041 #define EXTRACT_FMT_NOP_VARS \
1042   /* Instruction fields.  */ \
1043   UINT f_op1; \
1044   UINT f_r1; \
1045   UINT f_op2; \
1046   UINT f_r2; \
1047   unsigned int length;
1048 #define EXTRACT_FMT_NOP_CODE \
1049   length = 2; \
1050   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1051   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1052   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1053   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1054
1055 #define EXTRACT_FMT_RAC_VARS \
1056   /* Instruction fields.  */ \
1057   UINT f_op1; \
1058   UINT f_r1; \
1059   UINT f_op2; \
1060   UINT f_r2; \
1061   unsigned int length;
1062 #define EXTRACT_FMT_RAC_CODE \
1063   length = 2; \
1064   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1065   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1066   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1067   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1068
1069 #define EXTRACT_FMT_RTE_VARS \
1070   /* Instruction fields.  */ \
1071   UINT f_op1; \
1072   UINT f_r1; \
1073   UINT f_op2; \
1074   UINT f_r2; \
1075   unsigned int length;
1076 #define EXTRACT_FMT_RTE_CODE \
1077   length = 2; \
1078   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1079   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1080   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1081   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1082
1083 #define EXTRACT_FMT_SETH_VARS \
1084   /* Instruction fields.  */ \
1085   UINT f_op1; \
1086   UINT f_r1; \
1087   UINT f_op2; \
1088   UINT f_r2; \
1089   UINT f_hi16; \
1090   unsigned int length;
1091 #define EXTRACT_FMT_SETH_CODE \
1092   length = 4; \
1093   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1094   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1095   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1096   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1097   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1098
1099 #define EXTRACT_FMT_SLL3_VARS \
1100   /* Instruction fields.  */ \
1101   UINT f_op1; \
1102   UINT f_r1; \
1103   UINT f_op2; \
1104   UINT f_r2; \
1105   INT f_simm16; \
1106   unsigned int length;
1107 #define EXTRACT_FMT_SLL3_CODE \
1108   length = 4; \
1109   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1110   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1111   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1112   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1113   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1114
1115 #define EXTRACT_FMT_SLLI_VARS \
1116   /* Instruction fields.  */ \
1117   UINT f_op1; \
1118   UINT f_r1; \
1119   UINT f_shift_op2; \
1120   UINT f_uimm5; \
1121   unsigned int length;
1122 #define EXTRACT_FMT_SLLI_CODE \
1123   length = 2; \
1124   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1125   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1126   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1127   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1128
1129 #define EXTRACT_FMT_ST_VARS \
1130   /* Instruction fields.  */ \
1131   UINT f_op1; \
1132   UINT f_r1; \
1133   UINT f_op2; \
1134   UINT f_r2; \
1135   unsigned int length;
1136 #define EXTRACT_FMT_ST_CODE \
1137   length = 2; \
1138   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1139   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1140   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1141   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1142
1143 #define EXTRACT_FMT_ST_D_VARS \
1144   /* Instruction fields.  */ \
1145   UINT f_op1; \
1146   UINT f_r1; \
1147   UINT f_op2; \
1148   UINT f_r2; \
1149   INT f_simm16; \
1150   unsigned int length;
1151 #define EXTRACT_FMT_ST_D_CODE \
1152   length = 4; \
1153   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1154   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1155   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1156   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1157   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1158
1159 #define EXTRACT_FMT_STB_VARS \
1160   /* Instruction fields.  */ \
1161   UINT f_op1; \
1162   UINT f_r1; \
1163   UINT f_op2; \
1164   UINT f_r2; \
1165   unsigned int length;
1166 #define EXTRACT_FMT_STB_CODE \
1167   length = 2; \
1168   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1169   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1170   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1171   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1172
1173 #define EXTRACT_FMT_STB_D_VARS \
1174   /* Instruction fields.  */ \
1175   UINT f_op1; \
1176   UINT f_r1; \
1177   UINT f_op2; \
1178   UINT f_r2; \
1179   INT f_simm16; \
1180   unsigned int length;
1181 #define EXTRACT_FMT_STB_D_CODE \
1182   length = 4; \
1183   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1184   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1185   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1186   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1187   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1188
1189 #define EXTRACT_FMT_STH_VARS \
1190   /* Instruction fields.  */ \
1191   UINT f_op1; \
1192   UINT f_r1; \
1193   UINT f_op2; \
1194   UINT f_r2; \
1195   unsigned int length;
1196 #define EXTRACT_FMT_STH_CODE \
1197   length = 2; \
1198   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1199   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1200   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1201   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1202
1203 #define EXTRACT_FMT_STH_D_VARS \
1204   /* Instruction fields.  */ \
1205   UINT f_op1; \
1206   UINT f_r1; \
1207   UINT f_op2; \
1208   UINT f_r2; \
1209   INT f_simm16; \
1210   unsigned int length;
1211 #define EXTRACT_FMT_STH_D_CODE \
1212   length = 4; \
1213   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1214   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1215   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1216   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1217   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1218
1219 #define EXTRACT_FMT_ST_PLUS_VARS \
1220   /* Instruction fields.  */ \
1221   UINT f_op1; \
1222   UINT f_r1; \
1223   UINT f_op2; \
1224   UINT f_r2; \
1225   unsigned int length;
1226 #define EXTRACT_FMT_ST_PLUS_CODE \
1227   length = 2; \
1228   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1229   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1230   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1231   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1232
1233 #define EXTRACT_FMT_TRAP_VARS \
1234   /* Instruction fields.  */ \
1235   UINT f_op1; \
1236   UINT f_r1; \
1237   UINT f_op2; \
1238   UINT f_uimm4; \
1239   unsigned int length;
1240 #define EXTRACT_FMT_TRAP_CODE \
1241   length = 2; \
1242   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1243   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1244   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1245   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1246
1247 #define EXTRACT_FMT_UNLOCK_VARS \
1248   /* Instruction fields.  */ \
1249   UINT f_op1; \
1250   UINT f_r1; \
1251   UINT f_op2; \
1252   UINT f_r2; \
1253   unsigned int length;
1254 #define EXTRACT_FMT_UNLOCK_CODE \
1255   length = 2; \
1256   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1257   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1258   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1259   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1260
1261 /* Collection of various things for the trace handler to use.  */
1262
1263 typedef struct trace_record {
1264   PCADDR pc;
1265   /* FIXME:wip */
1266 } TRACE_RECORD;
1267
1268 #endif /* CPU_M32RBF_H */