1 /* CPU family header for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 /* GET_H_CR macro user-written */
50 /* SET_H_CR macro user-written */
53 /* GET_H_ACCUM macro user-written */
54 /* SET_H_ACCUM macro user-written */
55 /* start-sanitize-m32rx */
58 /* end-sanitize-m32rx */
59 /* start-sanitize-m32rx */
60 /* GET_H_ACCUMS macro user-written */
61 /* SET_H_ACCUMS macro user-written */
62 /* end-sanitize-m32rx */
65 #define GET_H_COND() CPU (h_cond)
66 #define SET_H_COND(x) (CPU (h_cond) = (x))
69 /* GET_H_PSW macro user-written */
70 /* SET_H_PSW macro user-written */
73 #define GET_H_BPSW() CPU (h_bpsw)
74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
77 #define GET_H_BBPSW() CPU (h_bbpsw)
78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
81 #define GET_H_LOCK() CPU (h_lock)
82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
87 /* Cover fns for register access. */
88 USI
m32rxf_h_pc_get (SIM_CPU
*);
89 void m32rxf_h_pc_set (SIM_CPU
*, USI
);
90 SI
m32rxf_h_gr_get (SIM_CPU
*, UINT
);
91 void m32rxf_h_gr_set (SIM_CPU
*, UINT
, SI
);
92 USI
m32rxf_h_cr_get (SIM_CPU
*, UINT
);
93 void m32rxf_h_cr_set (SIM_CPU
*, UINT
, USI
);
94 DI
m32rxf_h_accum_get (SIM_CPU
*);
95 void m32rxf_h_accum_set (SIM_CPU
*, DI
);
96 DI
m32rxf_h_accums_get (SIM_CPU
*, UINT
);
97 void m32rxf_h_accums_set (SIM_CPU
*, UINT
, DI
);
98 BI
m32rxf_h_cond_get (SIM_CPU
*);
99 void m32rxf_h_cond_set (SIM_CPU
*, BI
);
100 UQI
m32rxf_h_psw_get (SIM_CPU
*);
101 void m32rxf_h_psw_set (SIM_CPU
*, UQI
);
102 UQI
m32rxf_h_bpsw_get (SIM_CPU
*);
103 void m32rxf_h_bpsw_set (SIM_CPU
*, UQI
);
104 UQI
m32rxf_h_bbpsw_get (SIM_CPU
*);
105 void m32rxf_h_bbpsw_set (SIM_CPU
*, UQI
);
106 BI
m32rxf_h_lock_get (SIM_CPU
*);
107 void m32rxf_h_lock_set (SIM_CPU
*, BI
);
109 /* These must be hand-written. */
110 extern CPUREG_FETCH_FN m32rxf_fetch_register
;
111 extern CPUREG_STORE_FN m32rxf_store_register
;
117 /* The ARGBUF struct. */
119 /* These are the baseclass definitions. */
124 /* cpu specific data follows */
128 struct { /* empty format for unspecified field list */
131 struct { /* e.g. add $dr,$sr */
136 unsigned char out_dr
;
138 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
143 unsigned char out_dr
;
145 struct { /* e.g. and3 $dr,$sr,$uimm16 */
150 unsigned char out_dr
;
152 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
157 unsigned char out_dr
;
159 struct { /* e.g. addi $dr,$simm8 */
163 unsigned char out_dr
;
165 struct { /* e.g. addv $dr,$sr */
170 unsigned char out_dr
;
172 struct { /* e.g. addv3 $dr,$sr,$simm16 */
177 unsigned char out_dr
;
179 struct { /* e.g. addx $dr,$sr */
184 unsigned char out_dr
;
186 struct { /* e.g. cmp $src1,$src2 */
189 unsigned char in_src1
;
190 unsigned char in_src2
;
192 struct { /* e.g. cmpi $src2,$simm16 */
195 unsigned char in_src2
;
197 struct { /* e.g. cmpz $src2 */
199 unsigned char in_src2
;
201 struct { /* e.g. div $dr,$sr */
206 unsigned char out_dr
;
208 struct { /* e.g. ld $dr,@$sr */
212 unsigned char out_dr
;
214 struct { /* e.g. ld $dr,@($slo16,$sr) */
219 unsigned char out_dr
;
221 struct { /* e.g. ldb $dr,@$sr */
225 unsigned char out_dr
;
227 struct { /* e.g. ldb $dr,@($slo16,$sr) */
232 unsigned char out_dr
;
234 struct { /* e.g. ldh $dr,@$sr */
238 unsigned char out_dr
;
240 struct { /* e.g. ldh $dr,@($slo16,$sr) */
245 unsigned char out_dr
;
247 struct { /* e.g. ld $dr,@$sr+ */
251 unsigned char out_dr
;
252 unsigned char out_sr
;
254 struct { /* e.g. ld24 $dr,$uimm24 */
257 unsigned char out_dr
;
259 struct { /* e.g. ldi8 $dr,$simm8 */
262 unsigned char out_dr
;
264 struct { /* e.g. ldi16 $dr,$hash$slo16 */
267 unsigned char out_dr
;
269 struct { /* e.g. lock $dr,@$sr */
273 unsigned char out_dr
;
275 struct { /* e.g. machi $src1,$src2,$acc */
279 unsigned char in_src1
;
280 unsigned char in_src2
;
282 struct { /* e.g. mulhi $src1,$src2,$acc */
286 unsigned char in_src1
;
287 unsigned char in_src2
;
289 struct { /* e.g. mv $dr,$sr */
293 unsigned char out_dr
;
295 struct { /* e.g. mvfachi $dr,$accs */
298 unsigned char out_dr
;
300 struct { /* e.g. mvfc $dr,$scr */
303 unsigned char out_dr
;
305 struct { /* e.g. mvtachi $src1,$accs */
308 unsigned char in_src1
;
310 struct { /* e.g. mvtc $sr,$dcr */
315 struct { /* e.g. nop */
318 struct { /* e.g. rac $accd,$accs,$imm1 */
323 struct { /* e.g. seth $dr,$hash$hi16 */
326 unsigned char out_dr
;
328 struct { /* e.g. sll3 $dr,$sr,$simm16 */
333 unsigned char out_dr
;
335 struct { /* e.g. slli $dr,$uimm5 */
339 unsigned char out_dr
;
341 struct { /* e.g. st $src1,@$src2 */
344 unsigned char in_src2
;
345 unsigned char in_src1
;
347 struct { /* e.g. st $src1,@($slo16,$src2) */
351 unsigned char in_src2
;
352 unsigned char in_src1
;
354 struct { /* e.g. stb $src1,@$src2 */
357 unsigned char in_src2
;
358 unsigned char in_src1
;
360 struct { /* e.g. stb $src1,@($slo16,$src2) */
364 unsigned char in_src2
;
365 unsigned char in_src1
;
367 struct { /* e.g. sth $src1,@$src2 */
370 unsigned char in_src2
;
371 unsigned char in_src1
;
373 struct { /* e.g. sth $src1,@($slo16,$src2) */
377 unsigned char in_src2
;
378 unsigned char in_src1
;
380 struct { /* e.g. st $src1,@+$src2 */
383 unsigned char in_src2
;
384 unsigned char in_src1
;
385 unsigned char out_src2
;
387 struct { /* e.g. unlock $src1,@$src2 */
390 unsigned char in_src2
;
391 unsigned char in_src1
;
393 struct { /* e.g. satb $dr,$sr */
397 unsigned char out_dr
;
399 struct { /* e.g. sat $dr,$sr */
403 unsigned char out_dr
;
405 struct { /* e.g. sadd */
408 struct { /* e.g. macwu1 $src1,$src2 */
411 unsigned char in_src1
;
412 unsigned char in_src2
;
414 struct { /* e.g. msblo $src1,$src2 */
417 unsigned char in_src1
;
418 unsigned char in_src2
;
420 struct { /* e.g. mulwu1 $src1,$src2 */
423 unsigned char in_src1
;
424 unsigned char in_src2
;
426 /* cti insns, kept separately so addr_cache is in fixed place */
429 struct { /* e.g. bc.s $disp8 */
432 struct { /* e.g. bc.l $disp24 */
435 struct { /* e.g. beq $src1,$src2,$disp16 */
439 unsigned char in_src1
;
440 unsigned char in_src2
;
442 struct { /* e.g. beqz $src2,$disp16 */
445 unsigned char in_src2
;
447 struct { /* e.g. bl.s $disp8 */
449 unsigned char out_h_gr_14
;
451 struct { /* e.g. bl.l $disp24 */
453 unsigned char out_h_gr_14
;
455 struct { /* e.g. bcl.s $disp8 */
457 unsigned char out_h_gr_14
;
459 struct { /* e.g. bcl.l $disp24 */
461 unsigned char out_h_gr_14
;
463 struct { /* e.g. bra.s $disp8 */
466 struct { /* e.g. bra.l $disp24 */
469 struct { /* e.g. jc $sr */
473 struct { /* e.g. jl $sr */
476 unsigned char out_h_gr_14
;
478 struct { /* e.g. jmp $sr */
482 struct { /* e.g. rte */
485 struct { /* e.g. trap $uimm4 */
488 struct { /* e.g. sc */
497 /* Writeback handler. */
499 /* Pointer to argbuf entry for insn whose results need writing back. */
500 const struct argbuf
*abuf
;
502 /* x-before handler */
504 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
507 /* x-after handler */
511 /* This entry is used to terminate each pbb. */
513 /* Number of insns in pbb. */
515 /* Next pbb to execute. */
524 ??? SCACHE used to contain more than just argbuf. We could delete the
525 type entirely and always just use ARGBUF, but for future concerns and as
526 a level of abstraction it is left in. */
529 struct argbuf argbuf
;
532 /* Macros to simplify extraction, reading and semantic code.
533 These define and assign the local vars that contain the insn's fields. */
535 #define EXTRACT_FMT_EMPTY_VARS \
536 /* Instruction fields. */ \
538 #define EXTRACT_FMT_EMPTY_CODE \
541 #define EXTRACT_FMT_ADD_VARS \
542 /* Instruction fields. */ \
548 #define EXTRACT_FMT_ADD_CODE \
550 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
551 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
552 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
553 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
555 #define EXTRACT_FMT_ADD3_VARS \
556 /* Instruction fields. */ \
563 #define EXTRACT_FMT_ADD3_CODE \
565 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
566 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
567 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
568 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
569 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
571 #define EXTRACT_FMT_AND3_VARS \
572 /* Instruction fields. */ \
579 #define EXTRACT_FMT_AND3_CODE \
581 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
582 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
583 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
584 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
585 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
587 #define EXTRACT_FMT_OR3_VARS \
588 /* Instruction fields. */ \
595 #define EXTRACT_FMT_OR3_CODE \
597 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
598 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
599 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
600 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
601 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
603 #define EXTRACT_FMT_ADDI_VARS \
604 /* Instruction fields. */ \
609 #define EXTRACT_FMT_ADDI_CODE \
611 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
612 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
613 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
615 #define EXTRACT_FMT_ADDV_VARS \
616 /* Instruction fields. */ \
622 #define EXTRACT_FMT_ADDV_CODE \
624 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
625 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
626 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
627 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
629 #define EXTRACT_FMT_ADDV3_VARS \
630 /* Instruction fields. */ \
637 #define EXTRACT_FMT_ADDV3_CODE \
639 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
640 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
641 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
642 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
643 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
645 #define EXTRACT_FMT_ADDX_VARS \
646 /* Instruction fields. */ \
652 #define EXTRACT_FMT_ADDX_CODE \
654 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
655 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
656 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
657 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
659 #define EXTRACT_FMT_BC8_VARS \
660 /* Instruction fields. */ \
665 #define EXTRACT_FMT_BC8_CODE \
667 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
668 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
669 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
671 #define EXTRACT_FMT_BC24_VARS \
672 /* Instruction fields. */ \
677 #define EXTRACT_FMT_BC24_CODE \
679 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
680 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
681 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
683 #define EXTRACT_FMT_BEQ_VARS \
684 /* Instruction fields. */ \
691 #define EXTRACT_FMT_BEQ_CODE \
693 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
694 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
695 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
696 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
697 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
699 #define EXTRACT_FMT_BEQZ_VARS \
700 /* Instruction fields. */ \
707 #define EXTRACT_FMT_BEQZ_CODE \
709 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
710 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
711 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
712 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
713 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
715 #define EXTRACT_FMT_BL8_VARS \
716 /* Instruction fields. */ \
721 #define EXTRACT_FMT_BL8_CODE \
723 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
724 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
725 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
727 #define EXTRACT_FMT_BL24_VARS \
728 /* Instruction fields. */ \
733 #define EXTRACT_FMT_BL24_CODE \
735 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
736 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
737 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
739 #define EXTRACT_FMT_BCL8_VARS \
740 /* Instruction fields. */ \
745 #define EXTRACT_FMT_BCL8_CODE \
747 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
748 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
749 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
751 #define EXTRACT_FMT_BCL24_VARS \
752 /* Instruction fields. */ \
757 #define EXTRACT_FMT_BCL24_CODE \
759 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
760 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
761 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
763 #define EXTRACT_FMT_BRA8_VARS \
764 /* Instruction fields. */ \
769 #define EXTRACT_FMT_BRA8_CODE \
771 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
772 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
773 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
775 #define EXTRACT_FMT_BRA24_VARS \
776 /* Instruction fields. */ \
781 #define EXTRACT_FMT_BRA24_CODE \
783 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
784 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
785 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
787 #define EXTRACT_FMT_CMP_VARS \
788 /* Instruction fields. */ \
794 #define EXTRACT_FMT_CMP_CODE \
796 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
797 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
798 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
799 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
801 #define EXTRACT_FMT_CMPI_VARS \
802 /* Instruction fields. */ \
809 #define EXTRACT_FMT_CMPI_CODE \
811 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
812 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
813 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
814 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
815 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
817 #define EXTRACT_FMT_CMPZ_VARS \
818 /* Instruction fields. */ \
824 #define EXTRACT_FMT_CMPZ_CODE \
826 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
827 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
828 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
829 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
831 #define EXTRACT_FMT_DIV_VARS \
832 /* Instruction fields. */ \
839 #define EXTRACT_FMT_DIV_CODE \
841 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
842 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
843 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
844 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
845 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
847 #define EXTRACT_FMT_JC_VARS \
848 /* Instruction fields. */ \
854 #define EXTRACT_FMT_JC_CODE \
856 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
857 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
858 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
859 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
861 #define EXTRACT_FMT_JL_VARS \
862 /* Instruction fields. */ \
868 #define EXTRACT_FMT_JL_CODE \
870 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
871 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
872 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
873 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
875 #define EXTRACT_FMT_JMP_VARS \
876 /* Instruction fields. */ \
882 #define EXTRACT_FMT_JMP_CODE \
884 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
885 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
886 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
887 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
889 #define EXTRACT_FMT_LD_VARS \
890 /* Instruction fields. */ \
896 #define EXTRACT_FMT_LD_CODE \
898 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
899 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
900 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
901 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
903 #define EXTRACT_FMT_LD_D_VARS \
904 /* Instruction fields. */ \
911 #define EXTRACT_FMT_LD_D_CODE \
913 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
914 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
915 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
916 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
917 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
919 #define EXTRACT_FMT_LDB_VARS \
920 /* Instruction fields. */ \
926 #define EXTRACT_FMT_LDB_CODE \
928 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
929 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
930 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
931 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
933 #define EXTRACT_FMT_LDB_D_VARS \
934 /* Instruction fields. */ \
941 #define EXTRACT_FMT_LDB_D_CODE \
943 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
944 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
945 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
946 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
947 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
949 #define EXTRACT_FMT_LDH_VARS \
950 /* Instruction fields. */ \
956 #define EXTRACT_FMT_LDH_CODE \
958 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
959 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
960 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
961 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
963 #define EXTRACT_FMT_LDH_D_VARS \
964 /* Instruction fields. */ \
971 #define EXTRACT_FMT_LDH_D_CODE \
973 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
974 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
975 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
976 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
977 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
979 #define EXTRACT_FMT_LD_PLUS_VARS \
980 /* Instruction fields. */ \
986 #define EXTRACT_FMT_LD_PLUS_CODE \
988 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
989 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
990 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
991 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
993 #define EXTRACT_FMT_LD24_VARS \
994 /* Instruction fields. */ \
999 #define EXTRACT_FMT_LD24_CODE \
1001 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1002 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1003 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
1005 #define EXTRACT_FMT_LDI8_VARS \
1006 /* Instruction fields. */ \
1010 unsigned int length;
1011 #define EXTRACT_FMT_LDI8_CODE \
1013 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1014 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1015 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1017 #define EXTRACT_FMT_LDI16_VARS \
1018 /* Instruction fields. */ \
1024 unsigned int length;
1025 #define EXTRACT_FMT_LDI16_CODE \
1027 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1028 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1029 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1030 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1031 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1033 #define EXTRACT_FMT_LOCK_VARS \
1034 /* Instruction fields. */ \
1039 unsigned int length;
1040 #define EXTRACT_FMT_LOCK_CODE \
1042 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1043 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1044 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1045 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1047 #define EXTRACT_FMT_MACHI_A_VARS \
1048 /* Instruction fields. */ \
1054 unsigned int length;
1055 #define EXTRACT_FMT_MACHI_A_CODE \
1057 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1058 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1059 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1060 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1061 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1063 #define EXTRACT_FMT_MULHI_A_VARS \
1064 /* Instruction fields. */ \
1070 unsigned int length;
1071 #define EXTRACT_FMT_MULHI_A_CODE \
1073 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1074 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1075 f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1076 f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1077 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1079 #define EXTRACT_FMT_MV_VARS \
1080 /* Instruction fields. */ \
1085 unsigned int length;
1086 #define EXTRACT_FMT_MV_CODE \
1088 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1089 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1090 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1091 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1093 #define EXTRACT_FMT_MVFACHI_A_VARS \
1094 /* Instruction fields. */ \
1100 unsigned int length;
1101 #define EXTRACT_FMT_MVFACHI_A_CODE \
1103 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1104 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1105 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1106 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1107 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1109 #define EXTRACT_FMT_MVFC_VARS \
1110 /* Instruction fields. */ \
1115 unsigned int length;
1116 #define EXTRACT_FMT_MVFC_CODE \
1118 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1119 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1120 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1121 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1123 #define EXTRACT_FMT_MVTACHI_A_VARS \
1124 /* Instruction fields. */ \
1130 unsigned int length;
1131 #define EXTRACT_FMT_MVTACHI_A_CODE \
1133 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1134 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1135 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1136 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1137 f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1139 #define EXTRACT_FMT_MVTC_VARS \
1140 /* Instruction fields. */ \
1145 unsigned int length;
1146 #define EXTRACT_FMT_MVTC_CODE \
1148 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1149 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1150 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1151 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1153 #define EXTRACT_FMT_NOP_VARS \
1154 /* Instruction fields. */ \
1159 unsigned int length;
1160 #define EXTRACT_FMT_NOP_CODE \
1162 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1163 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1164 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1165 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1167 #define EXTRACT_FMT_RAC_DSI_VARS \
1168 /* Instruction fields. */ \
1176 unsigned int length;
1177 #define EXTRACT_FMT_RAC_DSI_CODE \
1179 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1180 f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1181 f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1182 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1183 f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1184 f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1185 f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1187 #define EXTRACT_FMT_RTE_VARS \
1188 /* Instruction fields. */ \
1193 unsigned int length;
1194 #define EXTRACT_FMT_RTE_CODE \
1196 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1197 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1198 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1199 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1201 #define EXTRACT_FMT_SETH_VARS \
1202 /* Instruction fields. */ \
1208 unsigned int length;
1209 #define EXTRACT_FMT_SETH_CODE \
1211 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1212 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1213 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1214 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1215 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1217 #define EXTRACT_FMT_SLL3_VARS \
1218 /* Instruction fields. */ \
1224 unsigned int length;
1225 #define EXTRACT_FMT_SLL3_CODE \
1227 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1228 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1229 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1230 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1231 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1233 #define EXTRACT_FMT_SLLI_VARS \
1234 /* Instruction fields. */ \
1239 unsigned int length;
1240 #define EXTRACT_FMT_SLLI_CODE \
1242 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1243 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1244 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1245 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1247 #define EXTRACT_FMT_ST_VARS \
1248 /* Instruction fields. */ \
1253 unsigned int length;
1254 #define EXTRACT_FMT_ST_CODE \
1256 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1257 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1258 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1259 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1261 #define EXTRACT_FMT_ST_D_VARS \
1262 /* Instruction fields. */ \
1268 unsigned int length;
1269 #define EXTRACT_FMT_ST_D_CODE \
1271 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1272 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1273 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1274 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1275 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1277 #define EXTRACT_FMT_STB_VARS \
1278 /* Instruction fields. */ \
1283 unsigned int length;
1284 #define EXTRACT_FMT_STB_CODE \
1286 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1287 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1288 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1289 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1291 #define EXTRACT_FMT_STB_D_VARS \
1292 /* Instruction fields. */ \
1298 unsigned int length;
1299 #define EXTRACT_FMT_STB_D_CODE \
1301 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1302 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1303 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1304 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1305 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1307 #define EXTRACT_FMT_STH_VARS \
1308 /* Instruction fields. */ \
1313 unsigned int length;
1314 #define EXTRACT_FMT_STH_CODE \
1316 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1317 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1318 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1319 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1321 #define EXTRACT_FMT_STH_D_VARS \
1322 /* Instruction fields. */ \
1328 unsigned int length;
1329 #define EXTRACT_FMT_STH_D_CODE \
1331 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1332 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1333 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1334 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1335 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1337 #define EXTRACT_FMT_ST_PLUS_VARS \
1338 /* Instruction fields. */ \
1343 unsigned int length;
1344 #define EXTRACT_FMT_ST_PLUS_CODE \
1346 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1347 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1348 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1349 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1351 #define EXTRACT_FMT_TRAP_VARS \
1352 /* Instruction fields. */ \
1357 unsigned int length;
1358 #define EXTRACT_FMT_TRAP_CODE \
1360 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1361 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1362 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1363 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1365 #define EXTRACT_FMT_UNLOCK_VARS \
1366 /* Instruction fields. */ \
1371 unsigned int length;
1372 #define EXTRACT_FMT_UNLOCK_CODE \
1374 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1375 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1376 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1377 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1379 #define EXTRACT_FMT_SATB_VARS \
1380 /* Instruction fields. */ \
1386 unsigned int length;
1387 #define EXTRACT_FMT_SATB_CODE \
1389 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1390 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1391 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1392 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1393 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1395 #define EXTRACT_FMT_SAT_VARS \
1396 /* Instruction fields. */ \
1402 unsigned int length;
1403 #define EXTRACT_FMT_SAT_CODE \
1405 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1406 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1407 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1408 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1409 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1411 #define EXTRACT_FMT_SADD_VARS \
1412 /* Instruction fields. */ \
1417 unsigned int length;
1418 #define EXTRACT_FMT_SADD_CODE \
1420 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1421 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1422 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1423 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1425 #define EXTRACT_FMT_MACWU1_VARS \
1426 /* Instruction fields. */ \
1431 unsigned int length;
1432 #define EXTRACT_FMT_MACWU1_CODE \
1434 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1435 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1436 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1437 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1439 #define EXTRACT_FMT_MSBLO_VARS \
1440 /* Instruction fields. */ \
1445 unsigned int length;
1446 #define EXTRACT_FMT_MSBLO_CODE \
1448 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1449 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1450 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1451 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1453 #define EXTRACT_FMT_MULWU1_VARS \
1454 /* Instruction fields. */ \
1459 unsigned int length;
1460 #define EXTRACT_FMT_MULWU1_CODE \
1462 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1463 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1464 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1465 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1467 #define EXTRACT_FMT_SC_VARS \
1468 /* Instruction fields. */ \
1473 unsigned int length;
1474 #define EXTRACT_FMT_SC_CODE \
1476 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1477 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1478 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1479 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1481 /* Queued output values of an instruction. */
1485 struct { /* empty format for unspecified field list */
1488 struct { /* e.g. add $dr,$sr */
1491 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1494 struct { /* e.g. and3 $dr,$sr,$uimm16 */
1497 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1500 struct { /* e.g. addi $dr,$simm8 */
1503 struct { /* e.g. addv $dr,$sr */
1507 struct { /* e.g. addv3 $dr,$sr,$simm16 */
1511 struct { /* e.g. addx $dr,$sr */
1515 struct { /* e.g. bc.s $disp8 */
1518 struct { /* e.g. bc.l $disp24 */
1521 struct { /* e.g. beq $src1,$src2,$disp16 */
1524 struct { /* e.g. beqz $src2,$disp16 */
1527 struct { /* e.g. bl.s $disp8 */
1531 struct { /* e.g. bl.l $disp24 */
1535 struct { /* e.g. bcl.s $disp8 */
1539 struct { /* e.g. bcl.l $disp24 */
1543 struct { /* e.g. bra.s $disp8 */
1546 struct { /* e.g. bra.l $disp24 */
1549 struct { /* e.g. cmp $src1,$src2 */
1552 struct { /* e.g. cmpi $src2,$simm16 */
1555 struct { /* e.g. cmpz $src2 */
1558 struct { /* e.g. div $dr,$sr */
1561 struct { /* e.g. jc $sr */
1564 struct { /* e.g. jl $sr */
1568 struct { /* e.g. jmp $sr */
1571 struct { /* e.g. ld $dr,@$sr */
1574 struct { /* e.g. ld $dr,@($slo16,$sr) */
1577 struct { /* e.g. ldb $dr,@$sr */
1580 struct { /* e.g. ldb $dr,@($slo16,$sr) */
1583 struct { /* e.g. ldh $dr,@$sr */
1586 struct { /* e.g. ldh $dr,@($slo16,$sr) */
1589 struct { /* e.g. ld $dr,@$sr+ */
1593 struct { /* e.g. ld24 $dr,$uimm24 */
1596 struct { /* e.g. ldi8 $dr,$simm8 */
1599 struct { /* e.g. ldi16 $dr,$hash$slo16 */
1602 struct { /* e.g. lock $dr,@$sr */
1606 struct { /* e.g. machi $src1,$src2,$acc */
1609 struct { /* e.g. mulhi $src1,$src2,$acc */
1612 struct { /* e.g. mv $dr,$sr */
1615 struct { /* e.g. mvfachi $dr,$accs */
1618 struct { /* e.g. mvfc $dr,$scr */
1621 struct { /* e.g. mvtachi $src1,$accs */
1624 struct { /* e.g. mvtc $sr,$dcr */
1627 struct { /* e.g. nop */
1630 struct { /* e.g. rac $accd,$accs,$imm1 */
1633 struct { /* e.g. rte */
1639 struct { /* e.g. seth $dr,$hash$hi16 */
1642 struct { /* e.g. sll3 $dr,$sr,$simm16 */
1645 struct { /* e.g. slli $dr,$uimm5 */
1648 struct { /* e.g. st $src1,@$src2 */
1650 USI h_memory_src2_idx
;
1652 struct { /* e.g. st $src1,@($slo16,$src2) */
1653 SI h_memory_add__VM_src2_slo16
;
1654 USI h_memory_add__VM_src2_slo16_idx
;
1656 struct { /* e.g. stb $src1,@$src2 */
1658 USI h_memory_src2_idx
;
1660 struct { /* e.g. stb $src1,@($slo16,$src2) */
1661 QI h_memory_add__VM_src2_slo16
;
1662 USI h_memory_add__VM_src2_slo16_idx
;
1664 struct { /* e.g. sth $src1,@$src2 */
1666 USI h_memory_src2_idx
;
1668 struct { /* e.g. sth $src1,@($slo16,$src2) */
1669 HI h_memory_add__VM_src2_slo16
;
1670 USI h_memory_add__VM_src2_slo16_idx
;
1672 struct { /* e.g. st $src1,@+$src2 */
1673 SI h_memory_new_src2
;
1674 USI h_memory_new_src2_idx
;
1677 struct { /* e.g. trap $uimm4 */
1685 struct { /* e.g. unlock $src1,@$src2 */
1687 USI h_memory_src2_idx
;
1690 struct { /* e.g. satb $dr,$sr */
1693 struct { /* e.g. sat $dr,$sr */
1696 struct { /* e.g. sadd */
1699 struct { /* e.g. macwu1 $src1,$src2 */
1702 struct { /* e.g. msblo $src1,$src2 */
1705 struct { /* e.g. mulwu1 $src1,$src2 */
1708 struct { /* e.g. sc */
1712 /* For conditionally written operands, bitmask of which ones were. */
1716 /* Collection of various things for the trace handler to use. */
1718 typedef struct trace_record
{
1723 #endif /* CPU_M32RXF_H */