sim/m32r/cpux.h

   1 /* CPU family header for m32rx.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23 #ifndef CPU_M32RX_H
  24 #define CPU_M32RX_H
  25
  26 /* Maximum number of instructions that are fetched at a time.
  27    This is for LIW type instructions sets (e.g. m32r).  */
  28 #define MAX_LIW_INSNS 2
  29
  30 /* Maximum number of instructions that can be executed in parallel.  */
  31 #define MAX_PARALLEL_INSNS 2
  32
  33 /* CPU state information.  */
  34 typedef struct {
  35   /* Hardware elements.  */
  36   struct {
  37   /* program counter */
  38   USI h_pc;
  39 #define GET_H_PC() CPU (h_pc)
  40 #define SET_H_PC(x) (CPU (h_pc) = (x))
  41   /* general registers */
  42   SI h_gr[16];
  43 #define GET_H_GR(a1) CPU (h_gr)[a1]
  44 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  45   /* control registers */
  46   SI h_cr[7];
  47 #define GET_H_CR(a1) CPU (h_cr)[a1]
  48 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  49   /* accumulator */
  50   DI h_accum;
  51 #define GET_H_ACCUM() CPU (h_accum)
  52 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  53   /* accumulators */
  54   DI h_accums[2];
  55 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  56 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  57   /* abort flag */
  58   UBI h_abort;
  59 #define GET_H_ABORT() CPU (h_abort)
  60 #define SET_H_ABORT(x) (CPU (h_abort) = (x))
  61   /* condition bit */
  62   UBI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* sm */
  66   UBI h_sm;
  67 #define GET_H_SM() CPU (h_sm)
  68 #define SET_H_SM(x) (CPU (h_sm) = (x))
  69   /* bsm */
  70   UBI h_bsm;
  71 #define GET_H_BSM() CPU (h_bsm)
  72 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
  73   /* ie */
  74   UBI h_ie;
  75 #define GET_H_IE() CPU (h_ie)
  76 #define SET_H_IE(x) (CPU (h_ie) = (x))
  77   /* bie */
  78   UBI h_bie;
  79 #define GET_H_BIE() CPU (h_bie)
  80 #define SET_H_BIE(x) (CPU (h_bie) = (x))
  81   /* bcond */
  82   UBI h_bcond;
  83 #define GET_H_BCOND() CPU (h_bcond)
  84 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
  85   /* bpc */
  86   SI h_bpc;
  87 #define GET_H_BPC() CPU (h_bpc)
  88 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
  89   } hardware;
  90 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  91   /* CPU profiling state information.  */
  92   struct {
  93   /* general registers */
  94   unsigned long h_gr;
  95   } profile;
  96 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
  97 } M32RX_CPU_DATA;
  98
  99 /* FIXME: length parm to decode() is currently unneeded.  */
 100 extern DECODE *m32rx_decode (SIM_CPU *, insn_t /*, int*/);
 101
 102 /* The ARGBUF struct.  */
 103 struct argbuf {
 104   /* These are the baseclass definitions.  */
 105   unsigned int length;
 106   PCADDR addr;
 107   const struct cgen_insn *opcode;
 108   /* unsigned long insn; - no longer needed */
 109   /* cpu specific data follows */
 110   union {
 111     struct { /* e.g. add $dr,$sr */
 112       UINT f_r1;
 113       UINT f_r2;
 114     } fmt_0_add;
 115     struct { /* e.g. add3 $dr,$sr,#$slo16 */
 116       UINT f_r1;
 117       UINT f_r2;
 118       HI f_simm16;
 119     } fmt_1_add3;
 120     struct { /* e.g. and3 $dr,$sr,#$uimm16 */
 121       UINT f_r1;
 122       UINT f_r2;
 123       USI f_uimm16;
 124     } fmt_2_and3;
 125     struct { /* e.g. or3 $dr,$sr,#$ulo16 */
 126       UINT f_r1;
 127       UINT f_r2;
 128       UHI f_uimm16;
 129     } fmt_3_or3;
 130     struct { /* e.g. addi $dr,#$simm8 */
 131       UINT f_r1;
 132       SI f_simm8;
 133     } fmt_4_addi;
 134     struct { /* e.g. addv3 $dr,$sr,#$simm16 */
 135       UINT f_r1;
 136       UINT f_r2;
 137       SI f_simm16;
 138     } fmt_5_addv3;
 139     struct { /* e.g. addx $dr,$sr */
 140       UINT f_r1;
 141       UINT f_r2;
 142     } fmt_6_addx;
 143     struct { /* e.g. bc $disp8 */
 144       IADDR f_disp8;
 145     } fmt_7_bc8;
 146     struct { /* e.g. bc $disp24 */
 147       IADDR f_disp24;
 148     } fmt_8_bc24;
 149     struct { /* e.g. beq $src1,$src2,$disp16 */
 150       UINT f_r1;
 151       UINT f_r2;
 152       IADDR f_disp16;
 153     } fmt_9_beq;
 154     struct { /* e.g. beqz $src2,$disp16 */
 155       UINT f_r2;
 156       IADDR f_disp16;
 157     } fmt_10_beqz;
 158     struct { /* e.g. bl $disp8 */
 159       IADDR f_disp8;
 160     } fmt_11_bl8;
 161     struct { /* e.g. bl $disp24 */
 162       IADDR f_disp24;
 163     } fmt_12_bl24;
 164     struct { /* e.g. bcl $disp8 */
 165       IADDR f_disp8;
 166     } fmt_13_bcl8;
 167     struct { /* e.g. bcl $disp24 */
 168       IADDR f_disp24;
 169     } fmt_14_bcl24;
 170     struct { /* e.g. bra $disp8 */
 171       IADDR f_disp8;
 172     } fmt_15_bra8;
 173     struct { /* e.g. bra $disp24 */
 174       IADDR f_disp24;
 175     } fmt_16_bra24;
 176     struct { /* e.g. cmp $src1,$src2 */
 177       UINT f_r1;
 178       UINT f_r2;
 179     } fmt_17_cmp;
 180     struct { /* e.g. cmpi $src2,#$simm16 */
 181       UINT f_r2;
 182       SI f_simm16;
 183     } fmt_18_cmpi;
 184     struct { /* e.g. cmpui $src2,#$uimm16 */
 185       UINT f_r2;
 186       USI f_uimm16;
 187     } fmt_19_cmpui;
 188     struct { /* e.g. cmpz $src2 */
 189       UINT f_r2;
 190     } fmt_20_cmpz;
 191     struct { /* e.g. div $dr,$sr */
 192       UINT f_r1;
 193       UINT f_r2;
 194     } fmt_21_div;
 195     struct { /* e.g. jc $sr */
 196       UINT f_r2;
 197     } fmt_22_jc;
 198     struct { /* e.g. jl $sr */
 199       UINT f_r2;
 200     } fmt_23_jl;
 201     struct { /* e.g. jmp $sr */
 202       UINT f_r2;
 203     } fmt_24_jmp;
 204     struct { /* e.g. ld $dr,@$sr */
 205       UINT f_r1;
 206       UINT f_r2;
 207     } fmt_25_ld;
 208     struct { /* e.g. ld $dr,@($slo16,$sr) */
 209       UINT f_r1;
 210       UINT f_r2;
 211       HI f_simm16;
 212     } fmt_26_ld_d;
 213     struct { /* e.g. ldb $dr,@$sr */
 214       UINT f_r1;
 215       UINT f_r2;
 216     } fmt_27_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       UINT f_r1;
 219       UINT f_r2;
 220       HI f_simm16;
 221     } fmt_28_ldb_d;
 222     struct { /* e.g. ldh $dr,@$sr */
 223       UINT f_r1;
 224       UINT f_r2;
 225     } fmt_29_ldh;
 226     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 227       UINT f_r1;
 228       UINT f_r2;
 229       HI f_simm16;
 230     } fmt_30_ldh_d;
 231     struct { /* e.g. ld24 $dr,#$uimm24 */
 232       UINT f_r1;
 233       ADDR f_uimm24;
 234     } fmt_31_ld24;
 235     struct { /* e.g. ldi $dr,#$simm8 */
 236       UINT f_r1;
 237       SI f_simm8;
 238     } fmt_32_ldi8;
 239     struct { /* e.g. ldi $dr,$slo16 */
 240       UINT f_r1;
 241       HI f_simm16;
 242     } fmt_33_ldi16;
 243     struct { /* e.g. machi $src1,$src2 */
 244       UINT f_r1;
 245       UINT f_r2;
 246     } fmt_34_machi;
 247     struct { /* e.g. machi $src1,$src2,$acc */
 248       UINT f_r1;
 249       UINT f_acc;
 250       UINT f_r2;
 251     } fmt_35_machi_a;
 252     struct { /* e.g. mulhi $src1,$src2,$acc */
 253       UINT f_r1;
 254       UINT f_acc;
 255       UINT f_r2;
 256     } fmt_36_mulhi_a;
 257     struct { /* e.g. mv $dr,$sr */
 258       UINT f_r1;
 259       UINT f_r2;
 260     } fmt_37_mv;
 261     struct { /* e.g. mvfachi $dr */
 262       UINT f_r1;
 263     } fmt_38_mvfachi;
 264     struct { /* e.g. mvfachi $dr,$accs */
 265       UINT f_r1;
 266       UINT f_accs;
 267     } fmt_39_mvfachi_a;
 268     struct { /* e.g. mvfc $dr,$scr */
 269       UINT f_r1;
 270       UINT f_r2;
 271     } fmt_40_mvfc;
 272     struct { /* e.g. mvtachi $src1 */
 273       UINT f_r1;
 274     } fmt_41_mvtachi;
 275     struct { /* e.g. mvtachi $src1,$accs */
 276       UINT f_r1;
 277       UINT f_accs;
 278     } fmt_42_mvtachi_a;
 279     struct { /* e.g. mvtc $sr,$dcr */
 280       UINT f_r1;
 281       UINT f_r2;
 282     } fmt_43_mvtc;
 283     struct { /* e.g. nop */
 284       int empty;
 285     } fmt_44_nop;
 286     struct { /* e.g. rac */
 287       int empty;
 288     } fmt_45_rac;
 289     struct { /* e.g. rac $accs */
 290       UINT f_accs;
 291     } fmt_46_rac_a;
 292     struct { /* e.g. seth $dr,$hi16 */
 293       UINT f_r1;
 294       UHI f_hi16;
 295     } fmt_47_seth;
 296     struct { /* e.g. slli $dr,#$uimm5 */
 297       UINT f_r1;
 298       USI f_uimm5;
 299     } fmt_48_slli;
 300     struct { /* e.g. st $src1,@($slo16,$src2) */
 301       UINT f_r1;
 302       UINT f_r2;
 303       HI f_simm16;
 304     } fmt_49_st_d;
 305     struct { /* e.g. trap #$uimm4 */
 306       USI f_uimm4;
 307     } fmt_50_trap;
 308     struct { /* e.g. satb $dr,$src2 */
 309       UINT f_r1;
 310       UINT f_r2;
 311     } fmt_51_satb;
 312     struct { /* e.g. pcmpbz $src2 */
 313       UINT f_r2;
 314     } fmt_52_pcmpbz;
 315     struct { /* e.g. sadd */
 316       int empty;
 317     } fmt_53_sadd;
 318     struct { /* e.g. macwu1 $src1,$src2 */
 319       UINT f_r1;
 320       UINT f_r2;
 321     } fmt_54_macwu1;
 322     struct { /* e.g. sc */
 323       int empty;
 324     } fmt_55_sc;
 325   } fields;
 326 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
 327   unsigned long h_gr_get;
 328   unsigned long h_gr_set;
 329 #endif
 330 };
 331
 332 /* A cached insn.
 333    This is also used in the non-scache case.  In this situation we assume
 334    the cache size is 1, and do a few things a little differently.  */
 335
 336 struct scache {
 337   IADDR next;
 338   union {
 339 #if ! WITH_SEM_SWITCH_FULL
 340     SEMANTIC_FN *sem_fn;
 341 #endif
 342 #if ! WITH_SEM_SWITCH_FAST
 343 #if WITH_SCACHE
 344     SEMANTIC_CACHE_FN *sem_fast_fn;
 345 #else
 346     SEMANTIC_FN *sem_fast_fn;
 347 #endif
 348 #endif
 349 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 350 #ifdef __GNUC__
 351     void *sem_case;
 352 #else
 353     int sem_case;
 354 #endif
 355 #endif
 356   } semantic;
 357   struct argbuf argbuf;
 358 };
 359
 360 /* Macros to simplify extraction, reading and semantic code.
 361    These define and assign the local vars that contain the insn's fields.  */
 362
 363 #define EXTRACT_FMT_0_ADD_VARS \
 364   /* Instruction fields.  */ \
 365   UINT f_op1; \
 366   UINT f_r1; \
 367   UINT f_op2; \
 368   UINT f_r2; \
 369   unsigned int length;
 370 #define EXTRACT_FMT_0_ADD_CODE \
 371   length = 2; \
 372   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 373   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 374   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 375   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 376
 377 #define EXTRACT_FMT_1_ADD3_VARS \
 378   /* Instruction fields.  */ \
 379   UINT f_op1; \
 380   UINT f_r1; \
 381   UINT f_op2; \
 382   UINT f_r2; \
 383   int f_simm16; \
 384   unsigned int length;
 385 #define EXTRACT_FMT_1_ADD3_CODE \
 386   length = 4; \
 387   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 388   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 389   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 390   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 391   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 392
 393 #define EXTRACT_FMT_2_AND3_VARS \
 394   /* Instruction fields.  */ \
 395   UINT f_op1; \
 396   UINT f_r1; \
 397   UINT f_op2; \
 398   UINT f_r2; \
 399   UINT f_uimm16; \
 400   unsigned int length;
 401 #define EXTRACT_FMT_2_AND3_CODE \
 402   length = 4; \
 403   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 404   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 405   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 406   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 407   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 408
 409 #define EXTRACT_FMT_3_OR3_VARS \
 410   /* Instruction fields.  */ \
 411   UINT f_op1; \
 412   UINT f_r1; \
 413   UINT f_op2; \
 414   UINT f_r2; \
 415   UINT f_uimm16; \
 416   unsigned int length;
 417 #define EXTRACT_FMT_3_OR3_CODE \
 418   length = 4; \
 419   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 420   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 421   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 422   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 423   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 424
 425 #define EXTRACT_FMT_4_ADDI_VARS \
 426   /* Instruction fields.  */ \
 427   UINT f_op1; \
 428   UINT f_r1; \
 429   int f_simm8; \
 430   unsigned int length;
 431 #define EXTRACT_FMT_4_ADDI_CODE \
 432   length = 2; \
 433   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 434   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 435   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 436
 437 #define EXTRACT_FMT_5_ADDV3_VARS \
 438   /* Instruction fields.  */ \
 439   UINT f_op1; \
 440   UINT f_r1; \
 441   UINT f_op2; \
 442   UINT f_r2; \
 443   int f_simm16; \
 444   unsigned int length;
 445 #define EXTRACT_FMT_5_ADDV3_CODE \
 446   length = 4; \
 447   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 448   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 449   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 450   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 451   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 452
 453 #define EXTRACT_FMT_6_ADDX_VARS \
 454   /* Instruction fields.  */ \
 455   UINT f_op1; \
 456   UINT f_r1; \
 457   UINT f_op2; \
 458   UINT f_r2; \
 459   unsigned int length;
 460 #define EXTRACT_FMT_6_ADDX_CODE \
 461   length = 2; \
 462   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 463   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 464   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 465   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 466
 467 #define EXTRACT_FMT_7_BC8_VARS \
 468   /* Instruction fields.  */ \
 469   UINT f_op1; \
 470   UINT f_r1; \
 471   int f_disp8; \
 472   unsigned int length;
 473 #define EXTRACT_FMT_7_BC8_CODE \
 474   length = 2; \
 475   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 476   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 477   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 478
 479 #define EXTRACT_FMT_8_BC24_VARS \
 480   /* Instruction fields.  */ \
 481   UINT f_op1; \
 482   UINT f_r1; \
 483   int f_disp24; \
 484   unsigned int length;
 485 #define EXTRACT_FMT_8_BC24_CODE \
 486   length = 4; \
 487   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 488   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 489   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 490
 491 #define EXTRACT_FMT_9_BEQ_VARS \
 492   /* Instruction fields.  */ \
 493   UINT f_op1; \
 494   UINT f_r1; \
 495   UINT f_op2; \
 496   UINT f_r2; \
 497   int f_disp16; \
 498   unsigned int length;
 499 #define EXTRACT_FMT_9_BEQ_CODE \
 500   length = 4; \
 501   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 502   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 503   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 504   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 505   f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
 506
 507 #define EXTRACT_FMT_10_BEQZ_VARS \
 508   /* Instruction fields.  */ \
 509   UINT f_op1; \
 510   UINT f_r1; \
 511   UINT f_op2; \
 512   UINT f_r2; \
 513   int f_disp16; \
 514   unsigned int length;
 515 #define EXTRACT_FMT_10_BEQZ_CODE \
 516   length = 4; \
 517   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 518   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 519   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 520   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 521   f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
 522
 523 #define EXTRACT_FMT_11_BL8_VARS \
 524   /* Instruction fields.  */ \
 525   UINT f_op1; \
 526   UINT f_r1; \
 527   int f_disp8; \
 528   unsigned int length;
 529 #define EXTRACT_FMT_11_BL8_CODE \
 530   length = 2; \
 531   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 532   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 533   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 534
 535 #define EXTRACT_FMT_12_BL24_VARS \
 536   /* Instruction fields.  */ \
 537   UINT f_op1; \
 538   UINT f_r1; \
 539   int f_disp24; \
 540   unsigned int length;
 541 #define EXTRACT_FMT_12_BL24_CODE \
 542   length = 4; \
 543   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 544   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 545   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 546
 547 #define EXTRACT_FMT_13_BCL8_VARS \
 548   /* Instruction fields.  */ \
 549   UINT f_op1; \
 550   UINT f_r1; \
 551   int f_disp8; \
 552   unsigned int length;
 553 #define EXTRACT_FMT_13_BCL8_CODE \
 554   length = 2; \
 555   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 556   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 557   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 558
 559 #define EXTRACT_FMT_14_BCL24_VARS \
 560   /* Instruction fields.  */ \
 561   UINT f_op1; \
 562   UINT f_r1; \
 563   int f_disp24; \
 564   unsigned int length;
 565 #define EXTRACT_FMT_14_BCL24_CODE \
 566   length = 4; \
 567   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 568   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 569   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 570
 571 #define EXTRACT_FMT_15_BRA8_VARS \
 572   /* Instruction fields.  */ \
 573   UINT f_op1; \
 574   UINT f_r1; \
 575   int f_disp8; \
 576   unsigned int length;
 577 #define EXTRACT_FMT_15_BRA8_CODE \
 578   length = 2; \
 579   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 580   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 581   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 582
 583 #define EXTRACT_FMT_16_BRA24_VARS \
 584   /* Instruction fields.  */ \
 585   UINT f_op1; \
 586   UINT f_r1; \
 587   int f_disp24; \
 588   unsigned int length;
 589 #define EXTRACT_FMT_16_BRA24_CODE \
 590   length = 4; \
 591   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 592   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 593   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 594
 595 #define EXTRACT_FMT_17_CMP_VARS \
 596   /* Instruction fields.  */ \
 597   UINT f_op1; \
 598   UINT f_r1; \
 599   UINT f_op2; \
 600   UINT f_r2; \
 601   unsigned int length;
 602 #define EXTRACT_FMT_17_CMP_CODE \
 603   length = 2; \
 604   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 605   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 606   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 607   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 608
 609 #define EXTRACT_FMT_18_CMPI_VARS \
 610   /* Instruction fields.  */ \
 611   UINT f_op1; \
 612   UINT f_r1; \
 613   UINT f_op2; \
 614   UINT f_r2; \
 615   int f_simm16; \
 616   unsigned int length;
 617 #define EXTRACT_FMT_18_CMPI_CODE \
 618   length = 4; \
 619   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 620   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 621   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 622   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 623   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 624
 625 #define EXTRACT_FMT_19_CMPUI_VARS \
 626   /* Instruction fields.  */ \
 627   UINT f_op1; \
 628   UINT f_r1; \
 629   UINT f_op2; \
 630   UINT f_r2; \
 631   UINT f_uimm16; \
 632   unsigned int length;
 633 #define EXTRACT_FMT_19_CMPUI_CODE \
 634   length = 4; \
 635   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 636   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 637   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 638   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 639   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 640
 641 #define EXTRACT_FMT_20_CMPZ_VARS \
 642   /* Instruction fields.  */ \
 643   UINT f_op1; \
 644   UINT f_r1; \
 645   UINT f_op2; \
 646   UINT f_r2; \
 647   unsigned int length;
 648 #define EXTRACT_FMT_20_CMPZ_CODE \
 649   length = 2; \
 650   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 651   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 652   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 653   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 654
 655 #define EXTRACT_FMT_21_DIV_VARS \
 656   /* Instruction fields.  */ \
 657   UINT f_op1; \
 658   UINT f_r1; \
 659   UINT f_op2; \
 660   UINT f_r2; \
 661   int f_simm16; \
 662   unsigned int length;
 663 #define EXTRACT_FMT_21_DIV_CODE \
 664   length = 4; \
 665   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 666   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 667   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 668   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 669   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 670
 671 #define EXTRACT_FMT_22_JC_VARS \
 672   /* Instruction fields.  */ \
 673   UINT f_op1; \
 674   UINT f_r1; \
 675   UINT f_op2; \
 676   UINT f_r2; \
 677   unsigned int length;
 678 #define EXTRACT_FMT_22_JC_CODE \
 679   length = 2; \
 680   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 681   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 682   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 683   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 684
 685 #define EXTRACT_FMT_23_JL_VARS \
 686   /* Instruction fields.  */ \
 687   UINT f_op1; \
 688   UINT f_r1; \
 689   UINT f_op2; \
 690   UINT f_r2; \
 691   unsigned int length;
 692 #define EXTRACT_FMT_23_JL_CODE \
 693   length = 2; \
 694   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 695   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 696   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 697   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 698
 699 #define EXTRACT_FMT_24_JMP_VARS \
 700   /* Instruction fields.  */ \
 701   UINT f_op1; \
 702   UINT f_r1; \
 703   UINT f_op2; \
 704   UINT f_r2; \
 705   unsigned int length;
 706 #define EXTRACT_FMT_24_JMP_CODE \
 707   length = 2; \
 708   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 709   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 710   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 711   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 712
 713 #define EXTRACT_FMT_25_LD_VARS \
 714   /* Instruction fields.  */ \
 715   UINT f_op1; \
 716   UINT f_r1; \
 717   UINT f_op2; \
 718   UINT f_r2; \
 719   unsigned int length;
 720 #define EXTRACT_FMT_25_LD_CODE \
 721   length = 2; \
 722   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 723   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 724   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 725   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 726
 727 #define EXTRACT_FMT_26_LD_D_VARS \
 728   /* Instruction fields.  */ \
 729   UINT f_op1; \
 730   UINT f_r1; \
 731   UINT f_op2; \
 732   UINT f_r2; \
 733   int f_simm16; \
 734   unsigned int length;
 735 #define EXTRACT_FMT_26_LD_D_CODE \
 736   length = 4; \
 737   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 738   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 739   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 740   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 741   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 742
 743 #define EXTRACT_FMT_27_LDB_VARS \
 744   /* Instruction fields.  */ \
 745   UINT f_op1; \
 746   UINT f_r1; \
 747   UINT f_op2; \
 748   UINT f_r2; \
 749   unsigned int length;
 750 #define EXTRACT_FMT_27_LDB_CODE \
 751   length = 2; \
 752   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 753   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 754   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 755   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 756
 757 #define EXTRACT_FMT_28_LDB_D_VARS \
 758   /* Instruction fields.  */ \
 759   UINT f_op1; \
 760   UINT f_r1; \
 761   UINT f_op2; \
 762   UINT f_r2; \
 763   int f_simm16; \
 764   unsigned int length;
 765 #define EXTRACT_FMT_28_LDB_D_CODE \
 766   length = 4; \
 767   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 768   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 769   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 770   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 771   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 772
 773 #define EXTRACT_FMT_29_LDH_VARS \
 774   /* Instruction fields.  */ \
 775   UINT f_op1; \
 776   UINT f_r1; \
 777   UINT f_op2; \
 778   UINT f_r2; \
 779   unsigned int length;
 780 #define EXTRACT_FMT_29_LDH_CODE \
 781   length = 2; \
 782   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 783   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 784   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 785   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 786
 787 #define EXTRACT_FMT_30_LDH_D_VARS \
 788   /* Instruction fields.  */ \
 789   UINT f_op1; \
 790   UINT f_r1; \
 791   UINT f_op2; \
 792   UINT f_r2; \
 793   int f_simm16; \
 794   unsigned int length;
 795 #define EXTRACT_FMT_30_LDH_D_CODE \
 796   length = 4; \
 797   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 798   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 799   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 800   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 801   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 802
 803 #define EXTRACT_FMT_31_LD24_VARS \
 804   /* Instruction fields.  */ \
 805   UINT f_op1; \
 806   UINT f_r1; \
 807   UINT f_uimm24; \
 808   unsigned int length;
 809 #define EXTRACT_FMT_31_LD24_CODE \
 810   length = 4; \
 811   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 812   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 813   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 814
 815 #define EXTRACT_FMT_32_LDI8_VARS \
 816   /* Instruction fields.  */ \
 817   UINT f_op1; \
 818   UINT f_r1; \
 819   int f_simm8; \
 820   unsigned int length;
 821 #define EXTRACT_FMT_32_LDI8_CODE \
 822   length = 2; \
 823   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 824   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 825   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 826
 827 #define EXTRACT_FMT_33_LDI16_VARS \
 828   /* Instruction fields.  */ \
 829   UINT f_op1; \
 830   UINT f_r1; \
 831   UINT f_op2; \
 832   UINT f_r2; \
 833   int f_simm16; \
 834   unsigned int length;
 835 #define EXTRACT_FMT_33_LDI16_CODE \
 836   length = 4; \
 837   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 838   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 839   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 840   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 841   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 842
 843 #define EXTRACT_FMT_34_MACHI_VARS \
 844   /* Instruction fields.  */ \
 845   UINT f_op1; \
 846   UINT f_r1; \
 847   UINT f_op2; \
 848   UINT f_r2; \
 849   unsigned int length;
 850 #define EXTRACT_FMT_34_MACHI_CODE \
 851   length = 2; \
 852   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 853   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 854   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 855   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 856
 857 #define EXTRACT_FMT_35_MACHI_A_VARS \
 858   /* Instruction fields.  */ \
 859   UINT f_op1; \
 860   UINT f_r1; \
 861   UINT f_acc; \
 862   UINT f_op23; \
 863   UINT f_r2; \
 864   unsigned int length;
 865 #define EXTRACT_FMT_35_MACHI_A_CODE \
 866   length = 2; \
 867   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 868   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 869   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 870   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 871   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 872
 873 #define EXTRACT_FMT_36_MULHI_A_VARS \
 874   /* Instruction fields.  */ \
 875   UINT f_op1; \
 876   UINT f_r1; \
 877   UINT f_acc; \
 878   UINT f_op23; \
 879   UINT f_r2; \
 880   unsigned int length;
 881 #define EXTRACT_FMT_36_MULHI_A_CODE \
 882   length = 2; \
 883   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 884   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 885   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 886   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 887   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 888
 889 #define EXTRACT_FMT_37_MV_VARS \
 890   /* Instruction fields.  */ \
 891   UINT f_op1; \
 892   UINT f_r1; \
 893   UINT f_op2; \
 894   UINT f_r2; \
 895   unsigned int length;
 896 #define EXTRACT_FMT_37_MV_CODE \
 897   length = 2; \
 898   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 899   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 900   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 901   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 902
 903 #define EXTRACT_FMT_38_MVFACHI_VARS \
 904   /* Instruction fields.  */ \
 905   UINT f_op1; \
 906   UINT f_r1; \
 907   UINT f_op2; \
 908   UINT f_r2; \
 909   unsigned int length;
 910 #define EXTRACT_FMT_38_MVFACHI_CODE \
 911   length = 2; \
 912   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 913   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 914   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 915   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 916
 917 #define EXTRACT_FMT_39_MVFACHI_A_VARS \
 918   /* Instruction fields.  */ \
 919   UINT f_op1; \
 920   UINT f_r1; \
 921   UINT f_op2; \
 922   UINT f_accs; \
 923   UINT f_op3; \
 924   unsigned int length;
 925 #define EXTRACT_FMT_39_MVFACHI_A_CODE \
 926   length = 2; \
 927   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 928   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 929   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 930   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
 931   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 932
 933 #define EXTRACT_FMT_40_MVFC_VARS \
 934   /* Instruction fields.  */ \
 935   UINT f_op1; \
 936   UINT f_r1; \
 937   UINT f_op2; \
 938   UINT f_r2; \
 939   unsigned int length;
 940 #define EXTRACT_FMT_40_MVFC_CODE \
 941   length = 2; \
 942   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 943   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 944   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 945   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 946
 947 #define EXTRACT_FMT_41_MVTACHI_VARS \
 948   /* Instruction fields.  */ \
 949   UINT f_op1; \
 950   UINT f_r1; \
 951   UINT f_op2; \
 952   UINT f_r2; \
 953   unsigned int length;
 954 #define EXTRACT_FMT_41_MVTACHI_CODE \
 955   length = 2; \
 956   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 957   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 958   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 959   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 960
 961 #define EXTRACT_FMT_42_MVTACHI_A_VARS \
 962   /* Instruction fields.  */ \
 963   UINT f_op1; \
 964   UINT f_r1; \
 965   UINT f_op2; \
 966   UINT f_accs; \
 967   UINT f_op3; \
 968   unsigned int length;
 969 #define EXTRACT_FMT_42_MVTACHI_A_CODE \
 970   length = 2; \
 971   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 972   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 973   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 974   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
 975   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
 976
 977 #define EXTRACT_FMT_43_MVTC_VARS \
 978   /* Instruction fields.  */ \
 979   UINT f_op1; \
 980   UINT f_r1; \
 981   UINT f_op2; \
 982   UINT f_r2; \
 983   unsigned int length;
 984 #define EXTRACT_FMT_43_MVTC_CODE \
 985   length = 2; \
 986   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 987   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 988   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 989   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 990
 991 #define EXTRACT_FMT_44_NOP_VARS \
 992   /* Instruction fields.  */ \
 993   UINT f_op1; \
 994   UINT f_r1; \
 995   UINT f_op2; \
 996   UINT f_r2; \
 997   unsigned int length;
 998 #define EXTRACT_FMT_44_NOP_CODE \
 999   length = 2; \
1000   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1001   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1002   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1003   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1004
1005 #define EXTRACT_FMT_45_RAC_VARS \
1006   /* Instruction fields.  */ \
1007   UINT f_op1; \
1008   UINT f_r1; \
1009   UINT f_op2; \
1010   UINT f_r2; \
1011   unsigned int length;
1012 #define EXTRACT_FMT_45_RAC_CODE \
1013   length = 2; \
1014   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1015   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1016   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1017   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1018
1019 #define EXTRACT_FMT_46_RAC_A_VARS \
1020   /* Instruction fields.  */ \
1021   UINT f_op1; \
1022   UINT f_r1; \
1023   UINT f_op2; \
1024   UINT f_accs; \
1025   UINT f_op3; \
1026   unsigned int length;
1027 #define EXTRACT_FMT_46_RAC_A_CODE \
1028   length = 2; \
1029   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1030   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1031   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1032   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1033   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1034
1035 #define EXTRACT_FMT_47_SETH_VARS \
1036   /* Instruction fields.  */ \
1037   UINT f_op1; \
1038   UINT f_r1; \
1039   UINT f_op2; \
1040   UINT f_r2; \
1041   UINT f_hi16; \
1042   unsigned int length;
1043 #define EXTRACT_FMT_47_SETH_CODE \
1044   length = 4; \
1045   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1046   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1047   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1048   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1049   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1050
1051 #define EXTRACT_FMT_48_SLLI_VARS \
1052   /* Instruction fields.  */ \
1053   UINT f_op1; \
1054   UINT f_r1; \
1055   UINT f_shift_op2; \
1056   UINT f_uimm5; \
1057   unsigned int length;
1058 #define EXTRACT_FMT_48_SLLI_CODE \
1059   length = 2; \
1060   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1061   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1062   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1063   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1064
1065 #define EXTRACT_FMT_49_ST_D_VARS \
1066   /* Instruction fields.  */ \
1067   UINT f_op1; \
1068   UINT f_r1; \
1069   UINT f_op2; \
1070   UINT f_r2; \
1071   int f_simm16; \
1072   unsigned int length;
1073 #define EXTRACT_FMT_49_ST_D_CODE \
1074   length = 4; \
1075   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1076   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1077   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1078   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1079   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1080
1081 #define EXTRACT_FMT_50_TRAP_VARS \
1082   /* Instruction fields.  */ \
1083   UINT f_op1; \
1084   UINT f_r1; \
1085   UINT f_op2; \
1086   UINT f_uimm4; \
1087   unsigned int length;
1088 #define EXTRACT_FMT_50_TRAP_CODE \
1089   length = 2; \
1090   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1091   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1092   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1093   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1094
1095 #define EXTRACT_FMT_51_SATB_VARS \
1096   /* Instruction fields.  */ \
1097   UINT f_op1; \
1098   UINT f_r1; \
1099   UINT f_op2; \
1100   UINT f_r2; \
1101   UINT f_uimm16; \
1102   unsigned int length;
1103 #define EXTRACT_FMT_51_SATB_CODE \
1104   length = 4; \
1105   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1106   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1107   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1108   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1109   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1110
1111 #define EXTRACT_FMT_52_PCMPBZ_VARS \
1112   /* Instruction fields.  */ \
1113   UINT f_op1; \
1114   UINT f_r1; \
1115   UINT f_op2; \
1116   UINT f_r2; \
1117   unsigned int length;
1118 #define EXTRACT_FMT_52_PCMPBZ_CODE \
1119   length = 2; \
1120   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1121   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1122   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1123   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1124
1125 #define EXTRACT_FMT_53_SADD_VARS \
1126   /* Instruction fields.  */ \
1127   UINT f_op1; \
1128   UINT f_r1; \
1129   UINT f_op2; \
1130   UINT f_r2; \
1131   unsigned int length;
1132 #define EXTRACT_FMT_53_SADD_CODE \
1133   length = 2; \
1134   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1135   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1136   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1137   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1138
1139 #define EXTRACT_FMT_54_MACWU1_VARS \
1140   /* Instruction fields.  */ \
1141   UINT f_op1; \
1142   UINT f_r1; \
1143   UINT f_op2; \
1144   UINT f_r2; \
1145   unsigned int length;
1146 #define EXTRACT_FMT_54_MACWU1_CODE \
1147   length = 2; \
1148   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1149   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1150   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1151   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1152
1153 #define EXTRACT_FMT_55_SC_VARS \
1154   /* Instruction fields.  */ \
1155   UINT f_op1; \
1156   UINT f_r1; \
1157   UINT f_op2; \
1158   UINT f_r2; \
1159   unsigned int length;
1160 #define EXTRACT_FMT_55_SC_CODE \
1161   length = 2; \
1162   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1163   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1164   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1165   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1166
1167 /* Fetched input values of an instruction.  */
1168
1169 struct parallel_exec {
1170   union {
1171     struct { /* e.g. add $dr,$sr */
1172       SI dr;
1173       SI sr;
1174     } fmt_0_add;
1175     struct { /* e.g. add3 $dr,$sr,#$slo16 */
1176       HI slo16;
1177       SI sr;
1178     } fmt_1_add3;
1179     struct { /* e.g. and3 $dr,$sr,#$uimm16 */
1180       SI sr;
1181       USI uimm16;
1182     } fmt_2_and3;
1183     struct { /* e.g. or3 $dr,$sr,#$ulo16 */
1184       SI sr;
1185       UHI ulo16;
1186     } fmt_3_or3;
1187     struct { /* e.g. addi $dr,#$simm8 */
1188       SI dr;
1189       SI simm8;
1190     } fmt_4_addi;
1191     struct { /* e.g. addv3 $dr,$sr,#$simm16 */
1192       SI simm16;
1193       SI sr;
1194     } fmt_5_addv3;
1195     struct { /* e.g. addx $dr,$sr */
1196       UBI condbit;
1197       SI dr;
1198       SI sr;
1199     } fmt_6_addx;
1200     struct { /* e.g. bc $disp8 */
1201       UBI condbit;
1202       IADDR disp8;
1203     } fmt_7_bc8;
1204     struct { /* e.g. bc $disp24 */
1205       UBI condbit;
1206       IADDR disp24;
1207     } fmt_8_bc24;
1208     struct { /* e.g. beq $src1,$src2,$disp16 */
1209       IADDR disp16;
1210       SI src1;
1211       SI src2;
1212     } fmt_9_beq;
1213     struct { /* e.g. beqz $src2,$disp16 */
1214       IADDR disp16;
1215       SI src2;
1216     } fmt_10_beqz;
1217     struct { /* e.g. bl $disp8 */
1218       IADDR disp8;
1219       USI pc;
1220     } fmt_11_bl8;
1221     struct { /* e.g. bl $disp24 */
1222       IADDR disp24;
1223       USI pc;
1224     } fmt_12_bl24;
1225     struct { /* e.g. bcl $disp8 */
1226       UBI condbit;
1227       IADDR disp8;
1228       USI pc;
1229     } fmt_13_bcl8;
1230     struct { /* e.g. bcl $disp24 */
1231       UBI condbit;
1232       IADDR disp24;
1233       USI pc;
1234     } fmt_14_bcl24;
1235     struct { /* e.g. bra $disp8 */
1236       IADDR disp8;
1237     } fmt_15_bra8;
1238     struct { /* e.g. bra $disp24 */
1239       IADDR disp24;
1240     } fmt_16_bra24;
1241     struct { /* e.g. cmp $src1,$src2 */
1242       SI src1;
1243       SI src2;
1244     } fmt_17_cmp;
1245     struct { /* e.g. cmpi $src2,#$simm16 */
1246       SI simm16;
1247       SI src2;
1248     } fmt_18_cmpi;
1249     struct { /* e.g. cmpui $src2,#$uimm16 */
1250       SI src2;
1251       USI uimm16;
1252     } fmt_19_cmpui;
1253     struct { /* e.g. cmpz $src2 */
1254       SI src2;
1255     } fmt_20_cmpz;
1256     struct { /* e.g. div $dr,$sr */
1257       SI dr;
1258       SI sr;
1259     } fmt_21_div;
1260     struct { /* e.g. jc $sr */
1261       UBI condbit;
1262       SI sr;
1263     } fmt_22_jc;
1264     struct { /* e.g. jl $sr */
1265       USI pc;
1266       SI sr;
1267     } fmt_23_jl;
1268     struct { /* e.g. jmp $sr */
1269       SI sr;
1270     } fmt_24_jmp;
1271     struct { /* e.g. ld $dr,@$sr */
1272       UQI h_memory;
1273       SI sr;
1274     } fmt_25_ld;
1275     struct { /* e.g. ld $dr,@($slo16,$sr) */
1276       UQI h_memory;
1277       HI slo16;
1278       SI sr;
1279     } fmt_26_ld_d;
1280     struct { /* e.g. ldb $dr,@$sr */
1281       UQI h_memory;
1282       SI sr;
1283     } fmt_27_ldb;
1284     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1285       UQI h_memory;
1286       HI slo16;
1287       SI sr;
1288     } fmt_28_ldb_d;
1289     struct { /* e.g. ldh $dr,@$sr */
1290       UQI h_memory;
1291       SI sr;
1292     } fmt_29_ldh;
1293     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1294       UQI h_memory;
1295       HI slo16;
1296       SI sr;
1297     } fmt_30_ldh_d;
1298     struct { /* e.g. ld24 $dr,#$uimm24 */
1299       ADDR uimm24;
1300     } fmt_31_ld24;
1301     struct { /* e.g. ldi $dr,#$simm8 */
1302       SI simm8;
1303     } fmt_32_ldi8;
1304     struct { /* e.g. ldi $dr,$slo16 */
1305       HI slo16;
1306     } fmt_33_ldi16;
1307     struct { /* e.g. machi $src1,$src2 */
1308       DI accum;
1309       SI src1;
1310       SI src2;
1311     } fmt_34_machi;
1312     struct { /* e.g. machi $src1,$src2,$acc */
1313       DI acc;
1314       SI src1;
1315       SI src2;
1316     } fmt_35_machi_a;
1317     struct { /* e.g. mulhi $src1,$src2,$acc */
1318       SI src1;
1319       SI src2;
1320     } fmt_36_mulhi_a;
1321     struct { /* e.g. mv $dr,$sr */
1322       SI sr;
1323     } fmt_37_mv;
1324     struct { /* e.g. mvfachi $dr */
1325       DI accum;
1326     } fmt_38_mvfachi;
1327     struct { /* e.g. mvfachi $dr,$accs */
1328       DI accs;
1329     } fmt_39_mvfachi_a;
1330     struct { /* e.g. mvfc $dr,$scr */
1331       SI scr;
1332     } fmt_40_mvfc;
1333     struct { /* e.g. mvtachi $src1 */
1334       DI accum;
1335       SI src1;
1336     } fmt_41_mvtachi;
1337     struct { /* e.g. mvtachi $src1,$accs */
1338       DI accs;
1339       SI src1;
1340     } fmt_42_mvtachi_a;
1341     struct { /* e.g. mvtc $sr,$dcr */
1342       SI sr;
1343     } fmt_43_mvtc;
1344     struct { /* e.g. nop */
1345       int empty;
1346     } fmt_44_nop;
1347     struct { /* e.g. rac */
1348       DI accum;
1349     } fmt_45_rac;
1350     struct { /* e.g. rac $accs */
1351       DI accs;
1352     } fmt_46_rac_a;
1353     struct { /* e.g. seth $dr,$hi16 */
1354       UHI hi16;
1355     } fmt_47_seth;
1356     struct { /* e.g. slli $dr,#$uimm5 */
1357       SI dr;
1358       USI uimm5;
1359     } fmt_48_slli;
1360     struct { /* e.g. st $src1,@($slo16,$src2) */
1361       HI slo16;
1362       SI src1;
1363       SI src2;
1364     } fmt_49_st_d;
1365     struct { /* e.g. trap #$uimm4 */
1366       USI uimm4;
1367     } fmt_50_trap;
1368     struct { /* e.g. satb $dr,$src2 */
1369       int empty;
1370     } fmt_51_satb;
1371     struct { /* e.g. pcmpbz $src2 */
1372       int empty;
1373     } fmt_52_pcmpbz;
1374     struct { /* e.g. sadd */
1375       DI h_accums;
1376       DI h_accums;
1377     } fmt_53_sadd;
1378     struct { /* e.g. macwu1 $src1,$src2 */
1379       DI h_accums;
1380       SI src1;
1381       SI src2;
1382     } fmt_54_macwu1;
1383     struct { /* e.g. sc */
1384       UBI condbit;
1385     } fmt_55_sc;
1386   } operands;
1387 };
1388
1389 #endif /* CPU_M32RX_H */