sim/m32r/cpux.h

   1 /* CPU family header for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RXF_H
  26 #define CPU_M32RXF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RXF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rxf_h_pc_get (SIM_CPU *);
  89 void m32rxf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rxf_h_accum_get (SIM_CPU *);
  95 void m32rxf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rxf_h_cond_get (SIM_CPU *);
  99 void m32rxf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rxf_h_psw_get (SIM_CPU *);
 101 void m32rxf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rxf_h_bpsw_get (SIM_CPU *);
 103 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
 105 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rxf_h_lock_get (SIM_CPU *);
 107 void m32rxf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rxf_fetch_register;
 111 extern CPUREG_STORE_FN m32rxf_store_register;
 112
 113 typedef struct {
 114   int empty;
 115 } MODEL_M32RX_DATA;
 116
 117 /* The ARGBUF struct.  */
 118 struct argbuf {
 119   /* These are the baseclass definitions.  */
 120   PCADDR addr;
 121   const IDESC *idesc;
 122   char trace_p;
 123   char profile_p;
 124   /* cpu specific data follows */
 125   union sem semantic;
 126   int written;
 127   union {
 128     struct { /* empty format for unspecified field list */
 129       int empty;
 130     } fmt_empty;
 131     struct { /* e.g. add $dr,$sr */
 132       SI * i_dr;
 133       SI * i_sr;
 134       unsigned char in_dr;
 135       unsigned char in_sr;
 136       unsigned char out_dr;
 137     } fmt_add;
 138     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 139       INT f_simm16;
 140       SI * i_sr;
 141       SI * i_dr;
 142       unsigned char in_sr;
 143       unsigned char out_dr;
 144     } fmt_add3;
 145     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 146       UINT f_uimm16;
 147       SI * i_sr;
 148       SI * i_dr;
 149       unsigned char in_sr;
 150       unsigned char out_dr;
 151     } fmt_and3;
 152     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 153       UINT f_uimm16;
 154       SI * i_sr;
 155       SI * i_dr;
 156       unsigned char in_sr;
 157       unsigned char out_dr;
 158     } fmt_or3;
 159     struct { /* e.g. addi $dr,$simm8 */
 160       INT f_simm8;
 161       SI * i_dr;
 162       unsigned char in_dr;
 163       unsigned char out_dr;
 164     } fmt_addi;
 165     struct { /* e.g. addv $dr,$sr */
 166       SI * i_dr;
 167       SI * i_sr;
 168       unsigned char in_dr;
 169       unsigned char in_sr;
 170       unsigned char out_dr;
 171     } fmt_addv;
 172     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 173       INT f_simm16;
 174       SI * i_sr;
 175       SI * i_dr;
 176       unsigned char in_sr;
 177       unsigned char out_dr;
 178     } fmt_addv3;
 179     struct { /* e.g. addx $dr,$sr */
 180       SI * i_dr;
 181       SI * i_sr;
 182       unsigned char in_dr;
 183       unsigned char in_sr;
 184       unsigned char out_dr;
 185     } fmt_addx;
 186     struct { /* e.g. cmp $src1,$src2 */
 187       SI * i_src1;
 188       SI * i_src2;
 189       unsigned char in_src1;
 190       unsigned char in_src2;
 191     } fmt_cmp;
 192     struct { /* e.g. cmpi $src2,$simm16 */
 193       INT f_simm16;
 194       SI * i_src2;
 195       unsigned char in_src2;
 196     } fmt_cmpi;
 197     struct { /* e.g. cmpz $src2 */
 198       SI * i_src2;
 199       unsigned char in_src2;
 200     } fmt_cmpz;
 201     struct { /* e.g. div $dr,$sr */
 202       SI * i_sr;
 203       SI * i_dr;
 204       unsigned char in_sr;
 205       unsigned char in_dr;
 206       unsigned char out_dr;
 207     } fmt_div;
 208     struct { /* e.g. ld $dr,@$sr */
 209       SI * i_sr;
 210       SI * i_dr;
 211       unsigned char in_sr;
 212       unsigned char out_dr;
 213     } fmt_ld;
 214     struct { /* e.g. ld $dr,@($slo16,$sr) */
 215       INT f_simm16;
 216       SI * i_sr;
 217       SI * i_dr;
 218       unsigned char in_sr;
 219       unsigned char out_dr;
 220     } fmt_ld_d;
 221     struct { /* e.g. ldb $dr,@$sr */
 222       SI * i_sr;
 223       SI * i_dr;
 224       unsigned char in_sr;
 225       unsigned char out_dr;
 226     } fmt_ldb;
 227     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 228       INT f_simm16;
 229       SI * i_sr;
 230       SI * i_dr;
 231       unsigned char in_sr;
 232       unsigned char out_dr;
 233     } fmt_ldb_d;
 234     struct { /* e.g. ldh $dr,@$sr */
 235       SI * i_sr;
 236       SI * i_dr;
 237       unsigned char in_sr;
 238       unsigned char out_dr;
 239     } fmt_ldh;
 240     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 241       INT f_simm16;
 242       SI * i_sr;
 243       SI * i_dr;
 244       unsigned char in_sr;
 245       unsigned char out_dr;
 246     } fmt_ldh_d;
 247     struct { /* e.g. ld $dr,@$sr+ */
 248       SI * i_sr;
 249       SI * i_dr;
 250       unsigned char in_sr;
 251       unsigned char out_dr;
 252       unsigned char out_sr;
 253     } fmt_ld_plus;
 254     struct { /* e.g. ld24 $dr,$uimm24 */
 255       ADDR i_uimm24;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ld24;
 259     struct { /* e.g. ldi8 $dr,$simm8 */
 260       INT f_simm8;
 261       SI * i_dr;
 262       unsigned char out_dr;
 263     } fmt_ldi8;
 264     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 265       INT f_simm16;
 266       SI * i_dr;
 267       unsigned char out_dr;
 268     } fmt_ldi16;
 269     struct { /* e.g. lock $dr,@$sr */
 270       SI * i_sr;
 271       SI * i_dr;
 272       unsigned char in_sr;
 273       unsigned char out_dr;
 274     } fmt_lock;
 275     struct { /* e.g. machi $src1,$src2,$acc */
 276       UINT f_acc;
 277       SI * i_src1;
 278       SI * i_src2;
 279       unsigned char in_src1;
 280       unsigned char in_src2;
 281     } fmt_machi_a;
 282     struct { /* e.g. mulhi $src1,$src2,$acc */
 283       UINT f_acc;
 284       SI * i_src1;
 285       SI * i_src2;
 286       unsigned char in_src1;
 287       unsigned char in_src2;
 288     } fmt_mulhi_a;
 289     struct { /* e.g. mv $dr,$sr */
 290       SI * i_sr;
 291       SI * i_dr;
 292       unsigned char in_sr;
 293       unsigned char out_dr;
 294     } fmt_mv;
 295     struct { /* e.g. mvfachi $dr,$accs */
 296       UINT f_accs;
 297       SI * i_dr;
 298       unsigned char out_dr;
 299     } fmt_mvfachi_a;
 300     struct { /* e.g. mvfc $dr,$scr */
 301       UINT f_r2;
 302       SI * i_dr;
 303       unsigned char out_dr;
 304     } fmt_mvfc;
 305     struct { /* e.g. mvtachi $src1,$accs */
 306       UINT f_accs;
 307       SI * i_src1;
 308       unsigned char in_src1;
 309     } fmt_mvtachi_a;
 310     struct { /* e.g. mvtc $sr,$dcr */
 311       UINT f_r1;
 312       SI * i_sr;
 313       unsigned char in_sr;
 314     } fmt_mvtc;
 315     struct { /* e.g. nop */
 316       int empty;
 317     } fmt_nop;
 318     struct { /* e.g. rac $accd,$accs,$imm1 */
 319       UINT f_accs;
 320       SI f_imm1;
 321       UINT f_accd;
 322     } fmt_rac_dsi;
 323     struct { /* e.g. seth $dr,$hash$hi16 */
 324       UINT f_hi16;
 325       SI * i_dr;
 326       unsigned char out_dr;
 327     } fmt_seth;
 328     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 329       INT f_simm16;
 330       SI * i_sr;
 331       SI * i_dr;
 332       unsigned char in_sr;
 333       unsigned char out_dr;
 334     } fmt_sll3;
 335     struct { /* e.g. slli $dr,$uimm5 */
 336       UINT f_uimm5;
 337       SI * i_dr;
 338       unsigned char in_dr;
 339       unsigned char out_dr;
 340     } fmt_slli;
 341     struct { /* e.g. st $src1,@$src2 */
 342       SI * i_src2;
 343       SI * i_src1;
 344       unsigned char in_src2;
 345       unsigned char in_src1;
 346     } fmt_st;
 347     struct { /* e.g. st $src1,@($slo16,$src2) */
 348       INT f_simm16;
 349       SI * i_src2;
 350       SI * i_src1;
 351       unsigned char in_src2;
 352       unsigned char in_src1;
 353     } fmt_st_d;
 354     struct { /* e.g. stb $src1,@$src2 */
 355       SI * i_src2;
 356       SI * i_src1;
 357       unsigned char in_src2;
 358       unsigned char in_src1;
 359     } fmt_stb;
 360     struct { /* e.g. stb $src1,@($slo16,$src2) */
 361       INT f_simm16;
 362       SI * i_src2;
 363       SI * i_src1;
 364       unsigned char in_src2;
 365       unsigned char in_src1;
 366     } fmt_stb_d;
 367     struct { /* e.g. sth $src1,@$src2 */
 368       SI * i_src2;
 369       SI * i_src1;
 370       unsigned char in_src2;
 371       unsigned char in_src1;
 372     } fmt_sth;
 373     struct { /* e.g. sth $src1,@($slo16,$src2) */
 374       INT f_simm16;
 375       SI * i_src2;
 376       SI * i_src1;
 377       unsigned char in_src2;
 378       unsigned char in_src1;
 379     } fmt_sth_d;
 380     struct { /* e.g. st $src1,@+$src2 */
 381       SI * i_src2;
 382       SI * i_src1;
 383       unsigned char in_src2;
 384       unsigned char in_src1;
 385       unsigned char out_src2;
 386     } fmt_st_plus;
 387     struct { /* e.g. unlock $src1,@$src2 */
 388       SI * i_src2;
 389       SI * i_src1;
 390       unsigned char in_src2;
 391       unsigned char in_src1;
 392     } fmt_unlock;
 393     struct { /* e.g. satb $dr,$sr */
 394       SI * i_sr;
 395       SI * i_dr;
 396       unsigned char in_sr;
 397       unsigned char out_dr;
 398     } fmt_satb;
 399     struct { /* e.g. sat $dr,$sr */
 400       SI * i_sr;
 401       SI * i_dr;
 402       unsigned char in_sr;
 403       unsigned char out_dr;
 404     } fmt_sat;
 405     struct { /* e.g. sadd */
 406       int empty;
 407     } fmt_sadd;
 408     struct { /* e.g. macwu1 $src1,$src2 */
 409       SI * i_src1;
 410       SI * i_src2;
 411       unsigned char in_src1;
 412       unsigned char in_src2;
 413     } fmt_macwu1;
 414     struct { /* e.g. msblo $src1,$src2 */
 415       SI * i_src1;
 416       SI * i_src2;
 417       unsigned char in_src1;
 418       unsigned char in_src2;
 419     } fmt_msblo;
 420     struct { /* e.g. mulwu1 $src1,$src2 */
 421       SI * i_src1;
 422       SI * i_src2;
 423       unsigned char in_src1;
 424       unsigned char in_src2;
 425     } fmt_mulwu1;
 426   /* cti insns, kept separately so addr_cache is in fixed place */
 427   struct {
 428     union {
 429     struct { /* e.g. bc.s $disp8 */
 430       IADDR i_disp8;
 431     } fmt_bc8;
 432     struct { /* e.g. bc.l $disp24 */
 433       IADDR i_disp24;
 434     } fmt_bc24;
 435     struct { /* e.g. beq $src1,$src2,$disp16 */
 436       SI * i_src1;
 437       SI * i_src2;
 438       IADDR i_disp16;
 439       unsigned char in_src1;
 440       unsigned char in_src2;
 441     } fmt_beq;
 442     struct { /* e.g. beqz $src2,$disp16 */
 443       SI * i_src2;
 444       IADDR i_disp16;
 445       unsigned char in_src2;
 446     } fmt_beqz;
 447     struct { /* e.g. bl.s $disp8 */
 448       IADDR i_disp8;
 449       unsigned char out_h_gr_14;
 450     } fmt_bl8;
 451     struct { /* e.g. bl.l $disp24 */
 452       IADDR i_disp24;
 453       unsigned char out_h_gr_14;
 454     } fmt_bl24;
 455     struct { /* e.g. bcl.s $disp8 */
 456       IADDR i_disp8;
 457       unsigned char out_h_gr_14;
 458     } fmt_bcl8;
 459     struct { /* e.g. bcl.l $disp24 */
 460       IADDR i_disp24;
 461       unsigned char out_h_gr_14;
 462     } fmt_bcl24;
 463     struct { /* e.g. bra.s $disp8 */
 464       IADDR i_disp8;
 465     } fmt_bra8;
 466     struct { /* e.g. bra.l $disp24 */
 467       IADDR i_disp24;
 468     } fmt_bra24;
 469     struct { /* e.g. jc $sr */
 470       SI * i_sr;
 471       unsigned char in_sr;
 472     } fmt_jc;
 473     struct { /* e.g. jl $sr */
 474       SI * i_sr;
 475       unsigned char in_sr;
 476       unsigned char out_h_gr_14;
 477     } fmt_jl;
 478     struct { /* e.g. jmp $sr */
 479       SI * i_sr;
 480       unsigned char in_sr;
 481     } fmt_jmp;
 482     struct { /* e.g. rte */
 483       int empty;
 484     } fmt_rte;
 485     struct { /* e.g. trap $uimm4 */
 486       UINT f_uimm4;
 487     } fmt_trap;
 488     struct { /* e.g. sc */
 489       int empty;
 490     } fmt_sc;
 491     } fields;
 492 #if WITH_SCACHE_PBB
 493     SEM_PC addr_cache;
 494 #endif
 495   } cti;
 496 #if WITH_SCACHE_PBB
 497     /* Writeback handler.  */
 498     struct {
 499       /* Pointer to argbuf entry for insn whose results need writing back.  */
 500       const struct argbuf *abuf;
 501     } write;
 502     /* x-before handler */
 503     struct {
 504       /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 505       int first_p;
 506     } before;
 507     /* x-after handler */
 508     struct {
 509       int empty;
 510     } after;
 511     /* This entry is used to terminate each pbb.  */
 512     struct {
 513       /* Number of insns in pbb.  */
 514       int insn_count;
 515       /* Next pbb to execute.  */
 516       SCACHE *next;
 517     } chain;
 518 #endif
 519   } fields;
 520 };
 521
 522 /* A cached insn.
 523
 524    ??? SCACHE used to contain more than just argbuf.  We could delete the
 525    type entirely and always just use ARGBUF, but for future concerns and as
 526    a level of abstraction it is left in.  */
 527
 528 struct scache {
 529   struct argbuf argbuf;
 530 };
 531
 532 /* Macros to simplify extraction, reading and semantic code.
 533    These define and assign the local vars that contain the insn's fields.  */
 534
 535 #define EXTRACT_FMT_EMPTY_VARS \
 536   /* Instruction fields.  */ \
 537   unsigned int length;
 538 #define EXTRACT_FMT_EMPTY_CODE \
 539   length = 0; \
 540
 541 #define EXTRACT_FMT_ADD_VARS \
 542   /* Instruction fields.  */ \
 543   UINT f_op1; \
 544   UINT f_r1; \
 545   UINT f_op2; \
 546   UINT f_r2; \
 547   unsigned int length;
 548 #define EXTRACT_FMT_ADD_CODE \
 549   length = 2; \
 550   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 551   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 552   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 553   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 554
 555 #define EXTRACT_FMT_ADD3_VARS \
 556   /* Instruction fields.  */ \
 557   UINT f_op1; \
 558   UINT f_r1; \
 559   UINT f_op2; \
 560   UINT f_r2; \
 561   INT f_simm16; \
 562   unsigned int length;
 563 #define EXTRACT_FMT_ADD3_CODE \
 564   length = 4; \
 565   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 566   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 567   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 568   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 569   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 570
 571 #define EXTRACT_FMT_AND3_VARS \
 572   /* Instruction fields.  */ \
 573   UINT f_op1; \
 574   UINT f_r1; \
 575   UINT f_op2; \
 576   UINT f_r2; \
 577   UINT f_uimm16; \
 578   unsigned int length;
 579 #define EXTRACT_FMT_AND3_CODE \
 580   length = 4; \
 581   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 582   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 583   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 584   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 585   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 586
 587 #define EXTRACT_FMT_OR3_VARS \
 588   /* Instruction fields.  */ \
 589   UINT f_op1; \
 590   UINT f_r1; \
 591   UINT f_op2; \
 592   UINT f_r2; \
 593   UINT f_uimm16; \
 594   unsigned int length;
 595 #define EXTRACT_FMT_OR3_CODE \
 596   length = 4; \
 597   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 598   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 599   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 600   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 601   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 602
 603 #define EXTRACT_FMT_ADDI_VARS \
 604   /* Instruction fields.  */ \
 605   UINT f_op1; \
 606   UINT f_r1; \
 607   INT f_simm8; \
 608   unsigned int length;
 609 #define EXTRACT_FMT_ADDI_CODE \
 610   length = 2; \
 611   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 612   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 613   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 614
 615 #define EXTRACT_FMT_ADDV_VARS \
 616   /* Instruction fields.  */ \
 617   UINT f_op1; \
 618   UINT f_r1; \
 619   UINT f_op2; \
 620   UINT f_r2; \
 621   unsigned int length;
 622 #define EXTRACT_FMT_ADDV_CODE \
 623   length = 2; \
 624   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 625   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 626   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 627   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 628
 629 #define EXTRACT_FMT_ADDV3_VARS \
 630   /* Instruction fields.  */ \
 631   UINT f_op1; \
 632   UINT f_r1; \
 633   UINT f_op2; \
 634   UINT f_r2; \
 635   INT f_simm16; \
 636   unsigned int length;
 637 #define EXTRACT_FMT_ADDV3_CODE \
 638   length = 4; \
 639   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 640   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 641   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 642   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 643   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 644
 645 #define EXTRACT_FMT_ADDX_VARS \
 646   /* Instruction fields.  */ \
 647   UINT f_op1; \
 648   UINT f_r1; \
 649   UINT f_op2; \
 650   UINT f_r2; \
 651   unsigned int length;
 652 #define EXTRACT_FMT_ADDX_CODE \
 653   length = 2; \
 654   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 655   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 656   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 657   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 658
 659 #define EXTRACT_FMT_BC8_VARS \
 660   /* Instruction fields.  */ \
 661   UINT f_op1; \
 662   UINT f_r1; \
 663   SI f_disp8; \
 664   unsigned int length;
 665 #define EXTRACT_FMT_BC8_CODE \
 666   length = 2; \
 667   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 668   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 669   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 670
 671 #define EXTRACT_FMT_BC24_VARS \
 672   /* Instruction fields.  */ \
 673   UINT f_op1; \
 674   UINT f_r1; \
 675   SI f_disp24; \
 676   unsigned int length;
 677 #define EXTRACT_FMT_BC24_CODE \
 678   length = 4; \
 679   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 680   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 681   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 682
 683 #define EXTRACT_FMT_BEQ_VARS \
 684   /* Instruction fields.  */ \
 685   UINT f_op1; \
 686   UINT f_r1; \
 687   UINT f_op2; \
 688   UINT f_r2; \
 689   SI f_disp16; \
 690   unsigned int length;
 691 #define EXTRACT_FMT_BEQ_CODE \
 692   length = 4; \
 693   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 694   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 695   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 696   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 697   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 698
 699 #define EXTRACT_FMT_BEQZ_VARS \
 700   /* Instruction fields.  */ \
 701   UINT f_op1; \
 702   UINT f_r1; \
 703   UINT f_op2; \
 704   UINT f_r2; \
 705   SI f_disp16; \
 706   unsigned int length;
 707 #define EXTRACT_FMT_BEQZ_CODE \
 708   length = 4; \
 709   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 710   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 711   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 712   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 713   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 714
 715 #define EXTRACT_FMT_BL8_VARS \
 716   /* Instruction fields.  */ \
 717   UINT f_op1; \
 718   UINT f_r1; \
 719   SI f_disp8; \
 720   unsigned int length;
 721 #define EXTRACT_FMT_BL8_CODE \
 722   length = 2; \
 723   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 724   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 725   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 726
 727 #define EXTRACT_FMT_BL24_VARS \
 728   /* Instruction fields.  */ \
 729   UINT f_op1; \
 730   UINT f_r1; \
 731   SI f_disp24; \
 732   unsigned int length;
 733 #define EXTRACT_FMT_BL24_CODE \
 734   length = 4; \
 735   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 736   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 737   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 738
 739 #define EXTRACT_FMT_BCL8_VARS \
 740   /* Instruction fields.  */ \
 741   UINT f_op1; \
 742   UINT f_r1; \
 743   SI f_disp8; \
 744   unsigned int length;
 745 #define EXTRACT_FMT_BCL8_CODE \
 746   length = 2; \
 747   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 748   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 749   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 750
 751 #define EXTRACT_FMT_BCL24_VARS \
 752   /* Instruction fields.  */ \
 753   UINT f_op1; \
 754   UINT f_r1; \
 755   SI f_disp24; \
 756   unsigned int length;
 757 #define EXTRACT_FMT_BCL24_CODE \
 758   length = 4; \
 759   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 760   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 761   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 762
 763 #define EXTRACT_FMT_BRA8_VARS \
 764   /* Instruction fields.  */ \
 765   UINT f_op1; \
 766   UINT f_r1; \
 767   SI f_disp8; \
 768   unsigned int length;
 769 #define EXTRACT_FMT_BRA8_CODE \
 770   length = 2; \
 771   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 772   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 773   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 774
 775 #define EXTRACT_FMT_BRA24_VARS \
 776   /* Instruction fields.  */ \
 777   UINT f_op1; \
 778   UINT f_r1; \
 779   SI f_disp24; \
 780   unsigned int length;
 781 #define EXTRACT_FMT_BRA24_CODE \
 782   length = 4; \
 783   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 784   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 785   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 786
 787 #define EXTRACT_FMT_CMP_VARS \
 788   /* Instruction fields.  */ \
 789   UINT f_op1; \
 790   UINT f_r1; \
 791   UINT f_op2; \
 792   UINT f_r2; \
 793   unsigned int length;
 794 #define EXTRACT_FMT_CMP_CODE \
 795   length = 2; \
 796   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 797   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 798   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 799   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 800
 801 #define EXTRACT_FMT_CMPI_VARS \
 802   /* Instruction fields.  */ \
 803   UINT f_op1; \
 804   UINT f_r1; \
 805   UINT f_op2; \
 806   UINT f_r2; \
 807   INT f_simm16; \
 808   unsigned int length;
 809 #define EXTRACT_FMT_CMPI_CODE \
 810   length = 4; \
 811   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 812   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 813   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 814   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 815   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 816
 817 #define EXTRACT_FMT_CMPZ_VARS \
 818   /* Instruction fields.  */ \
 819   UINT f_op1; \
 820   UINT f_r1; \
 821   UINT f_op2; \
 822   UINT f_r2; \
 823   unsigned int length;
 824 #define EXTRACT_FMT_CMPZ_CODE \
 825   length = 2; \
 826   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 827   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 828   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 829   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 830
 831 #define EXTRACT_FMT_DIV_VARS \
 832   /* Instruction fields.  */ \
 833   UINT f_op1; \
 834   UINT f_r1; \
 835   UINT f_op2; \
 836   UINT f_r2; \
 837   INT f_simm16; \
 838   unsigned int length;
 839 #define EXTRACT_FMT_DIV_CODE \
 840   length = 4; \
 841   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 842   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 843   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 844   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 845   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 846
 847 #define EXTRACT_FMT_JC_VARS \
 848   /* Instruction fields.  */ \
 849   UINT f_op1; \
 850   UINT f_r1; \
 851   UINT f_op2; \
 852   UINT f_r2; \
 853   unsigned int length;
 854 #define EXTRACT_FMT_JC_CODE \
 855   length = 2; \
 856   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 857   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 858   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 859   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 860
 861 #define EXTRACT_FMT_JL_VARS \
 862   /* Instruction fields.  */ \
 863   UINT f_op1; \
 864   UINT f_r1; \
 865   UINT f_op2; \
 866   UINT f_r2; \
 867   unsigned int length;
 868 #define EXTRACT_FMT_JL_CODE \
 869   length = 2; \
 870   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 871   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 872   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 873   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 874
 875 #define EXTRACT_FMT_JMP_VARS \
 876   /* Instruction fields.  */ \
 877   UINT f_op1; \
 878   UINT f_r1; \
 879   UINT f_op2; \
 880   UINT f_r2; \
 881   unsigned int length;
 882 #define EXTRACT_FMT_JMP_CODE \
 883   length = 2; \
 884   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 885   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 886   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 887   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 888
 889 #define EXTRACT_FMT_LD_VARS \
 890   /* Instruction fields.  */ \
 891   UINT f_op1; \
 892   UINT f_r1; \
 893   UINT f_op2; \
 894   UINT f_r2; \
 895   unsigned int length;
 896 #define EXTRACT_FMT_LD_CODE \
 897   length = 2; \
 898   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 899   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 900   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 901   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 902
 903 #define EXTRACT_FMT_LD_D_VARS \
 904   /* Instruction fields.  */ \
 905   UINT f_op1; \
 906   UINT f_r1; \
 907   UINT f_op2; \
 908   UINT f_r2; \
 909   INT f_simm16; \
 910   unsigned int length;
 911 #define EXTRACT_FMT_LD_D_CODE \
 912   length = 4; \
 913   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 914   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 915   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 916   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 917   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 918
 919 #define EXTRACT_FMT_LDB_VARS \
 920   /* Instruction fields.  */ \
 921   UINT f_op1; \
 922   UINT f_r1; \
 923   UINT f_op2; \
 924   UINT f_r2; \
 925   unsigned int length;
 926 #define EXTRACT_FMT_LDB_CODE \
 927   length = 2; \
 928   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 929   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 930   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 931   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 932
 933 #define EXTRACT_FMT_LDB_D_VARS \
 934   /* Instruction fields.  */ \
 935   UINT f_op1; \
 936   UINT f_r1; \
 937   UINT f_op2; \
 938   UINT f_r2; \
 939   INT f_simm16; \
 940   unsigned int length;
 941 #define EXTRACT_FMT_LDB_D_CODE \
 942   length = 4; \
 943   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 944   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 945   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 946   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 947   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 948
 949 #define EXTRACT_FMT_LDH_VARS \
 950   /* Instruction fields.  */ \
 951   UINT f_op1; \
 952   UINT f_r1; \
 953   UINT f_op2; \
 954   UINT f_r2; \
 955   unsigned int length;
 956 #define EXTRACT_FMT_LDH_CODE \
 957   length = 2; \
 958   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 959   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 960   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 961   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 962
 963 #define EXTRACT_FMT_LDH_D_VARS \
 964   /* Instruction fields.  */ \
 965   UINT f_op1; \
 966   UINT f_r1; \
 967   UINT f_op2; \
 968   UINT f_r2; \
 969   INT f_simm16; \
 970   unsigned int length;
 971 #define EXTRACT_FMT_LDH_D_CODE \
 972   length = 4; \
 973   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 974   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 975   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 976   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 977   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 978
 979 #define EXTRACT_FMT_LD_PLUS_VARS \
 980   /* Instruction fields.  */ \
 981   UINT f_op1; \
 982   UINT f_r1; \
 983   UINT f_op2; \
 984   UINT f_r2; \
 985   unsigned int length;
 986 #define EXTRACT_FMT_LD_PLUS_CODE \
 987   length = 2; \
 988   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 989   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 990   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 991   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 992
 993 #define EXTRACT_FMT_LD24_VARS \
 994   /* Instruction fields.  */ \
 995   UINT f_op1; \
 996   UINT f_r1; \
 997   UINT f_uimm24; \
 998   unsigned int length;
 999 #define EXTRACT_FMT_LD24_CODE \
1000   length = 4; \
1001   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1002   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1003   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
1004
1005 #define EXTRACT_FMT_LDI8_VARS \
1006   /* Instruction fields.  */ \
1007   UINT f_op1; \
1008   UINT f_r1; \
1009   INT f_simm8; \
1010   unsigned int length;
1011 #define EXTRACT_FMT_LDI8_CODE \
1012   length = 2; \
1013   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1014   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1015   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1016
1017 #define EXTRACT_FMT_LDI16_VARS \
1018   /* Instruction fields.  */ \
1019   UINT f_op1; \
1020   UINT f_r1; \
1021   UINT f_op2; \
1022   UINT f_r2; \
1023   INT f_simm16; \
1024   unsigned int length;
1025 #define EXTRACT_FMT_LDI16_CODE \
1026   length = 4; \
1027   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1028   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1029   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1030   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1031   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1032
1033 #define EXTRACT_FMT_LOCK_VARS \
1034   /* Instruction fields.  */ \
1035   UINT f_op1; \
1036   UINT f_r1; \
1037   UINT f_op2; \
1038   UINT f_r2; \
1039   unsigned int length;
1040 #define EXTRACT_FMT_LOCK_CODE \
1041   length = 2; \
1042   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1043   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1044   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1045   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1046
1047 #define EXTRACT_FMT_MACHI_A_VARS \
1048   /* Instruction fields.  */ \
1049   UINT f_op1; \
1050   UINT f_r1; \
1051   UINT f_acc; \
1052   UINT f_op23; \
1053   UINT f_r2; \
1054   unsigned int length;
1055 #define EXTRACT_FMT_MACHI_A_CODE \
1056   length = 2; \
1057   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1058   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1059   f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1060   f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1061   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1062
1063 #define EXTRACT_FMT_MULHI_A_VARS \
1064   /* Instruction fields.  */ \
1065   UINT f_op1; \
1066   UINT f_r1; \
1067   UINT f_acc; \
1068   UINT f_op23; \
1069   UINT f_r2; \
1070   unsigned int length;
1071 #define EXTRACT_FMT_MULHI_A_CODE \
1072   length = 2; \
1073   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1074   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1075   f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1076   f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1077   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1078
1079 #define EXTRACT_FMT_MV_VARS \
1080   /* Instruction fields.  */ \
1081   UINT f_op1; \
1082   UINT f_r1; \
1083   UINT f_op2; \
1084   UINT f_r2; \
1085   unsigned int length;
1086 #define EXTRACT_FMT_MV_CODE \
1087   length = 2; \
1088   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1089   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1090   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1091   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1092
1093 #define EXTRACT_FMT_MVFACHI_A_VARS \
1094   /* Instruction fields.  */ \
1095   UINT f_op1; \
1096   UINT f_r1; \
1097   UINT f_op2; \
1098   UINT f_accs; \
1099   UINT f_op3; \
1100   unsigned int length;
1101 #define EXTRACT_FMT_MVFACHI_A_CODE \
1102   length = 2; \
1103   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1104   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1105   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1106   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1107   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1108
1109 #define EXTRACT_FMT_MVFC_VARS \
1110   /* Instruction fields.  */ \
1111   UINT f_op1; \
1112   UINT f_r1; \
1113   UINT f_op2; \
1114   UINT f_r2; \
1115   unsigned int length;
1116 #define EXTRACT_FMT_MVFC_CODE \
1117   length = 2; \
1118   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1119   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1120   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1121   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1122
1123 #define EXTRACT_FMT_MVTACHI_A_VARS \
1124   /* Instruction fields.  */ \
1125   UINT f_op1; \
1126   UINT f_r1; \
1127   UINT f_op2; \
1128   UINT f_accs; \
1129   UINT f_op3; \
1130   unsigned int length;
1131 #define EXTRACT_FMT_MVTACHI_A_CODE \
1132   length = 2; \
1133   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1134   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1135   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1136   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1137   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1138
1139 #define EXTRACT_FMT_MVTC_VARS \
1140   /* Instruction fields.  */ \
1141   UINT f_op1; \
1142   UINT f_r1; \
1143   UINT f_op2; \
1144   UINT f_r2; \
1145   unsigned int length;
1146 #define EXTRACT_FMT_MVTC_CODE \
1147   length = 2; \
1148   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1149   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1150   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1151   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1152
1153 #define EXTRACT_FMT_NOP_VARS \
1154   /* Instruction fields.  */ \
1155   UINT f_op1; \
1156   UINT f_r1; \
1157   UINT f_op2; \
1158   UINT f_r2; \
1159   unsigned int length;
1160 #define EXTRACT_FMT_NOP_CODE \
1161   length = 2; \
1162   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1163   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1164   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1165   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1166
1167 #define EXTRACT_FMT_RAC_DSI_VARS \
1168   /* Instruction fields.  */ \
1169   UINT f_op1; \
1170   UINT f_accd; \
1171   UINT f_bits67; \
1172   UINT f_op2; \
1173   UINT f_accs; \
1174   UINT f_bit14; \
1175   SI f_imm1; \
1176   unsigned int length;
1177 #define EXTRACT_FMT_RAC_DSI_CODE \
1178   length = 2; \
1179   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1180   f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1181   f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1182   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1183   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1184   f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1185   f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1186
1187 #define EXTRACT_FMT_RTE_VARS \
1188   /* Instruction fields.  */ \
1189   UINT f_op1; \
1190   UINT f_r1; \
1191   UINT f_op2; \
1192   UINT f_r2; \
1193   unsigned int length;
1194 #define EXTRACT_FMT_RTE_CODE \
1195   length = 2; \
1196   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1197   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1198   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1199   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1200
1201 #define EXTRACT_FMT_SETH_VARS \
1202   /* Instruction fields.  */ \
1203   UINT f_op1; \
1204   UINT f_r1; \
1205   UINT f_op2; \
1206   UINT f_r2; \
1207   UINT f_hi16; \
1208   unsigned int length;
1209 #define EXTRACT_FMT_SETH_CODE \
1210   length = 4; \
1211   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1212   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1213   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1214   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1215   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1216
1217 #define EXTRACT_FMT_SLL3_VARS \
1218   /* Instruction fields.  */ \
1219   UINT f_op1; \
1220   UINT f_r1; \
1221   UINT f_op2; \
1222   UINT f_r2; \
1223   INT f_simm16; \
1224   unsigned int length;
1225 #define EXTRACT_FMT_SLL3_CODE \
1226   length = 4; \
1227   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1228   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1229   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1230   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1231   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1232
1233 #define EXTRACT_FMT_SLLI_VARS \
1234   /* Instruction fields.  */ \
1235   UINT f_op1; \
1236   UINT f_r1; \
1237   UINT f_shift_op2; \
1238   UINT f_uimm5; \
1239   unsigned int length;
1240 #define EXTRACT_FMT_SLLI_CODE \
1241   length = 2; \
1242   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1243   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1244   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1245   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1246
1247 #define EXTRACT_FMT_ST_VARS \
1248   /* Instruction fields.  */ \
1249   UINT f_op1; \
1250   UINT f_r1; \
1251   UINT f_op2; \
1252   UINT f_r2; \
1253   unsigned int length;
1254 #define EXTRACT_FMT_ST_CODE \
1255   length = 2; \
1256   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1257   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1258   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1259   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1260
1261 #define EXTRACT_FMT_ST_D_VARS \
1262   /* Instruction fields.  */ \
1263   UINT f_op1; \
1264   UINT f_r1; \
1265   UINT f_op2; \
1266   UINT f_r2; \
1267   INT f_simm16; \
1268   unsigned int length;
1269 #define EXTRACT_FMT_ST_D_CODE \
1270   length = 4; \
1271   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1272   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1273   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1274   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1275   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1276
1277 #define EXTRACT_FMT_STB_VARS \
1278   /* Instruction fields.  */ \
1279   UINT f_op1; \
1280   UINT f_r1; \
1281   UINT f_op2; \
1282   UINT f_r2; \
1283   unsigned int length;
1284 #define EXTRACT_FMT_STB_CODE \
1285   length = 2; \
1286   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1287   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1288   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1289   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1290
1291 #define EXTRACT_FMT_STB_D_VARS \
1292   /* Instruction fields.  */ \
1293   UINT f_op1; \
1294   UINT f_r1; \
1295   UINT f_op2; \
1296   UINT f_r2; \
1297   INT f_simm16; \
1298   unsigned int length;
1299 #define EXTRACT_FMT_STB_D_CODE \
1300   length = 4; \
1301   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1302   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1303   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1304   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1305   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1306
1307 #define EXTRACT_FMT_STH_VARS \
1308   /* Instruction fields.  */ \
1309   UINT f_op1; \
1310   UINT f_r1; \
1311   UINT f_op2; \
1312   UINT f_r2; \
1313   unsigned int length;
1314 #define EXTRACT_FMT_STH_CODE \
1315   length = 2; \
1316   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1317   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1318   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1319   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1320
1321 #define EXTRACT_FMT_STH_D_VARS \
1322   /* Instruction fields.  */ \
1323   UINT f_op1; \
1324   UINT f_r1; \
1325   UINT f_op2; \
1326   UINT f_r2; \
1327   INT f_simm16; \
1328   unsigned int length;
1329 #define EXTRACT_FMT_STH_D_CODE \
1330   length = 4; \
1331   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1332   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1333   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1334   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1335   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1336
1337 #define EXTRACT_FMT_ST_PLUS_VARS \
1338   /* Instruction fields.  */ \
1339   UINT f_op1; \
1340   UINT f_r1; \
1341   UINT f_op2; \
1342   UINT f_r2; \
1343   unsigned int length;
1344 #define EXTRACT_FMT_ST_PLUS_CODE \
1345   length = 2; \
1346   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1347   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1348   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1349   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1350
1351 #define EXTRACT_FMT_TRAP_VARS \
1352   /* Instruction fields.  */ \
1353   UINT f_op1; \
1354   UINT f_r1; \
1355   UINT f_op2; \
1356   UINT f_uimm4; \
1357   unsigned int length;
1358 #define EXTRACT_FMT_TRAP_CODE \
1359   length = 2; \
1360   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1361   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1362   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1363   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1364
1365 #define EXTRACT_FMT_UNLOCK_VARS \
1366   /* Instruction fields.  */ \
1367   UINT f_op1; \
1368   UINT f_r1; \
1369   UINT f_op2; \
1370   UINT f_r2; \
1371   unsigned int length;
1372 #define EXTRACT_FMT_UNLOCK_CODE \
1373   length = 2; \
1374   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1375   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1376   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1377   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1378
1379 #define EXTRACT_FMT_SATB_VARS \
1380   /* Instruction fields.  */ \
1381   UINT f_op1; \
1382   UINT f_r1; \
1383   UINT f_op2; \
1384   UINT f_r2; \
1385   UINT f_uimm16; \
1386   unsigned int length;
1387 #define EXTRACT_FMT_SATB_CODE \
1388   length = 4; \
1389   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1390   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1391   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1392   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1393   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1394
1395 #define EXTRACT_FMT_SAT_VARS \
1396   /* Instruction fields.  */ \
1397   UINT f_op1; \
1398   UINT f_r1; \
1399   UINT f_op2; \
1400   UINT f_r2; \
1401   UINT f_uimm16; \
1402   unsigned int length;
1403 #define EXTRACT_FMT_SAT_CODE \
1404   length = 4; \
1405   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1406   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1407   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1408   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1409   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1410
1411 #define EXTRACT_FMT_SADD_VARS \
1412   /* Instruction fields.  */ \
1413   UINT f_op1; \
1414   UINT f_r1; \
1415   UINT f_op2; \
1416   UINT f_r2; \
1417   unsigned int length;
1418 #define EXTRACT_FMT_SADD_CODE \
1419   length = 2; \
1420   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1421   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1422   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1423   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1424
1425 #define EXTRACT_FMT_MACWU1_VARS \
1426   /* Instruction fields.  */ \
1427   UINT f_op1; \
1428   UINT f_r1; \
1429   UINT f_op2; \
1430   UINT f_r2; \
1431   unsigned int length;
1432 #define EXTRACT_FMT_MACWU1_CODE \
1433   length = 2; \
1434   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1435   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1436   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1437   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1438
1439 #define EXTRACT_FMT_MSBLO_VARS \
1440   /* Instruction fields.  */ \
1441   UINT f_op1; \
1442   UINT f_r1; \
1443   UINT f_op2; \
1444   UINT f_r2; \
1445   unsigned int length;
1446 #define EXTRACT_FMT_MSBLO_CODE \
1447   length = 2; \
1448   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1449   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1450   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1451   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1452
1453 #define EXTRACT_FMT_MULWU1_VARS \
1454   /* Instruction fields.  */ \
1455   UINT f_op1; \
1456   UINT f_r1; \
1457   UINT f_op2; \
1458   UINT f_r2; \
1459   unsigned int length;
1460 #define EXTRACT_FMT_MULWU1_CODE \
1461   length = 2; \
1462   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1463   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1464   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1465   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1466
1467 #define EXTRACT_FMT_SC_VARS \
1468   /* Instruction fields.  */ \
1469   UINT f_op1; \
1470   UINT f_r1; \
1471   UINT f_op2; \
1472   UINT f_r2; \
1473   unsigned int length;
1474 #define EXTRACT_FMT_SC_CODE \
1475   length = 2; \
1476   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1477   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1478   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1479   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1480
1481 /* Queued output values of an instruction.  */
1482
1483 struct parexec {
1484   union {
1485     struct { /* empty format for unspecified field list */
1486       int empty;
1487     } fmt_empty;
1488     struct { /* e.g. add $dr,$sr */
1489       SI dr;
1490     } fmt_add;
1491     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1492       SI dr;
1493     } fmt_add3;
1494     struct { /* e.g. and3 $dr,$sr,$uimm16 */
1495       SI dr;
1496     } fmt_and3;
1497     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1498       SI dr;
1499     } fmt_or3;
1500     struct { /* e.g. addi $dr,$simm8 */
1501       SI dr;
1502     } fmt_addi;
1503     struct { /* e.g. addv $dr,$sr */
1504       SI dr;
1505       BI condbit;
1506     } fmt_addv;
1507     struct { /* e.g. addv3 $dr,$sr,$simm16 */
1508       SI dr;
1509       BI condbit;
1510     } fmt_addv3;
1511     struct { /* e.g. addx $dr,$sr */
1512       SI dr;
1513       BI condbit;
1514     } fmt_addx;
1515     struct { /* e.g. bc.s $disp8 */
1516       USI pc;
1517     } fmt_bc8;
1518     struct { /* e.g. bc.l $disp24 */
1519       USI pc;
1520     } fmt_bc24;
1521     struct { /* e.g. beq $src1,$src2,$disp16 */
1522       USI pc;
1523     } fmt_beq;
1524     struct { /* e.g. beqz $src2,$disp16 */
1525       USI pc;
1526     } fmt_beqz;
1527     struct { /* e.g. bl.s $disp8 */
1528       SI h_gr_14;
1529       USI pc;
1530     } fmt_bl8;
1531     struct { /* e.g. bl.l $disp24 */
1532       SI h_gr_14;
1533       USI pc;
1534     } fmt_bl24;
1535     struct { /* e.g. bcl.s $disp8 */
1536       SI h_gr_14;
1537       USI pc;
1538     } fmt_bcl8;
1539     struct { /* e.g. bcl.l $disp24 */
1540       SI h_gr_14;
1541       USI pc;
1542     } fmt_bcl24;
1543     struct { /* e.g. bra.s $disp8 */
1544       USI pc;
1545     } fmt_bra8;
1546     struct { /* e.g. bra.l $disp24 */
1547       USI pc;
1548     } fmt_bra24;
1549     struct { /* e.g. cmp $src1,$src2 */
1550       BI condbit;
1551     } fmt_cmp;
1552     struct { /* e.g. cmpi $src2,$simm16 */
1553       BI condbit;
1554     } fmt_cmpi;
1555     struct { /* e.g. cmpz $src2 */
1556       BI condbit;
1557     } fmt_cmpz;
1558     struct { /* e.g. div $dr,$sr */
1559       SI dr;
1560     } fmt_div;
1561     struct { /* e.g. jc $sr */
1562       USI pc;
1563     } fmt_jc;
1564     struct { /* e.g. jl $sr */
1565       SI h_gr_14;
1566       USI pc;
1567     } fmt_jl;
1568     struct { /* e.g. jmp $sr */
1569       USI pc;
1570     } fmt_jmp;
1571     struct { /* e.g. ld $dr,@$sr */
1572       SI dr;
1573     } fmt_ld;
1574     struct { /* e.g. ld $dr,@($slo16,$sr) */
1575       SI dr;
1576     } fmt_ld_d;
1577     struct { /* e.g. ldb $dr,@$sr */
1578       SI dr;
1579     } fmt_ldb;
1580     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1581       SI dr;
1582     } fmt_ldb_d;
1583     struct { /* e.g. ldh $dr,@$sr */
1584       SI dr;
1585     } fmt_ldh;
1586     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1587       SI dr;
1588     } fmt_ldh_d;
1589     struct { /* e.g. ld $dr,@$sr+ */
1590       SI dr;
1591       SI sr;
1592     } fmt_ld_plus;
1593     struct { /* e.g. ld24 $dr,$uimm24 */
1594       SI dr;
1595     } fmt_ld24;
1596     struct { /* e.g. ldi8 $dr,$simm8 */
1597       SI dr;
1598     } fmt_ldi8;
1599     struct { /* e.g. ldi16 $dr,$hash$slo16 */
1600       SI dr;
1601     } fmt_ldi16;
1602     struct { /* e.g. lock $dr,@$sr */
1603       BI h_lock_0;
1604       SI dr;
1605     } fmt_lock;
1606     struct { /* e.g. machi $src1,$src2,$acc */
1607       DI acc;
1608     } fmt_machi_a;
1609     struct { /* e.g. mulhi $src1,$src2,$acc */
1610       DI acc;
1611     } fmt_mulhi_a;
1612     struct { /* e.g. mv $dr,$sr */
1613       SI dr;
1614     } fmt_mv;
1615     struct { /* e.g. mvfachi $dr,$accs */
1616       SI dr;
1617     } fmt_mvfachi_a;
1618     struct { /* e.g. mvfc $dr,$scr */
1619       SI dr;
1620     } fmt_mvfc;
1621     struct { /* e.g. mvtachi $src1,$accs */
1622       DI accs;
1623     } fmt_mvtachi_a;
1624     struct { /* e.g. mvtc $sr,$dcr */
1625       USI dcr;
1626     } fmt_mvtc;
1627     struct { /* e.g. nop */
1628       int empty;
1629     } fmt_nop;
1630     struct { /* e.g. rac $accd,$accs,$imm1 */
1631       DI accd;
1632     } fmt_rac_dsi;
1633     struct { /* e.g. rte */
1634       USI pc;
1635       USI h_cr_6;
1636       UQI h_psw_0;
1637       UQI h_bpsw_0;
1638     } fmt_rte;
1639     struct { /* e.g. seth $dr,$hash$hi16 */
1640       SI dr;
1641     } fmt_seth;
1642     struct { /* e.g. sll3 $dr,$sr,$simm16 */
1643       SI dr;
1644     } fmt_sll3;
1645     struct { /* e.g. slli $dr,$uimm5 */
1646       SI dr;
1647     } fmt_slli;
1648     struct { /* e.g. st $src1,@$src2 */
1649       SI h_memory_src2;
1650       USI h_memory_src2_idx;
1651     } fmt_st;
1652     struct { /* e.g. st $src1,@($slo16,$src2) */
1653       SI h_memory_add__VM_src2_slo16;
1654       USI h_memory_add__VM_src2_slo16_idx;
1655     } fmt_st_d;
1656     struct { /* e.g. stb $src1,@$src2 */
1657       QI h_memory_src2;
1658       USI h_memory_src2_idx;
1659     } fmt_stb;
1660     struct { /* e.g. stb $src1,@($slo16,$src2) */
1661       QI h_memory_add__VM_src2_slo16;
1662       USI h_memory_add__VM_src2_slo16_idx;
1663     } fmt_stb_d;
1664     struct { /* e.g. sth $src1,@$src2 */
1665       HI h_memory_src2;
1666       USI h_memory_src2_idx;
1667     } fmt_sth;
1668     struct { /* e.g. sth $src1,@($slo16,$src2) */
1669       HI h_memory_add__VM_src2_slo16;
1670       USI h_memory_add__VM_src2_slo16_idx;
1671     } fmt_sth_d;
1672     struct { /* e.g. st $src1,@+$src2 */
1673       SI h_memory_new_src2;
1674       USI h_memory_new_src2_idx;
1675       SI src2;
1676     } fmt_st_plus;
1677     struct { /* e.g. trap $uimm4 */
1678       USI h_cr_14;
1679       USI h_cr_6;
1680       UQI h_bbpsw_0;
1681       UQI h_bpsw_0;
1682       UQI h_psw_0;
1683       SI pc;
1684     } fmt_trap;
1685     struct { /* e.g. unlock $src1,@$src2 */
1686       SI h_memory_src2;
1687       USI h_memory_src2_idx;
1688       BI h_lock_0;
1689     } fmt_unlock;
1690     struct { /* e.g. satb $dr,$sr */
1691       SI dr;
1692     } fmt_satb;
1693     struct { /* e.g. sat $dr,$sr */
1694       SI dr;
1695     } fmt_sat;
1696     struct { /* e.g. sadd */
1697       DI h_accums_0;
1698     } fmt_sadd;
1699     struct { /* e.g. macwu1 $src1,$src2 */
1700       DI h_accums_1;
1701     } fmt_macwu1;
1702     struct { /* e.g. msblo $src1,$src2 */
1703       DI accum;
1704     } fmt_msblo;
1705     struct { /* e.g. mulwu1 $src1,$src2 */
1706       DI h_accums_1;
1707     } fmt_mulwu1;
1708     struct { /* e.g. sc */
1709       int empty;
1710     } fmt_sc;
1711   } operands;
1712   /* For conditionally written operands, bitmask of which ones were.  */
1713   int written;
1714 };
1715
1716 /* Collection of various things for the trace handler to use.  */
1717
1718 typedef struct trace_record {
1719   PCADDR pc;
1720   /* FIXME:wip */
1721 } TRACE_RECORD;
1722
1723 #endif /* CPU_M32RXF_H */