sim/m32r/cpux.h

   1 /* CPU family header for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RXF_H
  26 #define CPU_M32RXF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RXF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rxf_h_pc_get (SIM_CPU *);
  89 void m32rxf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rxf_h_accum_get (SIM_CPU *);
  95 void m32rxf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rxf_h_cond_get (SIM_CPU *);
  99 void m32rxf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rxf_h_psw_get (SIM_CPU *);
 101 void m32rxf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rxf_h_bpsw_get (SIM_CPU *);
 103 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
 105 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rxf_h_lock_get (SIM_CPU *);
 107 void m32rxf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rxf_fetch_register;
 111 extern CPUREG_STORE_FN m32rxf_store_register;
 112
 113 typedef struct {
 114   int empty;
 115 } MODEL_M32RX_DATA;
 116
 117 union sem_fields {
 118     struct { /* empty format for unspecified field list */
 119       int empty;
 120     } fmt_empty;
 121     struct { /* e.g. add $dr,$sr */
 122       SI * i_dr;
 123       SI * i_sr;
 124       unsigned char in_dr;
 125       unsigned char in_sr;
 126       unsigned char out_dr;
 127     } fmt_add;
 128     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 129       INT f_simm16;
 130       SI * i_sr;
 131       SI * i_dr;
 132       unsigned char in_sr;
 133       unsigned char out_dr;
 134     } fmt_add3;
 135     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 136       UINT f_uimm16;
 137       SI * i_sr;
 138       SI * i_dr;
 139       unsigned char in_sr;
 140       unsigned char out_dr;
 141     } fmt_and3;
 142     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 143       UINT f_uimm16;
 144       SI * i_sr;
 145       SI * i_dr;
 146       unsigned char in_sr;
 147       unsigned char out_dr;
 148     } fmt_or3;
 149     struct { /* e.g. addi $dr,$simm8 */
 150       INT f_simm8;
 151       SI * i_dr;
 152       unsigned char in_dr;
 153       unsigned char out_dr;
 154     } fmt_addi;
 155     struct { /* e.g. addv $dr,$sr */
 156       SI * i_dr;
 157       SI * i_sr;
 158       unsigned char in_dr;
 159       unsigned char in_sr;
 160       unsigned char out_dr;
 161     } fmt_addv;
 162     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 163       INT f_simm16;
 164       SI * i_sr;
 165       SI * i_dr;
 166       unsigned char in_sr;
 167       unsigned char out_dr;
 168     } fmt_addv3;
 169     struct { /* e.g. addx $dr,$sr */
 170       SI * i_dr;
 171       SI * i_sr;
 172       unsigned char in_dr;
 173       unsigned char in_sr;
 174       unsigned char out_dr;
 175     } fmt_addx;
 176     struct { /* e.g. cmp $src1,$src2 */
 177       SI * i_src1;
 178       SI * i_src2;
 179       unsigned char in_src1;
 180       unsigned char in_src2;
 181     } fmt_cmp;
 182     struct { /* e.g. cmpi $src2,$simm16 */
 183       INT f_simm16;
 184       SI * i_src2;
 185       unsigned char in_src2;
 186     } fmt_cmpi;
 187     struct { /* e.g. cmpz $src2 */
 188       SI * i_src2;
 189       unsigned char in_src2;
 190     } fmt_cmpz;
 191     struct { /* e.g. div $dr,$sr */
 192       SI * i_sr;
 193       SI * i_dr;
 194       unsigned char in_sr;
 195       unsigned char in_dr;
 196       unsigned char out_dr;
 197     } fmt_div;
 198     struct { /* e.g. ld $dr,@$sr */
 199       SI * i_sr;
 200       SI * i_dr;
 201       unsigned char in_sr;
 202       unsigned char out_dr;
 203     } fmt_ld;
 204     struct { /* e.g. ld $dr,@($slo16,$sr) */
 205       INT f_simm16;
 206       SI * i_sr;
 207       SI * i_dr;
 208       unsigned char in_sr;
 209       unsigned char out_dr;
 210     } fmt_ld_d;
 211     struct { /* e.g. ldb $dr,@$sr */
 212       SI * i_sr;
 213       SI * i_dr;
 214       unsigned char in_sr;
 215       unsigned char out_dr;
 216     } fmt_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       INT f_simm16;
 219       SI * i_sr;
 220       SI * i_dr;
 221       unsigned char in_sr;
 222       unsigned char out_dr;
 223     } fmt_ldb_d;
 224     struct { /* e.g. ldh $dr,@$sr */
 225       SI * i_sr;
 226       SI * i_dr;
 227       unsigned char in_sr;
 228       unsigned char out_dr;
 229     } fmt_ldh;
 230     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 231       INT f_simm16;
 232       SI * i_sr;
 233       SI * i_dr;
 234       unsigned char in_sr;
 235       unsigned char out_dr;
 236     } fmt_ldh_d;
 237     struct { /* e.g. ld $dr,@$sr+ */
 238       SI * i_sr;
 239       SI * i_dr;
 240       unsigned char in_sr;
 241       unsigned char out_dr;
 242       unsigned char out_sr;
 243     } fmt_ld_plus;
 244     struct { /* e.g. ld24 $dr,$uimm24 */
 245       ADDR i_uimm24;
 246       SI * i_dr;
 247       unsigned char out_dr;
 248     } fmt_ld24;
 249     struct { /* e.g. ldi8 $dr,$simm8 */
 250       INT f_simm8;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ldi8;
 254     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 255       INT f_simm16;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi16;
 259     struct { /* e.g. lock $dr,@$sr */
 260       SI * i_sr;
 261       SI * i_dr;
 262       unsigned char in_sr;
 263       unsigned char out_dr;
 264     } fmt_lock;
 265     struct { /* e.g. machi $src1,$src2,$acc */
 266       UINT f_acc;
 267       SI * i_src1;
 268       SI * i_src2;
 269       unsigned char in_src1;
 270       unsigned char in_src2;
 271     } fmt_machi_a;
 272     struct { /* e.g. mulhi $src1,$src2,$acc */
 273       UINT f_acc;
 274       SI * i_src1;
 275       SI * i_src2;
 276       unsigned char in_src1;
 277       unsigned char in_src2;
 278     } fmt_mulhi_a;
 279     struct { /* e.g. mv $dr,$sr */
 280       SI * i_sr;
 281       SI * i_dr;
 282       unsigned char in_sr;
 283       unsigned char out_dr;
 284     } fmt_mv;
 285     struct { /* e.g. mvfachi $dr,$accs */
 286       UINT f_accs;
 287       SI * i_dr;
 288       unsigned char out_dr;
 289     } fmt_mvfachi_a;
 290     struct { /* e.g. mvfc $dr,$scr */
 291       UINT f_r2;
 292       SI * i_dr;
 293       unsigned char out_dr;
 294     } fmt_mvfc;
 295     struct { /* e.g. mvtachi $src1,$accs */
 296       UINT f_accs;
 297       SI * i_src1;
 298       unsigned char in_src1;
 299     } fmt_mvtachi_a;
 300     struct { /* e.g. mvtc $sr,$dcr */
 301       UINT f_r1;
 302       SI * i_sr;
 303       unsigned char in_sr;
 304     } fmt_mvtc;
 305     struct { /* e.g. nop */
 306       int empty;
 307     } fmt_nop;
 308     struct { /* e.g. rac $accd,$accs,$imm1 */
 309       UINT f_accs;
 310       SI f_imm1;
 311       UINT f_accd;
 312     } fmt_rac_dsi;
 313     struct { /* e.g. seth $dr,$hash$hi16 */
 314       UINT f_hi16;
 315       SI * i_dr;
 316       unsigned char out_dr;
 317     } fmt_seth;
 318     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 319       INT f_simm16;
 320       SI * i_sr;
 321       SI * i_dr;
 322       unsigned char in_sr;
 323       unsigned char out_dr;
 324     } fmt_sll3;
 325     struct { /* e.g. slli $dr,$uimm5 */
 326       UINT f_uimm5;
 327       SI * i_dr;
 328       unsigned char in_dr;
 329       unsigned char out_dr;
 330     } fmt_slli;
 331     struct { /* e.g. st $src1,@$src2 */
 332       SI * i_src2;
 333       SI * i_src1;
 334       unsigned char in_src2;
 335       unsigned char in_src1;
 336     } fmt_st;
 337     struct { /* e.g. st $src1,@($slo16,$src2) */
 338       INT f_simm16;
 339       SI * i_src2;
 340       SI * i_src1;
 341       unsigned char in_src2;
 342       unsigned char in_src1;
 343     } fmt_st_d;
 344     struct { /* e.g. stb $src1,@$src2 */
 345       SI * i_src2;
 346       SI * i_src1;
 347       unsigned char in_src2;
 348       unsigned char in_src1;
 349     } fmt_stb;
 350     struct { /* e.g. stb $src1,@($slo16,$src2) */
 351       INT f_simm16;
 352       SI * i_src2;
 353       SI * i_src1;
 354       unsigned char in_src2;
 355       unsigned char in_src1;
 356     } fmt_stb_d;
 357     struct { /* e.g. sth $src1,@$src2 */
 358       SI * i_src2;
 359       SI * i_src1;
 360       unsigned char in_src2;
 361       unsigned char in_src1;
 362     } fmt_sth;
 363     struct { /* e.g. sth $src1,@($slo16,$src2) */
 364       INT f_simm16;
 365       SI * i_src2;
 366       SI * i_src1;
 367       unsigned char in_src2;
 368       unsigned char in_src1;
 369     } fmt_sth_d;
 370     struct { /* e.g. st $src1,@+$src2 */
 371       SI * i_src2;
 372       SI * i_src1;
 373       unsigned char in_src2;
 374       unsigned char in_src1;
 375       unsigned char out_src2;
 376     } fmt_st_plus;
 377     struct { /* e.g. unlock $src1,@$src2 */
 378       SI * i_src2;
 379       SI * i_src1;
 380       unsigned char in_src2;
 381       unsigned char in_src1;
 382     } fmt_unlock;
 383     struct { /* e.g. satb $dr,$sr */
 384       SI * i_sr;
 385       SI * i_dr;
 386       unsigned char in_sr;
 387       unsigned char out_dr;
 388     } fmt_satb;
 389     struct { /* e.g. sat $dr,$sr */
 390       SI * i_sr;
 391       SI * i_dr;
 392       unsigned char in_sr;
 393       unsigned char out_dr;
 394     } fmt_sat;
 395     struct { /* e.g. sadd */
 396       int empty;
 397     } fmt_sadd;
 398     struct { /* e.g. macwu1 $src1,$src2 */
 399       SI * i_src1;
 400       SI * i_src2;
 401       unsigned char in_src1;
 402       unsigned char in_src2;
 403     } fmt_macwu1;
 404     struct { /* e.g. msblo $src1,$src2 */
 405       SI * i_src1;
 406       SI * i_src2;
 407       unsigned char in_src1;
 408       unsigned char in_src2;
 409     } fmt_msblo;
 410     struct { /* e.g. mulwu1 $src1,$src2 */
 411       SI * i_src1;
 412       SI * i_src2;
 413       unsigned char in_src1;
 414       unsigned char in_src2;
 415     } fmt_mulwu1;
 416   /* cti insns, kept separately so addr_cache is in fixed place */
 417   struct {
 418     union {
 419     struct { /* e.g. bc.s $disp8 */
 420       IADDR i_disp8;
 421     } fmt_bc8;
 422     struct { /* e.g. bc.l $disp24 */
 423       IADDR i_disp24;
 424     } fmt_bc24;
 425     struct { /* e.g. beq $src1,$src2,$disp16 */
 426       SI * i_src1;
 427       SI * i_src2;
 428       IADDR i_disp16;
 429       unsigned char in_src1;
 430       unsigned char in_src2;
 431     } fmt_beq;
 432     struct { /* e.g. beqz $src2,$disp16 */
 433       SI * i_src2;
 434       IADDR i_disp16;
 435       unsigned char in_src2;
 436     } fmt_beqz;
 437     struct { /* e.g. bl.s $disp8 */
 438       IADDR i_disp8;
 439       unsigned char out_h_gr_14;
 440     } fmt_bl8;
 441     struct { /* e.g. bl.l $disp24 */
 442       IADDR i_disp24;
 443       unsigned char out_h_gr_14;
 444     } fmt_bl24;
 445     struct { /* e.g. bcl.s $disp8 */
 446       IADDR i_disp8;
 447       unsigned char out_h_gr_14;
 448     } fmt_bcl8;
 449     struct { /* e.g. bcl.l $disp24 */
 450       IADDR i_disp24;
 451       unsigned char out_h_gr_14;
 452     } fmt_bcl24;
 453     struct { /* e.g. bra.s $disp8 */
 454       IADDR i_disp8;
 455     } fmt_bra8;
 456     struct { /* e.g. bra.l $disp24 */
 457       IADDR i_disp24;
 458     } fmt_bra24;
 459     struct { /* e.g. jc $sr */
 460       SI * i_sr;
 461       unsigned char in_sr;
 462     } fmt_jc;
 463     struct { /* e.g. jl $sr */
 464       SI * i_sr;
 465       unsigned char in_sr;
 466       unsigned char out_h_gr_14;
 467     } fmt_jl;
 468     struct { /* e.g. jmp $sr */
 469       SI * i_sr;
 470       unsigned char in_sr;
 471     } fmt_jmp;
 472     struct { /* e.g. rte */
 473       int empty;
 474     } fmt_rte;
 475     struct { /* e.g. trap $uimm4 */
 476       UINT f_uimm4;
 477     } fmt_trap;
 478     struct { /* e.g. sc */
 479       int empty;
 480     } fmt_sc;
 481     } fields;
 482 #if WITH_SCACHE_PBB
 483     SEM_PC addr_cache;
 484 #endif
 485   } cti;
 486 #if WITH_SCACHE_PBB
 487   /* Writeback handler.  */
 488   struct {
 489     /* Pointer to argbuf entry for insn whose results need writing back.  */
 490     const struct argbuf *abuf;
 491   } write;
 492   /* x-before handler */
 493   struct {
 494     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 495     int first_p;
 496   } before;
 497   /* x-after handler */
 498   struct {
 499     int empty;
 500   } after;
 501   /* This entry is used to terminate each pbb.  */
 502   struct {
 503     /* Number of insns in pbb.  */
 504     int insn_count;
 505     /* Next pbb to execute.  */
 506     SCACHE *next;
 507   } chain;
 508 #endif
 509 };
 510
 511 /* The ARGBUF struct.  */
 512 struct argbuf {
 513   /* These are the baseclass definitions.  */
 514   PCADDR addr;
 515   const IDESC *idesc;
 516   char trace_p;
 517   char profile_p;
 518   /* cpu specific data follows */
 519   union sem semantic;
 520   int written;
 521   union sem_fields fields;
 522 };
 523
 524 /* A cached insn.
 525
 526    ??? SCACHE used to contain more than just argbuf.  We could delete the
 527    type entirely and always just use ARGBUF, but for future concerns and as
 528    a level of abstraction it is left in.  */
 529
 530 struct scache {
 531   struct argbuf argbuf;
 532 };
 533
 534 /* Macros to simplify extraction, reading and semantic code.
 535    These define and assign the local vars that contain the insn's fields.  */
 536
 537 #define EXTRACT_FMT_EMPTY_VARS \
 538   /* Instruction fields.  */ \
 539   unsigned int length;
 540 #define EXTRACT_FMT_EMPTY_CODE \
 541   length = 0; \
 542
 543 #define EXTRACT_FMT_ADD_VARS \
 544   /* Instruction fields.  */ \
 545   UINT f_op1; \
 546   UINT f_r1; \
 547   UINT f_op2; \
 548   UINT f_r2; \
 549   unsigned int length;
 550 #define EXTRACT_FMT_ADD_CODE \
 551   length = 2; \
 552   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 553   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 554   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 555   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 556
 557 #define EXTRACT_FMT_ADD3_VARS \
 558   /* Instruction fields.  */ \
 559   UINT f_op1; \
 560   UINT f_r1; \
 561   UINT f_op2; \
 562   UINT f_r2; \
 563   INT f_simm16; \
 564   unsigned int length;
 565 #define EXTRACT_FMT_ADD3_CODE \
 566   length = 4; \
 567   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 568   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 569   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 570   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 571   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 572
 573 #define EXTRACT_FMT_AND3_VARS \
 574   /* Instruction fields.  */ \
 575   UINT f_op1; \
 576   UINT f_r1; \
 577   UINT f_op2; \
 578   UINT f_r2; \
 579   UINT f_uimm16; \
 580   unsigned int length;
 581 #define EXTRACT_FMT_AND3_CODE \
 582   length = 4; \
 583   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 584   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 585   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 586   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 587   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 588
 589 #define EXTRACT_FMT_OR3_VARS \
 590   /* Instruction fields.  */ \
 591   UINT f_op1; \
 592   UINT f_r1; \
 593   UINT f_op2; \
 594   UINT f_r2; \
 595   UINT f_uimm16; \
 596   unsigned int length;
 597 #define EXTRACT_FMT_OR3_CODE \
 598   length = 4; \
 599   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 600   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 601   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 602   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 603   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 604
 605 #define EXTRACT_FMT_ADDI_VARS \
 606   /* Instruction fields.  */ \
 607   UINT f_op1; \
 608   UINT f_r1; \
 609   INT f_simm8; \
 610   unsigned int length;
 611 #define EXTRACT_FMT_ADDI_CODE \
 612   length = 2; \
 613   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 614   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 615   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 616
 617 #define EXTRACT_FMT_ADDV_VARS \
 618   /* Instruction fields.  */ \
 619   UINT f_op1; \
 620   UINT f_r1; \
 621   UINT f_op2; \
 622   UINT f_r2; \
 623   unsigned int length;
 624 #define EXTRACT_FMT_ADDV_CODE \
 625   length = 2; \
 626   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 627   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 628   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 629   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 630
 631 #define EXTRACT_FMT_ADDV3_VARS \
 632   /* Instruction fields.  */ \
 633   UINT f_op1; \
 634   UINT f_r1; \
 635   UINT f_op2; \
 636   UINT f_r2; \
 637   INT f_simm16; \
 638   unsigned int length;
 639 #define EXTRACT_FMT_ADDV3_CODE \
 640   length = 4; \
 641   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 642   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 643   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 644   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 645   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 646
 647 #define EXTRACT_FMT_ADDX_VARS \
 648   /* Instruction fields.  */ \
 649   UINT f_op1; \
 650   UINT f_r1; \
 651   UINT f_op2; \
 652   UINT f_r2; \
 653   unsigned int length;
 654 #define EXTRACT_FMT_ADDX_CODE \
 655   length = 2; \
 656   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 657   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 658   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 659   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 660
 661 #define EXTRACT_FMT_BC8_VARS \
 662   /* Instruction fields.  */ \
 663   UINT f_op1; \
 664   UINT f_r1; \
 665   SI f_disp8; \
 666   unsigned int length;
 667 #define EXTRACT_FMT_BC8_CODE \
 668   length = 2; \
 669   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 670   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 671   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 672
 673 #define EXTRACT_FMT_BC24_VARS \
 674   /* Instruction fields.  */ \
 675   UINT f_op1; \
 676   UINT f_r1; \
 677   SI f_disp24; \
 678   unsigned int length;
 679 #define EXTRACT_FMT_BC24_CODE \
 680   length = 4; \
 681   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 682   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 683   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 684
 685 #define EXTRACT_FMT_BEQ_VARS \
 686   /* Instruction fields.  */ \
 687   UINT f_op1; \
 688   UINT f_r1; \
 689   UINT f_op2; \
 690   UINT f_r2; \
 691   SI f_disp16; \
 692   unsigned int length;
 693 #define EXTRACT_FMT_BEQ_CODE \
 694   length = 4; \
 695   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 696   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 697   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 698   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 699   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 700
 701 #define EXTRACT_FMT_BEQZ_VARS \
 702   /* Instruction fields.  */ \
 703   UINT f_op1; \
 704   UINT f_r1; \
 705   UINT f_op2; \
 706   UINT f_r2; \
 707   SI f_disp16; \
 708   unsigned int length;
 709 #define EXTRACT_FMT_BEQZ_CODE \
 710   length = 4; \
 711   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 712   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 713   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 714   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 715   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 716
 717 #define EXTRACT_FMT_BL8_VARS \
 718   /* Instruction fields.  */ \
 719   UINT f_op1; \
 720   UINT f_r1; \
 721   SI f_disp8; \
 722   unsigned int length;
 723 #define EXTRACT_FMT_BL8_CODE \
 724   length = 2; \
 725   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 726   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 727   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 728
 729 #define EXTRACT_FMT_BL24_VARS \
 730   /* Instruction fields.  */ \
 731   UINT f_op1; \
 732   UINT f_r1; \
 733   SI f_disp24; \
 734   unsigned int length;
 735 #define EXTRACT_FMT_BL24_CODE \
 736   length = 4; \
 737   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 738   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 739   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 740
 741 #define EXTRACT_FMT_BCL8_VARS \
 742   /* Instruction fields.  */ \
 743   UINT f_op1; \
 744   UINT f_r1; \
 745   SI f_disp8; \
 746   unsigned int length;
 747 #define EXTRACT_FMT_BCL8_CODE \
 748   length = 2; \
 749   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 750   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 751   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 752
 753 #define EXTRACT_FMT_BCL24_VARS \
 754   /* Instruction fields.  */ \
 755   UINT f_op1; \
 756   UINT f_r1; \
 757   SI f_disp24; \
 758   unsigned int length;
 759 #define EXTRACT_FMT_BCL24_CODE \
 760   length = 4; \
 761   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 762   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 763   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 764
 765 #define EXTRACT_FMT_BRA8_VARS \
 766   /* Instruction fields.  */ \
 767   UINT f_op1; \
 768   UINT f_r1; \
 769   SI f_disp8; \
 770   unsigned int length;
 771 #define EXTRACT_FMT_BRA8_CODE \
 772   length = 2; \
 773   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 774   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 775   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 776
 777 #define EXTRACT_FMT_BRA24_VARS \
 778   /* Instruction fields.  */ \
 779   UINT f_op1; \
 780   UINT f_r1; \
 781   SI f_disp24; \
 782   unsigned int length;
 783 #define EXTRACT_FMT_BRA24_CODE \
 784   length = 4; \
 785   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 786   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 787   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 788
 789 #define EXTRACT_FMT_CMP_VARS \
 790   /* Instruction fields.  */ \
 791   UINT f_op1; \
 792   UINT f_r1; \
 793   UINT f_op2; \
 794   UINT f_r2; \
 795   unsigned int length;
 796 #define EXTRACT_FMT_CMP_CODE \
 797   length = 2; \
 798   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 799   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 800   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 801   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 802
 803 #define EXTRACT_FMT_CMPI_VARS \
 804   /* Instruction fields.  */ \
 805   UINT f_op1; \
 806   UINT f_r1; \
 807   UINT f_op2; \
 808   UINT f_r2; \
 809   INT f_simm16; \
 810   unsigned int length;
 811 #define EXTRACT_FMT_CMPI_CODE \
 812   length = 4; \
 813   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 814   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 815   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 816   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 817   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 818
 819 #define EXTRACT_FMT_CMPZ_VARS \
 820   /* Instruction fields.  */ \
 821   UINT f_op1; \
 822   UINT f_r1; \
 823   UINT f_op2; \
 824   UINT f_r2; \
 825   unsigned int length;
 826 #define EXTRACT_FMT_CMPZ_CODE \
 827   length = 2; \
 828   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 829   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 830   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 831   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 832
 833 #define EXTRACT_FMT_DIV_VARS \
 834   /* Instruction fields.  */ \
 835   UINT f_op1; \
 836   UINT f_r1; \
 837   UINT f_op2; \
 838   UINT f_r2; \
 839   INT f_simm16; \
 840   unsigned int length;
 841 #define EXTRACT_FMT_DIV_CODE \
 842   length = 4; \
 843   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 844   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 845   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 846   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 847   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 848
 849 #define EXTRACT_FMT_JC_VARS \
 850   /* Instruction fields.  */ \
 851   UINT f_op1; \
 852   UINT f_r1; \
 853   UINT f_op2; \
 854   UINT f_r2; \
 855   unsigned int length;
 856 #define EXTRACT_FMT_JC_CODE \
 857   length = 2; \
 858   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 859   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 860   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 861   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 862
 863 #define EXTRACT_FMT_JL_VARS \
 864   /* Instruction fields.  */ \
 865   UINT f_op1; \
 866   UINT f_r1; \
 867   UINT f_op2; \
 868   UINT f_r2; \
 869   unsigned int length;
 870 #define EXTRACT_FMT_JL_CODE \
 871   length = 2; \
 872   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 873   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 874   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 875   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 876
 877 #define EXTRACT_FMT_JMP_VARS \
 878   /* Instruction fields.  */ \
 879   UINT f_op1; \
 880   UINT f_r1; \
 881   UINT f_op2; \
 882   UINT f_r2; \
 883   unsigned int length;
 884 #define EXTRACT_FMT_JMP_CODE \
 885   length = 2; \
 886   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 887   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 888   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 889   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 890
 891 #define EXTRACT_FMT_LD_VARS \
 892   /* Instruction fields.  */ \
 893   UINT f_op1; \
 894   UINT f_r1; \
 895   UINT f_op2; \
 896   UINT f_r2; \
 897   unsigned int length;
 898 #define EXTRACT_FMT_LD_CODE \
 899   length = 2; \
 900   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 901   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 902   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 903   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 904
 905 #define EXTRACT_FMT_LD_D_VARS \
 906   /* Instruction fields.  */ \
 907   UINT f_op1; \
 908   UINT f_r1; \
 909   UINT f_op2; \
 910   UINT f_r2; \
 911   INT f_simm16; \
 912   unsigned int length;
 913 #define EXTRACT_FMT_LD_D_CODE \
 914   length = 4; \
 915   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 916   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 917   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 918   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 919   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 920
 921 #define EXTRACT_FMT_LDB_VARS \
 922   /* Instruction fields.  */ \
 923   UINT f_op1; \
 924   UINT f_r1; \
 925   UINT f_op2; \
 926   UINT f_r2; \
 927   unsigned int length;
 928 #define EXTRACT_FMT_LDB_CODE \
 929   length = 2; \
 930   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 931   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 932   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 933   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 934
 935 #define EXTRACT_FMT_LDB_D_VARS \
 936   /* Instruction fields.  */ \
 937   UINT f_op1; \
 938   UINT f_r1; \
 939   UINT f_op2; \
 940   UINT f_r2; \
 941   INT f_simm16; \
 942   unsigned int length;
 943 #define EXTRACT_FMT_LDB_D_CODE \
 944   length = 4; \
 945   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 946   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 947   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 948   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 949   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 950
 951 #define EXTRACT_FMT_LDH_VARS \
 952   /* Instruction fields.  */ \
 953   UINT f_op1; \
 954   UINT f_r1; \
 955   UINT f_op2; \
 956   UINT f_r2; \
 957   unsigned int length;
 958 #define EXTRACT_FMT_LDH_CODE \
 959   length = 2; \
 960   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 961   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 962   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 963   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 964
 965 #define EXTRACT_FMT_LDH_D_VARS \
 966   /* Instruction fields.  */ \
 967   UINT f_op1; \
 968   UINT f_r1; \
 969   UINT f_op2; \
 970   UINT f_r2; \
 971   INT f_simm16; \
 972   unsigned int length;
 973 #define EXTRACT_FMT_LDH_D_CODE \
 974   length = 4; \
 975   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 976   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 977   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 978   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 979   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 980
 981 #define EXTRACT_FMT_LD_PLUS_VARS \
 982   /* Instruction fields.  */ \
 983   UINT f_op1; \
 984   UINT f_r1; \
 985   UINT f_op2; \
 986   UINT f_r2; \
 987   unsigned int length;
 988 #define EXTRACT_FMT_LD_PLUS_CODE \
 989   length = 2; \
 990   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 991   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 992   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 993   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 994
 995 #define EXTRACT_FMT_LD24_VARS \
 996   /* Instruction fields.  */ \
 997   UINT f_op1; \
 998   UINT f_r1; \
 999   UINT f_uimm24; \
1000   unsigned int length;
1001 #define EXTRACT_FMT_LD24_CODE \
1002   length = 4; \
1003   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1004   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1005   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
1006
1007 #define EXTRACT_FMT_LDI8_VARS \
1008   /* Instruction fields.  */ \
1009   UINT f_op1; \
1010   UINT f_r1; \
1011   INT f_simm8; \
1012   unsigned int length;
1013 #define EXTRACT_FMT_LDI8_CODE \
1014   length = 2; \
1015   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1016   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1017   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
1018
1019 #define EXTRACT_FMT_LDI16_VARS \
1020   /* Instruction fields.  */ \
1021   UINT f_op1; \
1022   UINT f_r1; \
1023   UINT f_op2; \
1024   UINT f_r2; \
1025   INT f_simm16; \
1026   unsigned int length;
1027 #define EXTRACT_FMT_LDI16_CODE \
1028   length = 4; \
1029   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1030   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1031   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1032   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1033   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1034
1035 #define EXTRACT_FMT_LOCK_VARS \
1036   /* Instruction fields.  */ \
1037   UINT f_op1; \
1038   UINT f_r1; \
1039   UINT f_op2; \
1040   UINT f_r2; \
1041   unsigned int length;
1042 #define EXTRACT_FMT_LOCK_CODE \
1043   length = 2; \
1044   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1045   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1046   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1047   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1048
1049 #define EXTRACT_FMT_MACHI_A_VARS \
1050   /* Instruction fields.  */ \
1051   UINT f_op1; \
1052   UINT f_r1; \
1053   UINT f_acc; \
1054   UINT f_op23; \
1055   UINT f_r2; \
1056   unsigned int length;
1057 #define EXTRACT_FMT_MACHI_A_CODE \
1058   length = 2; \
1059   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1060   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1061   f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1062   f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1063   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1064
1065 #define EXTRACT_FMT_MULHI_A_VARS \
1066   /* Instruction fields.  */ \
1067   UINT f_op1; \
1068   UINT f_r1; \
1069   UINT f_acc; \
1070   UINT f_op23; \
1071   UINT f_r2; \
1072   unsigned int length;
1073 #define EXTRACT_FMT_MULHI_A_CODE \
1074   length = 2; \
1075   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1076   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1077   f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
1078   f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
1079   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1080
1081 #define EXTRACT_FMT_MV_VARS \
1082   /* Instruction fields.  */ \
1083   UINT f_op1; \
1084   UINT f_r1; \
1085   UINT f_op2; \
1086   UINT f_r2; \
1087   unsigned int length;
1088 #define EXTRACT_FMT_MV_CODE \
1089   length = 2; \
1090   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1091   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1092   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1093   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1094
1095 #define EXTRACT_FMT_MVFACHI_A_VARS \
1096   /* Instruction fields.  */ \
1097   UINT f_op1; \
1098   UINT f_r1; \
1099   UINT f_op2; \
1100   UINT f_accs; \
1101   UINT f_op3; \
1102   unsigned int length;
1103 #define EXTRACT_FMT_MVFACHI_A_CODE \
1104   length = 2; \
1105   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1106   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1107   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1108   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1109   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1110
1111 #define EXTRACT_FMT_MVFC_VARS \
1112   /* Instruction fields.  */ \
1113   UINT f_op1; \
1114   UINT f_r1; \
1115   UINT f_op2; \
1116   UINT f_r2; \
1117   unsigned int length;
1118 #define EXTRACT_FMT_MVFC_CODE \
1119   length = 2; \
1120   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1121   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1122   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1123   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1124
1125 #define EXTRACT_FMT_MVTACHI_A_VARS \
1126   /* Instruction fields.  */ \
1127   UINT f_op1; \
1128   UINT f_r1; \
1129   UINT f_op2; \
1130   UINT f_accs; \
1131   UINT f_op3; \
1132   unsigned int length;
1133 #define EXTRACT_FMT_MVTACHI_A_CODE \
1134   length = 2; \
1135   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1136   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1137   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1138   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1139   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
1140
1141 #define EXTRACT_FMT_MVTC_VARS \
1142   /* Instruction fields.  */ \
1143   UINT f_op1; \
1144   UINT f_r1; \
1145   UINT f_op2; \
1146   UINT f_r2; \
1147   unsigned int length;
1148 #define EXTRACT_FMT_MVTC_CODE \
1149   length = 2; \
1150   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1151   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1152   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1153   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1154
1155 #define EXTRACT_FMT_NOP_VARS \
1156   /* Instruction fields.  */ \
1157   UINT f_op1; \
1158   UINT f_r1; \
1159   UINT f_op2; \
1160   UINT f_r2; \
1161   unsigned int length;
1162 #define EXTRACT_FMT_NOP_CODE \
1163   length = 2; \
1164   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1165   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1166   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1167   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1168
1169 #define EXTRACT_FMT_RAC_DSI_VARS \
1170   /* Instruction fields.  */ \
1171   UINT f_op1; \
1172   UINT f_accd; \
1173   UINT f_bits67; \
1174   UINT f_op2; \
1175   UINT f_accs; \
1176   UINT f_bit14; \
1177   SI f_imm1; \
1178   unsigned int length;
1179 #define EXTRACT_FMT_RAC_DSI_CODE \
1180   length = 2; \
1181   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1182   f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
1183   f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
1184   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1185   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
1186   f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
1187   f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
1188
1189 #define EXTRACT_FMT_RTE_VARS \
1190   /* Instruction fields.  */ \
1191   UINT f_op1; \
1192   UINT f_r1; \
1193   UINT f_op2; \
1194   UINT f_r2; \
1195   unsigned int length;
1196 #define EXTRACT_FMT_RTE_CODE \
1197   length = 2; \
1198   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1199   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1200   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1201   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1202
1203 #define EXTRACT_FMT_SETH_VARS \
1204   /* Instruction fields.  */ \
1205   UINT f_op1; \
1206   UINT f_r1; \
1207   UINT f_op2; \
1208   UINT f_r2; \
1209   UINT f_hi16; \
1210   unsigned int length;
1211 #define EXTRACT_FMT_SETH_CODE \
1212   length = 4; \
1213   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1214   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1215   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1216   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1217   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
1218
1219 #define EXTRACT_FMT_SLL3_VARS \
1220   /* Instruction fields.  */ \
1221   UINT f_op1; \
1222   UINT f_r1; \
1223   UINT f_op2; \
1224   UINT f_r2; \
1225   INT f_simm16; \
1226   unsigned int length;
1227 #define EXTRACT_FMT_SLL3_CODE \
1228   length = 4; \
1229   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1230   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1231   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1232   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1233   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1234
1235 #define EXTRACT_FMT_SLLI_VARS \
1236   /* Instruction fields.  */ \
1237   UINT f_op1; \
1238   UINT f_r1; \
1239   UINT f_shift_op2; \
1240   UINT f_uimm5; \
1241   unsigned int length;
1242 #define EXTRACT_FMT_SLLI_CODE \
1243   length = 2; \
1244   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1245   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1246   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
1247   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
1248
1249 #define EXTRACT_FMT_ST_VARS \
1250   /* Instruction fields.  */ \
1251   UINT f_op1; \
1252   UINT f_r1; \
1253   UINT f_op2; \
1254   UINT f_r2; \
1255   unsigned int length;
1256 #define EXTRACT_FMT_ST_CODE \
1257   length = 2; \
1258   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1259   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1260   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1261   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1262
1263 #define EXTRACT_FMT_ST_D_VARS \
1264   /* Instruction fields.  */ \
1265   UINT f_op1; \
1266   UINT f_r1; \
1267   UINT f_op2; \
1268   UINT f_r2; \
1269   INT f_simm16; \
1270   unsigned int length;
1271 #define EXTRACT_FMT_ST_D_CODE \
1272   length = 4; \
1273   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1274   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1275   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1276   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1277   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1278
1279 #define EXTRACT_FMT_STB_VARS \
1280   /* Instruction fields.  */ \
1281   UINT f_op1; \
1282   UINT f_r1; \
1283   UINT f_op2; \
1284   UINT f_r2; \
1285   unsigned int length;
1286 #define EXTRACT_FMT_STB_CODE \
1287   length = 2; \
1288   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1289   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1290   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1291   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1292
1293 #define EXTRACT_FMT_STB_D_VARS \
1294   /* Instruction fields.  */ \
1295   UINT f_op1; \
1296   UINT f_r1; \
1297   UINT f_op2; \
1298   UINT f_r2; \
1299   INT f_simm16; \
1300   unsigned int length;
1301 #define EXTRACT_FMT_STB_D_CODE \
1302   length = 4; \
1303   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1304   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1305   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1306   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1307   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1308
1309 #define EXTRACT_FMT_STH_VARS \
1310   /* Instruction fields.  */ \
1311   UINT f_op1; \
1312   UINT f_r1; \
1313   UINT f_op2; \
1314   UINT f_r2; \
1315   unsigned int length;
1316 #define EXTRACT_FMT_STH_CODE \
1317   length = 2; \
1318   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1319   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1320   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1321   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1322
1323 #define EXTRACT_FMT_STH_D_VARS \
1324   /* Instruction fields.  */ \
1325   UINT f_op1; \
1326   UINT f_r1; \
1327   UINT f_op2; \
1328   UINT f_r2; \
1329   INT f_simm16; \
1330   unsigned int length;
1331 #define EXTRACT_FMT_STH_D_CODE \
1332   length = 4; \
1333   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1334   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1335   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1336   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1337   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
1338
1339 #define EXTRACT_FMT_ST_PLUS_VARS \
1340   /* Instruction fields.  */ \
1341   UINT f_op1; \
1342   UINT f_r1; \
1343   UINT f_op2; \
1344   UINT f_r2; \
1345   unsigned int length;
1346 #define EXTRACT_FMT_ST_PLUS_CODE \
1347   length = 2; \
1348   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1349   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1350   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1351   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1352
1353 #define EXTRACT_FMT_TRAP_VARS \
1354   /* Instruction fields.  */ \
1355   UINT f_op1; \
1356   UINT f_r1; \
1357   UINT f_op2; \
1358   UINT f_uimm4; \
1359   unsigned int length;
1360 #define EXTRACT_FMT_TRAP_CODE \
1361   length = 2; \
1362   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1363   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1364   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1365   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
1366
1367 #define EXTRACT_FMT_UNLOCK_VARS \
1368   /* Instruction fields.  */ \
1369   UINT f_op1; \
1370   UINT f_r1; \
1371   UINT f_op2; \
1372   UINT f_r2; \
1373   unsigned int length;
1374 #define EXTRACT_FMT_UNLOCK_CODE \
1375   length = 2; \
1376   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1377   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1378   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1379   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1380
1381 #define EXTRACT_FMT_SATB_VARS \
1382   /* Instruction fields.  */ \
1383   UINT f_op1; \
1384   UINT f_r1; \
1385   UINT f_op2; \
1386   UINT f_r2; \
1387   UINT f_uimm16; \
1388   unsigned int length;
1389 #define EXTRACT_FMT_SATB_CODE \
1390   length = 4; \
1391   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1392   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1393   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1394   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1395   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1396
1397 #define EXTRACT_FMT_SAT_VARS \
1398   /* Instruction fields.  */ \
1399   UINT f_op1; \
1400   UINT f_r1; \
1401   UINT f_op2; \
1402   UINT f_r2; \
1403   UINT f_uimm16; \
1404   unsigned int length;
1405 #define EXTRACT_FMT_SAT_CODE \
1406   length = 4; \
1407   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
1408   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
1409   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
1410   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
1411   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
1412
1413 #define EXTRACT_FMT_SADD_VARS \
1414   /* Instruction fields.  */ \
1415   UINT f_op1; \
1416   UINT f_r1; \
1417   UINT f_op2; \
1418   UINT f_r2; \
1419   unsigned int length;
1420 #define EXTRACT_FMT_SADD_CODE \
1421   length = 2; \
1422   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1423   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1424   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1425   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1426
1427 #define EXTRACT_FMT_MACWU1_VARS \
1428   /* Instruction fields.  */ \
1429   UINT f_op1; \
1430   UINT f_r1; \
1431   UINT f_op2; \
1432   UINT f_r2; \
1433   unsigned int length;
1434 #define EXTRACT_FMT_MACWU1_CODE \
1435   length = 2; \
1436   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1437   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1438   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1439   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1440
1441 #define EXTRACT_FMT_MSBLO_VARS \
1442   /* Instruction fields.  */ \
1443   UINT f_op1; \
1444   UINT f_r1; \
1445   UINT f_op2; \
1446   UINT f_r2; \
1447   unsigned int length;
1448 #define EXTRACT_FMT_MSBLO_CODE \
1449   length = 2; \
1450   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1451   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1452   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1453   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1454
1455 #define EXTRACT_FMT_MULWU1_VARS \
1456   /* Instruction fields.  */ \
1457   UINT f_op1; \
1458   UINT f_r1; \
1459   UINT f_op2; \
1460   UINT f_r2; \
1461   unsigned int length;
1462 #define EXTRACT_FMT_MULWU1_CODE \
1463   length = 2; \
1464   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1465   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1466   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1467   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1468
1469 #define EXTRACT_FMT_SC_VARS \
1470   /* Instruction fields.  */ \
1471   UINT f_op1; \
1472   UINT f_r1; \
1473   UINT f_op2; \
1474   UINT f_r2; \
1475   unsigned int length;
1476 #define EXTRACT_FMT_SC_CODE \
1477   length = 2; \
1478   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
1479   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
1480   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
1481   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
1482
1483 /* Queued output values of an instruction.  */
1484
1485 struct parexec {
1486   union {
1487     struct { /* empty format for unspecified field list */
1488       int empty;
1489     } fmt_empty;
1490     struct { /* e.g. add $dr,$sr */
1491       SI dr;
1492     } fmt_add;
1493     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1494       SI dr;
1495     } fmt_add3;
1496     struct { /* e.g. and3 $dr,$sr,$uimm16 */
1497       SI dr;
1498     } fmt_and3;
1499     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1500       SI dr;
1501     } fmt_or3;
1502     struct { /* e.g. addi $dr,$simm8 */
1503       SI dr;
1504     } fmt_addi;
1505     struct { /* e.g. addv $dr,$sr */
1506       SI dr;
1507       BI condbit;
1508     } fmt_addv;
1509     struct { /* e.g. addv3 $dr,$sr,$simm16 */
1510       SI dr;
1511       BI condbit;
1512     } fmt_addv3;
1513     struct { /* e.g. addx $dr,$sr */
1514       SI dr;
1515       BI condbit;
1516     } fmt_addx;
1517     struct { /* e.g. bc.s $disp8 */
1518       USI pc;
1519     } fmt_bc8;
1520     struct { /* e.g. bc.l $disp24 */
1521       USI pc;
1522     } fmt_bc24;
1523     struct { /* e.g. beq $src1,$src2,$disp16 */
1524       USI pc;
1525     } fmt_beq;
1526     struct { /* e.g. beqz $src2,$disp16 */
1527       USI pc;
1528     } fmt_beqz;
1529     struct { /* e.g. bl.s $disp8 */
1530       SI h_gr_14;
1531       USI pc;
1532     } fmt_bl8;
1533     struct { /* e.g. bl.l $disp24 */
1534       SI h_gr_14;
1535       USI pc;
1536     } fmt_bl24;
1537     struct { /* e.g. bcl.s $disp8 */
1538       SI h_gr_14;
1539       USI pc;
1540     } fmt_bcl8;
1541     struct { /* e.g. bcl.l $disp24 */
1542       SI h_gr_14;
1543       USI pc;
1544     } fmt_bcl24;
1545     struct { /* e.g. bra.s $disp8 */
1546       USI pc;
1547     } fmt_bra8;
1548     struct { /* e.g. bra.l $disp24 */
1549       USI pc;
1550     } fmt_bra24;
1551     struct { /* e.g. cmp $src1,$src2 */
1552       BI condbit;
1553     } fmt_cmp;
1554     struct { /* e.g. cmpi $src2,$simm16 */
1555       BI condbit;
1556     } fmt_cmpi;
1557     struct { /* e.g. cmpz $src2 */
1558       BI condbit;
1559     } fmt_cmpz;
1560     struct { /* e.g. div $dr,$sr */
1561       SI dr;
1562     } fmt_div;
1563     struct { /* e.g. jc $sr */
1564       USI pc;
1565     } fmt_jc;
1566     struct { /* e.g. jl $sr */
1567       SI h_gr_14;
1568       USI pc;
1569     } fmt_jl;
1570     struct { /* e.g. jmp $sr */
1571       USI pc;
1572     } fmt_jmp;
1573     struct { /* e.g. ld $dr,@$sr */
1574       SI dr;
1575     } fmt_ld;
1576     struct { /* e.g. ld $dr,@($slo16,$sr) */
1577       SI dr;
1578     } fmt_ld_d;
1579     struct { /* e.g. ldb $dr,@$sr */
1580       SI dr;
1581     } fmt_ldb;
1582     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1583       SI dr;
1584     } fmt_ldb_d;
1585     struct { /* e.g. ldh $dr,@$sr */
1586       SI dr;
1587     } fmt_ldh;
1588     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1589       SI dr;
1590     } fmt_ldh_d;
1591     struct { /* e.g. ld $dr,@$sr+ */
1592       SI dr;
1593       SI sr;
1594     } fmt_ld_plus;
1595     struct { /* e.g. ld24 $dr,$uimm24 */
1596       SI dr;
1597     } fmt_ld24;
1598     struct { /* e.g. ldi8 $dr,$simm8 */
1599       SI dr;
1600     } fmt_ldi8;
1601     struct { /* e.g. ldi16 $dr,$hash$slo16 */
1602       SI dr;
1603     } fmt_ldi16;
1604     struct { /* e.g. lock $dr,@$sr */
1605       BI h_lock_0;
1606       SI dr;
1607     } fmt_lock;
1608     struct { /* e.g. machi $src1,$src2,$acc */
1609       DI acc;
1610     } fmt_machi_a;
1611     struct { /* e.g. mulhi $src1,$src2,$acc */
1612       DI acc;
1613     } fmt_mulhi_a;
1614     struct { /* e.g. mv $dr,$sr */
1615       SI dr;
1616     } fmt_mv;
1617     struct { /* e.g. mvfachi $dr,$accs */
1618       SI dr;
1619     } fmt_mvfachi_a;
1620     struct { /* e.g. mvfc $dr,$scr */
1621       SI dr;
1622     } fmt_mvfc;
1623     struct { /* e.g. mvtachi $src1,$accs */
1624       DI accs;
1625     } fmt_mvtachi_a;
1626     struct { /* e.g. mvtc $sr,$dcr */
1627       USI dcr;
1628     } fmt_mvtc;
1629     struct { /* e.g. nop */
1630       int empty;
1631     } fmt_nop;
1632     struct { /* e.g. rac $accd,$accs,$imm1 */
1633       DI accd;
1634     } fmt_rac_dsi;
1635     struct { /* e.g. rte */
1636       USI pc;
1637       USI h_cr_6;
1638       UQI h_psw_0;
1639       UQI h_bpsw_0;
1640     } fmt_rte;
1641     struct { /* e.g. seth $dr,$hash$hi16 */
1642       SI dr;
1643     } fmt_seth;
1644     struct { /* e.g. sll3 $dr,$sr,$simm16 */
1645       SI dr;
1646     } fmt_sll3;
1647     struct { /* e.g. slli $dr,$uimm5 */
1648       SI dr;
1649     } fmt_slli;
1650     struct { /* e.g. st $src1,@$src2 */
1651       SI h_memory_src2;
1652       USI h_memory_src2_idx;
1653     } fmt_st;
1654     struct { /* e.g. st $src1,@($slo16,$src2) */
1655       SI h_memory_add__VM_src2_slo16;
1656       USI h_memory_add__VM_src2_slo16_idx;
1657     } fmt_st_d;
1658     struct { /* e.g. stb $src1,@$src2 */
1659       QI h_memory_src2;
1660       USI h_memory_src2_idx;
1661     } fmt_stb;
1662     struct { /* e.g. stb $src1,@($slo16,$src2) */
1663       QI h_memory_add__VM_src2_slo16;
1664       USI h_memory_add__VM_src2_slo16_idx;
1665     } fmt_stb_d;
1666     struct { /* e.g. sth $src1,@$src2 */
1667       HI h_memory_src2;
1668       USI h_memory_src2_idx;
1669     } fmt_sth;
1670     struct { /* e.g. sth $src1,@($slo16,$src2) */
1671       HI h_memory_add__VM_src2_slo16;
1672       USI h_memory_add__VM_src2_slo16_idx;
1673     } fmt_sth_d;
1674     struct { /* e.g. st $src1,@+$src2 */
1675       SI h_memory_new_src2;
1676       USI h_memory_new_src2_idx;
1677       SI src2;
1678     } fmt_st_plus;
1679     struct { /* e.g. trap $uimm4 */
1680       USI h_cr_14;
1681       USI h_cr_6;
1682       UQI h_bbpsw_0;
1683       UQI h_bpsw_0;
1684       UQI h_psw_0;
1685       SI pc;
1686     } fmt_trap;
1687     struct { /* e.g. unlock $src1,@$src2 */
1688       SI h_memory_src2;
1689       USI h_memory_src2_idx;
1690       BI h_lock_0;
1691     } fmt_unlock;
1692     struct { /* e.g. satb $dr,$sr */
1693       SI dr;
1694     } fmt_satb;
1695     struct { /* e.g. sat $dr,$sr */
1696       SI dr;
1697     } fmt_sat;
1698     struct { /* e.g. sadd */
1699       DI h_accums_0;
1700     } fmt_sadd;
1701     struct { /* e.g. macwu1 $src1,$src2 */
1702       DI h_accums_1;
1703     } fmt_macwu1;
1704     struct { /* e.g. msblo $src1,$src2 */
1705       DI accum;
1706     } fmt_msblo;
1707     struct { /* e.g. mulwu1 $src1,$src2 */
1708       DI h_accums_1;
1709     } fmt_mulwu1;
1710     struct { /* e.g. sc */
1711       int empty;
1712     } fmt_sc;
1713   } operands;
1714   /* For conditionally written operands, bitmask of which ones were.  */
1715   int written;
1716 };
1717
1718 /* Collection of various things for the trace handler to use.  */
1719
1720 typedef struct trace_record {
1721   PCADDR pc;
1722   /* FIXME:wip */
1723 } TRACE_RECORD;
1724
1725 #endif /* CPU_M32RXF_H */