sim/m32r/cpux.h

   1 /* CPU family header for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RXF_H
  26 #define CPU_M32RXF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RXF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rxf_h_pc_get (SIM_CPU *);
  89 void m32rxf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rxf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rxf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rxf_h_accum_get (SIM_CPU *);
  95 void m32rxf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rxf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rxf_h_cond_get (SIM_CPU *);
  99 void m32rxf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rxf_h_psw_get (SIM_CPU *);
 101 void m32rxf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rxf_h_bpsw_get (SIM_CPU *);
 103 void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rxf_h_bbpsw_get (SIM_CPU *);
 105 void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rxf_h_lock_get (SIM_CPU *);
 107 void m32rxf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rxf_fetch_register;
 111 extern CPUREG_STORE_FN m32rxf_store_register;
 112
 113 typedef struct {
 114   int empty;
 115 } MODEL_M32RX_DATA;
 116
 117 union sem_fields {
 118     struct { /* empty sformat for unspecified field list */
 119       int empty;
 120     } fmt_empty;
 121     struct { /* e.g. add $dr,$sr */
 122       SI * i_dr;
 123       SI * i_sr;
 124       unsigned char in_dr;
 125       unsigned char in_sr;
 126       unsigned char out_dr;
 127     } fmt_add;
 128     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 129       INT f_simm16;
 130       SI * i_sr;
 131       SI * i_dr;
 132       unsigned char in_sr;
 133       unsigned char out_dr;
 134     } fmt_add3;
 135     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 136       UINT f_uimm16;
 137       SI * i_sr;
 138       SI * i_dr;
 139       unsigned char in_sr;
 140       unsigned char out_dr;
 141     } fmt_and3;
 142     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 143       UINT f_uimm16;
 144       SI * i_sr;
 145       SI * i_dr;
 146       unsigned char in_sr;
 147       unsigned char out_dr;
 148     } fmt_or3;
 149     struct { /* e.g. addi $dr,$simm8 */
 150       INT f_simm8;
 151       SI * i_dr;
 152       unsigned char in_dr;
 153       unsigned char out_dr;
 154     } fmt_addi;
 155     struct { /* e.g. addv $dr,$sr */
 156       SI * i_dr;
 157       SI * i_sr;
 158       unsigned char in_dr;
 159       unsigned char in_sr;
 160       unsigned char out_dr;
 161     } fmt_addv;
 162     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 163       INT f_simm16;
 164       SI * i_sr;
 165       SI * i_dr;
 166       unsigned char in_sr;
 167       unsigned char out_dr;
 168     } fmt_addv3;
 169     struct { /* e.g. addx $dr,$sr */
 170       SI * i_dr;
 171       SI * i_sr;
 172       unsigned char in_dr;
 173       unsigned char in_sr;
 174       unsigned char out_dr;
 175     } fmt_addx;
 176     struct { /* e.g. cmp $src1,$src2 */
 177       SI * i_src1;
 178       SI * i_src2;
 179       unsigned char in_src1;
 180       unsigned char in_src2;
 181     } fmt_cmp;
 182     struct { /* e.g. cmpi $src2,$simm16 */
 183       INT f_simm16;
 184       SI * i_src2;
 185       unsigned char in_src2;
 186     } fmt_cmpi;
 187     struct { /* e.g. cmpz $src2 */
 188       SI * i_src2;
 189       unsigned char in_src2;
 190     } fmt_cmpz;
 191     struct { /* e.g. div $dr,$sr */
 192       SI * i_dr;
 193       SI * i_sr;
 194       unsigned char in_dr;
 195       unsigned char in_sr;
 196       unsigned char out_dr;
 197     } fmt_div;
 198     struct { /* e.g. ld $dr,@$sr */
 199       SI * i_sr;
 200       SI * i_dr;
 201       unsigned char in_sr;
 202       unsigned char out_dr;
 203     } fmt_ld;
 204     struct { /* e.g. ld $dr,@($slo16,$sr) */
 205       INT f_simm16;
 206       SI * i_sr;
 207       SI * i_dr;
 208       unsigned char in_sr;
 209       unsigned char out_dr;
 210     } fmt_ld_d;
 211     struct { /* e.g. ldb $dr,@$sr */
 212       SI * i_sr;
 213       SI * i_dr;
 214       unsigned char in_sr;
 215       unsigned char out_dr;
 216     } fmt_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       INT f_simm16;
 219       SI * i_sr;
 220       SI * i_dr;
 221       unsigned char in_sr;
 222       unsigned char out_dr;
 223     } fmt_ldb_d;
 224     struct { /* e.g. ldh $dr,@$sr */
 225       SI * i_sr;
 226       SI * i_dr;
 227       unsigned char in_sr;
 228       unsigned char out_dr;
 229     } fmt_ldh;
 230     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 231       INT f_simm16;
 232       SI * i_sr;
 233       SI * i_dr;
 234       unsigned char in_sr;
 235       unsigned char out_dr;
 236     } fmt_ldh_d;
 237     struct { /* e.g. ld $dr,@$sr+ */
 238       SI * i_sr;
 239       SI * i_dr;
 240       unsigned char in_sr;
 241       unsigned char out_dr;
 242       unsigned char out_sr;
 243     } fmt_ld_plus;
 244     struct { /* e.g. ld24 $dr,$uimm24 */
 245       ADDR i_uimm24;
 246       SI * i_dr;
 247       unsigned char out_dr;
 248     } fmt_ld24;
 249     struct { /* e.g. ldi8 $dr,$simm8 */
 250       INT f_simm8;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ldi8;
 254     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 255       INT f_simm16;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi16;
 259     struct { /* e.g. lock $dr,@$sr */
 260       SI * i_sr;
 261       SI * i_dr;
 262       unsigned char in_sr;
 263       unsigned char out_dr;
 264     } fmt_lock;
 265     struct { /* e.g. machi $src1,$src2,$acc */
 266       UINT f_acc;
 267       SI * i_src1;
 268       SI * i_src2;
 269       unsigned char in_src1;
 270       unsigned char in_src2;
 271     } fmt_machi_a;
 272     struct { /* e.g. mulhi $src1,$src2,$acc */
 273       UINT f_acc;
 274       SI * i_src1;
 275       SI * i_src2;
 276       unsigned char in_src1;
 277       unsigned char in_src2;
 278     } fmt_mulhi_a;
 279     struct { /* e.g. mv $dr,$sr */
 280       SI * i_sr;
 281       SI * i_dr;
 282       unsigned char in_sr;
 283       unsigned char out_dr;
 284     } fmt_mv;
 285     struct { /* e.g. mvfachi $dr,$accs */
 286       UINT f_accs;
 287       SI * i_dr;
 288       unsigned char out_dr;
 289     } fmt_mvfachi_a;
 290     struct { /* e.g. mvfc $dr,$scr */
 291       UINT f_r2;
 292       SI * i_dr;
 293       unsigned char out_dr;
 294     } fmt_mvfc;
 295     struct { /* e.g. mvtachi $src1,$accs */
 296       UINT f_accs;
 297       SI * i_src1;
 298       unsigned char in_src1;
 299     } fmt_mvtachi_a;
 300     struct { /* e.g. mvtc $sr,$dcr */
 301       UINT f_r1;
 302       SI * i_sr;
 303       unsigned char in_sr;
 304     } fmt_mvtc;
 305     struct { /* e.g. nop */
 306       int empty;
 307     } fmt_nop;
 308     struct { /* e.g. rac $accd,$accs,$imm1 */
 309       UINT f_accs;
 310       SI f_imm1;
 311       UINT f_accd;
 312     } fmt_rac_dsi;
 313     struct { /* e.g. seth $dr,$hash$hi16 */
 314       UINT f_hi16;
 315       SI * i_dr;
 316       unsigned char out_dr;
 317     } fmt_seth;
 318     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 319       INT f_simm16;
 320       SI * i_sr;
 321       SI * i_dr;
 322       unsigned char in_sr;
 323       unsigned char out_dr;
 324     } fmt_sll3;
 325     struct { /* e.g. slli $dr,$uimm5 */
 326       UINT f_uimm5;
 327       SI * i_dr;
 328       unsigned char in_dr;
 329       unsigned char out_dr;
 330     } fmt_slli;
 331     struct { /* e.g. st $src1,@$src2 */
 332       SI * i_src1;
 333       SI * i_src2;
 334       unsigned char in_src1;
 335       unsigned char in_src2;
 336     } fmt_st;
 337     struct { /* e.g. st $src1,@($slo16,$src2) */
 338       INT f_simm16;
 339       SI * i_src1;
 340       SI * i_src2;
 341       unsigned char in_src1;
 342       unsigned char in_src2;
 343     } fmt_st_d;
 344     struct { /* e.g. stb $src1,@$src2 */
 345       SI * i_src1;
 346       SI * i_src2;
 347       unsigned char in_src1;
 348       unsigned char in_src2;
 349     } fmt_stb;
 350     struct { /* e.g. stb $src1,@($slo16,$src2) */
 351       INT f_simm16;
 352       SI * i_src1;
 353       SI * i_src2;
 354       unsigned char in_src1;
 355       unsigned char in_src2;
 356     } fmt_stb_d;
 357     struct { /* e.g. sth $src1,@$src2 */
 358       SI * i_src1;
 359       SI * i_src2;
 360       unsigned char in_src1;
 361       unsigned char in_src2;
 362     } fmt_sth;
 363     struct { /* e.g. sth $src1,@($slo16,$src2) */
 364       INT f_simm16;
 365       SI * i_src1;
 366       SI * i_src2;
 367       unsigned char in_src1;
 368       unsigned char in_src2;
 369     } fmt_sth_d;
 370     struct { /* e.g. st $src1,@+$src2 */
 371       SI * i_src1;
 372       SI * i_src2;
 373       unsigned char in_src1;
 374       unsigned char in_src2;
 375       unsigned char out_src2;
 376     } fmt_st_plus;
 377     struct { /* e.g. unlock $src1,@$src2 */
 378       SI * i_src1;
 379       SI * i_src2;
 380       unsigned char in_src1;
 381       unsigned char in_src2;
 382     } fmt_unlock;
 383     struct { /* e.g. satb $dr,$sr */
 384       SI * i_sr;
 385       SI * i_dr;
 386       unsigned char in_sr;
 387       unsigned char out_dr;
 388     } fmt_satb;
 389     struct { /* e.g. sat $dr,$sr */
 390       SI * i_sr;
 391       SI * i_dr;
 392       unsigned char in_sr;
 393       unsigned char out_dr;
 394     } fmt_sat;
 395     struct { /* e.g. sadd */
 396       int empty;
 397     } fmt_sadd;
 398     struct { /* e.g. macwu1 $src1,$src2 */
 399       SI * i_src1;
 400       SI * i_src2;
 401       unsigned char in_src1;
 402       unsigned char in_src2;
 403     } fmt_macwu1;
 404     struct { /* e.g. msblo $src1,$src2 */
 405       SI * i_src1;
 406       SI * i_src2;
 407       unsigned char in_src1;
 408       unsigned char in_src2;
 409     } fmt_msblo;
 410     struct { /* e.g. mulwu1 $src1,$src2 */
 411       SI * i_src1;
 412       SI * i_src2;
 413       unsigned char in_src1;
 414       unsigned char in_src2;
 415     } fmt_mulwu1;
 416   /* cti insns, kept separately so addr_cache is in fixed place */
 417   struct {
 418     union {
 419     struct { /* e.g. bc.s $disp8 */
 420       IADDR i_disp8;
 421     } fmt_bc8;
 422     struct { /* e.g. bc.l $disp24 */
 423       IADDR i_disp24;
 424     } fmt_bc24;
 425     struct { /* e.g. beq $src1,$src2,$disp16 */
 426       IADDR i_disp16;
 427       SI * i_src1;
 428       SI * i_src2;
 429       unsigned char in_src1;
 430       unsigned char in_src2;
 431     } fmt_beq;
 432     struct { /* e.g. beqz $src2,$disp16 */
 433       IADDR i_disp16;
 434       SI * i_src2;
 435       unsigned char in_src2;
 436     } fmt_beqz;
 437     struct { /* e.g. bl.s $disp8 */
 438       IADDR i_disp8;
 439       unsigned char out_h_gr_14;
 440     } fmt_bl8;
 441     struct { /* e.g. bl.l $disp24 */
 442       IADDR i_disp24;
 443       unsigned char out_h_gr_14;
 444     } fmt_bl24;
 445     struct { /* e.g. bcl.s $disp8 */
 446       IADDR i_disp8;
 447       unsigned char out_h_gr_14;
 448     } fmt_bcl8;
 449     struct { /* e.g. bcl.l $disp24 */
 450       IADDR i_disp24;
 451       unsigned char out_h_gr_14;
 452     } fmt_bcl24;
 453     struct { /* e.g. bra.s $disp8 */
 454       IADDR i_disp8;
 455     } fmt_bra8;
 456     struct { /* e.g. bra.l $disp24 */
 457       IADDR i_disp24;
 458     } fmt_bra24;
 459     struct { /* e.g. jc $sr */
 460       SI * i_sr;
 461       unsigned char in_sr;
 462     } fmt_jc;
 463     struct { /* e.g. jl $sr */
 464       SI * i_sr;
 465       unsigned char in_sr;
 466       unsigned char out_h_gr_14;
 467     } fmt_jl;
 468     struct { /* e.g. jmp $sr */
 469       SI * i_sr;
 470       unsigned char in_sr;
 471     } fmt_jmp;
 472     struct { /* e.g. rte */
 473       int empty;
 474     } fmt_rte;
 475     struct { /* e.g. trap $uimm4 */
 476       UINT f_uimm4;
 477     } fmt_trap;
 478     struct { /* e.g. sc */
 479       int empty;
 480     } fmt_sc;
 481     } fields;
 482 #if WITH_SCACHE_PBB
 483     SEM_PC addr_cache;
 484 #endif
 485   } cti;
 486 #if WITH_SCACHE_PBB
 487   /* Writeback handler.  */
 488   struct {
 489     /* Pointer to argbuf entry for insn whose results need writing back.  */
 490     const struct argbuf *abuf;
 491   } write;
 492   /* x-before handler */
 493   struct {
 494     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 495     int first_p;
 496   } before;
 497   /* x-after handler */
 498   struct {
 499     int empty;
 500   } after;
 501   /* This entry is used to terminate each pbb.  */
 502   struct {
 503     /* Number of insns in pbb.  */
 504     int insn_count;
 505     /* Next pbb to execute.  */
 506     SCACHE *next;
 507   } chain;
 508 #endif
 509 };
 510
 511 /* The ARGBUF struct.  */
 512 struct argbuf {
 513   /* These are the baseclass definitions.  */
 514   IADDR addr;
 515   const IDESC *idesc;
 516   char trace_p;
 517   char profile_p;
 518   /* cpu specific data follows */
 519   union sem semantic;
 520   int written;
 521   union sem_fields fields;
 522 };
 523
 524 /* A cached insn.
 525
 526    ??? SCACHE used to contain more than just argbuf.  We could delete the
 527    type entirely and always just use ARGBUF, but for future concerns and as
 528    a level of abstraction it is left in.  */
 529
 530 struct scache {
 531   struct argbuf argbuf;
 532 };
 533
 534 /* Macros to simplify extraction, reading and semantic code.
 535    These define and assign the local vars that contain the insn's fields.  */
 536
 537 #define EXTRACT_IFMT_EMPTY_VARS \
 538   /* Instruction fields.  */ \
 539   unsigned int length;
 540 #define EXTRACT_IFMT_EMPTY_CODE \
 541   length = 0; \
 542
 543 #define EXTRACT_IFMT_ADD_VARS \
 544   /* Instruction fields.  */ \
 545   UINT f_op1; \
 546   UINT f_r1; \
 547   UINT f_op2; \
 548   UINT f_r2; \
 549   unsigned int length;
 550 #define EXTRACT_IFMT_ADD_CODE \
 551   length = 2; \
 552   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 553   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 554   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 555   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 556
 557 #define EXTRACT_IFMT_ADD3_VARS \
 558   /* Instruction fields.  */ \
 559   UINT f_op1; \
 560   UINT f_r1; \
 561   UINT f_op2; \
 562   UINT f_r2; \
 563   INT f_simm16; \
 564   unsigned int length;
 565 #define EXTRACT_IFMT_ADD3_CODE \
 566   length = 4; \
 567   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 568   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 569   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 570   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 571   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 572
 573 #define EXTRACT_IFMT_AND3_VARS \
 574   /* Instruction fields.  */ \
 575   UINT f_op1; \
 576   UINT f_r1; \
 577   UINT f_op2; \
 578   UINT f_r2; \
 579   UINT f_uimm16; \
 580   unsigned int length;
 581 #define EXTRACT_IFMT_AND3_CODE \
 582   length = 4; \
 583   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 584   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 585   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 586   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 587   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 588
 589 #define EXTRACT_IFMT_OR3_VARS \
 590   /* Instruction fields.  */ \
 591   UINT f_op1; \
 592   UINT f_r1; \
 593   UINT f_op2; \
 594   UINT f_r2; \
 595   UINT f_uimm16; \
 596   unsigned int length;
 597 #define EXTRACT_IFMT_OR3_CODE \
 598   length = 4; \
 599   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 600   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 601   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 602   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 603   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 604
 605 #define EXTRACT_IFMT_ADDI_VARS \
 606   /* Instruction fields.  */ \
 607   UINT f_op1; \
 608   UINT f_r1; \
 609   INT f_simm8; \
 610   unsigned int length;
 611 #define EXTRACT_IFMT_ADDI_CODE \
 612   length = 2; \
 613   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 614   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 615   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 616
 617 #define EXTRACT_IFMT_ADDV3_VARS \
 618   /* Instruction fields.  */ \
 619   UINT f_op1; \
 620   UINT f_r1; \
 621   UINT f_op2; \
 622   UINT f_r2; \
 623   INT f_simm16; \
 624   unsigned int length;
 625 #define EXTRACT_IFMT_ADDV3_CODE \
 626   length = 4; \
 627   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 628   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 629   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 630   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 631   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 632
 633 #define EXTRACT_IFMT_BC8_VARS \
 634   /* Instruction fields.  */ \
 635   UINT f_op1; \
 636   UINT f_r1; \
 637   SI f_disp8; \
 638   unsigned int length;
 639 #define EXTRACT_IFMT_BC8_CODE \
 640   length = 2; \
 641   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 642   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 643   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 644
 645 #define EXTRACT_IFMT_BC24_VARS \
 646   /* Instruction fields.  */ \
 647   UINT f_op1; \
 648   UINT f_r1; \
 649   SI f_disp24; \
 650   unsigned int length;
 651 #define EXTRACT_IFMT_BC24_CODE \
 652   length = 4; \
 653   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 654   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 655   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 656
 657 #define EXTRACT_IFMT_BEQ_VARS \
 658   /* Instruction fields.  */ \
 659   UINT f_op1; \
 660   UINT f_r1; \
 661   UINT f_op2; \
 662   UINT f_r2; \
 663   SI f_disp16; \
 664   unsigned int length;
 665 #define EXTRACT_IFMT_BEQ_CODE \
 666   length = 4; \
 667   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 668   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 669   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 670   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 671   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 672
 673 #define EXTRACT_IFMT_BEQZ_VARS \
 674   /* Instruction fields.  */ \
 675   UINT f_op1; \
 676   UINT f_r1; \
 677   UINT f_op2; \
 678   UINT f_r2; \
 679   SI f_disp16; \
 680   unsigned int length;
 681 #define EXTRACT_IFMT_BEQZ_CODE \
 682   length = 4; \
 683   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 684   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 685   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 686   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 687   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 688
 689 #define EXTRACT_IFMT_CMP_VARS \
 690   /* Instruction fields.  */ \
 691   UINT f_op1; \
 692   UINT f_r1; \
 693   UINT f_op2; \
 694   UINT f_r2; \
 695   unsigned int length;
 696 #define EXTRACT_IFMT_CMP_CODE \
 697   length = 2; \
 698   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 699   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 700   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 701   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 702
 703 #define EXTRACT_IFMT_CMPI_VARS \
 704   /* Instruction fields.  */ \
 705   UINT f_op1; \
 706   UINT f_r1; \
 707   UINT f_op2; \
 708   UINT f_r2; \
 709   INT f_simm16; \
 710   unsigned int length;
 711 #define EXTRACT_IFMT_CMPI_CODE \
 712   length = 4; \
 713   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 714   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 715   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 716   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 717   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 718
 719 #define EXTRACT_IFMT_CMPZ_VARS \
 720   /* Instruction fields.  */ \
 721   UINT f_op1; \
 722   UINT f_r1; \
 723   UINT f_op2; \
 724   UINT f_r2; \
 725   unsigned int length;
 726 #define EXTRACT_IFMT_CMPZ_CODE \
 727   length = 2; \
 728   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 729   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 730   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 731   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 732
 733 #define EXTRACT_IFMT_DIV_VARS \
 734   /* Instruction fields.  */ \
 735   UINT f_op1; \
 736   UINT f_r1; \
 737   UINT f_op2; \
 738   UINT f_r2; \
 739   INT f_simm16; \
 740   unsigned int length;
 741 #define EXTRACT_IFMT_DIV_CODE \
 742   length = 4; \
 743   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 744   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 745   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 746   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 747   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 748
 749 #define EXTRACT_IFMT_JC_VARS \
 750   /* Instruction fields.  */ \
 751   UINT f_op1; \
 752   UINT f_r1; \
 753   UINT f_op2; \
 754   UINT f_r2; \
 755   unsigned int length;
 756 #define EXTRACT_IFMT_JC_CODE \
 757   length = 2; \
 758   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 759   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 760   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 761   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 762
 763 #define EXTRACT_IFMT_LD24_VARS \
 764   /* Instruction fields.  */ \
 765   UINT f_op1; \
 766   UINT f_r1; \
 767   UINT f_uimm24; \
 768   unsigned int length;
 769 #define EXTRACT_IFMT_LD24_CODE \
 770   length = 4; \
 771   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 772   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 773   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 774
 775 #define EXTRACT_IFMT_LDI16_VARS \
 776   /* Instruction fields.  */ \
 777   UINT f_op1; \
 778   UINT f_r1; \
 779   UINT f_op2; \
 780   UINT f_r2; \
 781   INT f_simm16; \
 782   unsigned int length;
 783 #define EXTRACT_IFMT_LDI16_CODE \
 784   length = 4; \
 785   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 786   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 787   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 788   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 789   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 790
 791 #define EXTRACT_IFMT_MACHI_A_VARS \
 792   /* Instruction fields.  */ \
 793   UINT f_op1; \
 794   UINT f_r1; \
 795   UINT f_acc; \
 796   UINT f_op23; \
 797   UINT f_r2; \
 798   unsigned int length;
 799 #define EXTRACT_IFMT_MACHI_A_CODE \
 800   length = 2; \
 801   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 802   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 803   f_acc = EXTRACT_UINT (insn, 16, 8, 1); \
 804   f_op23 = EXTRACT_UINT (insn, 16, 9, 3); \
 805   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 806
 807 #define EXTRACT_IFMT_MVFACHI_A_VARS \
 808   /* Instruction fields.  */ \
 809   UINT f_op1; \
 810   UINT f_r1; \
 811   UINT f_op2; \
 812   UINT f_accs; \
 813   UINT f_op3; \
 814   unsigned int length;
 815 #define EXTRACT_IFMT_MVFACHI_A_CODE \
 816   length = 2; \
 817   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 818   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 819   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 820   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
 821   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
 822
 823 #define EXTRACT_IFMT_MVFC_VARS \
 824   /* Instruction fields.  */ \
 825   UINT f_op1; \
 826   UINT f_r1; \
 827   UINT f_op2; \
 828   UINT f_r2; \
 829   unsigned int length;
 830 #define EXTRACT_IFMT_MVFC_CODE \
 831   length = 2; \
 832   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 833   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 834   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 835   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 836
 837 #define EXTRACT_IFMT_MVTACHI_A_VARS \
 838   /* Instruction fields.  */ \
 839   UINT f_op1; \
 840   UINT f_r1; \
 841   UINT f_op2; \
 842   UINT f_accs; \
 843   UINT f_op3; \
 844   unsigned int length;
 845 #define EXTRACT_IFMT_MVTACHI_A_CODE \
 846   length = 2; \
 847   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 848   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 849   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 850   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
 851   f_op3 = EXTRACT_UINT (insn, 16, 14, 2); \
 852
 853 #define EXTRACT_IFMT_MVTC_VARS \
 854   /* Instruction fields.  */ \
 855   UINT f_op1; \
 856   UINT f_r1; \
 857   UINT f_op2; \
 858   UINT f_r2; \
 859   unsigned int length;
 860 #define EXTRACT_IFMT_MVTC_CODE \
 861   length = 2; \
 862   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 863   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 864   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 865   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 866
 867 #define EXTRACT_IFMT_NOP_VARS \
 868   /* Instruction fields.  */ \
 869   UINT f_op1; \
 870   UINT f_r1; \
 871   UINT f_op2; \
 872   UINT f_r2; \
 873   unsigned int length;
 874 #define EXTRACT_IFMT_NOP_CODE \
 875   length = 2; \
 876   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 877   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 878   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 879   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 880
 881 #define EXTRACT_IFMT_RAC_DSI_VARS \
 882   /* Instruction fields.  */ \
 883   UINT f_op1; \
 884   UINT f_accd; \
 885   UINT f_bits67; \
 886   UINT f_op2; \
 887   UINT f_accs; \
 888   UINT f_bit14; \
 889   SI f_imm1; \
 890   unsigned int length;
 891 #define EXTRACT_IFMT_RAC_DSI_CODE \
 892   length = 2; \
 893   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 894   f_accd = EXTRACT_UINT (insn, 16, 4, 2); \
 895   f_bits67 = EXTRACT_UINT (insn, 16, 6, 2); \
 896   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 897   f_accs = EXTRACT_UINT (insn, 16, 12, 2); \
 898   f_bit14 = EXTRACT_UINT (insn, 16, 14, 1); \
 899   f_imm1 = ((EXTRACT_UINT (insn, 16, 15, 1)) + (1)); \
 900
 901 #define EXTRACT_IFMT_SETH_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   UINT f_op2; \
 906   UINT f_r2; \
 907   UINT f_hi16; \
 908   unsigned int length;
 909 #define EXTRACT_IFMT_SETH_CODE \
 910   length = 4; \
 911   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 912   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 913   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 914   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 915   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 916
 917 #define EXTRACT_IFMT_SLLI_VARS \
 918   /* Instruction fields.  */ \
 919   UINT f_op1; \
 920   UINT f_r1; \
 921   UINT f_shift_op2; \
 922   UINT f_uimm5; \
 923   unsigned int length;
 924 #define EXTRACT_IFMT_SLLI_CODE \
 925   length = 2; \
 926   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 927   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 928   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
 929   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 930
 931 #define EXTRACT_IFMT_ST_D_VARS \
 932   /* Instruction fields.  */ \
 933   UINT f_op1; \
 934   UINT f_r1; \
 935   UINT f_op2; \
 936   UINT f_r2; \
 937   INT f_simm16; \
 938   unsigned int length;
 939 #define EXTRACT_IFMT_ST_D_CODE \
 940   length = 4; \
 941   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 942   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 943   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 944   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 945   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 946
 947 #define EXTRACT_IFMT_TRAP_VARS \
 948   /* Instruction fields.  */ \
 949   UINT f_op1; \
 950   UINT f_r1; \
 951   UINT f_op2; \
 952   UINT f_uimm4; \
 953   unsigned int length;
 954 #define EXTRACT_IFMT_TRAP_CODE \
 955   length = 2; \
 956   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 957   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 958   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 959   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 960
 961 #define EXTRACT_IFMT_SATB_VARS \
 962   /* Instruction fields.  */ \
 963   UINT f_op1; \
 964   UINT f_r1; \
 965   UINT f_op2; \
 966   UINT f_r2; \
 967   UINT f_uimm16; \
 968   unsigned int length;
 969 #define EXTRACT_IFMT_SATB_CODE \
 970   length = 4; \
 971   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 972   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 973   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 974   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 975   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 976
 977 /* Queued output values of an instruction.  */
 978
 979 struct parexec {
 980   union {
 981     struct { /* empty sformat for unspecified field list */
 982       int empty;
 983     } fmt_empty;
 984     struct { /* e.g. add $dr,$sr */
 985       SI dr;
 986     } fmt_add;
 987     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 988       SI dr;
 989     } fmt_add3;
 990     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 991       SI dr;
 992     } fmt_and3;
 993     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 994       SI dr;
 995     } fmt_or3;
 996     struct { /* e.g. addi $dr,$simm8 */
 997       SI dr;
 998     } fmt_addi;
 999     struct { /* e.g. addv $dr,$sr */
1000       BI condbit;
1001       SI dr;
1002     } fmt_addv;
1003     struct { /* e.g. addv3 $dr,$sr,$simm16 */
1004       BI condbit;
1005       SI dr;
1006     } fmt_addv3;
1007     struct { /* e.g. addx $dr,$sr */
1008       BI condbit;
1009       SI dr;
1010     } fmt_addx;
1011     struct { /* e.g. bc.s $disp8 */
1012       USI pc;
1013     } fmt_bc8;
1014     struct { /* e.g. bc.l $disp24 */
1015       USI pc;
1016     } fmt_bc24;
1017     struct { /* e.g. beq $src1,$src2,$disp16 */
1018       USI pc;
1019     } fmt_beq;
1020     struct { /* e.g. beqz $src2,$disp16 */
1021       USI pc;
1022     } fmt_beqz;
1023     struct { /* e.g. bl.s $disp8 */
1024       SI h_gr_14;
1025       USI pc;
1026     } fmt_bl8;
1027     struct { /* e.g. bl.l $disp24 */
1028       SI h_gr_14;
1029       USI pc;
1030     } fmt_bl24;
1031     struct { /* e.g. bcl.s $disp8 */
1032       SI h_gr_14;
1033       USI pc;
1034     } fmt_bcl8;
1035     struct { /* e.g. bcl.l $disp24 */
1036       SI h_gr_14;
1037       USI pc;
1038     } fmt_bcl24;
1039     struct { /* e.g. bra.s $disp8 */
1040       USI pc;
1041     } fmt_bra8;
1042     struct { /* e.g. bra.l $disp24 */
1043       USI pc;
1044     } fmt_bra24;
1045     struct { /* e.g. cmp $src1,$src2 */
1046       BI condbit;
1047     } fmt_cmp;
1048     struct { /* e.g. cmpi $src2,$simm16 */
1049       BI condbit;
1050     } fmt_cmpi;
1051     struct { /* e.g. cmpz $src2 */
1052       BI condbit;
1053     } fmt_cmpz;
1054     struct { /* e.g. div $dr,$sr */
1055       SI dr;
1056     } fmt_div;
1057     struct { /* e.g. jc $sr */
1058       USI pc;
1059     } fmt_jc;
1060     struct { /* e.g. jl $sr */
1061       SI h_gr_14;
1062       USI pc;
1063     } fmt_jl;
1064     struct { /* e.g. jmp $sr */
1065       USI pc;
1066     } fmt_jmp;
1067     struct { /* e.g. ld $dr,@$sr */
1068       SI dr;
1069     } fmt_ld;
1070     struct { /* e.g. ld $dr,@($slo16,$sr) */
1071       SI dr;
1072     } fmt_ld_d;
1073     struct { /* e.g. ldb $dr,@$sr */
1074       SI dr;
1075     } fmt_ldb;
1076     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1077       SI dr;
1078     } fmt_ldb_d;
1079     struct { /* e.g. ldh $dr,@$sr */
1080       SI dr;
1081     } fmt_ldh;
1082     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1083       SI dr;
1084     } fmt_ldh_d;
1085     struct { /* e.g. ld $dr,@$sr+ */
1086       SI dr;
1087       SI sr;
1088     } fmt_ld_plus;
1089     struct { /* e.g. ld24 $dr,$uimm24 */
1090       SI dr;
1091     } fmt_ld24;
1092     struct { /* e.g. ldi8 $dr,$simm8 */
1093       SI dr;
1094     } fmt_ldi8;
1095     struct { /* e.g. ldi16 $dr,$hash$slo16 */
1096       SI dr;
1097     } fmt_ldi16;
1098     struct { /* e.g. lock $dr,@$sr */
1099       SI dr;
1100       BI h_lock_0;
1101     } fmt_lock;
1102     struct { /* e.g. machi $src1,$src2,$acc */
1103       DI acc;
1104     } fmt_machi_a;
1105     struct { /* e.g. mulhi $src1,$src2,$acc */
1106       DI acc;
1107     } fmt_mulhi_a;
1108     struct { /* e.g. mv $dr,$sr */
1109       SI dr;
1110     } fmt_mv;
1111     struct { /* e.g. mvfachi $dr,$accs */
1112       SI dr;
1113     } fmt_mvfachi_a;
1114     struct { /* e.g. mvfc $dr,$scr */
1115       SI dr;
1116     } fmt_mvfc;
1117     struct { /* e.g. mvtachi $src1,$accs */
1118       DI accs;
1119     } fmt_mvtachi_a;
1120     struct { /* e.g. mvtc $sr,$dcr */
1121       USI dcr;
1122     } fmt_mvtc;
1123     struct { /* e.g. nop */
1124       int empty;
1125     } fmt_nop;
1126     struct { /* e.g. rac $accd,$accs,$imm1 */
1127       DI accd;
1128     } fmt_rac_dsi;
1129     struct { /* e.g. rte */
1130       UQI h_bpsw_0;
1131       USI h_cr_6;
1132       UQI h_psw_0;
1133       USI pc;
1134     } fmt_rte;
1135     struct { /* e.g. seth $dr,$hash$hi16 */
1136       SI dr;
1137     } fmt_seth;
1138     struct { /* e.g. sll3 $dr,$sr,$simm16 */
1139       SI dr;
1140     } fmt_sll3;
1141     struct { /* e.g. slli $dr,$uimm5 */
1142       SI dr;
1143     } fmt_slli;
1144     struct { /* e.g. st $src1,@$src2 */
1145       SI h_memory_src2;
1146       USI h_memory_src2_idx;
1147     } fmt_st;
1148     struct { /* e.g. st $src1,@($slo16,$src2) */
1149       SI h_memory_add__VM_src2_slo16;
1150       USI h_memory_add__VM_src2_slo16_idx;
1151     } fmt_st_d;
1152     struct { /* e.g. stb $src1,@$src2 */
1153       QI h_memory_src2;
1154       USI h_memory_src2_idx;
1155     } fmt_stb;
1156     struct { /* e.g. stb $src1,@($slo16,$src2) */
1157       QI h_memory_add__VM_src2_slo16;
1158       USI h_memory_add__VM_src2_slo16_idx;
1159     } fmt_stb_d;
1160     struct { /* e.g. sth $src1,@$src2 */
1161       HI h_memory_src2;
1162       USI h_memory_src2_idx;
1163     } fmt_sth;
1164     struct { /* e.g. sth $src1,@($slo16,$src2) */
1165       HI h_memory_add__VM_src2_slo16;
1166       USI h_memory_add__VM_src2_slo16_idx;
1167     } fmt_sth_d;
1168     struct { /* e.g. st $src1,@+$src2 */
1169       SI h_memory_new_src2;
1170       USI h_memory_new_src2_idx;
1171       SI src2;
1172     } fmt_st_plus;
1173     struct { /* e.g. trap $uimm4 */
1174       UQI h_bbpsw_0;
1175       UQI h_bpsw_0;
1176       USI h_cr_14;
1177       USI h_cr_6;
1178       UQI h_psw_0;
1179       SI pc;
1180     } fmt_trap;
1181     struct { /* e.g. unlock $src1,@$src2 */
1182       BI h_lock_0;
1183       SI h_memory_src2;
1184       USI h_memory_src2_idx;
1185     } fmt_unlock;
1186     struct { /* e.g. satb $dr,$sr */
1187       SI dr;
1188     } fmt_satb;
1189     struct { /* e.g. sat $dr,$sr */
1190       SI dr;
1191     } fmt_sat;
1192     struct { /* e.g. sadd */
1193       DI h_accums_0;
1194     } fmt_sadd;
1195     struct { /* e.g. macwu1 $src1,$src2 */
1196       DI h_accums_1;
1197     } fmt_macwu1;
1198     struct { /* e.g. msblo $src1,$src2 */
1199       DI accum;
1200     } fmt_msblo;
1201     struct { /* e.g. mulwu1 $src1,$src2 */
1202       DI h_accums_1;
1203     } fmt_mulwu1;
1204     struct { /* e.g. sc */
1205       int empty;
1206     } fmt_sc;
1207   } operands;
1208   /* For conditionally written operands, bitmask of which ones were.  */
1209   int written;
1210 };
1211
1212 /* Collection of various things for the trace handler to use.  */
1213
1214 typedef struct trace_record {
1215   IADDR pc;
1216   /* FIXME:wip */
1217 } TRACE_RECORD;
1218
1219 #endif /* CPU_M32RXF_H */