1 /* Simulator instruction decoder for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
29 #include "sim-assert.h"
34 #define FMT(n) CONCAT2 (M32RXF_,n) ,
37 /* FIXME: Need to review choices for the following. */
39 #if WITH_SEM_SWITCH_FULL
42 #define FULL(fn) CONCAT3 (m32rxf,_sem_,fn) ,
46 #if WITH_SEM_SWITCH_FAST
49 #define FAST(fn) CONCAT3 (m32rxf,_semf_,fn) , /* f for fast */
55 /* The instruction descriptor array.
56 This is computed at runtime. Space for it is not malloc'd to save a
57 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
58 but won't be done until necessary (we don't currently support the runtime
59 addition of instructions nor an SMP machine with different cpus). */
60 static IDESC m32rxf_insn_data
[M32RXF_INSN_MAX
];
62 /* Instruction semantic handlers and support.
63 This struct defines the part of an IDESC that can be computed at
67 /* The instruction type (a number that identifies each insn over the
68 entire architecture). */
71 /* Index in IDESC table. */
74 /* Index in IDESC table of parallel handler. */
77 /* Index in IDESC table of writeback handler. */
80 /* Routines to execute the insn.
81 The full version has all features (profiling,tracing) compiled in.
82 The fast version has none of that. */
83 #if ! WITH_SEM_SWITCH_FULL
84 SEMANTIC_FN
*sem_full
;
86 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
87 SEMANTIC_FN
*sem_fast
;
91 /* The INSN_ prefix is not here and is instead part of the `insn' argument
92 to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
93 #define IDX(insn) CONCAT2 (M32RXF_,insn)
94 #define TYPE(insn) CONCAT2 (M32R_,insn)
96 /* Insn can't be executed in parallel.
97 Or is that "do NOt Pass to Air defense Radar"? :-) */
100 /* Commas between elements are contained in the macros.
101 Some of these are conditionally compiled out. */
103 static const struct insn_sem m32rxf_insn_sem
[] =
105 { VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), NOPAR
, NOPAR
, FULL (x_invalid
) FAST (x_invalid
) },
106 { VIRTUAL_INSN_X_AFTER
, IDX (INSN_X_AFTER
), NOPAR
, NOPAR
, FULL (x_after
) FAST (x_after
) },
107 { VIRTUAL_INSN_X_BEFORE
, IDX (INSN_X_BEFORE
), NOPAR
, NOPAR
, FULL (x_before
) FAST (x_before
) },
108 { VIRTUAL_INSN_X_CTI_CHAIN
, IDX (INSN_X_CTI_CHAIN
), NOPAR
, NOPAR
, FULL (x_cti_chain
) FAST (x_cti_chain
) },
109 { VIRTUAL_INSN_X_CHAIN
, IDX (INSN_X_CHAIN
), NOPAR
, NOPAR
, FULL (x_chain
) FAST (x_chain
) },
110 { VIRTUAL_INSN_X_BEGIN
, IDX (INSN_X_BEGIN
), NOPAR
, NOPAR
, FULL (x_begin
) FAST (x_begin
) },
111 { TYPE (INSN_ADD
), IDX (INSN_ADD
), IDX (INSN_PAR_ADD
), IDX (INSN_WRITE_ADD
), FULL (add
) FAST (add
) },
112 { TYPE (INSN_ADD3
), IDX (INSN_ADD3
), NOPAR
, NOPAR
, FULL (add3
) FAST (add3
) },
113 { TYPE (INSN_AND
), IDX (INSN_AND
), IDX (INSN_PAR_AND
), IDX (INSN_WRITE_AND
), FULL (and) FAST (and) },
114 { TYPE (INSN_AND3
), IDX (INSN_AND3
), NOPAR
, NOPAR
, FULL (and3
) FAST (and3
) },
115 { TYPE (INSN_OR
), IDX (INSN_OR
), IDX (INSN_PAR_OR
), IDX (INSN_WRITE_OR
), FULL (or) FAST (or) },
116 { TYPE (INSN_OR3
), IDX (INSN_OR3
), NOPAR
, NOPAR
, FULL (or3
) FAST (or3
) },
117 { TYPE (INSN_XOR
), IDX (INSN_XOR
), IDX (INSN_PAR_XOR
), IDX (INSN_WRITE_XOR
), FULL (xor) FAST (xor) },
118 { TYPE (INSN_XOR3
), IDX (INSN_XOR3
), NOPAR
, NOPAR
, FULL (xor3
) FAST (xor3
) },
119 { TYPE (INSN_ADDI
), IDX (INSN_ADDI
), IDX (INSN_PAR_ADDI
), IDX (INSN_WRITE_ADDI
), FULL (addi
) FAST (addi
) },
120 { TYPE (INSN_ADDV
), IDX (INSN_ADDV
), IDX (INSN_PAR_ADDV
), IDX (INSN_WRITE_ADDV
), FULL (addv
) FAST (addv
) },
121 { TYPE (INSN_ADDV3
), IDX (INSN_ADDV3
), NOPAR
, NOPAR
, FULL (addv3
) FAST (addv3
) },
122 { TYPE (INSN_ADDX
), IDX (INSN_ADDX
), IDX (INSN_PAR_ADDX
), IDX (INSN_WRITE_ADDX
), FULL (addx
) FAST (addx
) },
123 { TYPE (INSN_BC8
), IDX (INSN_BC8
), IDX (INSN_PAR_BC8
), IDX (INSN_WRITE_BC8
), FULL (bc8
) FAST (bc8
) },
124 { TYPE (INSN_BC24
), IDX (INSN_BC24
), NOPAR
, NOPAR
, FULL (bc24
) FAST (bc24
) },
125 { TYPE (INSN_BEQ
), IDX (INSN_BEQ
), NOPAR
, NOPAR
, FULL (beq
) FAST (beq
) },
126 { TYPE (INSN_BEQZ
), IDX (INSN_BEQZ
), NOPAR
, NOPAR
, FULL (beqz
) FAST (beqz
) },
127 { TYPE (INSN_BGEZ
), IDX (INSN_BGEZ
), NOPAR
, NOPAR
, FULL (bgez
) FAST (bgez
) },
128 { TYPE (INSN_BGTZ
), IDX (INSN_BGTZ
), NOPAR
, NOPAR
, FULL (bgtz
) FAST (bgtz
) },
129 { TYPE (INSN_BLEZ
), IDX (INSN_BLEZ
), NOPAR
, NOPAR
, FULL (blez
) FAST (blez
) },
130 { TYPE (INSN_BLTZ
), IDX (INSN_BLTZ
), NOPAR
, NOPAR
, FULL (bltz
) FAST (bltz
) },
131 { TYPE (INSN_BNEZ
), IDX (INSN_BNEZ
), NOPAR
, NOPAR
, FULL (bnez
) FAST (bnez
) },
132 { TYPE (INSN_BL8
), IDX (INSN_BL8
), IDX (INSN_PAR_BL8
), IDX (INSN_WRITE_BL8
), FULL (bl8
) FAST (bl8
) },
133 { TYPE (INSN_BL24
), IDX (INSN_BL24
), NOPAR
, NOPAR
, FULL (bl24
) FAST (bl24
) },
134 { TYPE (INSN_BCL8
), IDX (INSN_BCL8
), IDX (INSN_PAR_BCL8
), IDX (INSN_WRITE_BCL8
), FULL (bcl8
) FAST (bcl8
) },
135 { TYPE (INSN_BCL24
), IDX (INSN_BCL24
), NOPAR
, NOPAR
, FULL (bcl24
) FAST (bcl24
) },
136 { TYPE (INSN_BNC8
), IDX (INSN_BNC8
), IDX (INSN_PAR_BNC8
), IDX (INSN_WRITE_BNC8
), FULL (bnc8
) FAST (bnc8
) },
137 { TYPE (INSN_BNC24
), IDX (INSN_BNC24
), NOPAR
, NOPAR
, FULL (bnc24
) FAST (bnc24
) },
138 { TYPE (INSN_BNE
), IDX (INSN_BNE
), NOPAR
, NOPAR
, FULL (bne
) FAST (bne
) },
139 { TYPE (INSN_BRA8
), IDX (INSN_BRA8
), IDX (INSN_PAR_BRA8
), IDX (INSN_WRITE_BRA8
), FULL (bra8
) FAST (bra8
) },
140 { TYPE (INSN_BRA24
), IDX (INSN_BRA24
), NOPAR
, NOPAR
, FULL (bra24
) FAST (bra24
) },
141 { TYPE (INSN_BNCL8
), IDX (INSN_BNCL8
), IDX (INSN_PAR_BNCL8
), IDX (INSN_WRITE_BNCL8
), FULL (bncl8
) FAST (bncl8
) },
142 { TYPE (INSN_BNCL24
), IDX (INSN_BNCL24
), NOPAR
, NOPAR
, FULL (bncl24
) FAST (bncl24
) },
143 { TYPE (INSN_CMP
), IDX (INSN_CMP
), IDX (INSN_PAR_CMP
), IDX (INSN_WRITE_CMP
), FULL (cmp
) FAST (cmp
) },
144 { TYPE (INSN_CMPI
), IDX (INSN_CMPI
), NOPAR
, NOPAR
, FULL (cmpi
) FAST (cmpi
) },
145 { TYPE (INSN_CMPU
), IDX (INSN_CMPU
), IDX (INSN_PAR_CMPU
), IDX (INSN_WRITE_CMPU
), FULL (cmpu
) FAST (cmpu
) },
146 { TYPE (INSN_CMPUI
), IDX (INSN_CMPUI
), NOPAR
, NOPAR
, FULL (cmpui
) FAST (cmpui
) },
147 { TYPE (INSN_CMPEQ
), IDX (INSN_CMPEQ
), IDX (INSN_PAR_CMPEQ
), IDX (INSN_WRITE_CMPEQ
), FULL (cmpeq
) FAST (cmpeq
) },
148 { TYPE (INSN_CMPZ
), IDX (INSN_CMPZ
), IDX (INSN_PAR_CMPZ
), IDX (INSN_WRITE_CMPZ
), FULL (cmpz
) FAST (cmpz
) },
149 { TYPE (INSN_DIV
), IDX (INSN_DIV
), NOPAR
, NOPAR
, FULL (div
) FAST (div
) },
150 { TYPE (INSN_DIVU
), IDX (INSN_DIVU
), NOPAR
, NOPAR
, FULL (divu
) FAST (divu
) },
151 { TYPE (INSN_REM
), IDX (INSN_REM
), NOPAR
, NOPAR
, FULL (rem
) FAST (rem
) },
152 { TYPE (INSN_REMU
), IDX (INSN_REMU
), NOPAR
, NOPAR
, FULL (remu
) FAST (remu
) },
153 { TYPE (INSN_DIVH
), IDX (INSN_DIVH
), NOPAR
, NOPAR
, FULL (divh
) FAST (divh
) },
154 { TYPE (INSN_JC
), IDX (INSN_JC
), IDX (INSN_PAR_JC
), IDX (INSN_WRITE_JC
), FULL (jc
) FAST (jc
) },
155 { TYPE (INSN_JNC
), IDX (INSN_JNC
), IDX (INSN_PAR_JNC
), IDX (INSN_WRITE_JNC
), FULL (jnc
) FAST (jnc
) },
156 { TYPE (INSN_JL
), IDX (INSN_JL
), IDX (INSN_PAR_JL
), IDX (INSN_WRITE_JL
), FULL (jl
) FAST (jl
) },
157 { TYPE (INSN_JMP
), IDX (INSN_JMP
), IDX (INSN_PAR_JMP
), IDX (INSN_WRITE_JMP
), FULL (jmp
) FAST (jmp
) },
158 { TYPE (INSN_LD
), IDX (INSN_LD
), IDX (INSN_PAR_LD
), IDX (INSN_WRITE_LD
), FULL (ld
) FAST (ld
) },
159 { TYPE (INSN_LD_D
), IDX (INSN_LD_D
), NOPAR
, NOPAR
, FULL (ld_d
) FAST (ld_d
) },
160 { TYPE (INSN_LDB
), IDX (INSN_LDB
), IDX (INSN_PAR_LDB
), IDX (INSN_WRITE_LDB
), FULL (ldb
) FAST (ldb
) },
161 { TYPE (INSN_LDB_D
), IDX (INSN_LDB_D
), NOPAR
, NOPAR
, FULL (ldb_d
) FAST (ldb_d
) },
162 { TYPE (INSN_LDH
), IDX (INSN_LDH
), IDX (INSN_PAR_LDH
), IDX (INSN_WRITE_LDH
), FULL (ldh
) FAST (ldh
) },
163 { TYPE (INSN_LDH_D
), IDX (INSN_LDH_D
), NOPAR
, NOPAR
, FULL (ldh_d
) FAST (ldh_d
) },
164 { TYPE (INSN_LDUB
), IDX (INSN_LDUB
), IDX (INSN_PAR_LDUB
), IDX (INSN_WRITE_LDUB
), FULL (ldub
) FAST (ldub
) },
165 { TYPE (INSN_LDUB_D
), IDX (INSN_LDUB_D
), NOPAR
, NOPAR
, FULL (ldub_d
) FAST (ldub_d
) },
166 { TYPE (INSN_LDUH
), IDX (INSN_LDUH
), IDX (INSN_PAR_LDUH
), IDX (INSN_WRITE_LDUH
), FULL (lduh
) FAST (lduh
) },
167 { TYPE (INSN_LDUH_D
), IDX (INSN_LDUH_D
), NOPAR
, NOPAR
, FULL (lduh_d
) FAST (lduh_d
) },
168 { TYPE (INSN_LD_PLUS
), IDX (INSN_LD_PLUS
), IDX (INSN_PAR_LD_PLUS
), IDX (INSN_WRITE_LD_PLUS
), FULL (ld_plus
) FAST (ld_plus
) },
169 { TYPE (INSN_LD24
), IDX (INSN_LD24
), NOPAR
, NOPAR
, FULL (ld24
) FAST (ld24
) },
170 { TYPE (INSN_LDI8
), IDX (INSN_LDI8
), IDX (INSN_PAR_LDI8
), IDX (INSN_WRITE_LDI8
), FULL (ldi8
) FAST (ldi8
) },
171 { TYPE (INSN_LDI16
), IDX (INSN_LDI16
), NOPAR
, NOPAR
, FULL (ldi16
) FAST (ldi16
) },
172 { TYPE (INSN_LOCK
), IDX (INSN_LOCK
), IDX (INSN_PAR_LOCK
), IDX (INSN_WRITE_LOCK
), FULL (lock
) FAST (lock
) },
173 { TYPE (INSN_MACHI_A
), IDX (INSN_MACHI_A
), IDX (INSN_PAR_MACHI_A
), IDX (INSN_WRITE_MACHI_A
), FULL (machi_a
) FAST (machi_a
) },
174 { TYPE (INSN_MACLO_A
), IDX (INSN_MACLO_A
), IDX (INSN_PAR_MACLO_A
), IDX (INSN_WRITE_MACLO_A
), FULL (maclo_a
) FAST (maclo_a
) },
175 { TYPE (INSN_MACWHI_A
), IDX (INSN_MACWHI_A
), IDX (INSN_PAR_MACWHI_A
), IDX (INSN_WRITE_MACWHI_A
), FULL (macwhi_a
) FAST (macwhi_a
) },
176 { TYPE (INSN_MACWLO_A
), IDX (INSN_MACWLO_A
), IDX (INSN_PAR_MACWLO_A
), IDX (INSN_WRITE_MACWLO_A
), FULL (macwlo_a
) FAST (macwlo_a
) },
177 { TYPE (INSN_MUL
), IDX (INSN_MUL
), IDX (INSN_PAR_MUL
), IDX (INSN_WRITE_MUL
), FULL (mul
) FAST (mul
) },
178 { TYPE (INSN_MULHI_A
), IDX (INSN_MULHI_A
), IDX (INSN_PAR_MULHI_A
), IDX (INSN_WRITE_MULHI_A
), FULL (mulhi_a
) FAST (mulhi_a
) },
179 { TYPE (INSN_MULLO_A
), IDX (INSN_MULLO_A
), IDX (INSN_PAR_MULLO_A
), IDX (INSN_WRITE_MULLO_A
), FULL (mullo_a
) FAST (mullo_a
) },
180 { TYPE (INSN_MULWHI_A
), IDX (INSN_MULWHI_A
), IDX (INSN_PAR_MULWHI_A
), IDX (INSN_WRITE_MULWHI_A
), FULL (mulwhi_a
) FAST (mulwhi_a
) },
181 { TYPE (INSN_MULWLO_A
), IDX (INSN_MULWLO_A
), IDX (INSN_PAR_MULWLO_A
), IDX (INSN_WRITE_MULWLO_A
), FULL (mulwlo_a
) FAST (mulwlo_a
) },
182 { TYPE (INSN_MV
), IDX (INSN_MV
), IDX (INSN_PAR_MV
), IDX (INSN_WRITE_MV
), FULL (mv
) FAST (mv
) },
183 { TYPE (INSN_MVFACHI_A
), IDX (INSN_MVFACHI_A
), IDX (INSN_PAR_MVFACHI_A
), IDX (INSN_WRITE_MVFACHI_A
), FULL (mvfachi_a
) FAST (mvfachi_a
) },
184 { TYPE (INSN_MVFACLO_A
), IDX (INSN_MVFACLO_A
), IDX (INSN_PAR_MVFACLO_A
), IDX (INSN_WRITE_MVFACLO_A
), FULL (mvfaclo_a
) FAST (mvfaclo_a
) },
185 { TYPE (INSN_MVFACMI_A
), IDX (INSN_MVFACMI_A
), IDX (INSN_PAR_MVFACMI_A
), IDX (INSN_WRITE_MVFACMI_A
), FULL (mvfacmi_a
) FAST (mvfacmi_a
) },
186 { TYPE (INSN_MVFC
), IDX (INSN_MVFC
), IDX (INSN_PAR_MVFC
), IDX (INSN_WRITE_MVFC
), FULL (mvfc
) FAST (mvfc
) },
187 { TYPE (INSN_MVTACHI_A
), IDX (INSN_MVTACHI_A
), IDX (INSN_PAR_MVTACHI_A
), IDX (INSN_WRITE_MVTACHI_A
), FULL (mvtachi_a
) FAST (mvtachi_a
) },
188 { TYPE (INSN_MVTACLO_A
), IDX (INSN_MVTACLO_A
), IDX (INSN_PAR_MVTACLO_A
), IDX (INSN_WRITE_MVTACLO_A
), FULL (mvtaclo_a
) FAST (mvtaclo_a
) },
189 { TYPE (INSN_MVTC
), IDX (INSN_MVTC
), IDX (INSN_PAR_MVTC
), IDX (INSN_WRITE_MVTC
), FULL (mvtc
) FAST (mvtc
) },
190 { TYPE (INSN_NEG
), IDX (INSN_NEG
), IDX (INSN_PAR_NEG
), IDX (INSN_WRITE_NEG
), FULL (neg
) FAST (neg
) },
191 { TYPE (INSN_NOP
), IDX (INSN_NOP
), IDX (INSN_PAR_NOP
), IDX (INSN_WRITE_NOP
), FULL (nop
) FAST (nop
) },
192 { TYPE (INSN_NOT
), IDX (INSN_NOT
), IDX (INSN_PAR_NOT
), IDX (INSN_WRITE_NOT
), FULL (not) FAST (not) },
193 { TYPE (INSN_RAC_DSI
), IDX (INSN_RAC_DSI
), IDX (INSN_PAR_RAC_DSI
), IDX (INSN_WRITE_RAC_DSI
), FULL (rac_dsi
) FAST (rac_dsi
) },
194 { TYPE (INSN_RACH_DSI
), IDX (INSN_RACH_DSI
), IDX (INSN_PAR_RACH_DSI
), IDX (INSN_WRITE_RACH_DSI
), FULL (rach_dsi
) FAST (rach_dsi
) },
195 { TYPE (INSN_RTE
), IDX (INSN_RTE
), IDX (INSN_PAR_RTE
), IDX (INSN_WRITE_RTE
), FULL (rte
) FAST (rte
) },
196 { TYPE (INSN_SETH
), IDX (INSN_SETH
), NOPAR
, NOPAR
, FULL (seth
) FAST (seth
) },
197 { TYPE (INSN_SLL
), IDX (INSN_SLL
), IDX (INSN_PAR_SLL
), IDX (INSN_WRITE_SLL
), FULL (sll
) FAST (sll
) },
198 { TYPE (INSN_SLL3
), IDX (INSN_SLL3
), NOPAR
, NOPAR
, FULL (sll3
) FAST (sll3
) },
199 { TYPE (INSN_SLLI
), IDX (INSN_SLLI
), IDX (INSN_PAR_SLLI
), IDX (INSN_WRITE_SLLI
), FULL (slli
) FAST (slli
) },
200 { TYPE (INSN_SRA
), IDX (INSN_SRA
), IDX (INSN_PAR_SRA
), IDX (INSN_WRITE_SRA
), FULL (sra
) FAST (sra
) },
201 { TYPE (INSN_SRA3
), IDX (INSN_SRA3
), NOPAR
, NOPAR
, FULL (sra3
) FAST (sra3
) },
202 { TYPE (INSN_SRAI
), IDX (INSN_SRAI
), IDX (INSN_PAR_SRAI
), IDX (INSN_WRITE_SRAI
), FULL (srai
) FAST (srai
) },
203 { TYPE (INSN_SRL
), IDX (INSN_SRL
), IDX (INSN_PAR_SRL
), IDX (INSN_WRITE_SRL
), FULL (srl
) FAST (srl
) },
204 { TYPE (INSN_SRL3
), IDX (INSN_SRL3
), NOPAR
, NOPAR
, FULL (srl3
) FAST (srl3
) },
205 { TYPE (INSN_SRLI
), IDX (INSN_SRLI
), IDX (INSN_PAR_SRLI
), IDX (INSN_WRITE_SRLI
), FULL (srli
) FAST (srli
) },
206 { TYPE (INSN_ST
), IDX (INSN_ST
), IDX (INSN_PAR_ST
), IDX (INSN_WRITE_ST
), FULL (st
) FAST (st
) },
207 { TYPE (INSN_ST_D
), IDX (INSN_ST_D
), NOPAR
, NOPAR
, FULL (st_d
) FAST (st_d
) },
208 { TYPE (INSN_STB
), IDX (INSN_STB
), IDX (INSN_PAR_STB
), IDX (INSN_WRITE_STB
), FULL (stb
) FAST (stb
) },
209 { TYPE (INSN_STB_D
), IDX (INSN_STB_D
), NOPAR
, NOPAR
, FULL (stb_d
) FAST (stb_d
) },
210 { TYPE (INSN_STH
), IDX (INSN_STH
), IDX (INSN_PAR_STH
), IDX (INSN_WRITE_STH
), FULL (sth
) FAST (sth
) },
211 { TYPE (INSN_STH_D
), IDX (INSN_STH_D
), NOPAR
, NOPAR
, FULL (sth_d
) FAST (sth_d
) },
212 { TYPE (INSN_ST_PLUS
), IDX (INSN_ST_PLUS
), IDX (INSN_PAR_ST_PLUS
), IDX (INSN_WRITE_ST_PLUS
), FULL (st_plus
) FAST (st_plus
) },
213 { TYPE (INSN_ST_MINUS
), IDX (INSN_ST_MINUS
), IDX (INSN_PAR_ST_MINUS
), IDX (INSN_WRITE_ST_MINUS
), FULL (st_minus
) FAST (st_minus
) },
214 { TYPE (INSN_SUB
), IDX (INSN_SUB
), IDX (INSN_PAR_SUB
), IDX (INSN_WRITE_SUB
), FULL (sub
) FAST (sub
) },
215 { TYPE (INSN_SUBV
), IDX (INSN_SUBV
), IDX (INSN_PAR_SUBV
), IDX (INSN_WRITE_SUBV
), FULL (subv
) FAST (subv
) },
216 { TYPE (INSN_SUBX
), IDX (INSN_SUBX
), IDX (INSN_PAR_SUBX
), IDX (INSN_WRITE_SUBX
), FULL (subx
) FAST (subx
) },
217 { TYPE (INSN_TRAP
), IDX (INSN_TRAP
), IDX (INSN_PAR_TRAP
), IDX (INSN_WRITE_TRAP
), FULL (trap
) FAST (trap
) },
218 { TYPE (INSN_UNLOCK
), IDX (INSN_UNLOCK
), IDX (INSN_PAR_UNLOCK
), IDX (INSN_WRITE_UNLOCK
), FULL (unlock
) FAST (unlock
) },
219 { TYPE (INSN_SATB
), IDX (INSN_SATB
), NOPAR
, NOPAR
, FULL (satb
) FAST (satb
) },
220 { TYPE (INSN_SATH
), IDX (INSN_SATH
), NOPAR
, NOPAR
, FULL (sath
) FAST (sath
) },
221 { TYPE (INSN_SAT
), IDX (INSN_SAT
), NOPAR
, NOPAR
, FULL (sat
) FAST (sat
) },
222 { TYPE (INSN_PCMPBZ
), IDX (INSN_PCMPBZ
), IDX (INSN_PAR_PCMPBZ
), IDX (INSN_WRITE_PCMPBZ
), FULL (pcmpbz
) FAST (pcmpbz
) },
223 { TYPE (INSN_SADD
), IDX (INSN_SADD
), IDX (INSN_PAR_SADD
), IDX (INSN_WRITE_SADD
), FULL (sadd
) FAST (sadd
) },
224 { TYPE (INSN_MACWU1
), IDX (INSN_MACWU1
), IDX (INSN_PAR_MACWU1
), IDX (INSN_WRITE_MACWU1
), FULL (macwu1
) FAST (macwu1
) },
225 { TYPE (INSN_MSBLO
), IDX (INSN_MSBLO
), IDX (INSN_PAR_MSBLO
), IDX (INSN_WRITE_MSBLO
), FULL (msblo
) FAST (msblo
) },
226 { TYPE (INSN_MULWU1
), IDX (INSN_MULWU1
), IDX (INSN_PAR_MULWU1
), IDX (INSN_WRITE_MULWU1
), FULL (mulwu1
) FAST (mulwu1
) },
227 { TYPE (INSN_MACLH1
), IDX (INSN_MACLH1
), IDX (INSN_PAR_MACLH1
), IDX (INSN_WRITE_MACLH1
), FULL (maclh1
) FAST (maclh1
) },
228 { TYPE (INSN_SC
), IDX (INSN_SC
), IDX (INSN_PAR_SC
), IDX (INSN_WRITE_SC
), FULL (sc
) FAST (sc
) },
229 { TYPE (INSN_SNC
), IDX (INSN_SNC
), IDX (INSN_PAR_SNC
), IDX (INSN_WRITE_SNC
), FULL (snc
) FAST (snc
) },
232 static const struct insn_sem m32rxf_insn_sem_invalid
=
234 VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), IDX (INSN_X_INVALID
), 0 /*unused*/, FULL (x_invalid
) FAST (x_invalid
)
240 /* Initialize an IDESC from the compile-time computable parts. */
243 init_idesc (SIM_CPU
*cpu
, IDESC
*id
, const struct insn_sem
*t
)
245 const CGEN_INSN
*opcode_table
= m32r_cgen_insn_table_entries
;
248 if ((int) t
->type
<= 0)
249 id
->opcode
= & cgen_virtual_opcode_table
[- t
->type
];
251 id
->opcode
= & opcode_table
[t
->type
];
252 #if ! WITH_SEM_SWITCH_FULL
253 id
->sem_full
= t
->sem_full
;
255 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
256 id
->sem_fast
= t
->sem_fast
;
258 #if WITH_PROFILE_MODEL_P
259 id
->timing
= & MODEL_TIMING (CPU_MODEL (cpu
)) [t
->index
];
261 SIM_DESC sd
= CPU_STATE (cpu
);
262 SIM_ASSERT (t
->index
== id
->timing
->num
);
267 /* Initialize the instruction descriptor table. */
270 m32rxf_init_idesc_table (SIM_CPU
*cpu
)
273 const struct insn_sem
*t
,*tend
;
274 int tabsize
= M32RXF_INSN_MAX
;
275 IDESC
*table
= m32rxf_insn_data
;
277 memset (table
, 0, tabsize
* sizeof (IDESC
));
279 /* First set all entries to the `invalid insn'. */
280 t
= & m32rxf_insn_sem_invalid
;
281 for (id
= table
, tabend
= table
+ tabsize
; id
< tabend
; ++id
)
282 init_idesc (cpu
, id
, t
);
284 /* Now fill in the values for the chosen cpu. */
285 for (t
= m32rxf_insn_sem
, tend
= t
+ sizeof (m32rxf_insn_sem
) / sizeof (*t
);
288 init_idesc (cpu
, & table
[t
->index
], t
);
289 if (t
->par_index
!= NOPAR
)
291 init_idesc (cpu
, &table
[t
->par_index
], t
);
292 table
[t
->index
].par_idesc
= &table
[t
->par_index
];
294 if (t
->par_index
!= NOPAR
)
296 init_idesc (cpu
, &table
[t
->write_index
], t
);
297 table
[t
->par_index
].par_idesc
= &table
[t
->write_index
];
301 /* Link the IDESC table into the cpu. */
302 CPU_IDESC (cpu
) = table
;
305 /* Enum declaration for all instruction formats. */
307 FMT_EMPTY
, FMT_ADD
, FMT_ADD3
, FMT_AND3
308 , FMT_OR3
, FMT_ADDI
, FMT_ADDV
, FMT_ADDV3
309 , FMT_ADDX
, FMT_BC8
, FMT_BC24
, FMT_BEQ
310 , FMT_BEQZ
, FMT_BL8
, FMT_BL24
, FMT_BCL8
311 , FMT_BCL24
, FMT_BRA8
, FMT_BRA24
, FMT_CMP
312 , FMT_CMPI
, FMT_CMPZ
, FMT_DIV
, FMT_JC
313 , FMT_JL
, FMT_JMP
, FMT_LD
, FMT_LD_D
314 , FMT_LDB
, FMT_LDB_D
, FMT_LDH
, FMT_LDH_D
315 , FMT_LD_PLUS
, FMT_LD24
, FMT_LDI8
, FMT_LDI16
316 , FMT_LOCK
, FMT_MACHI_A
, FMT_MULHI_A
, FMT_MV
317 , FMT_MVFACHI_A
, FMT_MVFC
, FMT_MVTACHI_A
, FMT_MVTC
318 , FMT_NOP
, FMT_RAC_DSI
, FMT_RTE
, FMT_SETH
319 , FMT_SLL3
, FMT_SLLI
, FMT_ST
, FMT_ST_D
320 , FMT_STB
, FMT_STB_D
, FMT_STH
, FMT_STH_D
321 , FMT_ST_PLUS
, FMT_TRAP
, FMT_UNLOCK
, FMT_SATB
322 , FMT_SAT
, FMT_SADD
, FMT_MACWU1
, FMT_MSBLO
326 /* The decoder uses this to record insns and direct extraction handling. */
337 /* Macro to go from decode phase to extraction phase. */
340 #define GOTO_EXTRACT(id) goto *(id)->ifmt
342 #define GOTO_EXTRACT(id) goto extract
345 /* The decoder needs a slightly different computed goto switch control. */
347 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
349 #define DECODE_SWITCH(N, X) switch (X)
352 /* Given an instruction, return a pointer to its IDESC entry. */
355 m32rxf_decode (SIM_CPU
*current_cpu
, PCADDR pc
,
356 CGEN_INSN_INT base_insn
, CGEN_INSN_INT entire_insn
,
359 /* Result of decoder, used by extractor. */
360 const DECODE_DESC
*idecode
;
362 /* First decode the instruction. */
365 #define I(insn) & m32rxf_insn_data[CONCAT2 (M32RXF_,insn)]
367 #define E(fmt) && case_ex_##fmt
371 CGEN_INSN_INT insn
= base_insn
;
372 static const DECODE_DESC idecode_invalid
= { I (INSN_X_INVALID
), E (FMT_EMPTY
) };
375 static const void *labels_0
[256] = {
376 && default_0
, && default_0
, && default_0
, && default_0
,
377 && default_0
, && default_0
, && default_0
, && case_0_7
,
378 && default_0
, && default_0
, && default_0
, && default_0
,
379 && default_0
, && default_0
, && default_0
, && default_0
,
380 && default_0
, && default_0
, && default_0
, && default_0
,
381 && default_0
, && default_0
, && default_0
, && default_0
,
382 && default_0
, && default_0
, && default_0
, && default_0
,
383 && case_0_28
, && default_0
, && default_0
, && default_0
,
384 && default_0
, && default_0
, && default_0
, && default_0
,
385 && default_0
, && default_0
, && default_0
, && default_0
,
386 && default_0
, && default_0
, && default_0
, && default_0
,
387 && default_0
, && default_0
, && default_0
, && default_0
,
388 && default_0
, && default_0
, && default_0
, && default_0
,
389 && default_0
, && default_0
, && default_0
, && default_0
,
390 && default_0
, && default_0
, && default_0
, && default_0
,
391 && default_0
, && default_0
, && default_0
, && default_0
,
392 && default_0
, && default_0
, && default_0
, && default_0
,
393 && default_0
, && default_0
, && default_0
, && default_0
,
394 && default_0
, && default_0
, && default_0
, && default_0
,
395 && default_0
, && default_0
, && default_0
, && default_0
,
396 && default_0
, && default_0
, && default_0
, && default_0
,
397 && default_0
, && default_0
, && default_0
, && case_0_87
,
398 && default_0
, && default_0
, && default_0
, && default_0
,
399 && default_0
, && default_0
, && default_0
, && case_0_95
,
400 && default_0
, && default_0
, && default_0
, && default_0
,
401 && default_0
, && default_0
, && default_0
, && default_0
,
402 && default_0
, && default_0
, && default_0
, && default_0
,
403 && default_0
, && default_0
, && default_0
, && default_0
,
404 && case_0_112
, && case_0_113
, && case_0_114
, && case_0_115
,
405 && case_0_116
, && case_0_117
, && case_0_118
, && case_0_119
,
406 && case_0_120
, && case_0_121
, && case_0_122
, && case_0_123
,
407 && case_0_124
, && case_0_125
, && case_0_126
, && case_0_127
,
408 && default_0
, && default_0
, && default_0
, && default_0
,
409 && default_0
, && default_0
, && case_0_134
, && default_0
,
410 && default_0
, && default_0
, && default_0
, && default_0
,
411 && default_0
, && default_0
, && default_0
, && default_0
,
412 && case_0_144
, && default_0
, && default_0
, && default_0
,
413 && default_0
, && default_0
, && default_0
, && default_0
,
414 && default_0
, && default_0
, && default_0
, && default_0
,
415 && default_0
, && default_0
, && default_0
, && default_0
,
416 && default_0
, && default_0
, && default_0
, && default_0
,
417 && default_0
, && default_0
, && default_0
, && default_0
,
418 && default_0
, && default_0
, && default_0
, && default_0
,
419 && default_0
, && default_0
, && default_0
, && default_0
,
420 && default_0
, && default_0
, && default_0
, && default_0
,
421 && default_0
, && default_0
, && default_0
, && default_0
,
422 && default_0
, && default_0
, && default_0
, && default_0
,
423 && default_0
, && default_0
, && default_0
, && default_0
,
424 && default_0
, && default_0
, && default_0
, && default_0
,
425 && default_0
, && default_0
, && default_0
, && default_0
,
426 && default_0
, && default_0
, && default_0
, && default_0
,
427 && default_0
, && default_0
, && default_0
, && default_0
,
428 && default_0
, && default_0
, && default_0
, && default_0
,
429 && default_0
, && default_0
, && default_0
, && default_0
,
430 && default_0
, && default_0
, && default_0
, && default_0
,
431 && default_0
, && default_0
, && default_0
, && default_0
,
432 && default_0
, && default_0
, && default_0
, && default_0
,
433 && default_0
, && default_0
, && default_0
, && default_0
,
434 && default_0
, && default_0
, && default_0
, && default_0
,
435 && default_0
, && default_0
, && default_0
, && default_0
,
436 && case_0_240
, && case_0_241
, && case_0_242
, && case_0_243
,
437 && case_0_244
, && case_0_245
, && case_0_246
, && case_0_247
,
438 && case_0_248
, && case_0_249
, && case_0_250
, && case_0_251
,
439 && case_0_252
, && case_0_253
, && case_0_254
, && case_0_255
,
442 static const DECODE_DESC insns
[256] = {
443 { I (INSN_SUBV
), E (FMT_ADDV
) }, { I (INSN_SUBX
), E (FMT_ADDX
) },
444 { I (INSN_SUB
), E (FMT_ADD
) }, { I (INSN_NEG
), E (FMT_MV
) },
445 { I (INSN_CMP
), E (FMT_CMP
) }, { I (INSN_CMPU
), E (FMT_CMP
) },
446 { I (INSN_CMPEQ
), E (FMT_CMP
) }, { 0 },
447 { I (INSN_ADDV
), E (FMT_ADDV
) }, { I (INSN_ADDX
), E (FMT_ADDX
) },
448 { I (INSN_ADD
), E (FMT_ADD
) }, { I (INSN_NOT
), E (FMT_MV
) },
449 { I (INSN_AND
), E (FMT_ADD
) }, { I (INSN_XOR
), E (FMT_ADD
) },
450 { I (INSN_OR
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
451 { I (INSN_SRL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
452 { I (INSN_SRA
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
453 { I (INSN_SLL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
454 { I (INSN_MUL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
455 { I (INSN_MV
), E (FMT_MV
) }, { I (INSN_MVFC
), E (FMT_MVFC
) },
456 { I (INSN_MVTC
), E (FMT_MVTC
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
457 { 0 }, { I (INSN_RTE
), E (FMT_RTE
) },
458 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_TRAP
), E (FMT_TRAP
) },
459 { I (INSN_STB
), E (FMT_STB
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
460 { I (INSN_STH
), E (FMT_STH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
461 { I (INSN_ST
), E (FMT_ST
) }, { I (INSN_UNLOCK
), E (FMT_UNLOCK
) },
462 { I (INSN_ST_PLUS
), E (FMT_ST_PLUS
) }, { I (INSN_ST_MINUS
), E (FMT_ST_PLUS
) },
463 { I (INSN_LDB
), E (FMT_LDB
) }, { I (INSN_LDUB
), E (FMT_LDB
) },
464 { I (INSN_LDH
), E (FMT_LDH
) }, { I (INSN_LDUH
), E (FMT_LDH
) },
465 { I (INSN_LD
), E (FMT_LD
) }, { I (INSN_LOCK
), E (FMT_LOCK
) },
466 { I (INSN_LD_PLUS
), E (FMT_LD_PLUS
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
467 { I (INSN_MULHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULLO_A
), E (FMT_MULHI_A
) },
468 { I (INSN_MULWHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULWLO_A
), E (FMT_MULHI_A
) },
469 { I (INSN_MACHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACLO_A
), E (FMT_MACHI_A
) },
470 { I (INSN_MACWHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACWLO_A
), E (FMT_MACHI_A
) },
471 { I (INSN_MULHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULLO_A
), E (FMT_MULHI_A
) },
472 { I (INSN_MULWHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULWLO_A
), E (FMT_MULHI_A
) },
473 { I (INSN_MACHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACLO_A
), E (FMT_MACHI_A
) },
474 { I (INSN_MACWHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACWLO_A
), E (FMT_MACHI_A
) },
475 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
476 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
477 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
478 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
479 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
480 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
481 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
482 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
483 { I (INSN_SRLI
), E (FMT_SLLI
) }, { I (INSN_SRLI
), E (FMT_SLLI
) },
484 { I (INSN_SRAI
), E (FMT_SLLI
) }, { I (INSN_SRAI
), E (FMT_SLLI
) },
485 { I (INSN_SLLI
), E (FMT_SLLI
) }, { I (INSN_SLLI
), E (FMT_SLLI
) },
486 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { 0 },
487 { I (INSN_RACH_DSI
), E (FMT_RAC_DSI
) }, { I (INSN_RAC_DSI
), E (FMT_RAC_DSI
) },
488 { I (INSN_MULWU1
), E (FMT_MULWU1
) }, { I (INSN_MACWU1
), E (FMT_MACWU1
) },
489 { I (INSN_MACLH1
), E (FMT_MACWU1
) }, { I (INSN_MSBLO
), E (FMT_MSBLO
) },
490 { I (INSN_SADD
), E (FMT_SADD
) }, { 0 },
491 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
492 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
493 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
494 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
495 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
496 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
497 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
498 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
507 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
508 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
509 { I (INSN_CMPI
), E (FMT_CMPI
) }, { I (INSN_CMPUI
), E (FMT_CMPI
) },
510 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
511 { I (INSN_ADDV3
), E (FMT_ADDV3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
512 { I (INSN_ADD3
), E (FMT_ADD3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
513 { I (INSN_AND3
), E (FMT_AND3
) }, { I (INSN_XOR3
), E (FMT_AND3
) },
514 { I (INSN_OR3
), E (FMT_OR3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
515 { 0 }, { I (INSN_DIVU
), E (FMT_DIV
) },
516 { I (INSN_REM
), E (FMT_DIV
) }, { I (INSN_REMU
), E (FMT_DIV
) },
517 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
518 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
519 { I (INSN_SRL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
520 { I (INSN_SRA3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
521 { I (INSN_SLL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
522 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_LDI16
), E (FMT_LDI16
) },
523 { I (INSN_STB_D
), E (FMT_STB_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
524 { I (INSN_STH_D
), E (FMT_STH_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
525 { I (INSN_ST_D
), E (FMT_ST_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
526 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
527 { I (INSN_LDB_D
), E (FMT_LDB_D
) }, { I (INSN_LDUB_D
), E (FMT_LDB_D
) },
528 { I (INSN_LDH_D
), E (FMT_LDH_D
) }, { I (INSN_LDUH_D
), E (FMT_LDH_D
) },
529 { I (INSN_LD_D
), E (FMT_LD_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
530 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
531 { I (INSN_BEQ
), E (FMT_BEQ
) }, { I (INSN_BNE
), E (FMT_BEQ
) },
532 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
533 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
534 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
535 { I (INSN_BEQZ
), E (FMT_BEQZ
) }, { I (INSN_BNEZ
), E (FMT_BEQZ
) },
536 { I (INSN_BLTZ
), E (FMT_BEQZ
) }, { I (INSN_BGEZ
), E (FMT_BEQZ
) },
537 { I (INSN_BLEZ
), E (FMT_BEQZ
) }, { I (INSN_BGTZ
), E (FMT_BEQZ
) },
538 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
539 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
540 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
541 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
542 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
543 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
544 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
545 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
546 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
547 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
548 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
549 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
550 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
551 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
552 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
553 { I (INSN_SETH
), E (FMT_SETH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
554 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
555 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
556 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
557 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
558 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
559 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
560 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
561 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
562 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
573 val
= (((insn
>> 8) & (15 << 4)) | ((insn
>> 4) & (15 << 0)));
574 DECODE_SWITCH (0, val
)
578 static const DECODE_DESC insns
[16] = {
579 { I (INSN_CMPZ
), E (FMT_CMPZ
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
580 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_PCMPBZ
), E (FMT_CMPZ
) },
581 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
582 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
583 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
584 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
585 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
586 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
588 unsigned int val
= (((insn
>> 8) & (15 << 0)));
589 idecode
= &insns
[val
];
590 GOTO_EXTRACT (idecode
);
594 static const DECODE_DESC insns
[16] = {
595 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
596 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
597 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
598 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
599 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
600 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
601 { I (INSN_JC
), E (FMT_JC
) }, { I (INSN_JNC
), E (FMT_JC
) },
602 { I (INSN_JL
), E (FMT_JL
) }, { I (INSN_JMP
), E (FMT_JMP
) },
604 unsigned int val
= (((insn
>> 8) & (15 << 0)));
605 idecode
= &insns
[val
];
606 GOTO_EXTRACT (idecode
);
610 static const DECODE_DESC insns
[4] = {
611 { I (INSN_MVTACHI_A
), E (FMT_MVTACHI_A
) }, { I (INSN_MVTACLO_A
), E (FMT_MVTACHI_A
) },
612 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
614 unsigned int val
= (((insn
>> 0) & (3 << 0)));
615 idecode
= &insns
[val
];
616 GOTO_EXTRACT (idecode
);
620 static const DECODE_DESC insns
[4] = {
621 { I (INSN_MVFACHI_A
), E (FMT_MVFACHI_A
) }, { I (INSN_MVFACLO_A
), E (FMT_MVFACHI_A
) },
622 { I (INSN_MVFACMI_A
), E (FMT_MVFACHI_A
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
624 unsigned int val
= (((insn
>> 0) & (3 << 0)));
625 idecode
= &insns
[val
];
626 GOTO_EXTRACT (idecode
);
630 static const DECODE_DESC insns
[16] = {
631 { I (INSN_NOP
), E (FMT_NOP
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
632 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
633 { I (INSN_SC
), E (FMT_SC
) }, { I (INSN_SNC
), E (FMT_SC
) },
634 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
635 { I (INSN_BCL8
), E (FMT_BCL8
) }, { I (INSN_BNCL8
), E (FMT_BCL8
) },
636 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
637 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
638 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
640 unsigned int val
= (((insn
>> 8) & (15 << 0)));
641 idecode
= &insns
[val
];
642 GOTO_EXTRACT (idecode
);
644 CASE (0, 113) : /* fall through */
645 CASE (0, 114) : /* fall through */
646 CASE (0, 115) : /* fall through */
647 CASE (0, 116) : /* fall through */
648 CASE (0, 117) : /* fall through */
649 CASE (0, 118) : /* fall through */
650 CASE (0, 119) : /* fall through */
651 CASE (0, 120) : /* fall through */
652 CASE (0, 121) : /* fall through */
653 CASE (0, 122) : /* fall through */
654 CASE (0, 123) : /* fall through */
655 CASE (0, 124) : /* fall through */
656 CASE (0, 125) : /* fall through */
657 CASE (0, 126) : /* fall through */
660 static const DECODE_DESC insns
[16] = {
661 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
662 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
663 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
664 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
665 { I (INSN_BCL8
), E (FMT_BCL8
) }, { I (INSN_BNCL8
), E (FMT_BCL8
) },
666 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
667 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
668 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
670 unsigned int val
= (((insn
>> 8) & (15 << 0)));
671 idecode
= &insns
[val
];
672 GOTO_EXTRACT (idecode
);
677 static const void *labels_0_134
[16] = {
678 && case_0_134_0
, && default_0_134
, && default_0_134
, && default_0_134
,
679 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
680 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
681 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
684 static const DECODE_DESC insns
[16] = {
685 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
686 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
687 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
688 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
689 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
690 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
691 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
692 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
695 /* Must fetch more bits. */
696 insn
= GETIMEMUHI (current_cpu
, pc
+ 2);
697 val
= (((insn
>> 12) & (15 << 0)));
698 DECODE_SWITCH (0_134
, val
)
702 static const DECODE_DESC insns
[16] = {
703 { I (INSN_SAT
), E (FMT_SAT
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
704 { I (INSN_SATH
), E (FMT_SATB
) }, { I (INSN_SATB
), E (FMT_SATB
) },
705 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
706 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
707 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
708 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
709 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
710 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
712 unsigned int val
= (((insn
>> 8) & (15 << 0)));
713 idecode
= &insns
[val
];
714 GOTO_EXTRACT (idecode
);
717 idecode
= &insns
[val
];
718 GOTO_EXTRACT (idecode
);
725 static const void *labels_0_144
[16] = {
726 && case_0_144_0
, && default_0_144
, && default_0_144
, && default_0_144
,
727 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
728 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
729 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
732 static const DECODE_DESC insns
[16] = {
733 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
734 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
735 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
736 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
737 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
738 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
739 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
740 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
743 /* Must fetch more bits. */
744 insn
= GETIMEMUHI (current_cpu
, pc
+ 2);
745 val
= (((insn
>> 12) & (15 << 0)));
746 DECODE_SWITCH (0_144
, val
)
751 static const void *labels_0_144_0
[16] = {
752 && case_0_144_0_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
753 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
754 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
755 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
758 static const DECODE_DESC insns
[16] = {
759 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
760 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
761 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
762 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
763 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
764 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
765 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
766 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
769 val
= (((insn
>> 8) & (15 << 0)));
770 DECODE_SWITCH (0_144_0
, val
)
774 static const DECODE_DESC insns
[16] = {
775 { I (INSN_DIV
), E (FMT_DIV
) }, { I (INSN_DIVH
), E (FMT_DIV
) },
776 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
777 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
778 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
779 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
780 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
781 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
782 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
784 unsigned int val
= (((insn
>> 4) & (15 << 0)));
785 idecode
= &insns
[val
];
786 GOTO_EXTRACT (idecode
);
789 idecode
= &insns
[val
];
790 GOTO_EXTRACT (idecode
);
795 idecode
= &insns
[val
];
796 GOTO_EXTRACT (idecode
);
800 CASE (0, 240) : /* fall through */
801 CASE (0, 241) : /* fall through */
802 CASE (0, 242) : /* fall through */
803 CASE (0, 243) : /* fall through */
804 CASE (0, 244) : /* fall through */
805 CASE (0, 245) : /* fall through */
806 CASE (0, 246) : /* fall through */
807 CASE (0, 247) : /* fall through */
808 CASE (0, 248) : /* fall through */
809 CASE (0, 249) : /* fall through */
810 CASE (0, 250) : /* fall through */
811 CASE (0, 251) : /* fall through */
812 CASE (0, 252) : /* fall through */
813 CASE (0, 253) : /* fall through */
814 CASE (0, 254) : /* fall through */
817 static const DECODE_DESC insns
[16] = {
818 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
819 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
820 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
821 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
822 { I (INSN_BCL24
), E (FMT_BCL24
) }, { I (INSN_BNCL24
), E (FMT_BCL24
) },
823 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
824 { I (INSN_BC24
), E (FMT_BC24
) }, { I (INSN_BNC24
), E (FMT_BC24
) },
825 { I (INSN_BL24
), E (FMT_BL24
) }, { I (INSN_BRA24
), E (FMT_BRA24
) },
827 unsigned int val
= (((insn
>> 8) & (15 << 0)));
828 idecode
= &insns
[val
];
829 GOTO_EXTRACT (idecode
);
832 idecode
= &insns
[val
];
833 GOTO_EXTRACT (idecode
);
841 /* The instruction has been decoded, now extract the fields. */
846 switch (idecode
->ifmt
)
850 CASE (ex
, FMT_EMPTY
) :
852 CGEN_INSN_INT insn
= entire_insn
;
853 #define FLD(f) abuf->fields.fmt_empty.f
854 EXTRACT_FMT_EMPTY_VARS
/* */
856 EXTRACT_FMT_EMPTY_CODE
858 /* Record the fields for the semantic handler. */
859 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_empty", (char *) 0));
867 CGEN_INSN_INT insn
= entire_insn
;
868 #define FLD(f) abuf->fields.fmt_add.f
869 EXTRACT_FMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
873 /* Record the fields for the semantic handler. */
874 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
875 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
876 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_add", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
878 #if WITH_PROFILE_MODEL_P
879 /* Record the fields for profiling. */
880 if (PROFILE_MODEL_P (current_cpu
))
891 CASE (ex
, FMT_ADD3
) :
893 CGEN_INSN_INT insn
= entire_insn
;
894 #define FLD(f) abuf->fields.fmt_add3.f
895 EXTRACT_FMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
897 EXTRACT_FMT_ADD3_CODE
899 /* Record the fields for the semantic handler. */
900 FLD (f_simm16
) = f_simm16
;
901 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
902 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
903 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
905 #if WITH_PROFILE_MODEL_P
906 /* Record the fields for profiling. */
907 if (PROFILE_MODEL_P (current_cpu
))
917 CASE (ex
, FMT_AND3
) :
919 CGEN_INSN_INT insn
= entire_insn
;
920 #define FLD(f) abuf->fields.fmt_and3.f
921 EXTRACT_FMT_AND3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
923 EXTRACT_FMT_AND3_CODE
925 /* Record the fields for the semantic handler. */
926 FLD (f_uimm16
) = f_uimm16
;
927 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
928 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
929 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
931 #if WITH_PROFILE_MODEL_P
932 /* Record the fields for profiling. */
933 if (PROFILE_MODEL_P (current_cpu
))
945 CGEN_INSN_INT insn
= entire_insn
;
946 #define FLD(f) abuf->fields.fmt_or3.f
947 EXTRACT_FMT_OR3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
951 /* Record the fields for the semantic handler. */
952 FLD (f_uimm16
) = f_uimm16
;
953 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
954 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
955 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
957 #if WITH_PROFILE_MODEL_P
958 /* Record the fields for profiling. */
959 if (PROFILE_MODEL_P (current_cpu
))
969 CASE (ex
, FMT_ADDI
) :
971 CGEN_INSN_INT insn
= entire_insn
;
972 #define FLD(f) abuf->fields.fmt_addi.f
973 EXTRACT_FMT_ADDI_VARS
/* f-op1 f-r1 f-simm8 */
975 EXTRACT_FMT_ADDI_CODE
977 /* Record the fields for the semantic handler. */
978 FLD (f_simm8
) = f_simm8
;
979 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
980 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
982 #if WITH_PROFILE_MODEL_P
983 /* Record the fields for profiling. */
984 if (PROFILE_MODEL_P (current_cpu
))
994 CASE (ex
, FMT_ADDV
) :
996 CGEN_INSN_INT insn
= entire_insn
;
997 #define FLD(f) abuf->fields.fmt_addv.f
998 EXTRACT_FMT_ADDV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1000 EXTRACT_FMT_ADDV_CODE
1002 /* Record the fields for the semantic handler. */
1003 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1004 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1005 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addv", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1007 #if WITH_PROFILE_MODEL_P
1008 /* Record the fields for profiling. */
1009 if (PROFILE_MODEL_P (current_cpu
))
1013 FLD (out_dr
) = f_r1
;
1020 CASE (ex
, FMT_ADDV3
) :
1022 CGEN_INSN_INT insn
= entire_insn
;
1023 #define FLD(f) abuf->fields.fmt_addv3.f
1024 EXTRACT_FMT_ADDV3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1026 EXTRACT_FMT_ADDV3_CODE
1028 /* Record the fields for the semantic handler. */
1029 FLD (f_simm16
) = f_simm16
;
1030 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1031 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1032 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1034 #if WITH_PROFILE_MODEL_P
1035 /* Record the fields for profiling. */
1036 if (PROFILE_MODEL_P (current_cpu
))
1039 FLD (out_dr
) = f_r1
;
1046 CASE (ex
, FMT_ADDX
) :
1048 CGEN_INSN_INT insn
= entire_insn
;
1049 #define FLD(f) abuf->fields.fmt_addx.f
1050 EXTRACT_FMT_ADDX_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1052 EXTRACT_FMT_ADDX_CODE
1054 /* Record the fields for the semantic handler. */
1055 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1056 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1057 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_addx", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1059 #if WITH_PROFILE_MODEL_P
1060 /* Record the fields for profiling. */
1061 if (PROFILE_MODEL_P (current_cpu
))
1065 FLD (out_dr
) = f_r1
;
1072 CASE (ex
, FMT_BC8
) :
1074 CGEN_INSN_INT insn
= entire_insn
;
1075 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
1076 EXTRACT_FMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
1078 EXTRACT_FMT_BC8_CODE
1080 /* Record the fields for the semantic handler. */
1081 FLD (i_disp8
) = f_disp8
;
1082 SEM_BRANCH_INIT_EXTRACT (abuf
);
1083 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bc8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1085 #if WITH_PROFILE_MODEL_P
1086 /* Record the fields for profiling. */
1087 if (PROFILE_MODEL_P (current_cpu
))
1095 CASE (ex
, FMT_BC24
) :
1097 CGEN_INSN_INT insn
= entire_insn
;
1098 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
1099 EXTRACT_FMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
1101 EXTRACT_FMT_BC24_CODE
1103 /* Record the fields for the semantic handler. */
1104 FLD (i_disp24
) = f_disp24
;
1105 SEM_BRANCH_INIT_EXTRACT (abuf
);
1106 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bc24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1108 #if WITH_PROFILE_MODEL_P
1109 /* Record the fields for profiling. */
1110 if (PROFILE_MODEL_P (current_cpu
))
1118 CASE (ex
, FMT_BEQ
) :
1120 CGEN_INSN_INT insn
= entire_insn
;
1121 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
1122 EXTRACT_FMT_BEQ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1124 EXTRACT_FMT_BEQ_CODE
1126 /* Record the fields for the semantic handler. */
1127 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1128 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1129 FLD (i_disp16
) = f_disp16
;
1130 SEM_BRANCH_INIT_EXTRACT (abuf
);
1131 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_beq", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, (char *) 0));
1133 #if WITH_PROFILE_MODEL_P
1134 /* Record the fields for profiling. */
1135 if (PROFILE_MODEL_P (current_cpu
))
1137 FLD (in_src1
) = f_r1
;
1138 FLD (in_src2
) = f_r2
;
1145 CASE (ex
, FMT_BEQZ
) :
1147 CGEN_INSN_INT insn
= entire_insn
;
1148 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
1149 EXTRACT_FMT_BEQZ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1151 EXTRACT_FMT_BEQZ_CODE
1153 /* Record the fields for the semantic handler. */
1154 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1155 FLD (i_disp16
) = f_disp16
;
1156 SEM_BRANCH_INIT_EXTRACT (abuf
);
1157 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_beqz", "src2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, (char *) 0));
1159 #if WITH_PROFILE_MODEL_P
1160 /* Record the fields for profiling. */
1161 if (PROFILE_MODEL_P (current_cpu
))
1163 FLD (in_src2
) = f_r2
;
1170 CASE (ex
, FMT_BL8
) :
1172 CGEN_INSN_INT insn
= entire_insn
;
1173 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
1174 EXTRACT_FMT_BL8_VARS
/* f-op1 f-r1 f-disp8 */
1176 EXTRACT_FMT_BL8_CODE
1178 /* Record the fields for the semantic handler. */
1179 FLD (i_disp8
) = f_disp8
;
1180 SEM_BRANCH_INIT_EXTRACT (abuf
);
1181 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1183 #if WITH_PROFILE_MODEL_P
1184 /* Record the fields for profiling. */
1185 if (PROFILE_MODEL_P (current_cpu
))
1187 FLD (out_h_gr_14
) = 14;
1194 CASE (ex
, FMT_BL24
) :
1196 CGEN_INSN_INT insn
= entire_insn
;
1197 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1198 EXTRACT_FMT_BL24_VARS
/* f-op1 f-r1 f-disp24 */
1200 EXTRACT_FMT_BL24_CODE
1202 /* Record the fields for the semantic handler. */
1203 FLD (i_disp24
) = f_disp24
;
1204 SEM_BRANCH_INIT_EXTRACT (abuf
);
1205 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1207 #if WITH_PROFILE_MODEL_P
1208 /* Record the fields for profiling. */
1209 if (PROFILE_MODEL_P (current_cpu
))
1211 FLD (out_h_gr_14
) = 14;
1218 CASE (ex
, FMT_BCL8
) :
1220 CGEN_INSN_INT insn
= entire_insn
;
1221 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
1222 EXTRACT_FMT_BCL8_VARS
/* f-op1 f-r1 f-disp8 */
1224 EXTRACT_FMT_BCL8_CODE
1226 /* Record the fields for the semantic handler. */
1227 FLD (i_disp8
) = f_disp8
;
1228 SEM_BRANCH_INIT_EXTRACT (abuf
);
1229 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1231 #if WITH_PROFILE_MODEL_P
1232 /* Record the fields for profiling. */
1233 if (PROFILE_MODEL_P (current_cpu
))
1235 FLD (out_h_gr_14
) = 14;
1242 CASE (ex
, FMT_BCL24
) :
1244 CGEN_INSN_INT insn
= entire_insn
;
1245 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
1246 EXTRACT_FMT_BCL24_VARS
/* f-op1 f-r1 f-disp24 */
1248 EXTRACT_FMT_BCL24_CODE
1250 /* Record the fields for the semantic handler. */
1251 FLD (i_disp24
) = f_disp24
;
1252 SEM_BRANCH_INIT_EXTRACT (abuf
);
1253 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1255 #if WITH_PROFILE_MODEL_P
1256 /* Record the fields for profiling. */
1257 if (PROFILE_MODEL_P (current_cpu
))
1259 FLD (out_h_gr_14
) = 14;
1266 CASE (ex
, FMT_BRA8
) :
1268 CGEN_INSN_INT insn
= entire_insn
;
1269 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1270 EXTRACT_FMT_BRA8_VARS
/* f-op1 f-r1 f-disp8 */
1272 EXTRACT_FMT_BRA8_CODE
1274 /* Record the fields for the semantic handler. */
1275 FLD (i_disp8
) = f_disp8
;
1276 SEM_BRANCH_INIT_EXTRACT (abuf
);
1277 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bra8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1279 #if WITH_PROFILE_MODEL_P
1280 /* Record the fields for profiling. */
1281 if (PROFILE_MODEL_P (current_cpu
))
1289 CASE (ex
, FMT_BRA24
) :
1291 CGEN_INSN_INT insn
= entire_insn
;
1292 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1293 EXTRACT_FMT_BRA24_VARS
/* f-op1 f-r1 f-disp24 */
1295 EXTRACT_FMT_BRA24_CODE
1297 /* Record the fields for the semantic handler. */
1298 FLD (i_disp24
) = f_disp24
;
1299 SEM_BRANCH_INIT_EXTRACT (abuf
);
1300 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_bra24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1302 #if WITH_PROFILE_MODEL_P
1303 /* Record the fields for profiling. */
1304 if (PROFILE_MODEL_P (current_cpu
))
1312 CASE (ex
, FMT_CMP
) :
1314 CGEN_INSN_INT insn
= entire_insn
;
1315 #define FLD(f) abuf->fields.fmt_cmp.f
1316 EXTRACT_FMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1318 EXTRACT_FMT_CMP_CODE
1320 /* Record the fields for the semantic handler. */
1321 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1322 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1323 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_cmp", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1325 #if WITH_PROFILE_MODEL_P
1326 /* Record the fields for profiling. */
1327 if (PROFILE_MODEL_P (current_cpu
))
1329 FLD (in_src1
) = f_r1
;
1330 FLD (in_src2
) = f_r2
;
1337 CASE (ex
, FMT_CMPI
) :
1339 CGEN_INSN_INT insn
= entire_insn
;
1340 #define FLD(f) abuf->fields.fmt_cmpi.f
1341 EXTRACT_FMT_CMPI_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1343 EXTRACT_FMT_CMPI_CODE
1345 /* Record the fields for the semantic handler. */
1346 FLD (f_simm16
) = f_simm16
;
1347 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1348 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1350 #if WITH_PROFILE_MODEL_P
1351 /* Record the fields for profiling. */
1352 if (PROFILE_MODEL_P (current_cpu
))
1354 FLD (in_src2
) = f_r2
;
1361 CASE (ex
, FMT_CMPZ
) :
1363 CGEN_INSN_INT insn
= entire_insn
;
1364 #define FLD(f) abuf->fields.fmt_cmpz.f
1365 EXTRACT_FMT_CMPZ_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1367 EXTRACT_FMT_CMPZ_CODE
1369 /* Record the fields for the semantic handler. */
1370 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1371 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_cmpz", "src2 0x%x", 'x', f_r2
, (char *) 0));
1373 #if WITH_PROFILE_MODEL_P
1374 /* Record the fields for profiling. */
1375 if (PROFILE_MODEL_P (current_cpu
))
1377 FLD (in_src2
) = f_r2
;
1384 CASE (ex
, FMT_DIV
) :
1386 CGEN_INSN_INT insn
= entire_insn
;
1387 #define FLD(f) abuf->fields.fmt_div.f
1388 EXTRACT_FMT_DIV_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1390 EXTRACT_FMT_DIV_CODE
1392 /* Record the fields for the semantic handler. */
1393 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1394 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1395 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_div", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1397 #if WITH_PROFILE_MODEL_P
1398 /* Record the fields for profiling. */
1399 if (PROFILE_MODEL_P (current_cpu
))
1403 FLD (out_dr
) = f_r1
;
1412 CGEN_INSN_INT insn
= entire_insn
;
1413 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1414 EXTRACT_FMT_JC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1418 /* Record the fields for the semantic handler. */
1419 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1420 SEM_BRANCH_INIT_EXTRACT (abuf
);
1421 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_jc", "sr 0x%x", 'x', f_r2
, (char *) 0));
1423 #if WITH_PROFILE_MODEL_P
1424 /* Record the fields for profiling. */
1425 if (PROFILE_MODEL_P (current_cpu
))
1436 CGEN_INSN_INT insn
= entire_insn
;
1437 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1438 EXTRACT_FMT_JL_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1442 /* Record the fields for the semantic handler. */
1443 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1444 SEM_BRANCH_INIT_EXTRACT (abuf
);
1445 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_jl", "sr 0x%x", 'x', f_r2
, (char *) 0));
1447 #if WITH_PROFILE_MODEL_P
1448 /* Record the fields for profiling. */
1449 if (PROFILE_MODEL_P (current_cpu
))
1452 FLD (out_h_gr_14
) = 14;
1459 CASE (ex
, FMT_JMP
) :
1461 CGEN_INSN_INT insn
= entire_insn
;
1462 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1463 EXTRACT_FMT_JMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1465 EXTRACT_FMT_JMP_CODE
1467 /* Record the fields for the semantic handler. */
1468 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1469 SEM_BRANCH_INIT_EXTRACT (abuf
);
1470 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_jmp", "sr 0x%x", 'x', f_r2
, (char *) 0));
1472 #if WITH_PROFILE_MODEL_P
1473 /* Record the fields for profiling. */
1474 if (PROFILE_MODEL_P (current_cpu
))
1485 CGEN_INSN_INT insn
= entire_insn
;
1486 #define FLD(f) abuf->fields.fmt_ld.f
1487 EXTRACT_FMT_LD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1491 /* Record the fields for the semantic handler. */
1492 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1493 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1494 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1496 #if WITH_PROFILE_MODEL_P
1497 /* Record the fields for profiling. */
1498 if (PROFILE_MODEL_P (current_cpu
))
1501 FLD (out_dr
) = f_r1
;
1508 CASE (ex
, FMT_LD_D
) :
1510 CGEN_INSN_INT insn
= entire_insn
;
1511 #define FLD(f) abuf->fields.fmt_ld_d.f
1512 EXTRACT_FMT_LD_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1514 EXTRACT_FMT_LD_D_CODE
1516 /* Record the fields for the semantic handler. */
1517 FLD (f_simm16
) = f_simm16
;
1518 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1519 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1520 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1522 #if WITH_PROFILE_MODEL_P
1523 /* Record the fields for profiling. */
1524 if (PROFILE_MODEL_P (current_cpu
))
1527 FLD (out_dr
) = f_r1
;
1534 CASE (ex
, FMT_LDB
) :
1536 CGEN_INSN_INT insn
= entire_insn
;
1537 #define FLD(f) abuf->fields.fmt_ldb.f
1538 EXTRACT_FMT_LDB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1540 EXTRACT_FMT_LDB_CODE
1542 /* Record the fields for the semantic handler. */
1543 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1544 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1545 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldb", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1547 #if WITH_PROFILE_MODEL_P
1548 /* Record the fields for profiling. */
1549 if (PROFILE_MODEL_P (current_cpu
))
1552 FLD (out_dr
) = f_r1
;
1559 CASE (ex
, FMT_LDB_D
) :
1561 CGEN_INSN_INT insn
= entire_insn
;
1562 #define FLD(f) abuf->fields.fmt_ldb_d.f
1563 EXTRACT_FMT_LDB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1565 EXTRACT_FMT_LDB_D_CODE
1567 /* Record the fields for the semantic handler. */
1568 FLD (f_simm16
) = f_simm16
;
1569 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1570 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1571 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1573 #if WITH_PROFILE_MODEL_P
1574 /* Record the fields for profiling. */
1575 if (PROFILE_MODEL_P (current_cpu
))
1578 FLD (out_dr
) = f_r1
;
1585 CASE (ex
, FMT_LDH
) :
1587 CGEN_INSN_INT insn
= entire_insn
;
1588 #define FLD(f) abuf->fields.fmt_ldh.f
1589 EXTRACT_FMT_LDH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1591 EXTRACT_FMT_LDH_CODE
1593 /* Record the fields for the semantic handler. */
1594 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1595 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1596 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldh", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1598 #if WITH_PROFILE_MODEL_P
1599 /* Record the fields for profiling. */
1600 if (PROFILE_MODEL_P (current_cpu
))
1603 FLD (out_dr
) = f_r1
;
1610 CASE (ex
, FMT_LDH_D
) :
1612 CGEN_INSN_INT insn
= entire_insn
;
1613 #define FLD(f) abuf->fields.fmt_ldh_d.f
1614 EXTRACT_FMT_LDH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1616 EXTRACT_FMT_LDH_D_CODE
1618 /* Record the fields for the semantic handler. */
1619 FLD (f_simm16
) = f_simm16
;
1620 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1621 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1622 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1624 #if WITH_PROFILE_MODEL_P
1625 /* Record the fields for profiling. */
1626 if (PROFILE_MODEL_P (current_cpu
))
1629 FLD (out_dr
) = f_r1
;
1636 CASE (ex
, FMT_LD_PLUS
) :
1638 CGEN_INSN_INT insn
= entire_insn
;
1639 #define FLD(f) abuf->fields.fmt_ld_plus.f
1640 EXTRACT_FMT_LD_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1642 EXTRACT_FMT_LD_PLUS_CODE
1644 /* Record the fields for the semantic handler. */
1645 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1646 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1647 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld_plus", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1649 #if WITH_PROFILE_MODEL_P
1650 /* Record the fields for profiling. */
1651 if (PROFILE_MODEL_P (current_cpu
))
1654 FLD (out_dr
) = f_r1
;
1655 FLD (out_sr
) = f_r2
;
1662 CASE (ex
, FMT_LD24
) :
1664 CGEN_INSN_INT insn
= entire_insn
;
1665 #define FLD(f) abuf->fields.fmt_ld24.f
1666 EXTRACT_FMT_LD24_VARS
/* f-op1 f-r1 f-uimm24 */
1668 EXTRACT_FMT_LD24_CODE
1670 /* Record the fields for the semantic handler. */
1671 FLD (i_uimm24
) = f_uimm24
;
1672 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1673 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1675 #if WITH_PROFILE_MODEL_P
1676 /* Record the fields for profiling. */
1677 if (PROFILE_MODEL_P (current_cpu
))
1679 FLD (out_dr
) = f_r1
;
1686 CASE (ex
, FMT_LDI8
) :
1688 CGEN_INSN_INT insn
= entire_insn
;
1689 #define FLD(f) abuf->fields.fmt_ldi8.f
1690 EXTRACT_FMT_LDI8_VARS
/* f-op1 f-r1 f-simm8 */
1692 EXTRACT_FMT_LDI8_CODE
1694 /* Record the fields for the semantic handler. */
1695 FLD (f_simm8
) = f_simm8
;
1696 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1697 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1699 #if WITH_PROFILE_MODEL_P
1700 /* Record the fields for profiling. */
1701 if (PROFILE_MODEL_P (current_cpu
))
1703 FLD (out_dr
) = f_r1
;
1710 CASE (ex
, FMT_LDI16
) :
1712 CGEN_INSN_INT insn
= entire_insn
;
1713 #define FLD(f) abuf->fields.fmt_ldi16.f
1714 EXTRACT_FMT_LDI16_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1716 EXTRACT_FMT_LDI16_CODE
1718 /* Record the fields for the semantic handler. */
1719 FLD (f_simm16
) = f_simm16
;
1720 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1721 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1723 #if WITH_PROFILE_MODEL_P
1724 /* Record the fields for profiling. */
1725 if (PROFILE_MODEL_P (current_cpu
))
1727 FLD (out_dr
) = f_r1
;
1734 CASE (ex
, FMT_LOCK
) :
1736 CGEN_INSN_INT insn
= entire_insn
;
1737 #define FLD(f) abuf->fields.fmt_lock.f
1738 EXTRACT_FMT_LOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1740 EXTRACT_FMT_LOCK_CODE
1742 /* Record the fields for the semantic handler. */
1743 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1744 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1745 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_lock", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1747 #if WITH_PROFILE_MODEL_P
1748 /* Record the fields for profiling. */
1749 if (PROFILE_MODEL_P (current_cpu
))
1752 FLD (out_dr
) = f_r1
;
1759 CASE (ex
, FMT_MACHI_A
) :
1761 CGEN_INSN_INT insn
= entire_insn
;
1762 #define FLD(f) abuf->fields.fmt_machi_a.f
1763 EXTRACT_FMT_MACHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
1765 EXTRACT_FMT_MACHI_A_CODE
1767 /* Record the fields for the semantic handler. */
1768 FLD (f_acc
) = f_acc
;
1769 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1770 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1771 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_machi_a", "f_acc 0x%x", 'x', f_acc
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1773 #if WITH_PROFILE_MODEL_P
1774 /* Record the fields for profiling. */
1775 if (PROFILE_MODEL_P (current_cpu
))
1777 FLD (in_src1
) = f_r1
;
1778 FLD (in_src2
) = f_r2
;
1785 CASE (ex
, FMT_MULHI_A
) :
1787 CGEN_INSN_INT insn
= entire_insn
;
1788 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1789 EXTRACT_FMT_MULHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
1791 EXTRACT_FMT_MULHI_A_CODE
1793 /* Record the fields for the semantic handler. */
1794 FLD (f_acc
) = f_acc
;
1795 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1796 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1797 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mulhi_a", "f_acc 0x%x", 'x', f_acc
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1799 #if WITH_PROFILE_MODEL_P
1800 /* Record the fields for profiling. */
1801 if (PROFILE_MODEL_P (current_cpu
))
1803 FLD (in_src1
) = f_r1
;
1804 FLD (in_src2
) = f_r2
;
1813 CGEN_INSN_INT insn
= entire_insn
;
1814 #define FLD(f) abuf->fields.fmt_mv.f
1815 EXTRACT_FMT_MV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1819 /* Record the fields for the semantic handler. */
1820 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1821 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1822 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mv", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1824 #if WITH_PROFILE_MODEL_P
1825 /* Record the fields for profiling. */
1826 if (PROFILE_MODEL_P (current_cpu
))
1829 FLD (out_dr
) = f_r1
;
1836 CASE (ex
, FMT_MVFACHI_A
) :
1838 CGEN_INSN_INT insn
= entire_insn
;
1839 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1840 EXTRACT_FMT_MVFACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
1842 EXTRACT_FMT_MVFACHI_A_CODE
1844 /* Record the fields for the semantic handler. */
1845 FLD (f_accs
) = f_accs
;
1846 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1847 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1849 #if WITH_PROFILE_MODEL_P
1850 /* Record the fields for profiling. */
1851 if (PROFILE_MODEL_P (current_cpu
))
1853 FLD (out_dr
) = f_r1
;
1860 CASE (ex
, FMT_MVFC
) :
1862 CGEN_INSN_INT insn
= entire_insn
;
1863 #define FLD(f) abuf->fields.fmt_mvfc.f
1864 EXTRACT_FMT_MVFC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1866 EXTRACT_FMT_MVFC_CODE
1868 /* Record the fields for the semantic handler. */
1870 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1871 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1873 #if WITH_PROFILE_MODEL_P
1874 /* Record the fields for profiling. */
1875 if (PROFILE_MODEL_P (current_cpu
))
1877 FLD (out_dr
) = f_r1
;
1884 CASE (ex
, FMT_MVTACHI_A
) :
1886 CGEN_INSN_INT insn
= entire_insn
;
1887 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1888 EXTRACT_FMT_MVTACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
1890 EXTRACT_FMT_MVTACHI_A_CODE
1892 /* Record the fields for the semantic handler. */
1893 FLD (f_accs
) = f_accs
;
1894 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1895 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs
, "src1 0x%x", 'x', f_r1
, (char *) 0));
1897 #if WITH_PROFILE_MODEL_P
1898 /* Record the fields for profiling. */
1899 if (PROFILE_MODEL_P (current_cpu
))
1901 FLD (in_src1
) = f_r1
;
1908 CASE (ex
, FMT_MVTC
) :
1910 CGEN_INSN_INT insn
= entire_insn
;
1911 #define FLD(f) abuf->fields.fmt_mvtc.f
1912 EXTRACT_FMT_MVTC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1914 EXTRACT_FMT_MVTC_CODE
1916 /* Record the fields for the semantic handler. */
1918 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1919 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1921 #if WITH_PROFILE_MODEL_P
1922 /* Record the fields for profiling. */
1923 if (PROFILE_MODEL_P (current_cpu
))
1932 CASE (ex
, FMT_NOP
) :
1934 CGEN_INSN_INT insn
= entire_insn
;
1935 #define FLD(f) abuf->fields.fmt_nop.f
1936 EXTRACT_FMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1938 EXTRACT_FMT_NOP_CODE
1940 /* Record the fields for the semantic handler. */
1941 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_nop", (char *) 0));
1947 CASE (ex
, FMT_RAC_DSI
) :
1949 CGEN_INSN_INT insn
= entire_insn
;
1950 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1951 EXTRACT_FMT_RAC_DSI_VARS
/* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
1953 EXTRACT_FMT_RAC_DSI_CODE
1955 /* Record the fields for the semantic handler. */
1956 FLD (f_accs
) = f_accs
;
1957 FLD (f_imm1
) = f_imm1
;
1958 FLD (f_accd
) = f_accd
;
1959 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_rac_dsi", "f_accs 0x%x", 'x', f_accs
, "f_imm1 0x%x", 'x', f_imm1
, "f_accd 0x%x", 'x', f_accd
, (char *) 0));
1965 CASE (ex
, FMT_RTE
) :
1967 CGEN_INSN_INT insn
= entire_insn
;
1968 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1969 EXTRACT_FMT_RTE_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1971 EXTRACT_FMT_RTE_CODE
1973 /* Record the fields for the semantic handler. */
1974 SEM_BRANCH_INIT_EXTRACT (abuf
);
1975 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_rte", (char *) 0));
1977 #if WITH_PROFILE_MODEL_P
1978 /* Record the fields for profiling. */
1979 if (PROFILE_MODEL_P (current_cpu
))
1987 CASE (ex
, FMT_SETH
) :
1989 CGEN_INSN_INT insn
= entire_insn
;
1990 #define FLD(f) abuf->fields.fmt_seth.f
1991 EXTRACT_FMT_SETH_VARS
/* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1993 EXTRACT_FMT_SETH_CODE
1995 /* Record the fields for the semantic handler. */
1996 FLD (f_hi16
) = f_hi16
;
1997 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1998 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2000 #if WITH_PROFILE_MODEL_P
2001 /* Record the fields for profiling. */
2002 if (PROFILE_MODEL_P (current_cpu
))
2004 FLD (out_dr
) = f_r1
;
2011 CASE (ex
, FMT_SLL3
) :
2013 CGEN_INSN_INT insn
= entire_insn
;
2014 #define FLD(f) abuf->fields.fmt_sll3.f
2015 EXTRACT_FMT_SLL3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2017 EXTRACT_FMT_SLL3_CODE
2019 /* Record the fields for the semantic handler. */
2020 FLD (f_simm16
) = f_simm16
;
2021 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2022 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2023 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16
, "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2025 #if WITH_PROFILE_MODEL_P
2026 /* Record the fields for profiling. */
2027 if (PROFILE_MODEL_P (current_cpu
))
2030 FLD (out_dr
) = f_r1
;
2037 CASE (ex
, FMT_SLLI
) :
2039 CGEN_INSN_INT insn
= entire_insn
;
2040 #define FLD(f) abuf->fields.fmt_slli.f
2041 EXTRACT_FMT_SLLI_VARS
/* f-op1 f-r1 f-shift-op2 f-uimm5 */
2043 EXTRACT_FMT_SLLI_CODE
2045 /* Record the fields for the semantic handler. */
2046 FLD (f_uimm5
) = f_uimm5
;
2047 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2048 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2050 #if WITH_PROFILE_MODEL_P
2051 /* Record the fields for profiling. */
2052 if (PROFILE_MODEL_P (current_cpu
))
2055 FLD (out_dr
) = f_r1
;
2064 CGEN_INSN_INT insn
= entire_insn
;
2065 #define FLD(f) abuf->fields.fmt_st.f
2066 EXTRACT_FMT_ST_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2070 /* Record the fields for the semantic handler. */
2071 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2072 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2073 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2075 #if WITH_PROFILE_MODEL_P
2076 /* Record the fields for profiling. */
2077 if (PROFILE_MODEL_P (current_cpu
))
2079 FLD (in_src2
) = f_r2
;
2080 FLD (in_src1
) = f_r1
;
2087 CASE (ex
, FMT_ST_D
) :
2089 CGEN_INSN_INT insn
= entire_insn
;
2090 #define FLD(f) abuf->fields.fmt_st_d.f
2091 EXTRACT_FMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2093 EXTRACT_FMT_ST_D_CODE
2095 /* Record the fields for the semantic handler. */
2096 FLD (f_simm16
) = f_simm16
;
2097 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2098 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2099 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16
, "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2101 #if WITH_PROFILE_MODEL_P
2102 /* Record the fields for profiling. */
2103 if (PROFILE_MODEL_P (current_cpu
))
2105 FLD (in_src2
) = f_r2
;
2106 FLD (in_src1
) = f_r1
;
2113 CASE (ex
, FMT_STB
) :
2115 CGEN_INSN_INT insn
= entire_insn
;
2116 #define FLD(f) abuf->fields.fmt_stb.f
2117 EXTRACT_FMT_STB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2119 EXTRACT_FMT_STB_CODE
2121 /* Record the fields for the semantic handler. */
2122 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2123 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2124 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_stb", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2126 #if WITH_PROFILE_MODEL_P
2127 /* Record the fields for profiling. */
2128 if (PROFILE_MODEL_P (current_cpu
))
2130 FLD (in_src2
) = f_r2
;
2131 FLD (in_src1
) = f_r1
;
2138 CASE (ex
, FMT_STB_D
) :
2140 CGEN_INSN_INT insn
= entire_insn
;
2141 #define FLD(f) abuf->fields.fmt_stb_d.f
2142 EXTRACT_FMT_STB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2144 EXTRACT_FMT_STB_D_CODE
2146 /* Record the fields for the semantic handler. */
2147 FLD (f_simm16
) = f_simm16
;
2148 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2149 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2150 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16
, "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2152 #if WITH_PROFILE_MODEL_P
2153 /* Record the fields for profiling. */
2154 if (PROFILE_MODEL_P (current_cpu
))
2156 FLD (in_src2
) = f_r2
;
2157 FLD (in_src1
) = f_r1
;
2164 CASE (ex
, FMT_STH
) :
2166 CGEN_INSN_INT insn
= entire_insn
;
2167 #define FLD(f) abuf->fields.fmt_sth.f
2168 EXTRACT_FMT_STH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2170 EXTRACT_FMT_STH_CODE
2172 /* Record the fields for the semantic handler. */
2173 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2174 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2175 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sth", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2177 #if WITH_PROFILE_MODEL_P
2178 /* Record the fields for profiling. */
2179 if (PROFILE_MODEL_P (current_cpu
))
2181 FLD (in_src2
) = f_r2
;
2182 FLD (in_src1
) = f_r1
;
2189 CASE (ex
, FMT_STH_D
) :
2191 CGEN_INSN_INT insn
= entire_insn
;
2192 #define FLD(f) abuf->fields.fmt_sth_d.f
2193 EXTRACT_FMT_STH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2195 EXTRACT_FMT_STH_D_CODE
2197 /* Record the fields for the semantic handler. */
2198 FLD (f_simm16
) = f_simm16
;
2199 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2200 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2201 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16
, "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2203 #if WITH_PROFILE_MODEL_P
2204 /* Record the fields for profiling. */
2205 if (PROFILE_MODEL_P (current_cpu
))
2207 FLD (in_src2
) = f_r2
;
2208 FLD (in_src1
) = f_r1
;
2215 CASE (ex
, FMT_ST_PLUS
) :
2217 CGEN_INSN_INT insn
= entire_insn
;
2218 #define FLD(f) abuf->fields.fmt_st_plus.f
2219 EXTRACT_FMT_ST_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2221 EXTRACT_FMT_ST_PLUS_CODE
2223 /* Record the fields for the semantic handler. */
2224 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2225 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2226 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_st_plus", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2228 #if WITH_PROFILE_MODEL_P
2229 /* Record the fields for profiling. */
2230 if (PROFILE_MODEL_P (current_cpu
))
2232 FLD (in_src2
) = f_r2
;
2233 FLD (in_src1
) = f_r1
;
2234 FLD (out_src2
) = f_r2
;
2241 CASE (ex
, FMT_TRAP
) :
2243 CGEN_INSN_INT insn
= entire_insn
;
2244 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2245 EXTRACT_FMT_TRAP_VARS
/* f-op1 f-r1 f-op2 f-uimm4 */
2247 EXTRACT_FMT_TRAP_CODE
2249 /* Record the fields for the semantic handler. */
2250 FLD (f_uimm4
) = f_uimm4
;
2251 SEM_BRANCH_INIT_EXTRACT (abuf
);
2252 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4
, (char *) 0));
2254 #if WITH_PROFILE_MODEL_P
2255 /* Record the fields for profiling. */
2256 if (PROFILE_MODEL_P (current_cpu
))
2264 CASE (ex
, FMT_UNLOCK
) :
2266 CGEN_INSN_INT insn
= entire_insn
;
2267 #define FLD(f) abuf->fields.fmt_unlock.f
2268 EXTRACT_FMT_UNLOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2270 EXTRACT_FMT_UNLOCK_CODE
2272 /* Record the fields for the semantic handler. */
2273 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2274 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2275 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_unlock", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2277 #if WITH_PROFILE_MODEL_P
2278 /* Record the fields for profiling. */
2279 if (PROFILE_MODEL_P (current_cpu
))
2281 FLD (in_src2
) = f_r2
;
2282 FLD (in_src1
) = f_r1
;
2289 CASE (ex
, FMT_SATB
) :
2291 CGEN_INSN_INT insn
= entire_insn
;
2292 #define FLD(f) abuf->fields.fmt_satb.f
2293 EXTRACT_FMT_SATB_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2295 EXTRACT_FMT_SATB_CODE
2297 /* Record the fields for the semantic handler. */
2298 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2299 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2300 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_satb", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2302 #if WITH_PROFILE_MODEL_P
2303 /* Record the fields for profiling. */
2304 if (PROFILE_MODEL_P (current_cpu
))
2307 FLD (out_dr
) = f_r1
;
2314 CASE (ex
, FMT_SAT
) :
2316 CGEN_INSN_INT insn
= entire_insn
;
2317 #define FLD(f) abuf->fields.fmt_sat.f
2318 EXTRACT_FMT_SAT_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2320 EXTRACT_FMT_SAT_CODE
2322 /* Record the fields for the semantic handler. */
2323 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2324 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2325 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sat", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2327 #if WITH_PROFILE_MODEL_P
2328 /* Record the fields for profiling. */
2329 if (PROFILE_MODEL_P (current_cpu
))
2332 FLD (out_dr
) = f_r1
;
2339 CASE (ex
, FMT_SADD
) :
2341 CGEN_INSN_INT insn
= entire_insn
;
2342 #define FLD(f) abuf->fields.fmt_sadd.f
2343 EXTRACT_FMT_SADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2345 EXTRACT_FMT_SADD_CODE
2347 /* Record the fields for the semantic handler. */
2348 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sadd", (char *) 0));
2354 CASE (ex
, FMT_MACWU1
) :
2356 CGEN_INSN_INT insn
= entire_insn
;
2357 #define FLD(f) abuf->fields.fmt_macwu1.f
2358 EXTRACT_FMT_MACWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2360 EXTRACT_FMT_MACWU1_CODE
2362 /* Record the fields for the semantic handler. */
2363 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2364 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2365 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_macwu1", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2367 #if WITH_PROFILE_MODEL_P
2368 /* Record the fields for profiling. */
2369 if (PROFILE_MODEL_P (current_cpu
))
2371 FLD (in_src1
) = f_r1
;
2372 FLD (in_src2
) = f_r2
;
2379 CASE (ex
, FMT_MSBLO
) :
2381 CGEN_INSN_INT insn
= entire_insn
;
2382 #define FLD(f) abuf->fields.fmt_msblo.f
2383 EXTRACT_FMT_MSBLO_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2385 EXTRACT_FMT_MSBLO_CODE
2387 /* Record the fields for the semantic handler. */
2388 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2389 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2390 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_msblo", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2392 #if WITH_PROFILE_MODEL_P
2393 /* Record the fields for profiling. */
2394 if (PROFILE_MODEL_P (current_cpu
))
2396 FLD (in_src1
) = f_r1
;
2397 FLD (in_src2
) = f_r2
;
2404 CASE (ex
, FMT_MULWU1
) :
2406 CGEN_INSN_INT insn
= entire_insn
;
2407 #define FLD(f) abuf->fields.fmt_mulwu1.f
2408 EXTRACT_FMT_MULWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2410 EXTRACT_FMT_MULWU1_CODE
2412 /* Record the fields for the semantic handler. */
2413 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2414 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2415 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_mulwu1", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2417 #if WITH_PROFILE_MODEL_P
2418 /* Record the fields for profiling. */
2419 if (PROFILE_MODEL_P (current_cpu
))
2421 FLD (in_src1
) = f_r1
;
2422 FLD (in_src2
) = f_r2
;
2431 CGEN_INSN_INT insn
= entire_insn
;
2432 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2433 EXTRACT_FMT_SC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2437 /* Record the fields for the semantic handler. */
2438 SEM_BRANCH_INIT_EXTRACT (abuf
);
2439 TRACE_EXTRACT (current_cpu
, abuf
, (current_cpu
, pc
, "fmt_sc", (char *) 0));
2451 return idecode
->idesc
;
projects / binutils-gdb.git / blob