projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
2001-11-14 Dave Brolley <brolley@redhat.com>
[binutils-gdb.git] / sim / m32r / decodex.c
1 /* Simulator instruction decoder for m32rxf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
6
7 This file is part of the GNU simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
27
28 #include "sim-main.h"
29 #include "sim-assert.h"
30
31 /* Insn can't be executed in parallel.
32 Or is that "do NOt Pass to Air defense Radar"? :-) */
33 #define NOPAR (-1)
34
35 /* The instruction descriptor array.
36 This is computed at runtime. Space for it is not malloc'd to save a
37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
38 but won't be done until necessary (we don't currently support the runtime
39 addition of instructions nor an SMP machine with different cpus). */
40 static IDESC m32rxf_insn_data[M32RXF_INSN_SNC + 1];
41
42 /* Commas between elements are contained in the macros.
43 Some of these are conditionally compiled out. */
44
45 static const struct insn_sem m32rxf_insn_sem[] =
46 {
47 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
52 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
53 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
54 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR },
55 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
56 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
57 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
58 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR },
59 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
60 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
61 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
62 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
63 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR },
64 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
65 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
66 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
67 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
68 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
74 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
75 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR },
76 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
77 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
78 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
79 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
80 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
81 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
82 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR },
83 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
84 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
85 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
86 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
87 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
88 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
89 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
90 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
91 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR },
96 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
97 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
98 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
99 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
100 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
101 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
102 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
103 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
104 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
105 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
106 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LDB, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
107 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LDB_D, NOPAR, NOPAR },
108 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LDH, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
109 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LDH_D, NOPAR, NOPAR },
110 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
111 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR },
112 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
113 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR },
114 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
115 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
116 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
117 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
118 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
119 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
120 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
121 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
122 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
123 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
124 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
125 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
126 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
127 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
128 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
129 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
130 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
131 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
132 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
133 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
134 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
135 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
136 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
137 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
138 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR },
139 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
140 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
141 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
142 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
143 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
144 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
145 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
146 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
147 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
148 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
149 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR },
150 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
151 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR },
152 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
153 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
154 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
155 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
156 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
157 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
158 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
159 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
160 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
161 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR },
162 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR },
163 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR },
164 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
165 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
166 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
167 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
168 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
169 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
170 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
171 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
172 };
173
174 static const struct insn_sem m32rxf_insn_sem_invalid = {
175 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
176 };
177
178 /* Initialize an IDESC from the compile-time computable parts. */
179
180 static INLINE void
181 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
182 {
183 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
184
185 id->num = t->index;
186 id->sfmt = t->sfmt;
187 if ((int) t->type <= 0)
188 id->idata = & cgen_virtual_insn_table[- (int) t->type];
189 else
190 id->idata = & insn_table[t->type];
191 id->attrs = CGEN_INSN_ATTRS (id->idata);
192 /* Oh my god, a magic number. */
193 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
194
195 #if WITH_PROFILE_MODEL_P
196 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
197 {
198 SIM_DESC sd = CPU_STATE (cpu);
199 SIM_ASSERT (t->index == id->timing->num);
200 }
201 #endif
202
203 /* Semantic pointers are initialized elsewhere. */
204 }
205
206 /* Initialize the instruction descriptor table. */
207
208 void
209 m32rxf_init_idesc_table (SIM_CPU *cpu)
210 {
211 IDESC *id,*tabend;
212 const struct insn_sem *t,*tend;
213 int tabsize = sizeof (m32rxf_insn_data) / sizeof (IDESC);
214 IDESC *table = m32rxf_insn_data;
215
216 memset (table, 0, tabsize * sizeof (IDESC));
217
218 /* First set all entries to the `invalid insn'. */
219 t = & m32rxf_insn_sem_invalid;
220 for (id = table, tabend = table + tabsize; id < tabend; ++id)
221 init_idesc (cpu, id, t);
222
223 /* Now fill in the values for the chosen cpu. */
224 for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
225 t != tend; ++t)
226 {
227 init_idesc (cpu, & table[t->index], t);
228 if (t->par_index != NOPAR)
229 {
230 init_idesc (cpu, &table[t->par_index], t);
231 table[t->index].par_idesc = &table[t->par_index];
232 }
233 if (t->par_index != NOPAR)
234 {
235 init_idesc (cpu, &table[t->write_index], t);
236 table[t->par_index].par_idesc = &table[t->write_index];
237 }
238 }
239
240 /* Link the IDESC table into the cpu. */
241 CPU_IDESC (cpu) = table;
242 }
243
244 /* Given an instruction, return a pointer to its IDESC entry. */
245
246 const IDESC *
247 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
248 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
249 ARGBUF *abuf)
250 {
251 /* Result of decoder. */
252 M32RXF_INSN_TYPE itype;
253
254 {
255 CGEN_INSN_INT insn = base_insn;
256
257 {
258 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
259 switch (val)
260 {
261 case 0 : itype = M32RXF_INSN_SUBV;goto extract_sfmt_addv;
262 case 1 : itype = M32RXF_INSN_SUBX;goto extract_sfmt_addx;
263 case 2 : itype = M32RXF_INSN_SUB;goto extract_sfmt_add;
264 case 3 : itype = M32RXF_INSN_NEG;goto extract_sfmt_mv;
265 case 4 : itype = M32RXF_INSN_CMP;goto extract_sfmt_cmp;
266 case 5 : itype = M32RXF_INSN_CMPU;goto extract_sfmt_cmp;
267 case 6 : itype = M32RXF_INSN_CMPEQ;goto extract_sfmt_cmp;
268 case 7 :
269 {
270 unsigned int val = (((insn >> 8) & (3 << 0)));
271 switch (val)
272 {
273 case 0 : itype = M32RXF_INSN_CMPZ;goto extract_sfmt_cmpz;
274 case 3 : itype = M32RXF_INSN_PCMPBZ;goto extract_sfmt_cmpz;
275 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
276 }
277 }
278 case 8 : itype = M32RXF_INSN_ADDV;goto extract_sfmt_addv;
279 case 9 : itype = M32RXF_INSN_ADDX;goto extract_sfmt_addx;
280 case 10 : itype = M32RXF_INSN_ADD;goto extract_sfmt_add;
281 case 11 : itype = M32RXF_INSN_NOT;goto extract_sfmt_mv;
282 case 12 : itype = M32RXF_INSN_AND;goto extract_sfmt_add;
283 case 13 : itype = M32RXF_INSN_XOR;goto extract_sfmt_add;
284 case 14 : itype = M32RXF_INSN_OR;goto extract_sfmt_add;
285 case 16 : itype = M32RXF_INSN_SRL;goto extract_sfmt_add;
286 case 18 : itype = M32RXF_INSN_SRA;goto extract_sfmt_add;
287 case 20 : itype = M32RXF_INSN_SLL;goto extract_sfmt_add;
288 case 22 : itype = M32RXF_INSN_MUL;goto extract_sfmt_add;
289 case 24 : itype = M32RXF_INSN_MV;goto extract_sfmt_mv;
290 case 25 : itype = M32RXF_INSN_MVFC;goto extract_sfmt_mvfc;
291 case 26 : itype = M32RXF_INSN_MVTC;goto extract_sfmt_mvtc;
292 case 28 :
293 {
294 unsigned int val = (((insn >> 8) & (3 << 0)));
295 switch (val)
296 {
297 case 0 : itype = M32RXF_INSN_JC;goto extract_sfmt_jc;
298 case 1 : itype = M32RXF_INSN_JNC;goto extract_sfmt_jc;
299 case 2 : itype = M32RXF_INSN_JL;goto extract_sfmt_jl;
300 case 3 : itype = M32RXF_INSN_JMP;goto extract_sfmt_jmp;
301 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
302 }
303 }
304 case 29 : itype = M32RXF_INSN_RTE;goto extract_sfmt_rte;
305 case 31 : itype = M32RXF_INSN_TRAP;goto extract_sfmt_trap;
306 case 32 : itype = M32RXF_INSN_STB;goto extract_sfmt_stb;
307 case 34 : itype = M32RXF_INSN_STH;goto extract_sfmt_sth;
308 case 36 : itype = M32RXF_INSN_ST;goto extract_sfmt_st;
309 case 37 : itype = M32RXF_INSN_UNLOCK;goto extract_sfmt_unlock;
310 case 38 : itype = M32RXF_INSN_ST_PLUS;goto extract_sfmt_st_plus;
311 case 39 : itype = M32RXF_INSN_ST_MINUS;goto extract_sfmt_st_plus;
312 case 40 : itype = M32RXF_INSN_LDB;goto extract_sfmt_ldb;
313 case 41 : itype = M32RXF_INSN_LDUB;goto extract_sfmt_ldb;
314 case 42 : itype = M32RXF_INSN_LDH;goto extract_sfmt_ldh;
315 case 43 : itype = M32RXF_INSN_LDUH;goto extract_sfmt_ldh;
316 case 44 : itype = M32RXF_INSN_LD;goto extract_sfmt_ld;
317 case 45 : itype = M32RXF_INSN_LOCK;goto extract_sfmt_lock;
318 case 46 : itype = M32RXF_INSN_LD_PLUS;goto extract_sfmt_ld_plus;
319 case 48 : /* fall through */
320 case 56 : itype = M32RXF_INSN_MULHI_A;goto extract_sfmt_mulhi_a;
321 case 49 : /* fall through */
322 case 57 : itype = M32RXF_INSN_MULLO_A;goto extract_sfmt_mulhi_a;
323 case 50 : /* fall through */
324 case 58 : itype = M32RXF_INSN_MULWHI_A;goto extract_sfmt_mulhi_a;
325 case 51 : /* fall through */
326 case 59 : itype = M32RXF_INSN_MULWLO_A;goto extract_sfmt_mulhi_a;
327 case 52 : /* fall through */
328 case 60 : itype = M32RXF_INSN_MACHI_A;goto extract_sfmt_machi_a;
329 case 53 : /* fall through */
330 case 61 : itype = M32RXF_INSN_MACLO_A;goto extract_sfmt_machi_a;
331 case 54 : /* fall through */
332 case 62 : itype = M32RXF_INSN_MACWHI_A;goto extract_sfmt_machi_a;
333 case 55 : /* fall through */
334 case 63 : itype = M32RXF_INSN_MACWLO_A;goto extract_sfmt_machi_a;
335 case 64 : /* fall through */
336 case 65 : /* fall through */
337 case 66 : /* fall through */
338 case 67 : /* fall through */
339 case 68 : /* fall through */
340 case 69 : /* fall through */
341 case 70 : /* fall through */
342 case 71 : /* fall through */
343 case 72 : /* fall through */
344 case 73 : /* fall through */
345 case 74 : /* fall through */
346 case 75 : /* fall through */
347 case 76 : /* fall through */
348 case 77 : /* fall through */
349 case 78 : /* fall through */
350 case 79 : itype = M32RXF_INSN_ADDI;goto extract_sfmt_addi;
351 case 80 : /* fall through */
352 case 81 : itype = M32RXF_INSN_SRLI;goto extract_sfmt_slli;
353 case 82 : /* fall through */
354 case 83 : itype = M32RXF_INSN_SRAI;goto extract_sfmt_slli;
355 case 84 : /* fall through */
356 case 85 : itype = M32RXF_INSN_SLLI;goto extract_sfmt_slli;
357 case 87 :
358 {
359 unsigned int val = (((insn >> 0) & (1 << 0)));
360 switch (val)
361 {
362 case 0 : itype = M32RXF_INSN_MVTACHI_A;goto extract_sfmt_mvtachi_a;
363 case 1 : itype = M32RXF_INSN_MVTACLO_A;goto extract_sfmt_mvtachi_a;
364 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
365 }
366 }
367 case 88 : itype = M32RXF_INSN_RACH_DSI;goto extract_sfmt_rac_dsi;
368 case 89 : itype = M32RXF_INSN_RAC_DSI;goto extract_sfmt_rac_dsi;
369 case 90 : itype = M32RXF_INSN_MULWU1;goto extract_sfmt_mulwu1;
370 case 91 : itype = M32RXF_INSN_MACWU1;goto extract_sfmt_macwu1;
371 case 92 : itype = M32RXF_INSN_MACLH1;goto extract_sfmt_macwu1;
372 case 93 : itype = M32RXF_INSN_MSBLO;goto extract_sfmt_msblo;
373 case 94 : itype = M32RXF_INSN_SADD;goto extract_sfmt_sadd;
374 case 95 :
375 {
376 unsigned int val = (((insn >> 0) & (3 << 0)));
377 switch (val)
378 {
379 case 0 : itype = M32RXF_INSN_MVFACHI_A;goto extract_sfmt_mvfachi_a;
380 case 1 : itype = M32RXF_INSN_MVFACLO_A;goto extract_sfmt_mvfachi_a;
381 case 2 : itype = M32RXF_INSN_MVFACMI_A;goto extract_sfmt_mvfachi_a;
382 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
383 }
384 }
385 case 96 : /* fall through */
386 case 97 : /* fall through */
387 case 98 : /* fall through */
388 case 99 : /* fall through */
389 case 100 : /* fall through */
390 case 101 : /* fall through */
391 case 102 : /* fall through */
392 case 103 : /* fall through */
393 case 104 : /* fall through */
394 case 105 : /* fall through */
395 case 106 : /* fall through */
396 case 107 : /* fall through */
397 case 108 : /* fall through */
398 case 109 : /* fall through */
399 case 110 : /* fall through */
400 case 111 : itype = M32RXF_INSN_LDI8;goto extract_sfmt_ldi8;
401 case 112 :
402 {
403 unsigned int val = (((insn >> 8) & (15 << 0)));
404 switch (val)
405 {
406 case 0 : itype = M32RXF_INSN_NOP;goto extract_sfmt_nop;
407 case 4 : itype = M32RXF_INSN_SC;goto extract_sfmt_sc;
408 case 5 : itype = M32RXF_INSN_SNC;goto extract_sfmt_sc;
409 case 8 : itype = M32RXF_INSN_BCL8;goto extract_sfmt_bcl8;
410 case 9 : itype = M32RXF_INSN_BNCL8;goto extract_sfmt_bcl8;
411 case 12 : itype = M32RXF_INSN_BC8;goto extract_sfmt_bc8;
412 case 13 : itype = M32RXF_INSN_BNC8;goto extract_sfmt_bc8;
413 case 14 : itype = M32RXF_INSN_BL8;goto extract_sfmt_bl8;
414 case 15 : itype = M32RXF_INSN_BRA8;goto extract_sfmt_bra8;
415 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
416 }
417 }
418 case 113 : /* fall through */
419 case 114 : /* fall through */
420 case 115 : /* fall through */
421 case 116 : /* fall through */
422 case 117 : /* fall through */
423 case 118 : /* fall through */
424 case 119 : /* fall through */
425 case 120 : /* fall through */
426 case 121 : /* fall through */
427 case 122 : /* fall through */
428 case 123 : /* fall through */
429 case 124 : /* fall through */
430 case 125 : /* fall through */
431 case 126 : /* fall through */
432 case 127 :
433 {
434 unsigned int val = (((insn >> 8) & (7 << 0)));
435 switch (val)
436 {
437 case 0 : itype = M32RXF_INSN_BCL8;goto extract_sfmt_bcl8;
438 case 1 : itype = M32RXF_INSN_BNCL8;goto extract_sfmt_bcl8;
439 case 4 : itype = M32RXF_INSN_BC8;goto extract_sfmt_bc8;
440 case 5 : itype = M32RXF_INSN_BNC8;goto extract_sfmt_bc8;
441 case 6 : itype = M32RXF_INSN_BL8;goto extract_sfmt_bl8;
442 case 7 : itype = M32RXF_INSN_BRA8;goto extract_sfmt_bra8;
443 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
444 }
445 }
446 case 132 : itype = M32RXF_INSN_CMPI;goto extract_sfmt_cmpi;
447 case 133 : itype = M32RXF_INSN_CMPUI;goto extract_sfmt_cmpi;
448 case 134 :
449 {
450 unsigned int val = (((insn >> -8) & (3 << 0)));
451 switch (val)
452 {
453 case 0 : itype = M32RXF_INSN_SAT;goto extract_sfmt_sat;
454 case 2 : itype = M32RXF_INSN_SATH;goto extract_sfmt_satb;
455 case 3 : itype = M32RXF_INSN_SATB;goto extract_sfmt_satb;
456 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
457 }
458 }
459 case 136 : itype = M32RXF_INSN_ADDV3;goto extract_sfmt_addv3;
460 case 138 : itype = M32RXF_INSN_ADD3;goto extract_sfmt_add3;
461 case 140 : itype = M32RXF_INSN_AND3;goto extract_sfmt_and3;
462 case 141 : itype = M32RXF_INSN_XOR3;goto extract_sfmt_and3;
463 case 142 : itype = M32RXF_INSN_OR3;goto extract_sfmt_or3;
464 case 144 :
465 {
466 unsigned int val = (((insn >> -12) & (1 << 0)));
467 switch (val)
468 {
469 case 0 : itype = M32RXF_INSN_DIV;goto extract_sfmt_div;
470 case 1 : itype = M32RXF_INSN_DIVH;goto extract_sfmt_div;
471 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
472 }
473 }
474 case 145 : itype = M32RXF_INSN_DIVU;goto extract_sfmt_div;
475 case 146 : itype = M32RXF_INSN_REM;goto extract_sfmt_div;
476 case 147 : itype = M32RXF_INSN_REMU;goto extract_sfmt_div;
477 case 152 : itype = M32RXF_INSN_SRL3;goto extract_sfmt_sll3;
478 case 154 : itype = M32RXF_INSN_SRA3;goto extract_sfmt_sll3;
479 case 156 : itype = M32RXF_INSN_SLL3;goto extract_sfmt_sll3;
480 case 159 : itype = M32RXF_INSN_LDI16;goto extract_sfmt_ldi16;
481 case 160 : itype = M32RXF_INSN_STB_D;goto extract_sfmt_stb_d;
482 case 162 : itype = M32RXF_INSN_STH_D;goto extract_sfmt_sth_d;
483 case 164 : itype = M32RXF_INSN_ST_D;goto extract_sfmt_st_d;
484 case 168 : itype = M32RXF_INSN_LDB_D;goto extract_sfmt_ldb_d;
485 case 169 : itype = M32RXF_INSN_LDUB_D;goto extract_sfmt_ldb_d;
486 case 170 : itype = M32RXF_INSN_LDH_D;goto extract_sfmt_ldh_d;
487 case 171 : itype = M32RXF_INSN_LDUH_D;goto extract_sfmt_ldh_d;
488 case 172 : itype = M32RXF_INSN_LD_D;goto extract_sfmt_ld_d;
489 case 176 : itype = M32RXF_INSN_BEQ;goto extract_sfmt_beq;
490 case 177 : itype = M32RXF_INSN_BNE;goto extract_sfmt_beq;
491 case 184 : itype = M32RXF_INSN_BEQZ;goto extract_sfmt_beqz;
492 case 185 : itype = M32RXF_INSN_BNEZ;goto extract_sfmt_beqz;
493 case 186 : itype = M32RXF_INSN_BLTZ;goto extract_sfmt_beqz;
494 case 187 : itype = M32RXF_INSN_BGEZ;goto extract_sfmt_beqz;
495 case 188 : itype = M32RXF_INSN_BLEZ;goto extract_sfmt_beqz;
496 case 189 : itype = M32RXF_INSN_BGTZ;goto extract_sfmt_beqz;
497 case 220 : itype = M32RXF_INSN_SETH;goto extract_sfmt_seth;
498 case 224 : /* fall through */
499 case 225 : /* fall through */
500 case 226 : /* fall through */
501 case 227 : /* fall through */
502 case 228 : /* fall through */
503 case 229 : /* fall through */
504 case 230 : /* fall through */
505 case 231 : /* fall through */
506 case 232 : /* fall through */
507 case 233 : /* fall through */
508 case 234 : /* fall through */
509 case 235 : /* fall through */
510 case 236 : /* fall through */
511 case 237 : /* fall through */
512 case 238 : /* fall through */
513 case 239 : itype = M32RXF_INSN_LD24;goto extract_sfmt_ld24;
514 case 240 : /* fall through */
515 case 241 : /* fall through */
516 case 242 : /* fall through */
517 case 243 : /* fall through */
518 case 244 : /* fall through */
519 case 245 : /* fall through */
520 case 246 : /* fall through */
521 case 247 : /* fall through */
522 case 248 : /* fall through */
523 case 249 : /* fall through */
524 case 250 : /* fall through */
525 case 251 : /* fall through */
526 case 252 : /* fall through */
527 case 253 : /* fall through */
528 case 254 : /* fall through */
529 case 255 :
530 {
531 unsigned int val = (((insn >> 8) & (7 << 0)));
532 switch (val)
533 {
534 case 0 : itype = M32RXF_INSN_BCL24;goto extract_sfmt_bcl24;
535 case 1 : itype = M32RXF_INSN_BNCL24;goto extract_sfmt_bcl24;
536 case 4 : itype = M32RXF_INSN_BC24;goto extract_sfmt_bc24;
537 case 5 : itype = M32RXF_INSN_BNC24;goto extract_sfmt_bc24;
538 case 6 : itype = M32RXF_INSN_BL24;goto extract_sfmt_bl24;
539 case 7 : itype = M32RXF_INSN_BRA24;goto extract_sfmt_bra24;
540 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
541 }
542 }
543 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
544 }
545 }
546 }
547
548 /* The instruction has been decoded, now extract the fields. */
549
550 extract_sfmt_empty:
551 {
552 const IDESC *idesc = &m32rxf_insn_data[itype];
553 #define FLD(f) abuf->fields.fmt_empty.f
554
555
556 /* Record the fields for the semantic handler. */
557 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
558
559 #undef FLD
560 return idesc;
561 }
562
563 extract_sfmt_add:
564 {
565 const IDESC *idesc = &m32rxf_insn_data[itype];
566 CGEN_INSN_INT insn = entire_insn;
567 #define FLD(f) abuf->fields.sfmt_add.f
568 UINT f_r1;
569 UINT f_r2;
570
571 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
572 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
573
574 /* Record the fields for the semantic handler. */
575 FLD (f_r1) = f_r1;
576 FLD (f_r2) = f_r2;
577 FLD (i_dr) = & CPU (h_gr)[f_r1];
578 FLD (i_sr) = & CPU (h_gr)[f_r2];
579 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
580
581 #if WITH_PROFILE_MODEL_P
582 /* Record the fields for profiling. */
583 if (PROFILE_MODEL_P (current_cpu))
584 {
585 FLD (in_dr) = f_r1;
586 FLD (in_sr) = f_r2;
587 FLD (out_dr) = f_r1;
588 }
589 #endif
590 #undef FLD
591 return idesc;
592 }
593
594 extract_sfmt_add3:
595 {
596 const IDESC *idesc = &m32rxf_insn_data[itype];
597 CGEN_INSN_INT insn = entire_insn;
598 #define FLD(f) abuf->fields.sfmt_add3.f
599 UINT f_r1;
600 UINT f_r2;
601 INT f_simm16;
602
603 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
604 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
605 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
606
607 /* Record the fields for the semantic handler. */
608 FLD (f_simm16) = f_simm16;
609 FLD (f_r2) = f_r2;
610 FLD (f_r1) = f_r1;
611 FLD (i_sr) = & CPU (h_gr)[f_r2];
612 FLD (i_dr) = & CPU (h_gr)[f_r1];
613 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
614
615 #if WITH_PROFILE_MODEL_P
616 /* Record the fields for profiling. */
617 if (PROFILE_MODEL_P (current_cpu))
618 {
619 FLD (in_sr) = f_r2;
620 FLD (out_dr) = f_r1;
621 }
622 #endif
623 #undef FLD
624 return idesc;
625 }
626
627 extract_sfmt_and3:
628 {
629 const IDESC *idesc = &m32rxf_insn_data[itype];
630 CGEN_INSN_INT insn = entire_insn;
631 #define FLD(f) abuf->fields.sfmt_and3.f
632 UINT f_r1;
633 UINT f_r2;
634 UINT f_uimm16;
635
636 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
637 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
638 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
639
640 /* Record the fields for the semantic handler. */
641 FLD (f_r2) = f_r2;
642 FLD (f_uimm16) = f_uimm16;
643 FLD (f_r1) = f_r1;
644 FLD (i_sr) = & CPU (h_gr)[f_r2];
645 FLD (i_dr) = & CPU (h_gr)[f_r1];
646 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
647
648 #if WITH_PROFILE_MODEL_P
649 /* Record the fields for profiling. */
650 if (PROFILE_MODEL_P (current_cpu))
651 {
652 FLD (in_sr) = f_r2;
653 FLD (out_dr) = f_r1;
654 }
655 #endif
656 #undef FLD
657 return idesc;
658 }
659
660 extract_sfmt_or3:
661 {
662 const IDESC *idesc = &m32rxf_insn_data[itype];
663 CGEN_INSN_INT insn = entire_insn;
664 #define FLD(f) abuf->fields.sfmt_and3.f
665 UINT f_r1;
666 UINT f_r2;
667 UINT f_uimm16;
668
669 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
670 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
671 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
672
673 /* Record the fields for the semantic handler. */
674 FLD (f_r2) = f_r2;
675 FLD (f_uimm16) = f_uimm16;
676 FLD (f_r1) = f_r1;
677 FLD (i_sr) = & CPU (h_gr)[f_r2];
678 FLD (i_dr) = & CPU (h_gr)[f_r1];
679 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
680
681 #if WITH_PROFILE_MODEL_P
682 /* Record the fields for profiling. */
683 if (PROFILE_MODEL_P (current_cpu))
684 {
685 FLD (in_sr) = f_r2;
686 FLD (out_dr) = f_r1;
687 }
688 #endif
689 #undef FLD
690 return idesc;
691 }
692
693 extract_sfmt_addi:
694 {
695 const IDESC *idesc = &m32rxf_insn_data[itype];
696 CGEN_INSN_INT insn = entire_insn;
697 #define FLD(f) abuf->fields.sfmt_addi.f
698 UINT f_r1;
699 INT f_simm8;
700
701 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
702 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
703
704 /* Record the fields for the semantic handler. */
705 FLD (f_r1) = f_r1;
706 FLD (f_simm8) = f_simm8;
707 FLD (i_dr) = & CPU (h_gr)[f_r1];
708 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
709
710 #if WITH_PROFILE_MODEL_P
711 /* Record the fields for profiling. */
712 if (PROFILE_MODEL_P (current_cpu))
713 {
714 FLD (in_dr) = f_r1;
715 FLD (out_dr) = f_r1;
716 }
717 #endif
718 #undef FLD
719 return idesc;
720 }
721
722 extract_sfmt_addv:
723 {
724 const IDESC *idesc = &m32rxf_insn_data[itype];
725 CGEN_INSN_INT insn = entire_insn;
726 #define FLD(f) abuf->fields.sfmt_add.f
727 UINT f_r1;
728 UINT f_r2;
729
730 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
731 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
732
733 /* Record the fields for the semantic handler. */
734 FLD (f_r1) = f_r1;
735 FLD (f_r2) = f_r2;
736 FLD (i_dr) = & CPU (h_gr)[f_r1];
737 FLD (i_sr) = & CPU (h_gr)[f_r2];
738 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
739
740 #if WITH_PROFILE_MODEL_P
741 /* Record the fields for profiling. */
742 if (PROFILE_MODEL_P (current_cpu))
743 {
744 FLD (in_dr) = f_r1;
745 FLD (in_sr) = f_r2;
746 FLD (out_dr) = f_r1;
747 }
748 #endif
749 #undef FLD
750 return idesc;
751 }
752
753 extract_sfmt_addv3:
754 {
755 const IDESC *idesc = &m32rxf_insn_data[itype];
756 CGEN_INSN_INT insn = entire_insn;
757 #define FLD(f) abuf->fields.sfmt_add3.f
758 UINT f_r1;
759 UINT f_r2;
760 INT f_simm16;
761
762 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
763 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
764 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
765
766 /* Record the fields for the semantic handler. */
767 FLD (f_simm16) = f_simm16;
768 FLD (f_r2) = f_r2;
769 FLD (f_r1) = f_r1;
770 FLD (i_sr) = & CPU (h_gr)[f_r2];
771 FLD (i_dr) = & CPU (h_gr)[f_r1];
772 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
773
774 #if WITH_PROFILE_MODEL_P
775 /* Record the fields for profiling. */
776 if (PROFILE_MODEL_P (current_cpu))
777 {
778 FLD (in_sr) = f_r2;
779 FLD (out_dr) = f_r1;
780 }
781 #endif
782 #undef FLD
783 return idesc;
784 }
785
786 extract_sfmt_addx:
787 {
788 const IDESC *idesc = &m32rxf_insn_data[itype];
789 CGEN_INSN_INT insn = entire_insn;
790 #define FLD(f) abuf->fields.sfmt_add.f
791 UINT f_r1;
792 UINT f_r2;
793
794 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
795 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
796
797 /* Record the fields for the semantic handler. */
798 FLD (f_r1) = f_r1;
799 FLD (f_r2) = f_r2;
800 FLD (i_dr) = & CPU (h_gr)[f_r1];
801 FLD (i_sr) = & CPU (h_gr)[f_r2];
802 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
803
804 #if WITH_PROFILE_MODEL_P
805 /* Record the fields for profiling. */
806 if (PROFILE_MODEL_P (current_cpu))
807 {
808 FLD (in_dr) = f_r1;
809 FLD (in_sr) = f_r2;
810 FLD (out_dr) = f_r1;
811 }
812 #endif
813 #undef FLD
814 return idesc;
815 }
816
817 extract_sfmt_bc8:
818 {
819 const IDESC *idesc = &m32rxf_insn_data[itype];
820 CGEN_INSN_INT insn = entire_insn;
821 #define FLD(f) abuf->fields.sfmt_bl8.f
822 SI f_disp8;
823
824 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
825
826 /* Record the fields for the semantic handler. */
827 FLD (i_disp8) = f_disp8;
828 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
829
830 #if WITH_PROFILE_MODEL_P
831 /* Record the fields for profiling. */
832 if (PROFILE_MODEL_P (current_cpu))
833 {
834 }
835 #endif
836 #undef FLD
837 return idesc;
838 }
839
840 extract_sfmt_bc24:
841 {
842 const IDESC *idesc = &m32rxf_insn_data[itype];
843 CGEN_INSN_INT insn = entire_insn;
844 #define FLD(f) abuf->fields.sfmt_bl24.f
845 SI f_disp24;
846
847 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
848
849 /* Record the fields for the semantic handler. */
850 FLD (i_disp24) = f_disp24;
851 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
852
853 #if WITH_PROFILE_MODEL_P
854 /* Record the fields for profiling. */
855 if (PROFILE_MODEL_P (current_cpu))
856 {
857 }
858 #endif
859 #undef FLD
860 return idesc;
861 }
862
863 extract_sfmt_beq:
864 {
865 const IDESC *idesc = &m32rxf_insn_data[itype];
866 CGEN_INSN_INT insn = entire_insn;
867 #define FLD(f) abuf->fields.sfmt_beq.f
868 UINT f_r1;
869 UINT f_r2;
870 SI f_disp16;
871
872 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
873 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
874 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
875
876 /* Record the fields for the semantic handler. */
877 FLD (f_r1) = f_r1;
878 FLD (f_r2) = f_r2;
879 FLD (i_disp16) = f_disp16;
880 FLD (i_src1) = & CPU (h_gr)[f_r1];
881 FLD (i_src2) = & CPU (h_gr)[f_r2];
882 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
883
884 #if WITH_PROFILE_MODEL_P
885 /* Record the fields for profiling. */
886 if (PROFILE_MODEL_P (current_cpu))
887 {
888 FLD (in_src1) = f_r1;
889 FLD (in_src2) = f_r2;
890 }
891 #endif
892 #undef FLD
893 return idesc;
894 }
895
896 extract_sfmt_beqz:
897 {
898 const IDESC *idesc = &m32rxf_insn_data[itype];
899 CGEN_INSN_INT insn = entire_insn;
900 #define FLD(f) abuf->fields.sfmt_beq.f
901 UINT f_r2;
902 SI f_disp16;
903
904 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
905 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
906
907 /* Record the fields for the semantic handler. */
908 FLD (f_r2) = f_r2;
909 FLD (i_disp16) = f_disp16;
910 FLD (i_src2) = & CPU (h_gr)[f_r2];
911 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
912
913 #if WITH_PROFILE_MODEL_P
914 /* Record the fields for profiling. */
915 if (PROFILE_MODEL_P (current_cpu))
916 {
917 FLD (in_src2) = f_r2;
918 }
919 #endif
920 #undef FLD
921 return idesc;
922 }
923
924 extract_sfmt_bl8:
925 {
926 const IDESC *idesc = &m32rxf_insn_data[itype];
927 CGEN_INSN_INT insn = entire_insn;
928 #define FLD(f) abuf->fields.sfmt_bl8.f
929 SI f_disp8;
930
931 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
932
933 /* Record the fields for the semantic handler. */
934 FLD (i_disp8) = f_disp8;
935 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
936
937 #if WITH_PROFILE_MODEL_P
938 /* Record the fields for profiling. */
939 if (PROFILE_MODEL_P (current_cpu))
940 {
941 FLD (out_h_gr_SI_14) = 14;
942 }
943 #endif
944 #undef FLD
945 return idesc;
946 }
947
948 extract_sfmt_bl24:
949 {
950 const IDESC *idesc = &m32rxf_insn_data[itype];
951 CGEN_INSN_INT insn = entire_insn;
952 #define FLD(f) abuf->fields.sfmt_bl24.f
953 SI f_disp24;
954
955 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
956
957 /* Record the fields for the semantic handler. */
958 FLD (i_disp24) = f_disp24;
959 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
960
961 #if WITH_PROFILE_MODEL_P
962 /* Record the fields for profiling. */
963 if (PROFILE_MODEL_P (current_cpu))
964 {
965 FLD (out_h_gr_SI_14) = 14;
966 }
967 #endif
968 #undef FLD
969 return idesc;
970 }
971
972 extract_sfmt_bcl8:
973 {
974 const IDESC *idesc = &m32rxf_insn_data[itype];
975 CGEN_INSN_INT insn = entire_insn;
976 #define FLD(f) abuf->fields.sfmt_bl8.f
977 SI f_disp8;
978
979 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
980
981 /* Record the fields for the semantic handler. */
982 FLD (i_disp8) = f_disp8;
983 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
984
985 #if WITH_PROFILE_MODEL_P
986 /* Record the fields for profiling. */
987 if (PROFILE_MODEL_P (current_cpu))
988 {
989 FLD (out_h_gr_SI_14) = 14;
990 }
991 #endif
992 #undef FLD
993 return idesc;
994 }
995
996 extract_sfmt_bcl24:
997 {
998 const IDESC *idesc = &m32rxf_insn_data[itype];
999 CGEN_INSN_INT insn = entire_insn;
1000 #define FLD(f) abuf->fields.sfmt_bl24.f
1001 SI f_disp24;
1002
1003 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1004
1005 /* Record the fields for the semantic handler. */
1006 FLD (i_disp24) = f_disp24;
1007 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1008
1009 #if WITH_PROFILE_MODEL_P
1010 /* Record the fields for profiling. */
1011 if (PROFILE_MODEL_P (current_cpu))
1012 {
1013 FLD (out_h_gr_SI_14) = 14;
1014 }
1015 #endif
1016 #undef FLD
1017 return idesc;
1018 }
1019
1020 extract_sfmt_bra8:
1021 {
1022 const IDESC *idesc = &m32rxf_insn_data[itype];
1023 CGEN_INSN_INT insn = entire_insn;
1024 #define FLD(f) abuf->fields.sfmt_bl8.f
1025 SI f_disp8;
1026
1027 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1028
1029 /* Record the fields for the semantic handler. */
1030 FLD (i_disp8) = f_disp8;
1031 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1032
1033 #if WITH_PROFILE_MODEL_P
1034 /* Record the fields for profiling. */
1035 if (PROFILE_MODEL_P (current_cpu))
1036 {
1037 }
1038 #endif
1039 #undef FLD
1040 return idesc;
1041 }
1042
1043 extract_sfmt_bra24:
1044 {
1045 const IDESC *idesc = &m32rxf_insn_data[itype];
1046 CGEN_INSN_INT insn = entire_insn;
1047 #define FLD(f) abuf->fields.sfmt_bl24.f
1048 SI f_disp24;
1049
1050 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1051
1052 /* Record the fields for the semantic handler. */
1053 FLD (i_disp24) = f_disp24;
1054 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1055
1056 #if WITH_PROFILE_MODEL_P
1057 /* Record the fields for profiling. */
1058 if (PROFILE_MODEL_P (current_cpu))
1059 {
1060 }
1061 #endif
1062 #undef FLD
1063 return idesc;
1064 }
1065
1066 extract_sfmt_cmp:
1067 {
1068 const IDESC *idesc = &m32rxf_insn_data[itype];
1069 CGEN_INSN_INT insn = entire_insn;
1070 #define FLD(f) abuf->fields.sfmt_st_plus.f
1071 UINT f_r1;
1072 UINT f_r2;
1073
1074 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1075 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1076
1077 /* Record the fields for the semantic handler. */
1078 FLD (f_r1) = f_r1;
1079 FLD (f_r2) = f_r2;
1080 FLD (i_src1) = & CPU (h_gr)[f_r1];
1081 FLD (i_src2) = & CPU (h_gr)[f_r2];
1082 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1083
1084 #if WITH_PROFILE_MODEL_P
1085 /* Record the fields for profiling. */
1086 if (PROFILE_MODEL_P (current_cpu))
1087 {
1088 FLD (in_src1) = f_r1;
1089 FLD (in_src2) = f_r2;
1090 }
1091 #endif
1092 #undef FLD
1093 return idesc;
1094 }
1095
1096 extract_sfmt_cmpi:
1097 {
1098 const IDESC *idesc = &m32rxf_insn_data[itype];
1099 CGEN_INSN_INT insn = entire_insn;
1100 #define FLD(f) abuf->fields.sfmt_st_d.f
1101 UINT f_r2;
1102 INT f_simm16;
1103
1104 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1105 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1106
1107 /* Record the fields for the semantic handler. */
1108 FLD (f_simm16) = f_simm16;
1109 FLD (f_r2) = f_r2;
1110 FLD (i_src2) = & CPU (h_gr)[f_r2];
1111 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1112
1113 #if WITH_PROFILE_MODEL_P
1114 /* Record the fields for profiling. */
1115 if (PROFILE_MODEL_P (current_cpu))
1116 {
1117 FLD (in_src2) = f_r2;
1118 }
1119 #endif
1120 #undef FLD
1121 return idesc;
1122 }
1123
1124 extract_sfmt_cmpz:
1125 {
1126 const IDESC *idesc = &m32rxf_insn_data[itype];
1127 CGEN_INSN_INT insn = entire_insn;
1128 #define FLD(f) abuf->fields.sfmt_st_plus.f
1129 UINT f_r2;
1130
1131 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1132
1133 /* Record the fields for the semantic handler. */
1134 FLD (f_r2) = f_r2;
1135 FLD (i_src2) = & CPU (h_gr)[f_r2];
1136 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1137
1138 #if WITH_PROFILE_MODEL_P
1139 /* Record the fields for profiling. */
1140 if (PROFILE_MODEL_P (current_cpu))
1141 {
1142 FLD (in_src2) = f_r2;
1143 }
1144 #endif
1145 #undef FLD
1146 return idesc;
1147 }
1148
1149 extract_sfmt_div:
1150 {
1151 const IDESC *idesc = &m32rxf_insn_data[itype];
1152 CGEN_INSN_INT insn = entire_insn;
1153 #define FLD(f) abuf->fields.sfmt_add.f
1154 UINT f_r1;
1155 UINT f_r2;
1156
1157 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1158 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1159
1160 /* Record the fields for the semantic handler. */
1161 FLD (f_r1) = f_r1;
1162 FLD (f_r2) = f_r2;
1163 FLD (i_dr) = & CPU (h_gr)[f_r1];
1164 FLD (i_sr) = & CPU (h_gr)[f_r2];
1165 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1166
1167 #if WITH_PROFILE_MODEL_P
1168 /* Record the fields for profiling. */
1169 if (PROFILE_MODEL_P (current_cpu))
1170 {
1171 FLD (in_dr) = f_r1;
1172 FLD (in_sr) = f_r2;
1173 FLD (out_dr) = f_r1;
1174 }
1175 #endif
1176 #undef FLD
1177 return idesc;
1178 }
1179
1180 extract_sfmt_jc:
1181 {
1182 const IDESC *idesc = &m32rxf_insn_data[itype];
1183 CGEN_INSN_INT insn = entire_insn;
1184 #define FLD(f) abuf->fields.sfmt_jl.f
1185 UINT f_r2;
1186
1187 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1188
1189 /* Record the fields for the semantic handler. */
1190 FLD (f_r2) = f_r2;
1191 FLD (i_sr) = & CPU (h_gr)[f_r2];
1192 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1193
1194 #if WITH_PROFILE_MODEL_P
1195 /* Record the fields for profiling. */
1196 if (PROFILE_MODEL_P (current_cpu))
1197 {
1198 FLD (in_sr) = f_r2;
1199 }
1200 #endif
1201 #undef FLD
1202 return idesc;
1203 }
1204
1205 extract_sfmt_jl:
1206 {
1207 const IDESC *idesc = &m32rxf_insn_data[itype];
1208 CGEN_INSN_INT insn = entire_insn;
1209 #define FLD(f) abuf->fields.sfmt_jl.f
1210 UINT f_r2;
1211
1212 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1213
1214 /* Record the fields for the semantic handler. */
1215 FLD (f_r2) = f_r2;
1216 FLD (i_sr) = & CPU (h_gr)[f_r2];
1217 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1218
1219 #if WITH_PROFILE_MODEL_P
1220 /* Record the fields for profiling. */
1221 if (PROFILE_MODEL_P (current_cpu))
1222 {
1223 FLD (in_sr) = f_r2;
1224 FLD (out_h_gr_SI_14) = 14;
1225 }
1226 #endif
1227 #undef FLD
1228 return idesc;
1229 }
1230
1231 extract_sfmt_jmp:
1232 {
1233 const IDESC *idesc = &m32rxf_insn_data[itype];
1234 CGEN_INSN_INT insn = entire_insn;
1235 #define FLD(f) abuf->fields.sfmt_jl.f
1236 UINT f_r2;
1237
1238 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1239
1240 /* Record the fields for the semantic handler. */
1241 FLD (f_r2) = f_r2;
1242 FLD (i_sr) = & CPU (h_gr)[f_r2];
1243 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1244
1245 #if WITH_PROFILE_MODEL_P
1246 /* Record the fields for profiling. */
1247 if (PROFILE_MODEL_P (current_cpu))
1248 {
1249 FLD (in_sr) = f_r2;
1250 }
1251 #endif
1252 #undef FLD
1253 return idesc;
1254 }
1255
1256 extract_sfmt_ld:
1257 {
1258 const IDESC *idesc = &m32rxf_insn_data[itype];
1259 CGEN_INSN_INT insn = entire_insn;
1260 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1261 UINT f_r1;
1262 UINT f_r2;
1263
1264 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1265 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1266
1267 /* Record the fields for the semantic handler. */
1268 FLD (f_r2) = f_r2;
1269 FLD (f_r1) = f_r1;
1270 FLD (i_sr) = & CPU (h_gr)[f_r2];
1271 FLD (i_dr) = & CPU (h_gr)[f_r1];
1272 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1273
1274 #if WITH_PROFILE_MODEL_P
1275 /* Record the fields for profiling. */
1276 if (PROFILE_MODEL_P (current_cpu))
1277 {
1278 FLD (in_sr) = f_r2;
1279 FLD (out_dr) = f_r1;
1280 }
1281 #endif
1282 #undef FLD
1283 return idesc;
1284 }
1285
1286 extract_sfmt_ld_d:
1287 {
1288 const IDESC *idesc = &m32rxf_insn_data[itype];
1289 CGEN_INSN_INT insn = entire_insn;
1290 #define FLD(f) abuf->fields.sfmt_add3.f
1291 UINT f_r1;
1292 UINT f_r2;
1293 INT f_simm16;
1294
1295 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1296 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1297 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1298
1299 /* Record the fields for the semantic handler. */
1300 FLD (f_simm16) = f_simm16;
1301 FLD (f_r2) = f_r2;
1302 FLD (f_r1) = f_r1;
1303 FLD (i_sr) = & CPU (h_gr)[f_r2];
1304 FLD (i_dr) = & CPU (h_gr)[f_r1];
1305 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1306
1307 #if WITH_PROFILE_MODEL_P
1308 /* Record the fields for profiling. */
1309 if (PROFILE_MODEL_P (current_cpu))
1310 {
1311 FLD (in_sr) = f_r2;
1312 FLD (out_dr) = f_r1;
1313 }
1314 #endif
1315 #undef FLD
1316 return idesc;
1317 }
1318
1319 extract_sfmt_ldb:
1320 {
1321 const IDESC *idesc = &m32rxf_insn_data[itype];
1322 CGEN_INSN_INT insn = entire_insn;
1323 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1324 UINT f_r1;
1325 UINT f_r2;
1326
1327 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1328 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1329
1330 /* Record the fields for the semantic handler. */
1331 FLD (f_r2) = f_r2;
1332 FLD (f_r1) = f_r1;
1333 FLD (i_sr) = & CPU (h_gr)[f_r2];
1334 FLD (i_dr) = & CPU (h_gr)[f_r1];
1335 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1336
1337 #if WITH_PROFILE_MODEL_P
1338 /* Record the fields for profiling. */
1339 if (PROFILE_MODEL_P (current_cpu))
1340 {
1341 FLD (in_sr) = f_r2;
1342 FLD (out_dr) = f_r1;
1343 }
1344 #endif
1345 #undef FLD
1346 return idesc;
1347 }
1348
1349 extract_sfmt_ldb_d:
1350 {
1351 const IDESC *idesc = &m32rxf_insn_data[itype];
1352 CGEN_INSN_INT insn = entire_insn;
1353 #define FLD(f) abuf->fields.sfmt_add3.f
1354 UINT f_r1;
1355 UINT f_r2;
1356 INT f_simm16;
1357
1358 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1359 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1360 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1361
1362 /* Record the fields for the semantic handler. */
1363 FLD (f_simm16) = f_simm16;
1364 FLD (f_r2) = f_r2;
1365 FLD (f_r1) = f_r1;
1366 FLD (i_sr) = & CPU (h_gr)[f_r2];
1367 FLD (i_dr) = & CPU (h_gr)[f_r1];
1368 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1369
1370 #if WITH_PROFILE_MODEL_P
1371 /* Record the fields for profiling. */
1372 if (PROFILE_MODEL_P (current_cpu))
1373 {
1374 FLD (in_sr) = f_r2;
1375 FLD (out_dr) = f_r1;
1376 }
1377 #endif
1378 #undef FLD
1379 return idesc;
1380 }
1381
1382 extract_sfmt_ldh:
1383 {
1384 const IDESC *idesc = &m32rxf_insn_data[itype];
1385 CGEN_INSN_INT insn = entire_insn;
1386 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1387 UINT f_r1;
1388 UINT f_r2;
1389
1390 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1391 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1392
1393 /* Record the fields for the semantic handler. */
1394 FLD (f_r2) = f_r2;
1395 FLD (f_r1) = f_r1;
1396 FLD (i_sr) = & CPU (h_gr)[f_r2];
1397 FLD (i_dr) = & CPU (h_gr)[f_r1];
1398 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1399
1400 #if WITH_PROFILE_MODEL_P
1401 /* Record the fields for profiling. */
1402 if (PROFILE_MODEL_P (current_cpu))
1403 {
1404 FLD (in_sr) = f_r2;
1405 FLD (out_dr) = f_r1;
1406 }
1407 #endif
1408 #undef FLD
1409 return idesc;
1410 }
1411
1412 extract_sfmt_ldh_d:
1413 {
1414 const IDESC *idesc = &m32rxf_insn_data[itype];
1415 CGEN_INSN_INT insn = entire_insn;
1416 #define FLD(f) abuf->fields.sfmt_add3.f
1417 UINT f_r1;
1418 UINT f_r2;
1419 INT f_simm16;
1420
1421 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1422 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1423 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1424
1425 /* Record the fields for the semantic handler. */
1426 FLD (f_simm16) = f_simm16;
1427 FLD (f_r2) = f_r2;
1428 FLD (f_r1) = f_r1;
1429 FLD (i_sr) = & CPU (h_gr)[f_r2];
1430 FLD (i_dr) = & CPU (h_gr)[f_r1];
1431 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1432
1433 #if WITH_PROFILE_MODEL_P
1434 /* Record the fields for profiling. */
1435 if (PROFILE_MODEL_P (current_cpu))
1436 {
1437 FLD (in_sr) = f_r2;
1438 FLD (out_dr) = f_r1;
1439 }
1440 #endif
1441 #undef FLD
1442 return idesc;
1443 }
1444
1445 extract_sfmt_ld_plus:
1446 {
1447 const IDESC *idesc = &m32rxf_insn_data[itype];
1448 CGEN_INSN_INT insn = entire_insn;
1449 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1450 UINT f_r1;
1451 UINT f_r2;
1452
1453 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1454 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1455
1456 /* Record the fields for the semantic handler. */
1457 FLD (f_r2) = f_r2;
1458 FLD (f_r1) = f_r1;
1459 FLD (i_sr) = & CPU (h_gr)[f_r2];
1460 FLD (i_dr) = & CPU (h_gr)[f_r1];
1461 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1462
1463 #if WITH_PROFILE_MODEL_P
1464 /* Record the fields for profiling. */
1465 if (PROFILE_MODEL_P (current_cpu))
1466 {
1467 FLD (in_sr) = f_r2;
1468 FLD (out_dr) = f_r1;
1469 FLD (out_sr) = f_r2;
1470 }
1471 #endif
1472 #undef FLD
1473 return idesc;
1474 }
1475
1476 extract_sfmt_ld24:
1477 {
1478 const IDESC *idesc = &m32rxf_insn_data[itype];
1479 CGEN_INSN_INT insn = entire_insn;
1480 #define FLD(f) abuf->fields.sfmt_ld24.f
1481 UINT f_r1;
1482 UINT f_uimm24;
1483
1484 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1485 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1486
1487 /* Record the fields for the semantic handler. */
1488 FLD (f_r1) = f_r1;
1489 FLD (i_uimm24) = f_uimm24;
1490 FLD (i_dr) = & CPU (h_gr)[f_r1];
1491 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1492
1493 #if WITH_PROFILE_MODEL_P
1494 /* Record the fields for profiling. */
1495 if (PROFILE_MODEL_P (current_cpu))
1496 {
1497 FLD (out_dr) = f_r1;
1498 }
1499 #endif
1500 #undef FLD
1501 return idesc;
1502 }
1503
1504 extract_sfmt_ldi8:
1505 {
1506 const IDESC *idesc = &m32rxf_insn_data[itype];
1507 CGEN_INSN_INT insn = entire_insn;
1508 #define FLD(f) abuf->fields.sfmt_addi.f
1509 UINT f_r1;
1510 INT f_simm8;
1511
1512 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1513 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1514
1515 /* Record the fields for the semantic handler. */
1516 FLD (f_simm8) = f_simm8;
1517 FLD (f_r1) = f_r1;
1518 FLD (i_dr) = & CPU (h_gr)[f_r1];
1519 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1520
1521 #if WITH_PROFILE_MODEL_P
1522 /* Record the fields for profiling. */
1523 if (PROFILE_MODEL_P (current_cpu))
1524 {
1525 FLD (out_dr) = f_r1;
1526 }
1527 #endif
1528 #undef FLD
1529 return idesc;
1530 }
1531
1532 extract_sfmt_ldi16:
1533 {
1534 const IDESC *idesc = &m32rxf_insn_data[itype];
1535 CGEN_INSN_INT insn = entire_insn;
1536 #define FLD(f) abuf->fields.sfmt_add3.f
1537 UINT f_r1;
1538 INT f_simm16;
1539
1540 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1541 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1542
1543 /* Record the fields for the semantic handler. */
1544 FLD (f_simm16) = f_simm16;
1545 FLD (f_r1) = f_r1;
1546 FLD (i_dr) = & CPU (h_gr)[f_r1];
1547 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1548
1549 #if WITH_PROFILE_MODEL_P
1550 /* Record the fields for profiling. */
1551 if (PROFILE_MODEL_P (current_cpu))
1552 {
1553 FLD (out_dr) = f_r1;
1554 }
1555 #endif
1556 #undef FLD
1557 return idesc;
1558 }
1559
1560 extract_sfmt_lock:
1561 {
1562 const IDESC *idesc = &m32rxf_insn_data[itype];
1563 CGEN_INSN_INT insn = entire_insn;
1564 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1565 UINT f_r1;
1566 UINT f_r2;
1567
1568 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1569 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1570
1571 /* Record the fields for the semantic handler. */
1572 FLD (f_r2) = f_r2;
1573 FLD (f_r1) = f_r1;
1574 FLD (i_sr) = & CPU (h_gr)[f_r2];
1575 FLD (i_dr) = & CPU (h_gr)[f_r1];
1576 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1577
1578 #if WITH_PROFILE_MODEL_P
1579 /* Record the fields for profiling. */
1580 if (PROFILE_MODEL_P (current_cpu))
1581 {
1582 FLD (in_sr) = f_r2;
1583 FLD (out_dr) = f_r1;
1584 }
1585 #endif
1586 #undef FLD
1587 return idesc;
1588 }
1589
1590 extract_sfmt_machi_a:
1591 {
1592 const IDESC *idesc = &m32rxf_insn_data[itype];
1593 CGEN_INSN_INT insn = entire_insn;
1594 #define FLD(f) abuf->fields.sfmt_machi_a.f
1595 UINT f_r1;
1596 UINT f_acc;
1597 UINT f_r2;
1598
1599 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1600 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1601 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1602
1603 /* Record the fields for the semantic handler. */
1604 FLD (f_acc) = f_acc;
1605 FLD (f_r1) = f_r1;
1606 FLD (f_r2) = f_r2;
1607 FLD (i_src1) = & CPU (h_gr)[f_r1];
1608 FLD (i_src2) = & CPU (h_gr)[f_r2];
1609 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1610
1611 #if WITH_PROFILE_MODEL_P
1612 /* Record the fields for profiling. */
1613 if (PROFILE_MODEL_P (current_cpu))
1614 {
1615 FLD (in_src1) = f_r1;
1616 FLD (in_src2) = f_r2;
1617 }
1618 #endif
1619 #undef FLD
1620 return idesc;
1621 }
1622
1623 extract_sfmt_mulhi_a:
1624 {
1625 const IDESC *idesc = &m32rxf_insn_data[itype];
1626 CGEN_INSN_INT insn = entire_insn;
1627 #define FLD(f) abuf->fields.sfmt_machi_a.f
1628 UINT f_r1;
1629 UINT f_acc;
1630 UINT f_r2;
1631
1632 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1633 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1634 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1635
1636 /* Record the fields for the semantic handler. */
1637 FLD (f_r1) = f_r1;
1638 FLD (f_r2) = f_r2;
1639 FLD (f_acc) = f_acc;
1640 FLD (i_src1) = & CPU (h_gr)[f_r1];
1641 FLD (i_src2) = & CPU (h_gr)[f_r2];
1642 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1643
1644 #if WITH_PROFILE_MODEL_P
1645 /* Record the fields for profiling. */
1646 if (PROFILE_MODEL_P (current_cpu))
1647 {
1648 FLD (in_src1) = f_r1;
1649 FLD (in_src2) = f_r2;
1650 }
1651 #endif
1652 #undef FLD
1653 return idesc;
1654 }
1655
1656 extract_sfmt_mv:
1657 {
1658 const IDESC *idesc = &m32rxf_insn_data[itype];
1659 CGEN_INSN_INT insn = entire_insn;
1660 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1661 UINT f_r1;
1662 UINT f_r2;
1663
1664 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1665 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1666
1667 /* Record the fields for the semantic handler. */
1668 FLD (f_r2) = f_r2;
1669 FLD (f_r1) = f_r1;
1670 FLD (i_sr) = & CPU (h_gr)[f_r2];
1671 FLD (i_dr) = & CPU (h_gr)[f_r1];
1672 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1673
1674 #if WITH_PROFILE_MODEL_P
1675 /* Record the fields for profiling. */
1676 if (PROFILE_MODEL_P (current_cpu))
1677 {
1678 FLD (in_sr) = f_r2;
1679 FLD (out_dr) = f_r1;
1680 }
1681 #endif
1682 #undef FLD
1683 return idesc;
1684 }
1685
1686 extract_sfmt_mvfachi_a:
1687 {
1688 const IDESC *idesc = &m32rxf_insn_data[itype];
1689 CGEN_INSN_INT insn = entire_insn;
1690 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1691 UINT f_r1;
1692 UINT f_accs;
1693
1694 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1695 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1696
1697 /* Record the fields for the semantic handler. */
1698 FLD (f_accs) = f_accs;
1699 FLD (f_r1) = f_r1;
1700 FLD (i_dr) = & CPU (h_gr)[f_r1];
1701 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1702
1703 #if WITH_PROFILE_MODEL_P
1704 /* Record the fields for profiling. */
1705 if (PROFILE_MODEL_P (current_cpu))
1706 {
1707 FLD (out_dr) = f_r1;
1708 }
1709 #endif
1710 #undef FLD
1711 return idesc;
1712 }
1713
1714 extract_sfmt_mvfc:
1715 {
1716 const IDESC *idesc = &m32rxf_insn_data[itype];
1717 CGEN_INSN_INT insn = entire_insn;
1718 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1719 UINT f_r1;
1720 UINT f_r2;
1721
1722 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1723 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1724
1725 /* Record the fields for the semantic handler. */
1726 FLD (f_r2) = f_r2;
1727 FLD (f_r1) = f_r1;
1728 FLD (i_dr) = & CPU (h_gr)[f_r1];
1729 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1730
1731 #if WITH_PROFILE_MODEL_P
1732 /* Record the fields for profiling. */
1733 if (PROFILE_MODEL_P (current_cpu))
1734 {
1735 FLD (out_dr) = f_r1;
1736 }
1737 #endif
1738 #undef FLD
1739 return idesc;
1740 }
1741
1742 extract_sfmt_mvtachi_a:
1743 {
1744 const IDESC *idesc = &m32rxf_insn_data[itype];
1745 CGEN_INSN_INT insn = entire_insn;
1746 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1747 UINT f_r1;
1748 UINT f_accs;
1749
1750 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1751 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1752
1753 /* Record the fields for the semantic handler. */
1754 FLD (f_accs) = f_accs;
1755 FLD (f_r1) = f_r1;
1756 FLD (i_src1) = & CPU (h_gr)[f_r1];
1757 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1758
1759 #if WITH_PROFILE_MODEL_P
1760 /* Record the fields for profiling. */
1761 if (PROFILE_MODEL_P (current_cpu))
1762 {
1763 FLD (in_src1) = f_r1;
1764 }
1765 #endif
1766 #undef FLD
1767 return idesc;
1768 }
1769
1770 extract_sfmt_mvtc:
1771 {
1772 const IDESC *idesc = &m32rxf_insn_data[itype];
1773 CGEN_INSN_INT insn = entire_insn;
1774 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1775 UINT f_r1;
1776 UINT f_r2;
1777
1778 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1779 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1780
1781 /* Record the fields for the semantic handler. */
1782 FLD (f_r2) = f_r2;
1783 FLD (f_r1) = f_r1;
1784 FLD (i_sr) = & CPU (h_gr)[f_r2];
1785 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1786
1787 #if WITH_PROFILE_MODEL_P
1788 /* Record the fields for profiling. */
1789 if (PROFILE_MODEL_P (current_cpu))
1790 {
1791 FLD (in_sr) = f_r2;
1792 }
1793 #endif
1794 #undef FLD
1795 return idesc;
1796 }
1797
1798 extract_sfmt_nop:
1799 {
1800 const IDESC *idesc = &m32rxf_insn_data[itype];
1801 #define FLD(f) abuf->fields.fmt_empty.f
1802
1803
1804 /* Record the fields for the semantic handler. */
1805 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1806
1807 #undef FLD
1808 return idesc;
1809 }
1810
1811 extract_sfmt_rac_dsi:
1812 {
1813 const IDESC *idesc = &m32rxf_insn_data[itype];
1814 CGEN_INSN_INT insn = entire_insn;
1815 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1816 UINT f_accd;
1817 UINT f_accs;
1818 SI f_imm1;
1819
1820 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1821 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1822 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1823
1824 /* Record the fields for the semantic handler. */
1825 FLD (f_accs) = f_accs;
1826 FLD (f_imm1) = f_imm1;
1827 FLD (f_accd) = f_accd;
1828 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1829
1830 #undef FLD
1831 return idesc;
1832 }
1833
1834 extract_sfmt_rte:
1835 {
1836 const IDESC *idesc = &m32rxf_insn_data[itype];
1837 #define FLD(f) abuf->fields.fmt_empty.f
1838
1839
1840 /* Record the fields for the semantic handler. */
1841 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1842
1843 #if WITH_PROFILE_MODEL_P
1844 /* Record the fields for profiling. */
1845 if (PROFILE_MODEL_P (current_cpu))
1846 {
1847 }
1848 #endif
1849 #undef FLD
1850 return idesc;
1851 }
1852
1853 extract_sfmt_seth:
1854 {
1855 const IDESC *idesc = &m32rxf_insn_data[itype];
1856 CGEN_INSN_INT insn = entire_insn;
1857 #define FLD(f) abuf->fields.sfmt_seth.f
1858 UINT f_r1;
1859 UINT f_hi16;
1860
1861 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1862 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1863
1864 /* Record the fields for the semantic handler. */
1865 FLD (f_hi16) = f_hi16;
1866 FLD (f_r1) = f_r1;
1867 FLD (i_dr) = & CPU (h_gr)[f_r1];
1868 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1869
1870 #if WITH_PROFILE_MODEL_P
1871 /* Record the fields for profiling. */
1872 if (PROFILE_MODEL_P (current_cpu))
1873 {
1874 FLD (out_dr) = f_r1;
1875 }
1876 #endif
1877 #undef FLD
1878 return idesc;
1879 }
1880
1881 extract_sfmt_sll3:
1882 {
1883 const IDESC *idesc = &m32rxf_insn_data[itype];
1884 CGEN_INSN_INT insn = entire_insn;
1885 #define FLD(f) abuf->fields.sfmt_add3.f
1886 UINT f_r1;
1887 UINT f_r2;
1888 INT f_simm16;
1889
1890 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1891 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1892 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1893
1894 /* Record the fields for the semantic handler. */
1895 FLD (f_simm16) = f_simm16;
1896 FLD (f_r2) = f_r2;
1897 FLD (f_r1) = f_r1;
1898 FLD (i_sr) = & CPU (h_gr)[f_r2];
1899 FLD (i_dr) = & CPU (h_gr)[f_r1];
1900 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1901
1902 #if WITH_PROFILE_MODEL_P
1903 /* Record the fields for profiling. */
1904 if (PROFILE_MODEL_P (current_cpu))
1905 {
1906 FLD (in_sr) = f_r2;
1907 FLD (out_dr) = f_r1;
1908 }
1909 #endif
1910 #undef FLD
1911 return idesc;
1912 }
1913
1914 extract_sfmt_slli:
1915 {
1916 const IDESC *idesc = &m32rxf_insn_data[itype];
1917 CGEN_INSN_INT insn = entire_insn;
1918 #define FLD(f) abuf->fields.sfmt_slli.f
1919 UINT f_r1;
1920 UINT f_uimm5;
1921
1922 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1923 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1924
1925 /* Record the fields for the semantic handler. */
1926 FLD (f_r1) = f_r1;
1927 FLD (f_uimm5) = f_uimm5;
1928 FLD (i_dr) = & CPU (h_gr)[f_r1];
1929 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1930
1931 #if WITH_PROFILE_MODEL_P
1932 /* Record the fields for profiling. */
1933 if (PROFILE_MODEL_P (current_cpu))
1934 {
1935 FLD (in_dr) = f_r1;
1936 FLD (out_dr) = f_r1;
1937 }
1938 #endif
1939 #undef FLD
1940 return idesc;
1941 }
1942
1943 extract_sfmt_st:
1944 {
1945 const IDESC *idesc = &m32rxf_insn_data[itype];
1946 CGEN_INSN_INT insn = entire_insn;
1947 #define FLD(f) abuf->fields.sfmt_st_plus.f
1948 UINT f_r1;
1949 UINT f_r2;
1950
1951 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1952 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1953
1954 /* Record the fields for the semantic handler. */
1955 FLD (f_r1) = f_r1;
1956 FLD (f_r2) = f_r2;
1957 FLD (i_src1) = & CPU (h_gr)[f_r1];
1958 FLD (i_src2) = & CPU (h_gr)[f_r2];
1959 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1960
1961 #if WITH_PROFILE_MODEL_P
1962 /* Record the fields for profiling. */
1963 if (PROFILE_MODEL_P (current_cpu))
1964 {
1965 FLD (in_src1) = f_r1;
1966 FLD (in_src2) = f_r2;
1967 }
1968 #endif
1969 #undef FLD
1970 return idesc;
1971 }
1972
1973 extract_sfmt_st_d:
1974 {
1975 const IDESC *idesc = &m32rxf_insn_data[itype];
1976 CGEN_INSN_INT insn = entire_insn;
1977 #define FLD(f) abuf->fields.sfmt_st_d.f
1978 UINT f_r1;
1979 UINT f_r2;
1980 INT f_simm16;
1981
1982 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1983 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1984 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1985
1986 /* Record the fields for the semantic handler. */
1987 FLD (f_simm16) = f_simm16;
1988 FLD (f_r1) = f_r1;
1989 FLD (f_r2) = f_r2;
1990 FLD (i_src1) = & CPU (h_gr)[f_r1];
1991 FLD (i_src2) = & CPU (h_gr)[f_r2];
1992 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1993
1994 #if WITH_PROFILE_MODEL_P
1995 /* Record the fields for profiling. */
1996 if (PROFILE_MODEL_P (current_cpu))
1997 {
1998 FLD (in_src1) = f_r1;
1999 FLD (in_src2) = f_r2;
2000 }
2001 #endif
2002 #undef FLD
2003 return idesc;
2004 }
2005
2006 extract_sfmt_stb:
2007 {
2008 const IDESC *idesc = &m32rxf_insn_data[itype];
2009 CGEN_INSN_INT insn = entire_insn;
2010 #define FLD(f) abuf->fields.sfmt_st_plus.f
2011 UINT f_r1;
2012 UINT f_r2;
2013
2014 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2015 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2016
2017 /* Record the fields for the semantic handler. */
2018 FLD (f_r1) = f_r1;
2019 FLD (f_r2) = f_r2;
2020 FLD (i_src1) = & CPU (h_gr)[f_r1];
2021 FLD (i_src2) = & CPU (h_gr)[f_r2];
2022 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2023
2024 #if WITH_PROFILE_MODEL_P
2025 /* Record the fields for profiling. */
2026 if (PROFILE_MODEL_P (current_cpu))
2027 {
2028 FLD (in_src1) = f_r1;
2029 FLD (in_src2) = f_r2;
2030 }
2031 #endif
2032 #undef FLD
2033 return idesc;
2034 }
2035
2036 extract_sfmt_stb_d:
2037 {
2038 const IDESC *idesc = &m32rxf_insn_data[itype];
2039 CGEN_INSN_INT insn = entire_insn;
2040 #define FLD(f) abuf->fields.sfmt_st_d.f
2041 UINT f_r1;
2042 UINT f_r2;
2043 INT f_simm16;
2044
2045 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2046 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2047 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2048
2049 /* Record the fields for the semantic handler. */
2050 FLD (f_simm16) = f_simm16;
2051 FLD (f_r1) = f_r1;
2052 FLD (f_r2) = f_r2;
2053 FLD (i_src1) = & CPU (h_gr)[f_r1];
2054 FLD (i_src2) = & CPU (h_gr)[f_r2];
2055 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2056
2057 #if WITH_PROFILE_MODEL_P
2058 /* Record the fields for profiling. */
2059 if (PROFILE_MODEL_P (current_cpu))
2060 {
2061 FLD (in_src1) = f_r1;
2062 FLD (in_src2) = f_r2;
2063 }
2064 #endif
2065 #undef FLD
2066 return idesc;
2067 }
2068
2069 extract_sfmt_sth:
2070 {
2071 const IDESC *idesc = &m32rxf_insn_data[itype];
2072 CGEN_INSN_INT insn = entire_insn;
2073 #define FLD(f) abuf->fields.sfmt_st_plus.f
2074 UINT f_r1;
2075 UINT f_r2;
2076
2077 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2078 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2079
2080 /* Record the fields for the semantic handler. */
2081 FLD (f_r1) = f_r1;
2082 FLD (f_r2) = f_r2;
2083 FLD (i_src1) = & CPU (h_gr)[f_r1];
2084 FLD (i_src2) = & CPU (h_gr)[f_r2];
2085 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2086
2087 #if WITH_PROFILE_MODEL_P
2088 /* Record the fields for profiling. */
2089 if (PROFILE_MODEL_P (current_cpu))
2090 {
2091 FLD (in_src1) = f_r1;
2092 FLD (in_src2) = f_r2;
2093 }
2094 #endif
2095 #undef FLD
2096 return idesc;
2097 }
2098
2099 extract_sfmt_sth_d:
2100 {
2101 const IDESC *idesc = &m32rxf_insn_data[itype];
2102 CGEN_INSN_INT insn = entire_insn;
2103 #define FLD(f) abuf->fields.sfmt_st_d.f
2104 UINT f_r1;
2105 UINT f_r2;
2106 INT f_simm16;
2107
2108 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2109 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2110 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2111
2112 /* Record the fields for the semantic handler. */
2113 FLD (f_simm16) = f_simm16;
2114 FLD (f_r1) = f_r1;
2115 FLD (f_r2) = f_r2;
2116 FLD (i_src1) = & CPU (h_gr)[f_r1];
2117 FLD (i_src2) = & CPU (h_gr)[f_r2];
2118 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2119
2120 #if WITH_PROFILE_MODEL_P
2121 /* Record the fields for profiling. */
2122 if (PROFILE_MODEL_P (current_cpu))
2123 {
2124 FLD (in_src1) = f_r1;
2125 FLD (in_src2) = f_r2;
2126 }
2127 #endif
2128 #undef FLD
2129 return idesc;
2130 }
2131
2132 extract_sfmt_st_plus:
2133 {
2134 const IDESC *idesc = &m32rxf_insn_data[itype];
2135 CGEN_INSN_INT insn = entire_insn;
2136 #define FLD(f) abuf->fields.sfmt_st_plus.f
2137 UINT f_r1;
2138 UINT f_r2;
2139
2140 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2141 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2142
2143 /* Record the fields for the semantic handler. */
2144 FLD (f_r1) = f_r1;
2145 FLD (f_r2) = f_r2;
2146 FLD (i_src1) = & CPU (h_gr)[f_r1];
2147 FLD (i_src2) = & CPU (h_gr)[f_r2];
2148 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2149
2150 #if WITH_PROFILE_MODEL_P
2151 /* Record the fields for profiling. */
2152 if (PROFILE_MODEL_P (current_cpu))
2153 {
2154 FLD (in_src1) = f_r1;
2155 FLD (in_src2) = f_r2;
2156 FLD (out_src2) = f_r2;
2157 }
2158 #endif
2159 #undef FLD
2160 return idesc;
2161 }
2162
2163 extract_sfmt_trap:
2164 {
2165 const IDESC *idesc = &m32rxf_insn_data[itype];
2166 CGEN_INSN_INT insn = entire_insn;
2167 #define FLD(f) abuf->fields.sfmt_trap.f
2168 UINT f_uimm4;
2169
2170 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2171
2172 /* Record the fields for the semantic handler. */
2173 FLD (f_uimm4) = f_uimm4;
2174 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2175
2176 #if WITH_PROFILE_MODEL_P
2177 /* Record the fields for profiling. */
2178 if (PROFILE_MODEL_P (current_cpu))
2179 {
2180 }
2181 #endif
2182 #undef FLD
2183 return idesc;
2184 }
2185
2186 extract_sfmt_unlock:
2187 {
2188 const IDESC *idesc = &m32rxf_insn_data[itype];
2189 CGEN_INSN_INT insn = entire_insn;
2190 #define FLD(f) abuf->fields.sfmt_st_plus.f
2191 UINT f_r1;
2192 UINT f_r2;
2193
2194 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2195 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2196
2197 /* Record the fields for the semantic handler. */
2198 FLD (f_r1) = f_r1;
2199 FLD (f_r2) = f_r2;
2200 FLD (i_src1) = & CPU (h_gr)[f_r1];
2201 FLD (i_src2) = & CPU (h_gr)[f_r2];
2202 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2203
2204 #if WITH_PROFILE_MODEL_P
2205 /* Record the fields for profiling. */
2206 if (PROFILE_MODEL_P (current_cpu))
2207 {
2208 FLD (in_src1) = f_r1;
2209 FLD (in_src2) = f_r2;
2210 }
2211 #endif
2212 #undef FLD
2213 return idesc;
2214 }
2215
2216 extract_sfmt_satb:
2217 {
2218 const IDESC *idesc = &m32rxf_insn_data[itype];
2219 CGEN_INSN_INT insn = entire_insn;
2220 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2221 UINT f_r1;
2222 UINT f_r2;
2223
2224 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2225 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2226
2227 /* Record the fields for the semantic handler. */
2228 FLD (f_r2) = f_r2;
2229 FLD (f_r1) = f_r1;
2230 FLD (i_sr) = & CPU (h_gr)[f_r2];
2231 FLD (i_dr) = & CPU (h_gr)[f_r1];
2232 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2233
2234 #if WITH_PROFILE_MODEL_P
2235 /* Record the fields for profiling. */
2236 if (PROFILE_MODEL_P (current_cpu))
2237 {
2238 FLD (in_sr) = f_r2;
2239 FLD (out_dr) = f_r1;
2240 }
2241 #endif
2242 #undef FLD
2243 return idesc;
2244 }
2245
2246 extract_sfmt_sat:
2247 {
2248 const IDESC *idesc = &m32rxf_insn_data[itype];
2249 CGEN_INSN_INT insn = entire_insn;
2250 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2251 UINT f_r1;
2252 UINT f_r2;
2253
2254 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2255 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2256
2257 /* Record the fields for the semantic handler. */
2258 FLD (f_r2) = f_r2;
2259 FLD (f_r1) = f_r1;
2260 FLD (i_sr) = & CPU (h_gr)[f_r2];
2261 FLD (i_dr) = & CPU (h_gr)[f_r1];
2262 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2263
2264 #if WITH_PROFILE_MODEL_P
2265 /* Record the fields for profiling. */
2266 if (PROFILE_MODEL_P (current_cpu))
2267 {
2268 FLD (in_sr) = f_r2;
2269 FLD (out_dr) = f_r1;
2270 }
2271 #endif
2272 #undef FLD
2273 return idesc;
2274 }
2275
2276 extract_sfmt_sadd:
2277 {
2278 const IDESC *idesc = &m32rxf_insn_data[itype];
2279 #define FLD(f) abuf->fields.fmt_empty.f
2280
2281
2282 /* Record the fields for the semantic handler. */
2283 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2284
2285 #undef FLD
2286 return idesc;
2287 }
2288
2289 extract_sfmt_macwu1:
2290 {
2291 const IDESC *idesc = &m32rxf_insn_data[itype];
2292 CGEN_INSN_INT insn = entire_insn;
2293 #define FLD(f) abuf->fields.sfmt_st_plus.f
2294 UINT f_r1;
2295 UINT f_r2;
2296
2297 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2298 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2299
2300 /* Record the fields for the semantic handler. */
2301 FLD (f_r1) = f_r1;
2302 FLD (f_r2) = f_r2;
2303 FLD (i_src1) = & CPU (h_gr)[f_r1];
2304 FLD (i_src2) = & CPU (h_gr)[f_r2];
2305 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2306
2307 #if WITH_PROFILE_MODEL_P
2308 /* Record the fields for profiling. */
2309 if (PROFILE_MODEL_P (current_cpu))
2310 {
2311 FLD (in_src1) = f_r1;
2312 FLD (in_src2) = f_r2;
2313 }
2314 #endif
2315 #undef FLD
2316 return idesc;
2317 }
2318
2319 extract_sfmt_msblo:
2320 {
2321 const IDESC *idesc = &m32rxf_insn_data[itype];
2322 CGEN_INSN_INT insn = entire_insn;
2323 #define FLD(f) abuf->fields.sfmt_st_plus.f
2324 UINT f_r1;
2325 UINT f_r2;
2326
2327 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2328 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2329
2330 /* Record the fields for the semantic handler. */
2331 FLD (f_r1) = f_r1;
2332 FLD (f_r2) = f_r2;
2333 FLD (i_src1) = & CPU (h_gr)[f_r1];
2334 FLD (i_src2) = & CPU (h_gr)[f_r2];
2335 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2336
2337 #if WITH_PROFILE_MODEL_P
2338 /* Record the fields for profiling. */
2339 if (PROFILE_MODEL_P (current_cpu))
2340 {
2341 FLD (in_src1) = f_r1;
2342 FLD (in_src2) = f_r2;
2343 }
2344 #endif
2345 #undef FLD
2346 return idesc;
2347 }
2348
2349 extract_sfmt_mulwu1:
2350 {
2351 const IDESC *idesc = &m32rxf_insn_data[itype];
2352 CGEN_INSN_INT insn = entire_insn;
2353 #define FLD(f) abuf->fields.sfmt_st_plus.f
2354 UINT f_r1;
2355 UINT f_r2;
2356
2357 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2358 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2359
2360 /* Record the fields for the semantic handler. */
2361 FLD (f_r1) = f_r1;
2362 FLD (f_r2) = f_r2;
2363 FLD (i_src1) = & CPU (h_gr)[f_r1];
2364 FLD (i_src2) = & CPU (h_gr)[f_r2];
2365 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2366
2367 #if WITH_PROFILE_MODEL_P
2368 /* Record the fields for profiling. */
2369 if (PROFILE_MODEL_P (current_cpu))
2370 {
2371 FLD (in_src1) = f_r1;
2372 FLD (in_src2) = f_r2;
2373 }
2374 #endif
2375 #undef FLD
2376 return idesc;
2377 }
2378
2379 extract_sfmt_sc:
2380 {
2381 const IDESC *idesc = &m32rxf_insn_data[itype];
2382 #define FLD(f) abuf->fields.fmt_empty.f
2383
2384
2385 /* Record the fields for the semantic handler. */
2386 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2387
2388 #undef FLD
2389 return idesc;
2390 }
2391
2392 }