1 /* Simulator instruction decoder for m32rxf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #define WANT_CPU_M32RXF
29 #include "sim-assert.h"
34 #define FMT(n) CONCAT2 (M32RXF_,n) ,
37 /* FIXME: Need to review choices for the following. */
39 #if WITH_SEM_SWITCH_FULL
42 #define FULL(fn) CONCAT3 (m32rxf,_sem_,fn) ,
46 #if WITH_SEM_SWITCH_FAST
49 #define FAST(fn) CONCAT3 (m32rxf,_semf_,fn) , /* f for fast */
55 /* The instruction descriptor array.
56 This is computed at runtime. Space for it is not malloc'd to save a
57 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
58 but won't be done until necessary (we don't currently support the runtime
59 addition of instructions nor an SMP machine with different cpus). */
60 static IDESC m32rxf_insn_data
[M32RXF_INSN_MAX
];
62 /* Instruction semantic handlers and support.
63 This struct defines the part of an IDESC that can be computed at
67 /* The instruction type (a number that identifies each insn over the
68 entire architecture). */
71 /* Index in IDESC table. */
74 /* Index in IDESC table of parallel handler. */
77 /* Index in IDESC table of writeback handler. */
80 /* Routines to execute the insn.
81 The full version has all features (profiling,tracing) compiled in.
82 The fast version has none of that. */
83 #if ! WITH_SEM_SWITCH_FULL
84 SEMANTIC_FN
*sem_full
;
86 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
87 SEMANTIC_FN
*sem_fast
;
91 /* The INSN_ prefix is not here and is instead part of the `insn' argument
92 to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
93 #define IDX(insn) CONCAT2 (M32RXF_,insn)
94 #define TYPE(insn) CONCAT2 (M32R_,insn)
96 /* Insn can't be executed in parallel.
97 Or is that "do NOt Pass to Air defense Radar"? :-) */
100 /* Commas between elements are contained in the macros.
101 Some of these are conditionally compiled out. */
103 static const struct insn_sem m32rxf_insn_sem
[] =
105 { VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), NOPAR
, NOPAR
, FULL (x_invalid
) FAST (x_invalid
) },
106 { VIRTUAL_INSN_X_AFTER
, IDX (INSN_X_AFTER
), NOPAR
, NOPAR
, FULL (x_after
) FAST (x_after
) },
107 { VIRTUAL_INSN_X_BEFORE
, IDX (INSN_X_BEFORE
), NOPAR
, NOPAR
, FULL (x_before
) FAST (x_before
) },
108 { VIRTUAL_INSN_X_CTI_CHAIN
, IDX (INSN_X_CTI_CHAIN
), NOPAR
, NOPAR
, FULL (x_cti_chain
) FAST (x_cti_chain
) },
109 { VIRTUAL_INSN_X_CHAIN
, IDX (INSN_X_CHAIN
), NOPAR
, NOPAR
, FULL (x_chain
) FAST (x_chain
) },
110 { VIRTUAL_INSN_X_BEGIN
, IDX (INSN_X_BEGIN
), NOPAR
, NOPAR
, FULL (x_begin
) FAST (x_begin
) },
111 { TYPE (INSN_ADD
), IDX (INSN_ADD
), IDX (INSN_PAR_ADD
), IDX (INSN_WRITE_ADD
), FULL (add
) FAST (add
) },
112 { TYPE (INSN_ADD3
), IDX (INSN_ADD3
), NOPAR
, NOPAR
, FULL (add3
) FAST (add3
) },
113 { TYPE (INSN_AND
), IDX (INSN_AND
), IDX (INSN_PAR_AND
), IDX (INSN_WRITE_AND
), FULL (and) FAST (and) },
114 { TYPE (INSN_AND3
), IDX (INSN_AND3
), NOPAR
, NOPAR
, FULL (and3
) FAST (and3
) },
115 { TYPE (INSN_OR
), IDX (INSN_OR
), IDX (INSN_PAR_OR
), IDX (INSN_WRITE_OR
), FULL (or) FAST (or) },
116 { TYPE (INSN_OR3
), IDX (INSN_OR3
), NOPAR
, NOPAR
, FULL (or3
) FAST (or3
) },
117 { TYPE (INSN_XOR
), IDX (INSN_XOR
), IDX (INSN_PAR_XOR
), IDX (INSN_WRITE_XOR
), FULL (xor) FAST (xor) },
118 { TYPE (INSN_XOR3
), IDX (INSN_XOR3
), NOPAR
, NOPAR
, FULL (xor3
) FAST (xor3
) },
119 { TYPE (INSN_ADDI
), IDX (INSN_ADDI
), IDX (INSN_PAR_ADDI
), IDX (INSN_WRITE_ADDI
), FULL (addi
) FAST (addi
) },
120 { TYPE (INSN_ADDV
), IDX (INSN_ADDV
), IDX (INSN_PAR_ADDV
), IDX (INSN_WRITE_ADDV
), FULL (addv
) FAST (addv
) },
121 { TYPE (INSN_ADDV3
), IDX (INSN_ADDV3
), NOPAR
, NOPAR
, FULL (addv3
) FAST (addv3
) },
122 { TYPE (INSN_ADDX
), IDX (INSN_ADDX
), IDX (INSN_PAR_ADDX
), IDX (INSN_WRITE_ADDX
), FULL (addx
) FAST (addx
) },
123 { TYPE (INSN_BC8
), IDX (INSN_BC8
), IDX (INSN_PAR_BC8
), IDX (INSN_WRITE_BC8
), FULL (bc8
) FAST (bc8
) },
124 { TYPE (INSN_BC24
), IDX (INSN_BC24
), NOPAR
, NOPAR
, FULL (bc24
) FAST (bc24
) },
125 { TYPE (INSN_BEQ
), IDX (INSN_BEQ
), NOPAR
, NOPAR
, FULL (beq
) FAST (beq
) },
126 { TYPE (INSN_BEQZ
), IDX (INSN_BEQZ
), NOPAR
, NOPAR
, FULL (beqz
) FAST (beqz
) },
127 { TYPE (INSN_BGEZ
), IDX (INSN_BGEZ
), NOPAR
, NOPAR
, FULL (bgez
) FAST (bgez
) },
128 { TYPE (INSN_BGTZ
), IDX (INSN_BGTZ
), NOPAR
, NOPAR
, FULL (bgtz
) FAST (bgtz
) },
129 { TYPE (INSN_BLEZ
), IDX (INSN_BLEZ
), NOPAR
, NOPAR
, FULL (blez
) FAST (blez
) },
130 { TYPE (INSN_BLTZ
), IDX (INSN_BLTZ
), NOPAR
, NOPAR
, FULL (bltz
) FAST (bltz
) },
131 { TYPE (INSN_BNEZ
), IDX (INSN_BNEZ
), NOPAR
, NOPAR
, FULL (bnez
) FAST (bnez
) },
132 { TYPE (INSN_BL8
), IDX (INSN_BL8
), IDX (INSN_PAR_BL8
), IDX (INSN_WRITE_BL8
), FULL (bl8
) FAST (bl8
) },
133 { TYPE (INSN_BL24
), IDX (INSN_BL24
), NOPAR
, NOPAR
, FULL (bl24
) FAST (bl24
) },
134 { TYPE (INSN_BCL8
), IDX (INSN_BCL8
), IDX (INSN_PAR_BCL8
), IDX (INSN_WRITE_BCL8
), FULL (bcl8
) FAST (bcl8
) },
135 { TYPE (INSN_BCL24
), IDX (INSN_BCL24
), NOPAR
, NOPAR
, FULL (bcl24
) FAST (bcl24
) },
136 { TYPE (INSN_BNC8
), IDX (INSN_BNC8
), IDX (INSN_PAR_BNC8
), IDX (INSN_WRITE_BNC8
), FULL (bnc8
) FAST (bnc8
) },
137 { TYPE (INSN_BNC24
), IDX (INSN_BNC24
), NOPAR
, NOPAR
, FULL (bnc24
) FAST (bnc24
) },
138 { TYPE (INSN_BNE
), IDX (INSN_BNE
), NOPAR
, NOPAR
, FULL (bne
) FAST (bne
) },
139 { TYPE (INSN_BRA8
), IDX (INSN_BRA8
), IDX (INSN_PAR_BRA8
), IDX (INSN_WRITE_BRA8
), FULL (bra8
) FAST (bra8
) },
140 { TYPE (INSN_BRA24
), IDX (INSN_BRA24
), NOPAR
, NOPAR
, FULL (bra24
) FAST (bra24
) },
141 { TYPE (INSN_BNCL8
), IDX (INSN_BNCL8
), IDX (INSN_PAR_BNCL8
), IDX (INSN_WRITE_BNCL8
), FULL (bncl8
) FAST (bncl8
) },
142 { TYPE (INSN_BNCL24
), IDX (INSN_BNCL24
), NOPAR
, NOPAR
, FULL (bncl24
) FAST (bncl24
) },
143 { TYPE (INSN_CMP
), IDX (INSN_CMP
), IDX (INSN_PAR_CMP
), IDX (INSN_WRITE_CMP
), FULL (cmp
) FAST (cmp
) },
144 { TYPE (INSN_CMPI
), IDX (INSN_CMPI
), NOPAR
, NOPAR
, FULL (cmpi
) FAST (cmpi
) },
145 { TYPE (INSN_CMPU
), IDX (INSN_CMPU
), IDX (INSN_PAR_CMPU
), IDX (INSN_WRITE_CMPU
), FULL (cmpu
) FAST (cmpu
) },
146 { TYPE (INSN_CMPUI
), IDX (INSN_CMPUI
), NOPAR
, NOPAR
, FULL (cmpui
) FAST (cmpui
) },
147 { TYPE (INSN_CMPEQ
), IDX (INSN_CMPEQ
), IDX (INSN_PAR_CMPEQ
), IDX (INSN_WRITE_CMPEQ
), FULL (cmpeq
) FAST (cmpeq
) },
148 { TYPE (INSN_CMPZ
), IDX (INSN_CMPZ
), IDX (INSN_PAR_CMPZ
), IDX (INSN_WRITE_CMPZ
), FULL (cmpz
) FAST (cmpz
) },
149 { TYPE (INSN_DIV
), IDX (INSN_DIV
), NOPAR
, NOPAR
, FULL (div
) FAST (div
) },
150 { TYPE (INSN_DIVU
), IDX (INSN_DIVU
), NOPAR
, NOPAR
, FULL (divu
) FAST (divu
) },
151 { TYPE (INSN_REM
), IDX (INSN_REM
), NOPAR
, NOPAR
, FULL (rem
) FAST (rem
) },
152 { TYPE (INSN_REMU
), IDX (INSN_REMU
), NOPAR
, NOPAR
, FULL (remu
) FAST (remu
) },
153 { TYPE (INSN_DIVH
), IDX (INSN_DIVH
), NOPAR
, NOPAR
, FULL (divh
) FAST (divh
) },
154 { TYPE (INSN_JC
), IDX (INSN_JC
), IDX (INSN_PAR_JC
), IDX (INSN_WRITE_JC
), FULL (jc
) FAST (jc
) },
155 { TYPE (INSN_JNC
), IDX (INSN_JNC
), IDX (INSN_PAR_JNC
), IDX (INSN_WRITE_JNC
), FULL (jnc
) FAST (jnc
) },
156 { TYPE (INSN_JL
), IDX (INSN_JL
), IDX (INSN_PAR_JL
), IDX (INSN_WRITE_JL
), FULL (jl
) FAST (jl
) },
157 { TYPE (INSN_JMP
), IDX (INSN_JMP
), IDX (INSN_PAR_JMP
), IDX (INSN_WRITE_JMP
), FULL (jmp
) FAST (jmp
) },
158 { TYPE (INSN_LD
), IDX (INSN_LD
), IDX (INSN_PAR_LD
), IDX (INSN_WRITE_LD
), FULL (ld
) FAST (ld
) },
159 { TYPE (INSN_LD_D
), IDX (INSN_LD_D
), NOPAR
, NOPAR
, FULL (ld_d
) FAST (ld_d
) },
160 { TYPE (INSN_LDB
), IDX (INSN_LDB
), IDX (INSN_PAR_LDB
), IDX (INSN_WRITE_LDB
), FULL (ldb
) FAST (ldb
) },
161 { TYPE (INSN_LDB_D
), IDX (INSN_LDB_D
), NOPAR
, NOPAR
, FULL (ldb_d
) FAST (ldb_d
) },
162 { TYPE (INSN_LDH
), IDX (INSN_LDH
), IDX (INSN_PAR_LDH
), IDX (INSN_WRITE_LDH
), FULL (ldh
) FAST (ldh
) },
163 { TYPE (INSN_LDH_D
), IDX (INSN_LDH_D
), NOPAR
, NOPAR
, FULL (ldh_d
) FAST (ldh_d
) },
164 { TYPE (INSN_LDUB
), IDX (INSN_LDUB
), IDX (INSN_PAR_LDUB
), IDX (INSN_WRITE_LDUB
), FULL (ldub
) FAST (ldub
) },
165 { TYPE (INSN_LDUB_D
), IDX (INSN_LDUB_D
), NOPAR
, NOPAR
, FULL (ldub_d
) FAST (ldub_d
) },
166 { TYPE (INSN_LDUH
), IDX (INSN_LDUH
), IDX (INSN_PAR_LDUH
), IDX (INSN_WRITE_LDUH
), FULL (lduh
) FAST (lduh
) },
167 { TYPE (INSN_LDUH_D
), IDX (INSN_LDUH_D
), NOPAR
, NOPAR
, FULL (lduh_d
) FAST (lduh_d
) },
168 { TYPE (INSN_LD_PLUS
), IDX (INSN_LD_PLUS
), IDX (INSN_PAR_LD_PLUS
), IDX (INSN_WRITE_LD_PLUS
), FULL (ld_plus
) FAST (ld_plus
) },
169 { TYPE (INSN_LD24
), IDX (INSN_LD24
), NOPAR
, NOPAR
, FULL (ld24
) FAST (ld24
) },
170 { TYPE (INSN_LDI8
), IDX (INSN_LDI8
), IDX (INSN_PAR_LDI8
), IDX (INSN_WRITE_LDI8
), FULL (ldi8
) FAST (ldi8
) },
171 { TYPE (INSN_LDI16
), IDX (INSN_LDI16
), NOPAR
, NOPAR
, FULL (ldi16
) FAST (ldi16
) },
172 { TYPE (INSN_LOCK
), IDX (INSN_LOCK
), IDX (INSN_PAR_LOCK
), IDX (INSN_WRITE_LOCK
), FULL (lock
) FAST (lock
) },
173 { TYPE (INSN_MACHI_A
), IDX (INSN_MACHI_A
), IDX (INSN_PAR_MACHI_A
), IDX (INSN_WRITE_MACHI_A
), FULL (machi_a
) FAST (machi_a
) },
174 { TYPE (INSN_MACLO_A
), IDX (INSN_MACLO_A
), IDX (INSN_PAR_MACLO_A
), IDX (INSN_WRITE_MACLO_A
), FULL (maclo_a
) FAST (maclo_a
) },
175 { TYPE (INSN_MACWHI_A
), IDX (INSN_MACWHI_A
), IDX (INSN_PAR_MACWHI_A
), IDX (INSN_WRITE_MACWHI_A
), FULL (macwhi_a
) FAST (macwhi_a
) },
176 { TYPE (INSN_MACWLO_A
), IDX (INSN_MACWLO_A
), IDX (INSN_PAR_MACWLO_A
), IDX (INSN_WRITE_MACWLO_A
), FULL (macwlo_a
) FAST (macwlo_a
) },
177 { TYPE (INSN_MUL
), IDX (INSN_MUL
), IDX (INSN_PAR_MUL
), IDX (INSN_WRITE_MUL
), FULL (mul
) FAST (mul
) },
178 { TYPE (INSN_MULHI_A
), IDX (INSN_MULHI_A
), IDX (INSN_PAR_MULHI_A
), IDX (INSN_WRITE_MULHI_A
), FULL (mulhi_a
) FAST (mulhi_a
) },
179 { TYPE (INSN_MULLO_A
), IDX (INSN_MULLO_A
), IDX (INSN_PAR_MULLO_A
), IDX (INSN_WRITE_MULLO_A
), FULL (mullo_a
) FAST (mullo_a
) },
180 { TYPE (INSN_MULWHI_A
), IDX (INSN_MULWHI_A
), IDX (INSN_PAR_MULWHI_A
), IDX (INSN_WRITE_MULWHI_A
), FULL (mulwhi_a
) FAST (mulwhi_a
) },
181 { TYPE (INSN_MULWLO_A
), IDX (INSN_MULWLO_A
), IDX (INSN_PAR_MULWLO_A
), IDX (INSN_WRITE_MULWLO_A
), FULL (mulwlo_a
) FAST (mulwlo_a
) },
182 { TYPE (INSN_MV
), IDX (INSN_MV
), IDX (INSN_PAR_MV
), IDX (INSN_WRITE_MV
), FULL (mv
) FAST (mv
) },
183 { TYPE (INSN_MVFACHI_A
), IDX (INSN_MVFACHI_A
), IDX (INSN_PAR_MVFACHI_A
), IDX (INSN_WRITE_MVFACHI_A
), FULL (mvfachi_a
) FAST (mvfachi_a
) },
184 { TYPE (INSN_MVFACLO_A
), IDX (INSN_MVFACLO_A
), IDX (INSN_PAR_MVFACLO_A
), IDX (INSN_WRITE_MVFACLO_A
), FULL (mvfaclo_a
) FAST (mvfaclo_a
) },
185 { TYPE (INSN_MVFACMI_A
), IDX (INSN_MVFACMI_A
), IDX (INSN_PAR_MVFACMI_A
), IDX (INSN_WRITE_MVFACMI_A
), FULL (mvfacmi_a
) FAST (mvfacmi_a
) },
186 { TYPE (INSN_MVFC
), IDX (INSN_MVFC
), IDX (INSN_PAR_MVFC
), IDX (INSN_WRITE_MVFC
), FULL (mvfc
) FAST (mvfc
) },
187 { TYPE (INSN_MVTACHI_A
), IDX (INSN_MVTACHI_A
), IDX (INSN_PAR_MVTACHI_A
), IDX (INSN_WRITE_MVTACHI_A
), FULL (mvtachi_a
) FAST (mvtachi_a
) },
188 { TYPE (INSN_MVTACLO_A
), IDX (INSN_MVTACLO_A
), IDX (INSN_PAR_MVTACLO_A
), IDX (INSN_WRITE_MVTACLO_A
), FULL (mvtaclo_a
) FAST (mvtaclo_a
) },
189 { TYPE (INSN_MVTC
), IDX (INSN_MVTC
), IDX (INSN_PAR_MVTC
), IDX (INSN_WRITE_MVTC
), FULL (mvtc
) FAST (mvtc
) },
190 { TYPE (INSN_NEG
), IDX (INSN_NEG
), IDX (INSN_PAR_NEG
), IDX (INSN_WRITE_NEG
), FULL (neg
) FAST (neg
) },
191 { TYPE (INSN_NOP
), IDX (INSN_NOP
), IDX (INSN_PAR_NOP
), IDX (INSN_WRITE_NOP
), FULL (nop
) FAST (nop
) },
192 { TYPE (INSN_NOT
), IDX (INSN_NOT
), IDX (INSN_PAR_NOT
), IDX (INSN_WRITE_NOT
), FULL (not) FAST (not) },
193 { TYPE (INSN_RAC_DSI
), IDX (INSN_RAC_DSI
), IDX (INSN_PAR_RAC_DSI
), IDX (INSN_WRITE_RAC_DSI
), FULL (rac_dsi
) FAST (rac_dsi
) },
194 { TYPE (INSN_RACH_DSI
), IDX (INSN_RACH_DSI
), IDX (INSN_PAR_RACH_DSI
), IDX (INSN_WRITE_RACH_DSI
), FULL (rach_dsi
) FAST (rach_dsi
) },
195 { TYPE (INSN_RTE
), IDX (INSN_RTE
), IDX (INSN_PAR_RTE
), IDX (INSN_WRITE_RTE
), FULL (rte
) FAST (rte
) },
196 { TYPE (INSN_SETH
), IDX (INSN_SETH
), NOPAR
, NOPAR
, FULL (seth
) FAST (seth
) },
197 { TYPE (INSN_SLL
), IDX (INSN_SLL
), IDX (INSN_PAR_SLL
), IDX (INSN_WRITE_SLL
), FULL (sll
) FAST (sll
) },
198 { TYPE (INSN_SLL3
), IDX (INSN_SLL3
), NOPAR
, NOPAR
, FULL (sll3
) FAST (sll3
) },
199 { TYPE (INSN_SLLI
), IDX (INSN_SLLI
), IDX (INSN_PAR_SLLI
), IDX (INSN_WRITE_SLLI
), FULL (slli
) FAST (slli
) },
200 { TYPE (INSN_SRA
), IDX (INSN_SRA
), IDX (INSN_PAR_SRA
), IDX (INSN_WRITE_SRA
), FULL (sra
) FAST (sra
) },
201 { TYPE (INSN_SRA3
), IDX (INSN_SRA3
), NOPAR
, NOPAR
, FULL (sra3
) FAST (sra3
) },
202 { TYPE (INSN_SRAI
), IDX (INSN_SRAI
), IDX (INSN_PAR_SRAI
), IDX (INSN_WRITE_SRAI
), FULL (srai
) FAST (srai
) },
203 { TYPE (INSN_SRL
), IDX (INSN_SRL
), IDX (INSN_PAR_SRL
), IDX (INSN_WRITE_SRL
), FULL (srl
) FAST (srl
) },
204 { TYPE (INSN_SRL3
), IDX (INSN_SRL3
), NOPAR
, NOPAR
, FULL (srl3
) FAST (srl3
) },
205 { TYPE (INSN_SRLI
), IDX (INSN_SRLI
), IDX (INSN_PAR_SRLI
), IDX (INSN_WRITE_SRLI
), FULL (srli
) FAST (srli
) },
206 { TYPE (INSN_ST
), IDX (INSN_ST
), IDX (INSN_PAR_ST
), IDX (INSN_WRITE_ST
), FULL (st
) FAST (st
) },
207 { TYPE (INSN_ST_D
), IDX (INSN_ST_D
), NOPAR
, NOPAR
, FULL (st_d
) FAST (st_d
) },
208 { TYPE (INSN_STB
), IDX (INSN_STB
), IDX (INSN_PAR_STB
), IDX (INSN_WRITE_STB
), FULL (stb
) FAST (stb
) },
209 { TYPE (INSN_STB_D
), IDX (INSN_STB_D
), NOPAR
, NOPAR
, FULL (stb_d
) FAST (stb_d
) },
210 { TYPE (INSN_STH
), IDX (INSN_STH
), IDX (INSN_PAR_STH
), IDX (INSN_WRITE_STH
), FULL (sth
) FAST (sth
) },
211 { TYPE (INSN_STH_D
), IDX (INSN_STH_D
), NOPAR
, NOPAR
, FULL (sth_d
) FAST (sth_d
) },
212 { TYPE (INSN_ST_PLUS
), IDX (INSN_ST_PLUS
), IDX (INSN_PAR_ST_PLUS
), IDX (INSN_WRITE_ST_PLUS
), FULL (st_plus
) FAST (st_plus
) },
213 { TYPE (INSN_ST_MINUS
), IDX (INSN_ST_MINUS
), IDX (INSN_PAR_ST_MINUS
), IDX (INSN_WRITE_ST_MINUS
), FULL (st_minus
) FAST (st_minus
) },
214 { TYPE (INSN_SUB
), IDX (INSN_SUB
), IDX (INSN_PAR_SUB
), IDX (INSN_WRITE_SUB
), FULL (sub
) FAST (sub
) },
215 { TYPE (INSN_SUBV
), IDX (INSN_SUBV
), IDX (INSN_PAR_SUBV
), IDX (INSN_WRITE_SUBV
), FULL (subv
) FAST (subv
) },
216 { TYPE (INSN_SUBX
), IDX (INSN_SUBX
), IDX (INSN_PAR_SUBX
), IDX (INSN_WRITE_SUBX
), FULL (subx
) FAST (subx
) },
217 { TYPE (INSN_TRAP
), IDX (INSN_TRAP
), IDX (INSN_PAR_TRAP
), IDX (INSN_WRITE_TRAP
), FULL (trap
) FAST (trap
) },
218 { TYPE (INSN_UNLOCK
), IDX (INSN_UNLOCK
), IDX (INSN_PAR_UNLOCK
), IDX (INSN_WRITE_UNLOCK
), FULL (unlock
) FAST (unlock
) },
219 { TYPE (INSN_SATB
), IDX (INSN_SATB
), NOPAR
, NOPAR
, FULL (satb
) FAST (satb
) },
220 { TYPE (INSN_SATH
), IDX (INSN_SATH
), NOPAR
, NOPAR
, FULL (sath
) FAST (sath
) },
221 { TYPE (INSN_SAT
), IDX (INSN_SAT
), NOPAR
, NOPAR
, FULL (sat
) FAST (sat
) },
222 { TYPE (INSN_PCMPBZ
), IDX (INSN_PCMPBZ
), IDX (INSN_PAR_PCMPBZ
), IDX (INSN_WRITE_PCMPBZ
), FULL (pcmpbz
) FAST (pcmpbz
) },
223 { TYPE (INSN_SADD
), IDX (INSN_SADD
), IDX (INSN_PAR_SADD
), IDX (INSN_WRITE_SADD
), FULL (sadd
) FAST (sadd
) },
224 { TYPE (INSN_MACWU1
), IDX (INSN_MACWU1
), IDX (INSN_PAR_MACWU1
), IDX (INSN_WRITE_MACWU1
), FULL (macwu1
) FAST (macwu1
) },
225 { TYPE (INSN_MSBLO
), IDX (INSN_MSBLO
), IDX (INSN_PAR_MSBLO
), IDX (INSN_WRITE_MSBLO
), FULL (msblo
) FAST (msblo
) },
226 { TYPE (INSN_MULWU1
), IDX (INSN_MULWU1
), IDX (INSN_PAR_MULWU1
), IDX (INSN_WRITE_MULWU1
), FULL (mulwu1
) FAST (mulwu1
) },
227 { TYPE (INSN_MACLH1
), IDX (INSN_MACLH1
), IDX (INSN_PAR_MACLH1
), IDX (INSN_WRITE_MACLH1
), FULL (maclh1
) FAST (maclh1
) },
228 { TYPE (INSN_SC
), IDX (INSN_SC
), IDX (INSN_PAR_SC
), IDX (INSN_WRITE_SC
), FULL (sc
) FAST (sc
) },
229 { TYPE (INSN_SNC
), IDX (INSN_SNC
), IDX (INSN_PAR_SNC
), IDX (INSN_WRITE_SNC
), FULL (snc
) FAST (snc
) },
232 static const struct insn_sem m32rxf_insn_sem_invalid
=
234 VIRTUAL_INSN_X_INVALID
, IDX (INSN_X_INVALID
), IDX (INSN_X_INVALID
), 0 /*unused*/, FULL (x_invalid
) FAST (x_invalid
)
240 /* Initialize an IDESC from the compile-time computable parts. */
243 init_idesc (SIM_CPU
*cpu
, IDESC
*id
, const struct insn_sem
*t
)
245 const CGEN_INSN
*opcode_table
= m32r_cgen_insn_table_entries
;
248 if ((int) t
->type
<= 0)
249 id
->opcode
= & cgen_virtual_opcode_table
[- t
->type
];
251 id
->opcode
= & opcode_table
[t
->type
];
252 #if ! WITH_SEM_SWITCH_FULL
253 id
->sem_full
= t
->sem_full
;
255 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
256 id
->sem_fast
= t
->sem_fast
;
258 #if WITH_PROFILE_MODEL_P
259 id
->timing
= & MODEL_TIMING (CPU_MODEL (cpu
)) [t
->index
];
261 SIM_DESC sd
= CPU_STATE (cpu
);
262 SIM_ASSERT (t
->index
== id
->timing
->num
);
267 /* Initialize the instruction descriptor table. */
270 m32rxf_init_idesc_table (SIM_CPU
*cpu
)
273 const struct insn_sem
*t
,*tend
;
274 int tabsize
= M32RXF_INSN_MAX
;
275 IDESC
*table
= m32rxf_insn_data
;
277 memset (table
, 0, tabsize
* sizeof (IDESC
));
279 /* First set all entries to the `invalid insn'. */
280 t
= & m32rxf_insn_sem_invalid
;
281 for (id
= table
, tabend
= table
+ tabsize
; id
< tabend
; ++id
)
282 init_idesc (cpu
, id
, t
);
284 /* Now fill in the values for the chosen cpu. */
285 for (t
= m32rxf_insn_sem
, tend
= t
+ sizeof (m32rxf_insn_sem
) / sizeof (*t
);
288 init_idesc (cpu
, & table
[t
->index
], t
);
289 if (t
->par_index
!= NOPAR
)
291 init_idesc (cpu
, &table
[t
->par_index
], t
);
292 table
[t
->index
].par_idesc
= &table
[t
->par_index
];
294 if (t
->par_index
!= NOPAR
)
296 init_idesc (cpu
, &table
[t
->write_index
], t
);
297 table
[t
->par_index
].par_idesc
= &table
[t
->write_index
];
301 /* Link the IDESC table into the cpu. */
302 CPU_IDESC (cpu
) = table
;
305 /* Enum declaration for all instruction formats. */
307 FMT_ADD
, FMT_ADD3
, FMT_AND3
, FMT_OR3
308 , FMT_ADDI
, FMT_ADDV
, FMT_ADDV3
, FMT_ADDX
309 , FMT_BC8
, FMT_BC24
, FMT_BEQ
, FMT_BEQZ
310 , FMT_BL8
, FMT_BL24
, FMT_BCL8
, FMT_BCL24
311 , FMT_BRA8
, FMT_BRA24
, FMT_CMP
, FMT_CMPI
312 , FMT_CMPZ
, FMT_DIV
, FMT_JC
, FMT_JL
313 , FMT_JMP
, FMT_LD
, FMT_LD_D
, FMT_LDB
314 , FMT_LDB_D
, FMT_LDH
, FMT_LDH_D
, FMT_LD_PLUS
315 , FMT_LD24
, FMT_LDI8
, FMT_LDI16
, FMT_LOCK
316 , FMT_MACHI_A
, FMT_MULHI_A
, FMT_MV
, FMT_MVFACHI_A
317 , FMT_MVFC
, FMT_MVTACHI_A
, FMT_MVTC
, FMT_NOP
318 , FMT_RAC_DSI
, FMT_RTE
, FMT_SETH
, FMT_SLL3
319 , FMT_SLLI
, FMT_ST
, FMT_ST_D
, FMT_STB
320 , FMT_STB_D
, FMT_STH
, FMT_STH_D
, FMT_ST_PLUS
321 , FMT_TRAP
, FMT_UNLOCK
, FMT_SATB
, FMT_SAT
322 , FMT_SADD
, FMT_MACWU1
, FMT_MSBLO
, FMT_MULWU1
326 /* The decoder uses this to record insns and direct extraction handling. */
337 /* Macro to go from decode phase to extraction phase. */
340 #define GOTO_EXTRACT(id) goto *(id)->ifmt
342 #define GOTO_EXTRACT(id) goto extract
345 /* The decoder needs a slightly different computed goto switch control. */
347 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
349 #define DECODE_SWITCH(N, X) switch (X)
352 /* Given an instruction, return a pointer to its IDESC entry. */
355 m32rxf_decode (SIM_CPU
*current_cpu
, PCADDR pc
,
356 CGEN_INSN_INT base_insn
, CGEN_INSN_INT entire_insn
,
359 /* Result of decoder, used by extractor. */
360 const DECODE_DESC
*idecode
;
362 /* First decode the instruction. */
365 #define I(insn) & m32rxf_insn_data[CONCAT2 (M32RXF_,insn)]
367 #define E(fmt) && case_ex_##fmt
371 CGEN_INSN_INT insn
= base_insn
;
372 static const DECODE_DESC idecode_invalid
= { I (INSN_X_INVALID
), E (FMT_EMPTY
) };
375 static const void *labels_0
[256] = {
376 && default_0
, && default_0
, && default_0
, && default_0
,
377 && default_0
, && default_0
, && default_0
, && case_0_7
,
378 && default_0
, && default_0
, && default_0
, && default_0
,
379 && default_0
, && default_0
, && default_0
, && default_0
,
380 && default_0
, && default_0
, && default_0
, && default_0
,
381 && default_0
, && default_0
, && default_0
, && default_0
,
382 && default_0
, && default_0
, && default_0
, && default_0
,
383 && case_0_28
, && default_0
, && default_0
, && default_0
,
384 && default_0
, && default_0
, && default_0
, && default_0
,
385 && default_0
, && default_0
, && default_0
, && default_0
,
386 && default_0
, && default_0
, && default_0
, && default_0
,
387 && default_0
, && default_0
, && default_0
, && default_0
,
388 && default_0
, && default_0
, && default_0
, && default_0
,
389 && default_0
, && default_0
, && default_0
, && default_0
,
390 && default_0
, && default_0
, && default_0
, && default_0
,
391 && default_0
, && default_0
, && default_0
, && default_0
,
392 && default_0
, && default_0
, && default_0
, && default_0
,
393 && default_0
, && default_0
, && default_0
, && default_0
,
394 && default_0
, && default_0
, && default_0
, && default_0
,
395 && default_0
, && default_0
, && default_0
, && default_0
,
396 && default_0
, && default_0
, && default_0
, && default_0
,
397 && default_0
, && default_0
, && default_0
, && case_0_87
,
398 && default_0
, && default_0
, && default_0
, && default_0
,
399 && default_0
, && default_0
, && default_0
, && case_0_95
,
400 && default_0
, && default_0
, && default_0
, && default_0
,
401 && default_0
, && default_0
, && default_0
, && default_0
,
402 && default_0
, && default_0
, && default_0
, && default_0
,
403 && default_0
, && default_0
, && default_0
, && default_0
,
404 && case_0_112
, && case_0_113
, && case_0_114
, && case_0_115
,
405 && case_0_116
, && case_0_117
, && case_0_118
, && case_0_119
,
406 && case_0_120
, && case_0_121
, && case_0_122
, && case_0_123
,
407 && case_0_124
, && case_0_125
, && case_0_126
, && case_0_127
,
408 && default_0
, && default_0
, && default_0
, && default_0
,
409 && default_0
, && default_0
, && case_0_134
, && default_0
,
410 && default_0
, && default_0
, && default_0
, && default_0
,
411 && default_0
, && default_0
, && default_0
, && default_0
,
412 && case_0_144
, && default_0
, && default_0
, && default_0
,
413 && default_0
, && default_0
, && default_0
, && default_0
,
414 && default_0
, && default_0
, && default_0
, && default_0
,
415 && default_0
, && default_0
, && default_0
, && default_0
,
416 && default_0
, && default_0
, && default_0
, && default_0
,
417 && default_0
, && default_0
, && default_0
, && default_0
,
418 && default_0
, && default_0
, && default_0
, && default_0
,
419 && default_0
, && default_0
, && default_0
, && default_0
,
420 && default_0
, && default_0
, && default_0
, && default_0
,
421 && default_0
, && default_0
, && default_0
, && default_0
,
422 && default_0
, && default_0
, && default_0
, && default_0
,
423 && default_0
, && default_0
, && default_0
, && default_0
,
424 && default_0
, && default_0
, && default_0
, && default_0
,
425 && default_0
, && default_0
, && default_0
, && default_0
,
426 && default_0
, && default_0
, && default_0
, && default_0
,
427 && default_0
, && default_0
, && default_0
, && default_0
,
428 && default_0
, && default_0
, && default_0
, && default_0
,
429 && default_0
, && default_0
, && default_0
, && default_0
,
430 && default_0
, && default_0
, && default_0
, && default_0
,
431 && default_0
, && default_0
, && default_0
, && default_0
,
432 && default_0
, && default_0
, && default_0
, && default_0
,
433 && default_0
, && default_0
, && default_0
, && default_0
,
434 && default_0
, && default_0
, && default_0
, && default_0
,
435 && default_0
, && default_0
, && default_0
, && default_0
,
436 && case_0_240
, && case_0_241
, && case_0_242
, && case_0_243
,
437 && case_0_244
, && case_0_245
, && case_0_246
, && case_0_247
,
438 && case_0_248
, && case_0_249
, && case_0_250
, && case_0_251
,
439 && case_0_252
, && case_0_253
, && case_0_254
, && case_0_255
,
442 static const DECODE_DESC insns
[256] = {
443 { I (INSN_SUBV
), E (FMT_ADDV
) }, { I (INSN_SUBX
), E (FMT_ADDX
) },
444 { I (INSN_SUB
), E (FMT_ADD
) }, { I (INSN_NEG
), E (FMT_MV
) },
445 { I (INSN_CMP
), E (FMT_CMP
) }, { I (INSN_CMPU
), E (FMT_CMP
) },
446 { I (INSN_CMPEQ
), E (FMT_CMP
) }, { 0 },
447 { I (INSN_ADDV
), E (FMT_ADDV
) }, { I (INSN_ADDX
), E (FMT_ADDX
) },
448 { I (INSN_ADD
), E (FMT_ADD
) }, { I (INSN_NOT
), E (FMT_MV
) },
449 { I (INSN_AND
), E (FMT_ADD
) }, { I (INSN_XOR
), E (FMT_ADD
) },
450 { I (INSN_OR
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
451 { I (INSN_SRL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
452 { I (INSN_SRA
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
453 { I (INSN_SLL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
454 { I (INSN_MUL
), E (FMT_ADD
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
455 { I (INSN_MV
), E (FMT_MV
) }, { I (INSN_MVFC
), E (FMT_MVFC
) },
456 { I (INSN_MVTC
), E (FMT_MVTC
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
457 { 0 }, { I (INSN_RTE
), E (FMT_RTE
) },
458 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_TRAP
), E (FMT_TRAP
) },
459 { I (INSN_STB
), E (FMT_STB
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
460 { I (INSN_STH
), E (FMT_STH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
461 { I (INSN_ST
), E (FMT_ST
) }, { I (INSN_UNLOCK
), E (FMT_UNLOCK
) },
462 { I (INSN_ST_PLUS
), E (FMT_ST_PLUS
) }, { I (INSN_ST_MINUS
), E (FMT_ST_PLUS
) },
463 { I (INSN_LDB
), E (FMT_LDB
) }, { I (INSN_LDUB
), E (FMT_LDB
) },
464 { I (INSN_LDH
), E (FMT_LDH
) }, { I (INSN_LDUH
), E (FMT_LDH
) },
465 { I (INSN_LD
), E (FMT_LD
) }, { I (INSN_LOCK
), E (FMT_LOCK
) },
466 { I (INSN_LD_PLUS
), E (FMT_LD_PLUS
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
467 { I (INSN_MULHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULLO_A
), E (FMT_MULHI_A
) },
468 { I (INSN_MULWHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULWLO_A
), E (FMT_MULHI_A
) },
469 { I (INSN_MACHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACLO_A
), E (FMT_MACHI_A
) },
470 { I (INSN_MACWHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACWLO_A
), E (FMT_MACHI_A
) },
471 { I (INSN_MULHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULLO_A
), E (FMT_MULHI_A
) },
472 { I (INSN_MULWHI_A
), E (FMT_MULHI_A
) }, { I (INSN_MULWLO_A
), E (FMT_MULHI_A
) },
473 { I (INSN_MACHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACLO_A
), E (FMT_MACHI_A
) },
474 { I (INSN_MACWHI_A
), E (FMT_MACHI_A
) }, { I (INSN_MACWLO_A
), E (FMT_MACHI_A
) },
475 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
476 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
477 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
478 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
479 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
480 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
481 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
482 { I (INSN_ADDI
), E (FMT_ADDI
) }, { I (INSN_ADDI
), E (FMT_ADDI
) },
483 { I (INSN_SRLI
), E (FMT_SLLI
) }, { I (INSN_SRLI
), E (FMT_SLLI
) },
484 { I (INSN_SRAI
), E (FMT_SLLI
) }, { I (INSN_SRAI
), E (FMT_SLLI
) },
485 { I (INSN_SLLI
), E (FMT_SLLI
) }, { I (INSN_SLLI
), E (FMT_SLLI
) },
486 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { 0 },
487 { I (INSN_RACH_DSI
), E (FMT_RAC_DSI
) }, { I (INSN_RAC_DSI
), E (FMT_RAC_DSI
) },
488 { I (INSN_MULWU1
), E (FMT_MULWU1
) }, { I (INSN_MACWU1
), E (FMT_MACWU1
) },
489 { I (INSN_MACLH1
), E (FMT_MACWU1
) }, { I (INSN_MSBLO
), E (FMT_MSBLO
) },
490 { I (INSN_SADD
), E (FMT_SADD
) }, { 0 },
491 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
492 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
493 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
494 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
495 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
496 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
497 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
498 { I (INSN_LDI8
), E (FMT_LDI8
) }, { I (INSN_LDI8
), E (FMT_LDI8
) },
507 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
508 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
509 { I (INSN_CMPI
), E (FMT_CMPI
) }, { I (INSN_CMPUI
), E (FMT_CMPI
) },
510 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
511 { I (INSN_ADDV3
), E (FMT_ADDV3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
512 { I (INSN_ADD3
), E (FMT_ADD3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
513 { I (INSN_AND3
), E (FMT_AND3
) }, { I (INSN_XOR3
), E (FMT_AND3
) },
514 { I (INSN_OR3
), E (FMT_OR3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
515 { 0 }, { I (INSN_DIVU
), E (FMT_DIV
) },
516 { I (INSN_REM
), E (FMT_DIV
) }, { I (INSN_REMU
), E (FMT_DIV
) },
517 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
518 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
519 { I (INSN_SRL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
520 { I (INSN_SRA3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
521 { I (INSN_SLL3
), E (FMT_SLL3
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
522 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_LDI16
), E (FMT_LDI16
) },
523 { I (INSN_STB_D
), E (FMT_STB_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
524 { I (INSN_STH_D
), E (FMT_STH_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
525 { I (INSN_ST_D
), E (FMT_ST_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
526 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
527 { I (INSN_LDB_D
), E (FMT_LDB_D
) }, { I (INSN_LDUB_D
), E (FMT_LDB_D
) },
528 { I (INSN_LDH_D
), E (FMT_LDH_D
) }, { I (INSN_LDUH_D
), E (FMT_LDH_D
) },
529 { I (INSN_LD_D
), E (FMT_LD_D
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
530 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
531 { I (INSN_BEQ
), E (FMT_BEQ
) }, { I (INSN_BNE
), E (FMT_BEQ
) },
532 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
533 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
534 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
535 { I (INSN_BEQZ
), E (FMT_BEQZ
) }, { I (INSN_BNEZ
), E (FMT_BEQZ
) },
536 { I (INSN_BLTZ
), E (FMT_BEQZ
) }, { I (INSN_BGEZ
), E (FMT_BEQZ
) },
537 { I (INSN_BLEZ
), E (FMT_BEQZ
) }, { I (INSN_BGTZ
), E (FMT_BEQZ
) },
538 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
539 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
540 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
541 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
542 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
543 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
544 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
545 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
546 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
547 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
548 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
549 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
550 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
551 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
552 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
553 { I (INSN_SETH
), E (FMT_SETH
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
554 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
555 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
556 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
557 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
558 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
559 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
560 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
561 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
562 { I (INSN_LD24
), E (FMT_LD24
) }, { I (INSN_LD24
), E (FMT_LD24
) },
573 val
= (((insn
>> 8) & (15 << 4)) | ((insn
>> 4) & (15 << 0)));
574 DECODE_SWITCH (0, val
)
578 static const DECODE_DESC insns
[16] = {
579 { I (INSN_CMPZ
), E (FMT_CMPZ
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
580 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_PCMPBZ
), E (FMT_CMPZ
) },
581 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
582 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
583 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
584 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
585 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
586 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
588 unsigned int val
= (((insn
>> 8) & (15 << 0)));
589 idecode
= &insns
[val
];
590 GOTO_EXTRACT (idecode
);
594 static const DECODE_DESC insns
[16] = {
595 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
596 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
597 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
598 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
599 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
600 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
601 { I (INSN_JC
), E (FMT_JC
) }, { I (INSN_JNC
), E (FMT_JC
) },
602 { I (INSN_JL
), E (FMT_JL
) }, { I (INSN_JMP
), E (FMT_JMP
) },
604 unsigned int val
= (((insn
>> 8) & (15 << 0)));
605 idecode
= &insns
[val
];
606 GOTO_EXTRACT (idecode
);
610 static const DECODE_DESC insns
[4] = {
611 { I (INSN_MVTACHI_A
), E (FMT_MVTACHI_A
) }, { I (INSN_MVTACLO_A
), E (FMT_MVTACHI_A
) },
612 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
614 unsigned int val
= (((insn
>> 0) & (3 << 0)));
615 idecode
= &insns
[val
];
616 GOTO_EXTRACT (idecode
);
620 static const DECODE_DESC insns
[4] = {
621 { I (INSN_MVFACHI_A
), E (FMT_MVFACHI_A
) }, { I (INSN_MVFACLO_A
), E (FMT_MVFACHI_A
) },
622 { I (INSN_MVFACMI_A
), E (FMT_MVFACHI_A
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
624 unsigned int val
= (((insn
>> 0) & (3 << 0)));
625 idecode
= &insns
[val
];
626 GOTO_EXTRACT (idecode
);
630 static const DECODE_DESC insns
[16] = {
631 { I (INSN_NOP
), E (FMT_NOP
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
632 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
633 { I (INSN_SC
), E (FMT_SC
) }, { I (INSN_SNC
), E (FMT_SC
) },
634 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
635 { I (INSN_BCL8
), E (FMT_BCL8
) }, { I (INSN_BNCL8
), E (FMT_BCL8
) },
636 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
637 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
638 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
640 unsigned int val
= (((insn
>> 8) & (15 << 0)));
641 idecode
= &insns
[val
];
642 GOTO_EXTRACT (idecode
);
644 CASE (0, 113) : /* fall through */
645 CASE (0, 114) : /* fall through */
646 CASE (0, 115) : /* fall through */
647 CASE (0, 116) : /* fall through */
648 CASE (0, 117) : /* fall through */
649 CASE (0, 118) : /* fall through */
650 CASE (0, 119) : /* fall through */
651 CASE (0, 120) : /* fall through */
652 CASE (0, 121) : /* fall through */
653 CASE (0, 122) : /* fall through */
654 CASE (0, 123) : /* fall through */
655 CASE (0, 124) : /* fall through */
656 CASE (0, 125) : /* fall through */
657 CASE (0, 126) : /* fall through */
660 static const DECODE_DESC insns
[16] = {
661 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
662 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
663 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
664 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
665 { I (INSN_BCL8
), E (FMT_BCL8
) }, { I (INSN_BNCL8
), E (FMT_BCL8
) },
666 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
667 { I (INSN_BC8
), E (FMT_BC8
) }, { I (INSN_BNC8
), E (FMT_BC8
) },
668 { I (INSN_BL8
), E (FMT_BL8
) }, { I (INSN_BRA8
), E (FMT_BRA8
) },
670 unsigned int val
= (((insn
>> 8) & (15 << 0)));
671 idecode
= &insns
[val
];
672 GOTO_EXTRACT (idecode
);
677 static const void *labels_0_134
[16] = {
678 && case_0_134_0
, && default_0_134
, && default_0_134
, && default_0_134
,
679 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
680 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
681 && default_0_134
, && default_0_134
, && default_0_134
, && default_0_134
,
684 static const DECODE_DESC insns
[16] = {
685 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
686 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
687 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
688 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
689 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
690 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
691 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
692 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
695 /* Must fetch more bits. */
696 insn
= GETIMEMUHI (current_cpu
, pc
+ 2);
697 val
= (((insn
>> 12) & (15 << 0)));
698 DECODE_SWITCH (0_134
, val
)
702 static const DECODE_DESC insns
[16] = {
703 { I (INSN_SAT
), E (FMT_SAT
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
704 { I (INSN_SATH
), E (FMT_SATB
) }, { I (INSN_SATB
), E (FMT_SATB
) },
705 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
706 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
707 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
708 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
709 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
710 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
712 unsigned int val
= (((insn
>> 8) & (15 << 0)));
713 idecode
= &insns
[val
];
714 GOTO_EXTRACT (idecode
);
717 idecode
= &insns
[val
];
718 GOTO_EXTRACT (idecode
);
725 static const void *labels_0_144
[16] = {
726 && case_0_144_0
, && default_0_144
, && default_0_144
, && default_0_144
,
727 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
728 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
729 && default_0_144
, && default_0_144
, && default_0_144
, && default_0_144
,
732 static const DECODE_DESC insns
[16] = {
733 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
734 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
735 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
736 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
737 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
738 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
739 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
740 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
743 /* Must fetch more bits. */
744 insn
= GETIMEMUHI (current_cpu
, pc
+ 2);
745 val
= (((insn
>> 12) & (15 << 0)));
746 DECODE_SWITCH (0_144
, val
)
751 static const void *labels_0_144_0
[16] = {
752 && case_0_144_0_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
753 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
754 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
755 && default_0_144_0
, && default_0_144_0
, && default_0_144_0
, && default_0_144_0
,
758 static const DECODE_DESC insns
[16] = {
759 { 0 }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
760 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
761 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
762 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
763 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
764 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
765 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
766 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
769 val
= (((insn
>> 8) & (15 << 0)));
770 DECODE_SWITCH (0_144_0
, val
)
774 static const DECODE_DESC insns
[16] = {
775 { I (INSN_DIV
), E (FMT_DIV
) }, { I (INSN_DIVH
), E (FMT_DIV
) },
776 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
777 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
778 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
779 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
780 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
781 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
782 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
784 unsigned int val
= (((insn
>> 4) & (15 << 0)));
785 idecode
= &insns
[val
];
786 GOTO_EXTRACT (idecode
);
789 idecode
= &insns
[val
];
790 GOTO_EXTRACT (idecode
);
795 idecode
= &insns
[val
];
796 GOTO_EXTRACT (idecode
);
800 CASE (0, 240) : /* fall through */
801 CASE (0, 241) : /* fall through */
802 CASE (0, 242) : /* fall through */
803 CASE (0, 243) : /* fall through */
804 CASE (0, 244) : /* fall through */
805 CASE (0, 245) : /* fall through */
806 CASE (0, 246) : /* fall through */
807 CASE (0, 247) : /* fall through */
808 CASE (0, 248) : /* fall through */
809 CASE (0, 249) : /* fall through */
810 CASE (0, 250) : /* fall through */
811 CASE (0, 251) : /* fall through */
812 CASE (0, 252) : /* fall through */
813 CASE (0, 253) : /* fall through */
814 CASE (0, 254) : /* fall through */
817 static const DECODE_DESC insns
[16] = {
818 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
819 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
820 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
821 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
822 { I (INSN_BCL24
), E (FMT_BCL24
) }, { I (INSN_BNCL24
), E (FMT_BCL24
) },
823 { I (INSN_X_INVALID
), E (FMT_EMPTY
) }, { I (INSN_X_INVALID
), E (FMT_EMPTY
) },
824 { I (INSN_BC24
), E (FMT_BC24
) }, { I (INSN_BNC24
), E (FMT_BC24
) },
825 { I (INSN_BL24
), E (FMT_BL24
) }, { I (INSN_BRA24
), E (FMT_BRA24
) },
827 unsigned int val
= (((insn
>> 8) & (15 << 0)));
828 idecode
= &insns
[val
];
829 GOTO_EXTRACT (idecode
);
832 idecode
= &insns
[val
];
833 GOTO_EXTRACT (idecode
);
841 /* The instruction has been decoded, now extract the fields. */
846 switch (idecode
->ifmt
)
852 CGEN_INSN_INT insn
= entire_insn
;
853 #define FLD(f) abuf->fields.fmt_add.f
854 EXTRACT_FMT_ADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
858 /* Record the fields for the semantic handler. */
859 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
860 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
861 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_add", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
863 #if WITH_PROFILE_MODEL_P
864 /* Record the fields for profiling. */
865 if (PROFILE_MODEL_P (current_cpu
))
876 CASE (ex
, FMT_ADD3
) :
878 CGEN_INSN_INT insn
= entire_insn
;
879 #define FLD(f) abuf->fields.fmt_add3.f
880 EXTRACT_FMT_ADD3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
882 EXTRACT_FMT_ADD3_CODE
884 /* Record the fields for the semantic handler. */
885 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
886 FLD (f_simm16
) = f_simm16
;
887 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
888 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_add3", "sr 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
890 #if WITH_PROFILE_MODEL_P
891 /* Record the fields for profiling. */
892 if (PROFILE_MODEL_P (current_cpu
))
902 CASE (ex
, FMT_AND3
) :
904 CGEN_INSN_INT insn
= entire_insn
;
905 #define FLD(f) abuf->fields.fmt_and3.f
906 EXTRACT_FMT_AND3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
908 EXTRACT_FMT_AND3_CODE
910 /* Record the fields for the semantic handler. */
911 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
912 FLD (f_uimm16
) = f_uimm16
;
913 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
914 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_and3", "sr 0x%x", 'x', f_r2
, "uimm16 0x%x", 'x', f_uimm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
916 #if WITH_PROFILE_MODEL_P
917 /* Record the fields for profiling. */
918 if (PROFILE_MODEL_P (current_cpu
))
930 CGEN_INSN_INT insn
= entire_insn
;
931 #define FLD(f) abuf->fields.fmt_or3.f
932 EXTRACT_FMT_OR3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
936 /* Record the fields for the semantic handler. */
937 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
938 FLD (f_uimm16
) = f_uimm16
;
939 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
940 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_or3", "sr 0x%x", 'x', f_r2
, "ulo16 0x%x", 'x', f_uimm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
942 #if WITH_PROFILE_MODEL_P
943 /* Record the fields for profiling. */
944 if (PROFILE_MODEL_P (current_cpu
))
954 CASE (ex
, FMT_ADDI
) :
956 CGEN_INSN_INT insn
= entire_insn
;
957 #define FLD(f) abuf->fields.fmt_addi.f
958 EXTRACT_FMT_ADDI_VARS
/* f-op1 f-r1 f-simm8 */
960 EXTRACT_FMT_ADDI_CODE
962 /* Record the fields for the semantic handler. */
963 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
964 FLD (f_simm8
) = f_simm8
;
965 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_addi", "dr 0x%x", 'x', f_r1
, "simm8 0x%x", 'x', f_simm8
, (char *) 0));
967 #if WITH_PROFILE_MODEL_P
968 /* Record the fields for profiling. */
969 if (PROFILE_MODEL_P (current_cpu
))
979 CASE (ex
, FMT_ADDV
) :
981 CGEN_INSN_INT insn
= entire_insn
;
982 #define FLD(f) abuf->fields.fmt_addv.f
983 EXTRACT_FMT_ADDV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
985 EXTRACT_FMT_ADDV_CODE
987 /* Record the fields for the semantic handler. */
988 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
989 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
990 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_addv", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
992 #if WITH_PROFILE_MODEL_P
993 /* Record the fields for profiling. */
994 if (PROFILE_MODEL_P (current_cpu
))
1005 CASE (ex
, FMT_ADDV3
) :
1007 CGEN_INSN_INT insn
= entire_insn
;
1008 #define FLD(f) abuf->fields.fmt_addv3.f
1009 EXTRACT_FMT_ADDV3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1011 EXTRACT_FMT_ADDV3_CODE
1013 /* Record the fields for the semantic handler. */
1014 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1015 FLD (f_simm16
) = f_simm16
;
1016 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1017 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_addv3", "sr 0x%x", 'x', f_r2
, "simm16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1019 #if WITH_PROFILE_MODEL_P
1020 /* Record the fields for profiling. */
1021 if (PROFILE_MODEL_P (current_cpu
))
1024 FLD (out_dr
) = f_r1
;
1031 CASE (ex
, FMT_ADDX
) :
1033 CGEN_INSN_INT insn
= entire_insn
;
1034 #define FLD(f) abuf->fields.fmt_addx.f
1035 EXTRACT_FMT_ADDX_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1037 EXTRACT_FMT_ADDX_CODE
1039 /* Record the fields for the semantic handler. */
1040 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1041 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1042 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_addx", "dr 0x%x", 'x', f_r1
, "sr 0x%x", 'x', f_r2
, (char *) 0));
1044 #if WITH_PROFILE_MODEL_P
1045 /* Record the fields for profiling. */
1046 if (PROFILE_MODEL_P (current_cpu
))
1050 FLD (out_dr
) = f_r1
;
1057 CASE (ex
, FMT_BC8
) :
1059 CGEN_INSN_INT insn
= entire_insn
;
1060 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
1061 EXTRACT_FMT_BC8_VARS
/* f-op1 f-r1 f-disp8 */
1063 EXTRACT_FMT_BC8_CODE
1065 /* Record the fields for the semantic handler. */
1066 FLD (f_disp8
) = f_disp8
;
1067 SEM_BRANCH_INIT_EXTRACT (abuf
);
1068 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bc8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1070 #if WITH_PROFILE_MODEL_P
1071 /* Record the fields for profiling. */
1072 if (PROFILE_MODEL_P (current_cpu
))
1080 CASE (ex
, FMT_BC24
) :
1082 CGEN_INSN_INT insn
= entire_insn
;
1083 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
1084 EXTRACT_FMT_BC24_VARS
/* f-op1 f-r1 f-disp24 */
1086 EXTRACT_FMT_BC24_CODE
1088 /* Record the fields for the semantic handler. */
1089 FLD (f_disp24
) = f_disp24
;
1090 SEM_BRANCH_INIT_EXTRACT (abuf
);
1091 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bc24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1093 #if WITH_PROFILE_MODEL_P
1094 /* Record the fields for profiling. */
1095 if (PROFILE_MODEL_P (current_cpu
))
1103 CASE (ex
, FMT_BEQ
) :
1105 CGEN_INSN_INT insn
= entire_insn
;
1106 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
1107 EXTRACT_FMT_BEQ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1109 EXTRACT_FMT_BEQ_CODE
1111 /* Record the fields for the semantic handler. */
1112 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1113 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1114 FLD (f_disp16
) = f_disp16
;
1115 SEM_BRANCH_INIT_EXTRACT (abuf
);
1116 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_beq", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, (char *) 0));
1118 #if WITH_PROFILE_MODEL_P
1119 /* Record the fields for profiling. */
1120 if (PROFILE_MODEL_P (current_cpu
))
1122 FLD (in_src1
) = f_r1
;
1123 FLD (in_src2
) = f_r2
;
1130 CASE (ex
, FMT_BEQZ
) :
1132 CGEN_INSN_INT insn
= entire_insn
;
1133 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
1134 EXTRACT_FMT_BEQZ_VARS
/* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1136 EXTRACT_FMT_BEQZ_CODE
1138 /* Record the fields for the semantic handler. */
1139 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1140 FLD (f_disp16
) = f_disp16
;
1141 SEM_BRANCH_INIT_EXTRACT (abuf
);
1142 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_beqz", "src2 0x%x", 'x', f_r2
, "disp16 0x%x", 'x', f_disp16
, (char *) 0));
1144 #if WITH_PROFILE_MODEL_P
1145 /* Record the fields for profiling. */
1146 if (PROFILE_MODEL_P (current_cpu
))
1148 FLD (in_src2
) = f_r2
;
1155 CASE (ex
, FMT_BL8
) :
1157 CGEN_INSN_INT insn
= entire_insn
;
1158 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
1159 EXTRACT_FMT_BL8_VARS
/* f-op1 f-r1 f-disp8 */
1161 EXTRACT_FMT_BL8_CODE
1163 /* Record the fields for the semantic handler. */
1164 FLD (f_disp8
) = f_disp8
;
1165 SEM_BRANCH_INIT_EXTRACT (abuf
);
1166 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1168 #if WITH_PROFILE_MODEL_P
1169 /* Record the fields for profiling. */
1170 if (PROFILE_MODEL_P (current_cpu
))
1172 FLD (out_h_gr_14
) = 14;
1179 CASE (ex
, FMT_BL24
) :
1181 CGEN_INSN_INT insn
= entire_insn
;
1182 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1183 EXTRACT_FMT_BL24_VARS
/* f-op1 f-r1 f-disp24 */
1185 EXTRACT_FMT_BL24_CODE
1187 /* Record the fields for the semantic handler. */
1188 FLD (f_disp24
) = f_disp24
;
1189 SEM_BRANCH_INIT_EXTRACT (abuf
);
1190 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1192 #if WITH_PROFILE_MODEL_P
1193 /* Record the fields for profiling. */
1194 if (PROFILE_MODEL_P (current_cpu
))
1196 FLD (out_h_gr_14
) = 14;
1203 CASE (ex
, FMT_BCL8
) :
1205 CGEN_INSN_INT insn
= entire_insn
;
1206 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
1207 EXTRACT_FMT_BCL8_VARS
/* f-op1 f-r1 f-disp8 */
1209 EXTRACT_FMT_BCL8_CODE
1211 /* Record the fields for the semantic handler. */
1212 FLD (f_disp8
) = f_disp8
;
1213 SEM_BRANCH_INIT_EXTRACT (abuf
);
1214 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1216 #if WITH_PROFILE_MODEL_P
1217 /* Record the fields for profiling. */
1218 if (PROFILE_MODEL_P (current_cpu
))
1220 FLD (out_h_gr_14
) = 14;
1227 CASE (ex
, FMT_BCL24
) :
1229 CGEN_INSN_INT insn
= entire_insn
;
1230 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
1231 EXTRACT_FMT_BCL24_VARS
/* f-op1 f-r1 f-disp24 */
1233 EXTRACT_FMT_BCL24_CODE
1235 /* Record the fields for the semantic handler. */
1236 FLD (f_disp24
) = f_disp24
;
1237 SEM_BRANCH_INIT_EXTRACT (abuf
);
1238 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1240 #if WITH_PROFILE_MODEL_P
1241 /* Record the fields for profiling. */
1242 if (PROFILE_MODEL_P (current_cpu
))
1244 FLD (out_h_gr_14
) = 14;
1251 CASE (ex
, FMT_BRA8
) :
1253 CGEN_INSN_INT insn
= entire_insn
;
1254 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1255 EXTRACT_FMT_BRA8_VARS
/* f-op1 f-r1 f-disp8 */
1257 EXTRACT_FMT_BRA8_CODE
1259 /* Record the fields for the semantic handler. */
1260 FLD (f_disp8
) = f_disp8
;
1261 SEM_BRANCH_INIT_EXTRACT (abuf
);
1262 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bra8", "disp8 0x%x", 'x', f_disp8
, (char *) 0));
1264 #if WITH_PROFILE_MODEL_P
1265 /* Record the fields for profiling. */
1266 if (PROFILE_MODEL_P (current_cpu
))
1274 CASE (ex
, FMT_BRA24
) :
1276 CGEN_INSN_INT insn
= entire_insn
;
1277 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1278 EXTRACT_FMT_BRA24_VARS
/* f-op1 f-r1 f-disp24 */
1280 EXTRACT_FMT_BRA24_CODE
1282 /* Record the fields for the semantic handler. */
1283 FLD (f_disp24
) = f_disp24
;
1284 SEM_BRANCH_INIT_EXTRACT (abuf
);
1285 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_bra24", "disp24 0x%x", 'x', f_disp24
, (char *) 0));
1287 #if WITH_PROFILE_MODEL_P
1288 /* Record the fields for profiling. */
1289 if (PROFILE_MODEL_P (current_cpu
))
1297 CASE (ex
, FMT_CMP
) :
1299 CGEN_INSN_INT insn
= entire_insn
;
1300 #define FLD(f) abuf->fields.fmt_cmp.f
1301 EXTRACT_FMT_CMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1303 EXTRACT_FMT_CMP_CODE
1305 /* Record the fields for the semantic handler. */
1306 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1307 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1308 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_cmp", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1310 #if WITH_PROFILE_MODEL_P
1311 /* Record the fields for profiling. */
1312 if (PROFILE_MODEL_P (current_cpu
))
1314 FLD (in_src1
) = f_r1
;
1315 FLD (in_src2
) = f_r2
;
1322 CASE (ex
, FMT_CMPI
) :
1324 CGEN_INSN_INT insn
= entire_insn
;
1325 #define FLD(f) abuf->fields.fmt_cmpi.f
1326 EXTRACT_FMT_CMPI_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1328 EXTRACT_FMT_CMPI_CODE
1330 /* Record the fields for the semantic handler. */
1331 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1332 FLD (f_simm16
) = f_simm16
;
1333 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_cmpi", "src2 0x%x", 'x', f_r2
, "simm16 0x%x", 'x', f_simm16
, (char *) 0));
1335 #if WITH_PROFILE_MODEL_P
1336 /* Record the fields for profiling. */
1337 if (PROFILE_MODEL_P (current_cpu
))
1339 FLD (in_src2
) = f_r2
;
1346 CASE (ex
, FMT_CMPZ
) :
1348 CGEN_INSN_INT insn
= entire_insn
;
1349 #define FLD(f) abuf->fields.fmt_cmpz.f
1350 EXTRACT_FMT_CMPZ_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1352 EXTRACT_FMT_CMPZ_CODE
1354 /* Record the fields for the semantic handler. */
1355 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1356 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_cmpz", "src2 0x%x", 'x', f_r2
, (char *) 0));
1358 #if WITH_PROFILE_MODEL_P
1359 /* Record the fields for profiling. */
1360 if (PROFILE_MODEL_P (current_cpu
))
1362 FLD (in_src2
) = f_r2
;
1369 CASE (ex
, FMT_DIV
) :
1371 CGEN_INSN_INT insn
= entire_insn
;
1372 #define FLD(f) abuf->fields.fmt_div.f
1373 EXTRACT_FMT_DIV_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1375 EXTRACT_FMT_DIV_CODE
1377 /* Record the fields for the semantic handler. */
1378 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1379 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1380 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_div", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1382 #if WITH_PROFILE_MODEL_P
1383 /* Record the fields for profiling. */
1384 if (PROFILE_MODEL_P (current_cpu
))
1388 FLD (out_dr
) = f_r1
;
1397 CGEN_INSN_INT insn
= entire_insn
;
1398 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1399 EXTRACT_FMT_JC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1403 /* Record the fields for the semantic handler. */
1404 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1405 SEM_BRANCH_INIT_EXTRACT (abuf
);
1406 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_jc", "sr 0x%x", 'x', f_r2
, (char *) 0));
1408 #if WITH_PROFILE_MODEL_P
1409 /* Record the fields for profiling. */
1410 if (PROFILE_MODEL_P (current_cpu
))
1421 CGEN_INSN_INT insn
= entire_insn
;
1422 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1423 EXTRACT_FMT_JL_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1427 /* Record the fields for the semantic handler. */
1428 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1429 SEM_BRANCH_INIT_EXTRACT (abuf
);
1430 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_jl", "sr 0x%x", 'x', f_r2
, (char *) 0));
1432 #if WITH_PROFILE_MODEL_P
1433 /* Record the fields for profiling. */
1434 if (PROFILE_MODEL_P (current_cpu
))
1437 FLD (out_h_gr_14
) = 14;
1444 CASE (ex
, FMT_JMP
) :
1446 CGEN_INSN_INT insn
= entire_insn
;
1447 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1448 EXTRACT_FMT_JMP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1450 EXTRACT_FMT_JMP_CODE
1452 /* Record the fields for the semantic handler. */
1453 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1454 SEM_BRANCH_INIT_EXTRACT (abuf
);
1455 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_jmp", "sr 0x%x", 'x', f_r2
, (char *) 0));
1457 #if WITH_PROFILE_MODEL_P
1458 /* Record the fields for profiling. */
1459 if (PROFILE_MODEL_P (current_cpu
))
1470 CGEN_INSN_INT insn
= entire_insn
;
1471 #define FLD(f) abuf->fields.fmt_ld.f
1472 EXTRACT_FMT_LD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1476 /* Record the fields for the semantic handler. */
1477 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1478 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1479 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ld", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1481 #if WITH_PROFILE_MODEL_P
1482 /* Record the fields for profiling. */
1483 if (PROFILE_MODEL_P (current_cpu
))
1486 FLD (out_dr
) = f_r1
;
1493 CASE (ex
, FMT_LD_D
) :
1495 CGEN_INSN_INT insn
= entire_insn
;
1496 #define FLD(f) abuf->fields.fmt_ld_d.f
1497 EXTRACT_FMT_LD_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1499 EXTRACT_FMT_LD_D_CODE
1501 /* Record the fields for the semantic handler. */
1502 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1503 FLD (f_simm16
) = f_simm16
;
1504 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1505 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ld_d", "sr 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1507 #if WITH_PROFILE_MODEL_P
1508 /* Record the fields for profiling. */
1509 if (PROFILE_MODEL_P (current_cpu
))
1512 FLD (out_dr
) = f_r1
;
1519 CASE (ex
, FMT_LDB
) :
1521 CGEN_INSN_INT insn
= entire_insn
;
1522 #define FLD(f) abuf->fields.fmt_ldb.f
1523 EXTRACT_FMT_LDB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1525 EXTRACT_FMT_LDB_CODE
1527 /* Record the fields for the semantic handler. */
1528 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1529 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1530 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldb", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1532 #if WITH_PROFILE_MODEL_P
1533 /* Record the fields for profiling. */
1534 if (PROFILE_MODEL_P (current_cpu
))
1537 FLD (out_dr
) = f_r1
;
1544 CASE (ex
, FMT_LDB_D
) :
1546 CGEN_INSN_INT insn
= entire_insn
;
1547 #define FLD(f) abuf->fields.fmt_ldb_d.f
1548 EXTRACT_FMT_LDB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1550 EXTRACT_FMT_LDB_D_CODE
1552 /* Record the fields for the semantic handler. */
1553 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1554 FLD (f_simm16
) = f_simm16
;
1555 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1556 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldb_d", "sr 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1558 #if WITH_PROFILE_MODEL_P
1559 /* Record the fields for profiling. */
1560 if (PROFILE_MODEL_P (current_cpu
))
1563 FLD (out_dr
) = f_r1
;
1570 CASE (ex
, FMT_LDH
) :
1572 CGEN_INSN_INT insn
= entire_insn
;
1573 #define FLD(f) abuf->fields.fmt_ldh.f
1574 EXTRACT_FMT_LDH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1576 EXTRACT_FMT_LDH_CODE
1578 /* Record the fields for the semantic handler. */
1579 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1580 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1581 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldh", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1583 #if WITH_PROFILE_MODEL_P
1584 /* Record the fields for profiling. */
1585 if (PROFILE_MODEL_P (current_cpu
))
1588 FLD (out_dr
) = f_r1
;
1595 CASE (ex
, FMT_LDH_D
) :
1597 CGEN_INSN_INT insn
= entire_insn
;
1598 #define FLD(f) abuf->fields.fmt_ldh_d.f
1599 EXTRACT_FMT_LDH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1601 EXTRACT_FMT_LDH_D_CODE
1603 /* Record the fields for the semantic handler. */
1604 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1605 FLD (f_simm16
) = f_simm16
;
1606 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1607 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldh_d", "sr 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1609 #if WITH_PROFILE_MODEL_P
1610 /* Record the fields for profiling. */
1611 if (PROFILE_MODEL_P (current_cpu
))
1614 FLD (out_dr
) = f_r1
;
1621 CASE (ex
, FMT_LD_PLUS
) :
1623 CGEN_INSN_INT insn
= entire_insn
;
1624 #define FLD(f) abuf->fields.fmt_ld_plus.f
1625 EXTRACT_FMT_LD_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1627 EXTRACT_FMT_LD_PLUS_CODE
1629 /* Record the fields for the semantic handler. */
1630 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1631 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1632 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ld_plus", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1634 #if WITH_PROFILE_MODEL_P
1635 /* Record the fields for profiling. */
1636 if (PROFILE_MODEL_P (current_cpu
))
1639 FLD (out_dr
) = f_r1
;
1640 FLD (out_sr
) = f_r2
;
1647 CASE (ex
, FMT_LD24
) :
1649 CGEN_INSN_INT insn
= entire_insn
;
1650 #define FLD(f) abuf->fields.fmt_ld24.f
1651 EXTRACT_FMT_LD24_VARS
/* f-op1 f-r1 f-uimm24 */
1653 EXTRACT_FMT_LD24_CODE
1655 /* Record the fields for the semantic handler. */
1656 FLD (f_uimm24
) = f_uimm24
;
1657 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1658 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1660 #if WITH_PROFILE_MODEL_P
1661 /* Record the fields for profiling. */
1662 if (PROFILE_MODEL_P (current_cpu
))
1664 FLD (out_dr
) = f_r1
;
1671 CASE (ex
, FMT_LDI8
) :
1673 CGEN_INSN_INT insn
= entire_insn
;
1674 #define FLD(f) abuf->fields.fmt_ldi8.f
1675 EXTRACT_FMT_LDI8_VARS
/* f-op1 f-r1 f-simm8 */
1677 EXTRACT_FMT_LDI8_CODE
1679 /* Record the fields for the semantic handler. */
1680 FLD (f_simm8
) = f_simm8
;
1681 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1682 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1684 #if WITH_PROFILE_MODEL_P
1685 /* Record the fields for profiling. */
1686 if (PROFILE_MODEL_P (current_cpu
))
1688 FLD (out_dr
) = f_r1
;
1695 CASE (ex
, FMT_LDI16
) :
1697 CGEN_INSN_INT insn
= entire_insn
;
1698 #define FLD(f) abuf->fields.fmt_ldi16.f
1699 EXTRACT_FMT_LDI16_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1701 EXTRACT_FMT_LDI16_CODE
1703 /* Record the fields for the semantic handler. */
1704 FLD (f_simm16
) = f_simm16
;
1705 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1706 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1708 #if WITH_PROFILE_MODEL_P
1709 /* Record the fields for profiling. */
1710 if (PROFILE_MODEL_P (current_cpu
))
1712 FLD (out_dr
) = f_r1
;
1719 CASE (ex
, FMT_LOCK
) :
1721 CGEN_INSN_INT insn
= entire_insn
;
1722 #define FLD(f) abuf->fields.fmt_lock.f
1723 EXTRACT_FMT_LOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1725 EXTRACT_FMT_LOCK_CODE
1727 /* Record the fields for the semantic handler. */
1728 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1729 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1730 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_lock", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1732 #if WITH_PROFILE_MODEL_P
1733 /* Record the fields for profiling. */
1734 if (PROFILE_MODEL_P (current_cpu
))
1737 FLD (out_dr
) = f_r1
;
1744 CASE (ex
, FMT_MACHI_A
) :
1746 CGEN_INSN_INT insn
= entire_insn
;
1747 #define FLD(f) abuf->fields.fmt_machi_a.f
1748 EXTRACT_FMT_MACHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
1750 EXTRACT_FMT_MACHI_A_CODE
1752 /* Record the fields for the semantic handler. */
1753 FLD (f_acc
) = f_acc
;
1754 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1755 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1756 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_machi_a", "acc 0x%x", 'x', f_acc
, "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
1758 #if WITH_PROFILE_MODEL_P
1759 /* Record the fields for profiling. */
1760 if (PROFILE_MODEL_P (current_cpu
))
1762 FLD (in_src1
) = f_r1
;
1763 FLD (in_src2
) = f_r2
;
1770 CASE (ex
, FMT_MULHI_A
) :
1772 CGEN_INSN_INT insn
= entire_insn
;
1773 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1774 EXTRACT_FMT_MULHI_A_VARS
/* f-op1 f-r1 f-acc f-op23 f-r2 */
1776 EXTRACT_FMT_MULHI_A_CODE
1778 /* Record the fields for the semantic handler. */
1779 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1780 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
1781 FLD (f_acc
) = f_acc
;
1782 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mulhi_a", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, "acc 0x%x", 'x', f_acc
, (char *) 0));
1784 #if WITH_PROFILE_MODEL_P
1785 /* Record the fields for profiling. */
1786 if (PROFILE_MODEL_P (current_cpu
))
1788 FLD (in_src1
) = f_r1
;
1789 FLD (in_src2
) = f_r2
;
1798 CGEN_INSN_INT insn
= entire_insn
;
1799 #define FLD(f) abuf->fields.fmt_mv.f
1800 EXTRACT_FMT_MV_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1804 /* Record the fields for the semantic handler. */
1805 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1806 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1807 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mv", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1809 #if WITH_PROFILE_MODEL_P
1810 /* Record the fields for profiling. */
1811 if (PROFILE_MODEL_P (current_cpu
))
1814 FLD (out_dr
) = f_r1
;
1821 CASE (ex
, FMT_MVFACHI_A
) :
1823 CGEN_INSN_INT insn
= entire_insn
;
1824 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1825 EXTRACT_FMT_MVFACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
1827 EXTRACT_FMT_MVFACHI_A_CODE
1829 /* Record the fields for the semantic handler. */
1830 FLD (f_accs
) = f_accs
;
1831 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1832 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mvfachi_a", "accs 0x%x", 'x', f_accs
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1834 #if WITH_PROFILE_MODEL_P
1835 /* Record the fields for profiling. */
1836 if (PROFILE_MODEL_P (current_cpu
))
1838 FLD (out_dr
) = f_r1
;
1845 CASE (ex
, FMT_MVFC
) :
1847 CGEN_INSN_INT insn
= entire_insn
;
1848 #define FLD(f) abuf->fields.fmt_mvfc.f
1849 EXTRACT_FMT_MVFC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1851 EXTRACT_FMT_MVFC_CODE
1853 /* Record the fields for the semantic handler. */
1855 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1856 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mvfc", "scr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1858 #if WITH_PROFILE_MODEL_P
1859 /* Record the fields for profiling. */
1860 if (PROFILE_MODEL_P (current_cpu
))
1862 FLD (out_dr
) = f_r1
;
1869 CASE (ex
, FMT_MVTACHI_A
) :
1871 CGEN_INSN_INT insn
= entire_insn
;
1872 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1873 EXTRACT_FMT_MVTACHI_A_VARS
/* f-op1 f-r1 f-op2 f-accs f-op3 */
1875 EXTRACT_FMT_MVTACHI_A_CODE
1877 /* Record the fields for the semantic handler. */
1878 FLD (f_accs
) = f_accs
;
1879 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
1880 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mvtachi_a", "accs 0x%x", 'x', f_accs
, "src1 0x%x", 'x', f_r1
, (char *) 0));
1882 #if WITH_PROFILE_MODEL_P
1883 /* Record the fields for profiling. */
1884 if (PROFILE_MODEL_P (current_cpu
))
1886 FLD (in_src1
) = f_r1
;
1893 CASE (ex
, FMT_MVTC
) :
1895 CGEN_INSN_INT insn
= entire_insn
;
1896 #define FLD(f) abuf->fields.fmt_mvtc.f
1897 EXTRACT_FMT_MVTC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1899 EXTRACT_FMT_MVTC_CODE
1901 /* Record the fields for the semantic handler. */
1902 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
1904 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mvtc", "sr 0x%x", 'x', f_r2
, "dcr 0x%x", 'x', f_r1
, (char *) 0));
1906 #if WITH_PROFILE_MODEL_P
1907 /* Record the fields for profiling. */
1908 if (PROFILE_MODEL_P (current_cpu
))
1917 CASE (ex
, FMT_NOP
) :
1919 CGEN_INSN_INT insn
= entire_insn
;
1920 #define FLD(f) abuf->fields.fmt_nop.f
1921 EXTRACT_FMT_NOP_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1923 EXTRACT_FMT_NOP_CODE
1925 /* Record the fields for the semantic handler. */
1926 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_nop", (char *) 0));
1932 CASE (ex
, FMT_RAC_DSI
) :
1934 CGEN_INSN_INT insn
= entire_insn
;
1935 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1936 EXTRACT_FMT_RAC_DSI_VARS
/* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
1938 EXTRACT_FMT_RAC_DSI_CODE
1940 /* Record the fields for the semantic handler. */
1941 FLD (f_accs
) = f_accs
;
1942 FLD (f_imm1
) = f_imm1
;
1943 FLD (f_accd
) = f_accd
;
1944 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_rac_dsi", "accs 0x%x", 'x', f_accs
, "imm1 0x%x", 'x', f_imm1
, "accd 0x%x", 'x', f_accd
, (char *) 0));
1950 CASE (ex
, FMT_RTE
) :
1952 CGEN_INSN_INT insn
= entire_insn
;
1953 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1954 EXTRACT_FMT_RTE_VARS
/* f-op1 f-r1 f-op2 f-r2 */
1956 EXTRACT_FMT_RTE_CODE
1958 /* Record the fields for the semantic handler. */
1959 SEM_BRANCH_INIT_EXTRACT (abuf
);
1960 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_rte", (char *) 0));
1962 #if WITH_PROFILE_MODEL_P
1963 /* Record the fields for profiling. */
1964 if (PROFILE_MODEL_P (current_cpu
))
1972 CASE (ex
, FMT_SETH
) :
1974 CGEN_INSN_INT insn
= entire_insn
;
1975 #define FLD(f) abuf->fields.fmt_seth.f
1976 EXTRACT_FMT_SETH_VARS
/* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1978 EXTRACT_FMT_SETH_CODE
1980 /* Record the fields for the semantic handler. */
1981 FLD (f_hi16
) = f_hi16
;
1982 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
1983 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_seth", "hi16 0x%x", 'x', f_hi16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
1985 #if WITH_PROFILE_MODEL_P
1986 /* Record the fields for profiling. */
1987 if (PROFILE_MODEL_P (current_cpu
))
1989 FLD (out_dr
) = f_r1
;
1996 CASE (ex
, FMT_SLL3
) :
1998 CGEN_INSN_INT insn
= entire_insn
;
1999 #define FLD(f) abuf->fields.fmt_sll3.f
2000 EXTRACT_FMT_SLL3_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2002 EXTRACT_FMT_SLL3_CODE
2004 /* Record the fields for the semantic handler. */
2005 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2006 FLD (f_simm16
) = f_simm16
;
2007 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2008 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sll3", "sr 0x%x", 'x', f_r2
, "simm16 0x%x", 'x', f_simm16
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2010 #if WITH_PROFILE_MODEL_P
2011 /* Record the fields for profiling. */
2012 if (PROFILE_MODEL_P (current_cpu
))
2015 FLD (out_dr
) = f_r1
;
2022 CASE (ex
, FMT_SLLI
) :
2024 CGEN_INSN_INT insn
= entire_insn
;
2025 #define FLD(f) abuf->fields.fmt_slli.f
2026 EXTRACT_FMT_SLLI_VARS
/* f-op1 f-r1 f-shift-op2 f-uimm5 */
2028 EXTRACT_FMT_SLLI_CODE
2030 /* Record the fields for the semantic handler. */
2031 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2032 FLD (f_uimm5
) = f_uimm5
;
2033 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_slli", "dr 0x%x", 'x', f_r1
, "uimm5 0x%x", 'x', f_uimm5
, (char *) 0));
2035 #if WITH_PROFILE_MODEL_P
2036 /* Record the fields for profiling. */
2037 if (PROFILE_MODEL_P (current_cpu
))
2040 FLD (out_dr
) = f_r1
;
2049 CGEN_INSN_INT insn
= entire_insn
;
2050 #define FLD(f) abuf->fields.fmt_st.f
2051 EXTRACT_FMT_ST_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2055 /* Record the fields for the semantic handler. */
2056 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2057 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2058 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_st", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2060 #if WITH_PROFILE_MODEL_P
2061 /* Record the fields for profiling. */
2062 if (PROFILE_MODEL_P (current_cpu
))
2064 FLD (in_src2
) = f_r2
;
2065 FLD (in_src1
) = f_r1
;
2072 CASE (ex
, FMT_ST_D
) :
2074 CGEN_INSN_INT insn
= entire_insn
;
2075 #define FLD(f) abuf->fields.fmt_st_d.f
2076 EXTRACT_FMT_ST_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2078 EXTRACT_FMT_ST_D_CODE
2080 /* Record the fields for the semantic handler. */
2081 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2082 FLD (f_simm16
) = f_simm16
;
2083 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2084 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_st_d", "src2 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2086 #if WITH_PROFILE_MODEL_P
2087 /* Record the fields for profiling. */
2088 if (PROFILE_MODEL_P (current_cpu
))
2090 FLD (in_src2
) = f_r2
;
2091 FLD (in_src1
) = f_r1
;
2098 CASE (ex
, FMT_STB
) :
2100 CGEN_INSN_INT insn
= entire_insn
;
2101 #define FLD(f) abuf->fields.fmt_stb.f
2102 EXTRACT_FMT_STB_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2104 EXTRACT_FMT_STB_CODE
2106 /* Record the fields for the semantic handler. */
2107 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2108 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2109 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_stb", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2111 #if WITH_PROFILE_MODEL_P
2112 /* Record the fields for profiling. */
2113 if (PROFILE_MODEL_P (current_cpu
))
2115 FLD (in_src2
) = f_r2
;
2116 FLD (in_src1
) = f_r1
;
2123 CASE (ex
, FMT_STB_D
) :
2125 CGEN_INSN_INT insn
= entire_insn
;
2126 #define FLD(f) abuf->fields.fmt_stb_d.f
2127 EXTRACT_FMT_STB_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2129 EXTRACT_FMT_STB_D_CODE
2131 /* Record the fields for the semantic handler. */
2132 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2133 FLD (f_simm16
) = f_simm16
;
2134 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2135 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_stb_d", "src2 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2137 #if WITH_PROFILE_MODEL_P
2138 /* Record the fields for profiling. */
2139 if (PROFILE_MODEL_P (current_cpu
))
2141 FLD (in_src2
) = f_r2
;
2142 FLD (in_src1
) = f_r1
;
2149 CASE (ex
, FMT_STH
) :
2151 CGEN_INSN_INT insn
= entire_insn
;
2152 #define FLD(f) abuf->fields.fmt_sth.f
2153 EXTRACT_FMT_STH_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2155 EXTRACT_FMT_STH_CODE
2157 /* Record the fields for the semantic handler. */
2158 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2159 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2160 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sth", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2162 #if WITH_PROFILE_MODEL_P
2163 /* Record the fields for profiling. */
2164 if (PROFILE_MODEL_P (current_cpu
))
2166 FLD (in_src2
) = f_r2
;
2167 FLD (in_src1
) = f_r1
;
2174 CASE (ex
, FMT_STH_D
) :
2176 CGEN_INSN_INT insn
= entire_insn
;
2177 #define FLD(f) abuf->fields.fmt_sth_d.f
2178 EXTRACT_FMT_STH_D_VARS
/* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2180 EXTRACT_FMT_STH_D_CODE
2182 /* Record the fields for the semantic handler. */
2183 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2184 FLD (f_simm16
) = f_simm16
;
2185 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2186 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sth_d", "src2 0x%x", 'x', f_r2
, "slo16 0x%x", 'x', f_simm16
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2188 #if WITH_PROFILE_MODEL_P
2189 /* Record the fields for profiling. */
2190 if (PROFILE_MODEL_P (current_cpu
))
2192 FLD (in_src2
) = f_r2
;
2193 FLD (in_src1
) = f_r1
;
2200 CASE (ex
, FMT_ST_PLUS
) :
2202 CGEN_INSN_INT insn
= entire_insn
;
2203 #define FLD(f) abuf->fields.fmt_st_plus.f
2204 EXTRACT_FMT_ST_PLUS_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2206 EXTRACT_FMT_ST_PLUS_CODE
2208 /* Record the fields for the semantic handler. */
2209 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2210 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2211 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_st_plus", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2213 #if WITH_PROFILE_MODEL_P
2214 /* Record the fields for profiling. */
2215 if (PROFILE_MODEL_P (current_cpu
))
2217 FLD (in_src2
) = f_r2
;
2218 FLD (in_src1
) = f_r1
;
2219 FLD (out_src2
) = f_r2
;
2226 CASE (ex
, FMT_TRAP
) :
2228 CGEN_INSN_INT insn
= entire_insn
;
2229 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2230 EXTRACT_FMT_TRAP_VARS
/* f-op1 f-r1 f-op2 f-uimm4 */
2232 EXTRACT_FMT_TRAP_CODE
2234 /* Record the fields for the semantic handler. */
2235 FLD (f_uimm4
) = f_uimm4
;
2236 SEM_BRANCH_INIT_EXTRACT (abuf
);
2237 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4
, (char *) 0));
2239 #if WITH_PROFILE_MODEL_P
2240 /* Record the fields for profiling. */
2241 if (PROFILE_MODEL_P (current_cpu
))
2249 CASE (ex
, FMT_UNLOCK
) :
2251 CGEN_INSN_INT insn
= entire_insn
;
2252 #define FLD(f) abuf->fields.fmt_unlock.f
2253 EXTRACT_FMT_UNLOCK_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2255 EXTRACT_FMT_UNLOCK_CODE
2257 /* Record the fields for the semantic handler. */
2258 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2259 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2260 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_unlock", "src2 0x%x", 'x', f_r2
, "src1 0x%x", 'x', f_r1
, (char *) 0));
2262 #if WITH_PROFILE_MODEL_P
2263 /* Record the fields for profiling. */
2264 if (PROFILE_MODEL_P (current_cpu
))
2266 FLD (in_src2
) = f_r2
;
2267 FLD (in_src1
) = f_r1
;
2274 CASE (ex
, FMT_SATB
) :
2276 CGEN_INSN_INT insn
= entire_insn
;
2277 #define FLD(f) abuf->fields.fmt_satb.f
2278 EXTRACT_FMT_SATB_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2280 EXTRACT_FMT_SATB_CODE
2282 /* Record the fields for the semantic handler. */
2283 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2284 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2285 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_satb", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2287 #if WITH_PROFILE_MODEL_P
2288 /* Record the fields for profiling. */
2289 if (PROFILE_MODEL_P (current_cpu
))
2292 FLD (out_dr
) = f_r1
;
2299 CASE (ex
, FMT_SAT
) :
2301 CGEN_INSN_INT insn
= entire_insn
;
2302 #define FLD(f) abuf->fields.fmt_sat.f
2303 EXTRACT_FMT_SAT_VARS
/* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2305 EXTRACT_FMT_SAT_CODE
2307 /* Record the fields for the semantic handler. */
2308 FLD (i_sr
) = & CPU (h_gr
)[f_r2
];
2309 FLD (i_dr
) = & CPU (h_gr
)[f_r1
];
2310 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sat", "sr 0x%x", 'x', f_r2
, "dr 0x%x", 'x', f_r1
, (char *) 0));
2312 #if WITH_PROFILE_MODEL_P
2313 /* Record the fields for profiling. */
2314 if (PROFILE_MODEL_P (current_cpu
))
2317 FLD (out_dr
) = f_r1
;
2324 CASE (ex
, FMT_SADD
) :
2326 CGEN_INSN_INT insn
= entire_insn
;
2327 #define FLD(f) abuf->fields.fmt_sadd.f
2328 EXTRACT_FMT_SADD_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2330 EXTRACT_FMT_SADD_CODE
2332 /* Record the fields for the semantic handler. */
2333 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sadd", (char *) 0));
2339 CASE (ex
, FMT_MACWU1
) :
2341 CGEN_INSN_INT insn
= entire_insn
;
2342 #define FLD(f) abuf->fields.fmt_macwu1.f
2343 EXTRACT_FMT_MACWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2345 EXTRACT_FMT_MACWU1_CODE
2347 /* Record the fields for the semantic handler. */
2348 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2349 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2350 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_macwu1", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2352 #if WITH_PROFILE_MODEL_P
2353 /* Record the fields for profiling. */
2354 if (PROFILE_MODEL_P (current_cpu
))
2356 FLD (in_src1
) = f_r1
;
2357 FLD (in_src2
) = f_r2
;
2364 CASE (ex
, FMT_MSBLO
) :
2366 CGEN_INSN_INT insn
= entire_insn
;
2367 #define FLD(f) abuf->fields.fmt_msblo.f
2368 EXTRACT_FMT_MSBLO_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2370 EXTRACT_FMT_MSBLO_CODE
2372 /* Record the fields for the semantic handler. */
2373 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2374 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2375 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_msblo", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2377 #if WITH_PROFILE_MODEL_P
2378 /* Record the fields for profiling. */
2379 if (PROFILE_MODEL_P (current_cpu
))
2381 FLD (in_src1
) = f_r1
;
2382 FLD (in_src2
) = f_r2
;
2389 CASE (ex
, FMT_MULWU1
) :
2391 CGEN_INSN_INT insn
= entire_insn
;
2392 #define FLD(f) abuf->fields.fmt_mulwu1.f
2393 EXTRACT_FMT_MULWU1_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2395 EXTRACT_FMT_MULWU1_CODE
2397 /* Record the fields for the semantic handler. */
2398 FLD (i_src1
) = & CPU (h_gr
)[f_r1
];
2399 FLD (i_src2
) = & CPU (h_gr
)[f_r2
];
2400 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_mulwu1", "src1 0x%x", 'x', f_r1
, "src2 0x%x", 'x', f_r2
, (char *) 0));
2402 #if WITH_PROFILE_MODEL_P
2403 /* Record the fields for profiling. */
2404 if (PROFILE_MODEL_P (current_cpu
))
2406 FLD (in_src1
) = f_r1
;
2407 FLD (in_src2
) = f_r2
;
2416 CGEN_INSN_INT insn
= entire_insn
;
2417 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2418 EXTRACT_FMT_SC_VARS
/* f-op1 f-r1 f-op2 f-r2 */
2422 /* Record the fields for the semantic handler. */
2423 SEM_BRANCH_INIT_EXTRACT (abuf
);
2424 TRACE_EXTRACT (current_cpu
, (current_cpu
, pc
, "fmt_sc", (char *) 0));
2430 CASE (ex
, FMT_EMPTY
) :
2436 return idecode
->idesc
;
projects / binutils-gdb.git / blob