sim/m32r/decodex.h

   1 /* Decode header for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef M32RXF_DECODE_H
  26 #define M32RXF_DECODE_H
  27
  28 /* Run-time computed instruction descriptor.  */
  29
  30 struct idesc {
  31   /* Pointer to parallel handler if serial insn.
  32      Pointer to writeback handler if parallel insn.  */
  33   struct idesc *par_idesc;
  34
  35 #if WITH_SEM_SWITCH_FULL
  36 #ifdef __GNUC__
  37   void *sem_full_lab;
  38 #endif
  39 #else
  40   SEMANTIC_FN *sem_full;
  41 #endif
  42
  43 #if WITH_SEM_SWITCH_FAST
  44 #ifdef __GNUC__
  45   void *sem_fast_lab;
  46 #endif
  47 #else
  48   SEMANTIC_FN *sem_fast;
  49 #endif
  50
  51   /* Instruction number (index in IDESC table, profile table).
  52      Also used to switch on in non-gcc semantic switches.  */
  53   int num;
  54
  55   /* opcode table data */
  56   const CGEN_INSN *opcode;
  57
  58   /* profiling/modelling support */
  59   const INSN_TIMING *timing;
  60 };
  61
  62 extern const IDESC *m32rxf_decode (SIM_CPU *, IADDR,
  63                                   CGEN_INSN_INT, CGEN_INSN_INT,
  64                                   ARGBUF *);
  65
  66 /* Enum declaration for instructions in cpu family m32rxf.  */
  67 typedef enum m32rxf_insn_type {
  68   M32RXF_INSN_X_INVALID, M32RXF_INSN_X_AFTER, M32RXF_INSN_X_BEFORE, M32RXF_INSN_X_CTI_CHAIN
  69  , M32RXF_INSN_X_CHAIN, M32RXF_INSN_X_BEGIN, M32RXF_INSN_ADD, M32RXF_INSN_ADD3
  70  , M32RXF_INSN_AND, M32RXF_INSN_AND3, M32RXF_INSN_OR, M32RXF_INSN_OR3
  71  , M32RXF_INSN_XOR, M32RXF_INSN_XOR3, M32RXF_INSN_ADDI, M32RXF_INSN_ADDV
  72  , M32RXF_INSN_ADDV3, M32RXF_INSN_ADDX, M32RXF_INSN_BC8, M32RXF_INSN_BC24
  73  , M32RXF_INSN_BEQ, M32RXF_INSN_BEQZ, M32RXF_INSN_BGEZ, M32RXF_INSN_BGTZ
  74  , M32RXF_INSN_BLEZ, M32RXF_INSN_BLTZ, M32RXF_INSN_BNEZ, M32RXF_INSN_BL8
  75  , M32RXF_INSN_BL24
  76 /* start-sanitize-m32rx */
  77  , M32RXF_INSN_BCL8
  78 /* end-sanitize-m32rx */
  79 /* start-sanitize-m32rx */
  80  , M32RXF_INSN_BCL24
  81 /* end-sanitize-m32rx */
  82  , M32RXF_INSN_BNC8, M32RXF_INSN_BNC24, M32RXF_INSN_BNE, M32RXF_INSN_BRA8
  83  , M32RXF_INSN_BRA24
  84 /* start-sanitize-m32rx */
  85  , M32RXF_INSN_BNCL8
  86 /* end-sanitize-m32rx */
  87 /* start-sanitize-m32rx */
  88  , M32RXF_INSN_BNCL24
  89 /* end-sanitize-m32rx */
  90  , M32RXF_INSN_CMP, M32RXF_INSN_CMPI, M32RXF_INSN_CMPU, M32RXF_INSN_CMPUI
  91 /* start-sanitize-m32rx */
  92  , M32RXF_INSN_CMPEQ
  93 /* end-sanitize-m32rx */
  94 /* start-sanitize-m32rx */
  95  , M32RXF_INSN_CMPZ
  96 /* end-sanitize-m32rx */
  97  , M32RXF_INSN_DIV, M32RXF_INSN_DIVU, M32RXF_INSN_REM, M32RXF_INSN_REMU
  98 /* start-sanitize-m32rx */
  99  , M32RXF_INSN_DIVH
 100 /* end-sanitize-m32rx */
 101 /* start-sanitize-m32rx */
 102  , M32RXF_INSN_JC
 103 /* end-sanitize-m32rx */
 104 /* start-sanitize-m32rx */
 105  , M32RXF_INSN_JNC
 106 /* end-sanitize-m32rx */
 107  , M32RXF_INSN_JL, M32RXF_INSN_JMP, M32RXF_INSN_LD, M32RXF_INSN_LD_D
 108  , M32RXF_INSN_LDB, M32RXF_INSN_LDB_D, M32RXF_INSN_LDH, M32RXF_INSN_LDH_D
 109  , M32RXF_INSN_LDUB, M32RXF_INSN_LDUB_D, M32RXF_INSN_LDUH, M32RXF_INSN_LDUH_D
 110  , M32RXF_INSN_LD_PLUS, M32RXF_INSN_LD24, M32RXF_INSN_LDI8, M32RXF_INSN_LDI16
 111  , M32RXF_INSN_LOCK
 112 /* start-sanitize-m32rx */
 113  , M32RXF_INSN_MACHI_A
 114 /* end-sanitize-m32rx */
 115 /* start-sanitize-m32rx */
 116  , M32RXF_INSN_MACLO_A
 117 /* end-sanitize-m32rx */
 118 /* start-sanitize-m32rx */
 119  , M32RXF_INSN_MACWHI_A
 120 /* end-sanitize-m32rx */
 121 /* start-sanitize-m32rx */
 122  , M32RXF_INSN_MACWLO_A
 123 /* end-sanitize-m32rx */
 124  , M32RXF_INSN_MUL
 125 /* start-sanitize-m32rx */
 126  , M32RXF_INSN_MULHI_A
 127 /* end-sanitize-m32rx */
 128 /* start-sanitize-m32rx */
 129  , M32RXF_INSN_MULLO_A
 130 /* end-sanitize-m32rx */
 131 /* start-sanitize-m32rx */
 132  , M32RXF_INSN_MULWHI_A
 133 /* end-sanitize-m32rx */
 134 /* start-sanitize-m32rx */
 135  , M32RXF_INSN_MULWLO_A
 136 /* end-sanitize-m32rx */
 137  , M32RXF_INSN_MV
 138 /* start-sanitize-m32rx */
 139  , M32RXF_INSN_MVFACHI_A
 140 /* end-sanitize-m32rx */
 141 /* start-sanitize-m32rx */
 142  , M32RXF_INSN_MVFACLO_A
 143 /* end-sanitize-m32rx */
 144 /* start-sanitize-m32rx */
 145  , M32RXF_INSN_MVFACMI_A
 146 /* end-sanitize-m32rx */
 147  , M32RXF_INSN_MVFC
 148 /* start-sanitize-m32rx */
 149  , M32RXF_INSN_MVTACHI_A
 150 /* end-sanitize-m32rx */
 151 /* start-sanitize-m32rx */
 152  , M32RXF_INSN_MVTACLO_A
 153 /* end-sanitize-m32rx */
 154  , M32RXF_INSN_MVTC, M32RXF_INSN_NEG, M32RXF_INSN_NOP, M32RXF_INSN_NOT
 155 /* start-sanitize-m32rx */
 156  , M32RXF_INSN_RAC_DSI
 157 /* end-sanitize-m32rx */
 158 /* start-sanitize-m32rx */
 159  , M32RXF_INSN_RACH_DSI
 160 /* end-sanitize-m32rx */
 161  , M32RXF_INSN_RTE, M32RXF_INSN_SETH, M32RXF_INSN_SLL, M32RXF_INSN_SLL3
 162  , M32RXF_INSN_SLLI, M32RXF_INSN_SRA, M32RXF_INSN_SRA3, M32RXF_INSN_SRAI
 163  , M32RXF_INSN_SRL, M32RXF_INSN_SRL3, M32RXF_INSN_SRLI, M32RXF_INSN_ST
 164  , M32RXF_INSN_ST_D, M32RXF_INSN_STB, M32RXF_INSN_STB_D, M32RXF_INSN_STH
 165  , M32RXF_INSN_STH_D, M32RXF_INSN_ST_PLUS, M32RXF_INSN_ST_MINUS, M32RXF_INSN_SUB
 166  , M32RXF_INSN_SUBV, M32RXF_INSN_SUBX, M32RXF_INSN_TRAP, M32RXF_INSN_UNLOCK
 167 /* start-sanitize-m32rx */
 168  , M32RXF_INSN_SATB
 169 /* end-sanitize-m32rx */
 170 /* start-sanitize-m32rx */
 171  , M32RXF_INSN_SATH
 172 /* end-sanitize-m32rx */
 173 /* start-sanitize-m32rx */
 174  , M32RXF_INSN_SAT
 175 /* end-sanitize-m32rx */
 176 /* start-sanitize-m32rx */
 177  , M32RXF_INSN_PCMPBZ
 178 /* end-sanitize-m32rx */
 179 /* start-sanitize-m32rx */
 180  , M32RXF_INSN_SADD
 181 /* end-sanitize-m32rx */
 182 /* start-sanitize-m32rx */
 183  , M32RXF_INSN_MACWU1
 184 /* end-sanitize-m32rx */
 185 /* start-sanitize-m32rx */
 186  , M32RXF_INSN_MSBLO
 187 /* end-sanitize-m32rx */
 188 /* start-sanitize-m32rx */
 189  , M32RXF_INSN_MULWU1
 190 /* end-sanitize-m32rx */
 191 /* start-sanitize-m32rx */
 192  , M32RXF_INSN_MACLH1
 193 /* end-sanitize-m32rx */
 194 /* start-sanitize-m32rx */
 195  , M32RXF_INSN_SC
 196 /* end-sanitize-m32rx */
 197 /* start-sanitize-m32rx */
 198  , M32RXF_INSN_SNC
 199 /* end-sanitize-m32rx */
 200  , M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND
 201  , M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR
 202  , M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV
 203  , M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8
 204  , M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8
 205 /* start-sanitize-m32rx */
 206  , M32RXF_INSN_PAR_BCL8
 207 /* end-sanitize-m32rx */
 208 /* start-sanitize-m32rx */
 209  , M32RXF_INSN_WRITE_BCL8
 210 /* end-sanitize-m32rx */
 211  , M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8
 212 /* start-sanitize-m32rx */
 213  , M32RXF_INSN_PAR_BNCL8
 214 /* end-sanitize-m32rx */
 215 /* start-sanitize-m32rx */
 216  , M32RXF_INSN_WRITE_BNCL8
 217 /* end-sanitize-m32rx */
 218  , M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU
 219 /* start-sanitize-m32rx */
 220  , M32RXF_INSN_PAR_CMPEQ
 221 /* end-sanitize-m32rx */
 222 /* start-sanitize-m32rx */
 223  , M32RXF_INSN_WRITE_CMPEQ
 224 /* end-sanitize-m32rx */
 225 /* start-sanitize-m32rx */
 226  , M32RXF_INSN_PAR_CMPZ
 227 /* end-sanitize-m32rx */
 228 /* start-sanitize-m32rx */
 229  , M32RXF_INSN_WRITE_CMPZ
 230 /* end-sanitize-m32rx */
 231 /* start-sanitize-m32rx */
 232  , M32RXF_INSN_PAR_JC
 233 /* end-sanitize-m32rx */
 234 /* start-sanitize-m32rx */
 235  , M32RXF_INSN_WRITE_JC
 236 /* end-sanitize-m32rx */
 237 /* start-sanitize-m32rx */
 238  , M32RXF_INSN_PAR_JNC
 239 /* end-sanitize-m32rx */
 240 /* start-sanitize-m32rx */
 241  , M32RXF_INSN_WRITE_JNC
 242 /* end-sanitize-m32rx */
 243  , M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP
 244  , M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB
 245  , M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB
 246  , M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS
 247  , M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK
 248 /* start-sanitize-m32rx */
 249  , M32RXF_INSN_PAR_MACHI_A
 250 /* end-sanitize-m32rx */
 251 /* start-sanitize-m32rx */
 252  , M32RXF_INSN_WRITE_MACHI_A
 253 /* end-sanitize-m32rx */
 254 /* start-sanitize-m32rx */
 255  , M32RXF_INSN_PAR_MACLO_A
 256 /* end-sanitize-m32rx */
 257 /* start-sanitize-m32rx */
 258  , M32RXF_INSN_WRITE_MACLO_A
 259 /* end-sanitize-m32rx */
 260 /* start-sanitize-m32rx */
 261  , M32RXF_INSN_PAR_MACWHI_A
 262 /* end-sanitize-m32rx */
 263 /* start-sanitize-m32rx */
 264  , M32RXF_INSN_WRITE_MACWHI_A
 265 /* end-sanitize-m32rx */
 266 /* start-sanitize-m32rx */
 267  , M32RXF_INSN_PAR_MACWLO_A
 268 /* end-sanitize-m32rx */
 269 /* start-sanitize-m32rx */
 270  , M32RXF_INSN_WRITE_MACWLO_A
 271 /* end-sanitize-m32rx */
 272  , M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL
 273 /* start-sanitize-m32rx */
 274  , M32RXF_INSN_PAR_MULHI_A
 275 /* end-sanitize-m32rx */
 276 /* start-sanitize-m32rx */
 277  , M32RXF_INSN_WRITE_MULHI_A
 278 /* end-sanitize-m32rx */
 279 /* start-sanitize-m32rx */
 280  , M32RXF_INSN_PAR_MULLO_A
 281 /* end-sanitize-m32rx */
 282 /* start-sanitize-m32rx */
 283  , M32RXF_INSN_WRITE_MULLO_A
 284 /* end-sanitize-m32rx */
 285 /* start-sanitize-m32rx */
 286  , M32RXF_INSN_PAR_MULWHI_A
 287 /* end-sanitize-m32rx */
 288 /* start-sanitize-m32rx */
 289  , M32RXF_INSN_WRITE_MULWHI_A
 290 /* end-sanitize-m32rx */
 291 /* start-sanitize-m32rx */
 292  , M32RXF_INSN_PAR_MULWLO_A
 293 /* end-sanitize-m32rx */
 294 /* start-sanitize-m32rx */
 295  , M32RXF_INSN_WRITE_MULWLO_A
 296 /* end-sanitize-m32rx */
 297  , M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV
 298 /* start-sanitize-m32rx */
 299  , M32RXF_INSN_PAR_MVFACHI_A
 300 /* end-sanitize-m32rx */
 301 /* start-sanitize-m32rx */
 302  , M32RXF_INSN_WRITE_MVFACHI_A
 303 /* end-sanitize-m32rx */
 304 /* start-sanitize-m32rx */
 305  , M32RXF_INSN_PAR_MVFACLO_A
 306 /* end-sanitize-m32rx */
 307 /* start-sanitize-m32rx */
 308  , M32RXF_INSN_WRITE_MVFACLO_A
 309 /* end-sanitize-m32rx */
 310 /* start-sanitize-m32rx */
 311  , M32RXF_INSN_PAR_MVFACMI_A
 312 /* end-sanitize-m32rx */
 313 /* start-sanitize-m32rx */
 314  , M32RXF_INSN_WRITE_MVFACMI_A
 315 /* end-sanitize-m32rx */
 316  , M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC
 317 /* start-sanitize-m32rx */
 318  , M32RXF_INSN_PAR_MVTACHI_A
 319 /* end-sanitize-m32rx */
 320 /* start-sanitize-m32rx */
 321  , M32RXF_INSN_WRITE_MVTACHI_A
 322 /* end-sanitize-m32rx */
 323 /* start-sanitize-m32rx */
 324  , M32RXF_INSN_PAR_MVTACLO_A
 325 /* end-sanitize-m32rx */
 326 /* start-sanitize-m32rx */
 327  , M32RXF_INSN_WRITE_MVTACLO_A
 328 /* end-sanitize-m32rx */
 329  , M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG
 330  , M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT
 331 /* start-sanitize-m32rx */
 332  , M32RXF_INSN_PAR_RAC_DSI
 333 /* end-sanitize-m32rx */
 334 /* start-sanitize-m32rx */
 335  , M32RXF_INSN_WRITE_RAC_DSI
 336 /* end-sanitize-m32rx */
 337 /* start-sanitize-m32rx */
 338  , M32RXF_INSN_PAR_RACH_DSI
 339 /* end-sanitize-m32rx */
 340 /* start-sanitize-m32rx */
 341  , M32RXF_INSN_WRITE_RACH_DSI
 342 /* end-sanitize-m32rx */
 343  , M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL
 344  , M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA
 345  , M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL
 346  , M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST
 347  , M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH
 348  , M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS
 349  , M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV
 350  , M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP
 351  , M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK
 352 /* start-sanitize-m32rx */
 353  , M32RXF_INSN_PAR_PCMPBZ
 354 /* end-sanitize-m32rx */
 355 /* start-sanitize-m32rx */
 356  , M32RXF_INSN_WRITE_PCMPBZ
 357 /* end-sanitize-m32rx */
 358 /* start-sanitize-m32rx */
 359  , M32RXF_INSN_PAR_SADD
 360 /* end-sanitize-m32rx */
 361 /* start-sanitize-m32rx */
 362  , M32RXF_INSN_WRITE_SADD
 363 /* end-sanitize-m32rx */
 364 /* start-sanitize-m32rx */
 365  , M32RXF_INSN_PAR_MACWU1
 366 /* end-sanitize-m32rx */
 367 /* start-sanitize-m32rx */
 368  , M32RXF_INSN_WRITE_MACWU1
 369 /* end-sanitize-m32rx */
 370 /* start-sanitize-m32rx */
 371  , M32RXF_INSN_PAR_MSBLO
 372 /* end-sanitize-m32rx */
 373 /* start-sanitize-m32rx */
 374  , M32RXF_INSN_WRITE_MSBLO
 375 /* end-sanitize-m32rx */
 376 /* start-sanitize-m32rx */
 377  , M32RXF_INSN_PAR_MULWU1
 378 /* end-sanitize-m32rx */
 379 /* start-sanitize-m32rx */
 380  , M32RXF_INSN_WRITE_MULWU1
 381 /* end-sanitize-m32rx */
 382 /* start-sanitize-m32rx */
 383  , M32RXF_INSN_PAR_MACLH1
 384 /* end-sanitize-m32rx */
 385 /* start-sanitize-m32rx */
 386  , M32RXF_INSN_WRITE_MACLH1
 387 /* end-sanitize-m32rx */
 388 /* start-sanitize-m32rx */
 389  , M32RXF_INSN_PAR_SC
 390 /* end-sanitize-m32rx */
 391 /* start-sanitize-m32rx */
 392  , M32RXF_INSN_WRITE_SC
 393 /* end-sanitize-m32rx */
 394 /* start-sanitize-m32rx */
 395  , M32RXF_INSN_PAR_SNC
 396 /* end-sanitize-m32rx */
 397 /* start-sanitize-m32rx */
 398  , M32RXF_INSN_WRITE_SNC
 399 /* end-sanitize-m32rx */
 400  , M32RXF_INSN_MAX
 401 } M32RXF_INSN_TYPE;
 402
 403 #if ! WITH_SEM_SWITCH_FULL
 404 #define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,fn);
 405 #else
 406 #define SEMFULL(fn)
 407 #endif
 408
 409 #if ! WITH_SEM_SWITCH_FAST
 410 #define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rxf,_semf_,fn);
 411 #else
 412 #define SEMFAST(fn)
 413 #endif
 414
 415 #define SEM(fn) SEMFULL (fn) SEMFAST (fn)
 416
 417 /* The function version of the before/after handlers is always needed,
 418    so we always want the SEMFULL declaration of them.  */
 419 extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,x_before);
 420 extern SEMANTIC_FN CONCAT3 (m32rxf,_sem_,x_after);
 421
 422 SEM (x_invalid)
 423 SEM (x_after)
 424 SEM (x_before)
 425 SEM (x_cti_chain)
 426 SEM (x_chain)
 427 SEM (x_begin)
 428 SEM (add)
 429 SEM (add3)
 430 SEM (and)
 431 SEM (and3)
 432 SEM (or)
 433 SEM (or3)
 434 SEM (xor)
 435 SEM (xor3)
 436 SEM (addi)
 437 SEM (addv)
 438 SEM (addv3)
 439 SEM (addx)
 440 SEM (bc8)
 441 SEM (bc24)
 442 SEM (beq)
 443 SEM (beqz)
 444 SEM (bgez)
 445 SEM (bgtz)
 446 SEM (blez)
 447 SEM (bltz)
 448 SEM (bnez)
 449 SEM (bl8)
 450 SEM (bl24)
 451 SEM (bcl8)
 452 SEM (bcl24)
 453 SEM (bnc8)
 454 SEM (bnc24)
 455 SEM (bne)
 456 SEM (bra8)
 457 SEM (bra24)
 458 SEM (bncl8)
 459 SEM (bncl24)
 460 SEM (cmp)
 461 SEM (cmpi)
 462 SEM (cmpu)
 463 SEM (cmpui)
 464 SEM (cmpeq)
 465 SEM (cmpz)
 466 SEM (div)
 467 SEM (divu)
 468 SEM (rem)
 469 SEM (remu)
 470 SEM (divh)
 471 SEM (jc)
 472 SEM (jnc)
 473 SEM (jl)
 474 SEM (jmp)
 475 SEM (ld)
 476 SEM (ld_d)
 477 SEM (ldb)
 478 SEM (ldb_d)
 479 SEM (ldh)
 480 SEM (ldh_d)
 481 SEM (ldub)
 482 SEM (ldub_d)
 483 SEM (lduh)
 484 SEM (lduh_d)
 485 SEM (ld_plus)
 486 SEM (ld24)
 487 SEM (ldi8)
 488 SEM (ldi16)
 489 SEM (lock)
 490 SEM (machi_a)
 491 SEM (maclo_a)
 492 SEM (macwhi_a)
 493 SEM (macwlo_a)
 494 SEM (mul)
 495 SEM (mulhi_a)
 496 SEM (mullo_a)
 497 SEM (mulwhi_a)
 498 SEM (mulwlo_a)
 499 SEM (mv)
 500 SEM (mvfachi_a)
 501 SEM (mvfaclo_a)
 502 SEM (mvfacmi_a)
 503 SEM (mvfc)
 504 SEM (mvtachi_a)
 505 SEM (mvtaclo_a)
 506 SEM (mvtc)
 507 SEM (neg)
 508 SEM (nop)
 509 SEM (not)
 510 SEM (rac_dsi)
 511 SEM (rach_dsi)
 512 SEM (rte)
 513 SEM (seth)
 514 SEM (sll)
 515 SEM (sll3)
 516 SEM (slli)
 517 SEM (sra)
 518 SEM (sra3)
 519 SEM (srai)
 520 SEM (srl)
 521 SEM (srl3)
 522 SEM (srli)
 523 SEM (st)
 524 SEM (st_d)
 525 SEM (stb)
 526 SEM (stb_d)
 527 SEM (sth)
 528 SEM (sth_d)
 529 SEM (st_plus)
 530 SEM (st_minus)
 531 SEM (sub)
 532 SEM (subv)
 533 SEM (subx)
 534 SEM (trap)
 535 SEM (unlock)
 536 SEM (satb)
 537 SEM (sath)
 538 SEM (sat)
 539 SEM (pcmpbz)
 540 SEM (sadd)
 541 SEM (macwu1)
 542 SEM (msblo)
 543 SEM (mulwu1)
 544 SEM (maclh1)
 545 SEM (sc)
 546 SEM (snc)
 547
 548 #undef SEMFULL
 549 #undef SEMFAST
 550 #undef SEM
 551
 552 /* Function unit handlers (user written).  */
 553
 554 extern int m32rxf_model_m32rx_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 555 extern int m32rxf_model_m32rx_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
 556 extern int m32rxf_model_m32rx_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
 557 extern int m32rxf_model_m32rx_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 558 extern int m32rxf_model_m32rx_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 559 extern int m32rxf_model_m32rx_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*sr2*/, INT /*dr*/);
 560
 561 /* Profiling before/after handlers (user written) */
 562
 563 extern void m32rxf_model_insn_before (SIM_CPU *, int /*first_p*/);
 564 extern void m32rxf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
 565
 566 #endif /* M32RXF_DECODE_H */