sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996-2023 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef M32R_SIM_H
  21 #define M32R_SIM_H
  22
  23 #include "symcat.h"
  24
  25 /* GDB register numbers.  */
  26 #define PSW_REGNUM      16
  27 #define CBR_REGNUM      17
  28 #define SPI_REGNUM      18
  29 #define SPU_REGNUM      19
  30 #define BPC_REGNUM      20
  31 #define PC_REGNUM       21
  32 #define ACCL_REGNUM     22
  33 #define ACCH_REGNUM     23
  34 #define ACC1L_REGNUM    24
  35 #define ACC1H_REGNUM    25
  36 #define BBPSW_REGNUM    26
  37 #define BBPC_REGNUM     27
  38 #define EVB_REGNUM      28
  39
  40 extern int m32r_decode_gdb_ctrl_regnum (int);
  41
  42 /* Cover macros for hardware accesses.
  43    FIXME: Eventually move to cgen.  */
  44 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  45
  46 #ifndef GET_H_CR
  47 extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  48 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  49
  50 #define GET_H_CR(regno) \
  51   XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
  52 #define SET_H_CR(regno, val) \
  53   XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
  54 #endif
  55
  56 #ifndef  GET_H_PSW
  57 extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
  58 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  59
  60 #define GET_H_PSW() \
  61   XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
  62 #define SET_H_PSW(val) \
  63   XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
  64 #endif
  65
  66 /* FIXME: These prototypes are necessary because the cgen generated
  67    cpu.h, cpux.h and cpu2.h headers do not provide them, and functions
  68    which take or return parameters that are larger than an int must be
  69    prototyed in order for them to work correctly.
  70
  71    The correct solution is to fix the code in cgen/sim.scm to generate
  72    prototypes for each of the functions it generates.  */
  73 extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
  74 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
  75 extern DI   m32r2f_h_accums_get_handler (SIM_CPU *, UINT);
  76 extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI);
  77
  78 #ifndef  GET_H_ACCUM
  79 #define GET_H_ACCUM() \
  80   XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
  81 #define SET_H_ACCUM(val) \
  82   XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
  83 #endif
  84 \f
  85 /* Misc. profile data.  */
  86
  87 typedef struct {
  88   /* nop insn slot filler count */
  89   unsigned int fillnop_count;
  90   /* number of parallel insns */
  91   unsigned int parallel_count;
  92
  93   /* FIXME: generalize this to handle all insn lengths, move to common.  */
  94   /* number of short insns, not including parallel ones */
  95   unsigned int short_count;
  96   /* number of long insns */
  97   unsigned int long_count;
  98
  99   /* Working area for computing cycle counts.  */
 100   unsigned long insn_cycles; /* FIXME: delete */
 101   unsigned long cti_stall;
 102   unsigned long load_stall;
 103   unsigned long biggest_cycles;
 104
 105   /* Bitmask of registers loaded by previous insn.  */
 106   unsigned int load_regs;
 107   /* Bitmask of registers loaded by current insn.  */
 108   unsigned int load_regs_pending;
 109 } M32R_MISC_PROFILE;
 110
 111 /* Initialize the working area.  */
 112 void m32r_init_insn_cycles (SIM_CPU *, int);
 113 /* Update the totals for the insn.  */
 114 void m32r_record_insn_cycles (SIM_CPU *, int);
 115
 116 /* This is invoked by the nop pattern in the .cpu file.  */
 117 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
 118 do { \
 119   if (PROFILE_INSN_P (cpu) \
 120       && (addr & 3) != 0) \
 121     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 122 } while (0)
 123
 124 /* This is invoked by the execute section of mloop{,x}.in.  */
 125 #define PROFILE_COUNT_PARINSNS(cpu) \
 126 do { \
 127   if (PROFILE_INSN_P (cpu)) \
 128     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 129 } while (0)
 130
 131 /* This is invoked by the execute section of mloop{,x}.in.  */
 132 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 133 do { \
 134   if (PROFILE_INSN_P (cpu)) \
 135     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 136 } while (0)
 137
 138 /* This is invoked by the execute section of mloop{,x}.in.  */
 139 #define PROFILE_COUNT_LONGINSNS(cpu) \
 140 do { \
 141   if (PROFILE_INSN_P (cpu)) \
 142     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 143 } while (0)
 144 \f
 145 #define GETTWI GETTSI
 146 #define SETTWI SETTSI
 147 \f
 148 /* Additional execution support.  */
 149
 150 \f
 151 /* Hardware/device support.
 152    ??? Will eventually want to move device stuff to config files.  */
 153
 154 /* Exception, Interrupt, and Trap addresses */
 155 #define EIT_SYSBREAK_ADDR       0x10
 156 #define EIT_RSVD_INSN_ADDR      0x20
 157 #define EIT_ADDR_EXCP_ADDR      0x30
 158 #define EIT_TRAP_BASE_ADDR      0x40
 159 #define EIT_EXTERN_ADDR         0x80
 160 #define EIT_RESET_ADDR          0x7ffffff0
 161 #define EIT_WAKEUP_ADDR         0x7ffffff0
 162
 163 /* Special purpose traps.  */
 164 #define TRAP_SYSCALL    0
 165 #define TRAP_BREAKPOINT 1
 166
 167 /* Handle the trap insn.  */
 168 USI m32r_trap (SIM_CPU *, PCADDR, int);
 169 \f
 170 struct m32r_sim_cpu {
 171   M32R_MISC_PROFILE m32r_misc_profile;
 172 #define CPU_M32R_MISC_PROFILE(cpu) (& M32R_SIM_CPU (cpu)->m32r_misc_profile)
 173
 174   /* CPU specific parts go here.
 175      Note that in files that don't need to access these pieces WANT_CPU_FOO
 176      won't be defined and thus these parts won't appear.  This is ok in the
 177      sense that things work.  It is a source of bugs though.
 178      One has to of course be careful to not take the size of this
 179      struct and no structure members accessed in non-cpu specific files can
 180      go after here.  Oh for a better language.  */
 181 #if defined (WANT_CPU_M32RBF)
 182   M32RBF_CPU_DATA cpu_data;
 183 #endif
 184 #if defined (WANT_CPU_M32RXF)
 185   M32RXF_CPU_DATA cpu_data;
 186 #elif defined (WANT_CPU_M32R2F)
 187   M32R2F_CPU_DATA cpu_data;
 188 #endif
 189 };
 190 #define M32R_SIM_CPU(cpu) ((struct m32r_sim_cpu *) CPU_ARCH_DATA (cpu))
 191
 192 #endif /* M32R_SIM_H */