1 /* m32rx simulator support code
2 Copyright (C) 1997-2021 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
23 #define WANT_CPU m32rxf
24 #define WANT_CPU_M32RXF
30 /* The contents of BUF are in target byte order. */
33 m32rxf_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
35 return m32rbf_fetch_register (current_cpu
, rn
, buf
, len
);
38 /* The contents of BUF are in target byte order. */
41 m32rxf_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
43 return m32rbf_store_register (current_cpu
, rn
, buf
, len
);
46 /* Cover fns to get/set the control registers.
47 FIXME: Duplicated from m32r.c. The issue is structure offsets. */
50 m32rxf_h_cr_get_handler (SIM_CPU
*current_cpu
, UINT cr
)
54 case H_CR_PSW
: /* psw */
55 return (((CPU (h_bpsw
) & 0xc1) << 8)
56 | ((CPU (h_psw
) & 0xc0) << 0)
58 case H_CR_BBPSW
: /* backup backup psw */
59 return CPU (h_bbpsw
) & 0xc1;
60 case H_CR_CBR
: /* condition bit */
62 case H_CR_SPI
: /* interrupt stack pointer */
64 return CPU (h_gr
[H_GR_SP
]);
66 return CPU (h_cr
[H_CR_SPI
]);
67 case H_CR_SPU
: /* user stack pointer */
69 return CPU (h_gr
[H_GR_SP
]);
71 return CPU (h_cr
[H_CR_SPU
]);
72 case H_CR_BPC
: /* backup pc */
73 return CPU (h_cr
[H_CR_BPC
]) & 0xfffffffe;
74 case H_CR_BBPC
: /* backup backup pc */
75 return CPU (h_cr
[H_CR_BBPC
]) & 0xfffffffe;
76 case 4 : /* ??? unspecified, but apparently available */
77 case 5 : /* ??? unspecified, but apparently available */
78 return CPU (h_cr
[cr
]);
85 m32rxf_h_cr_set_handler (SIM_CPU
*current_cpu
, UINT cr
, USI newval
)
89 case H_CR_PSW
: /* psw */
91 int old_sm
= (CPU (h_psw
) & 0x80) != 0;
92 int new_sm
= (newval
& 0x80) != 0;
93 CPU (h_bpsw
) = (newval
>> 8) & 0xff;
94 CPU (h_psw
) = newval
& 0xff;
95 SET_H_COND (newval
& 1);
96 /* When switching stack modes, update the registers. */
101 /* Switching user -> system. */
102 CPU (h_cr
[H_CR_SPU
]) = CPU (h_gr
[H_GR_SP
]);
103 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPI
]);
107 /* Switching system -> user. */
108 CPU (h_cr
[H_CR_SPI
]) = CPU (h_gr
[H_GR_SP
]);
109 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPU
]);
114 case H_CR_BBPSW
: /* backup backup psw */
115 CPU (h_bbpsw
) = newval
& 0xff;
117 case H_CR_CBR
: /* condition bit */
118 SET_H_COND (newval
& 1);
120 case H_CR_SPI
: /* interrupt stack pointer */
122 CPU (h_gr
[H_GR_SP
]) = newval
;
124 CPU (h_cr
[H_CR_SPI
]) = newval
;
126 case H_CR_SPU
: /* user stack pointer */
128 CPU (h_gr
[H_GR_SP
]) = newval
;
130 CPU (h_cr
[H_CR_SPU
]) = newval
;
132 case H_CR_BPC
: /* backup pc */
133 CPU (h_cr
[H_CR_BPC
]) = newval
;
135 case H_CR_BBPC
: /* backup backup pc */
136 CPU (h_cr
[H_CR_BBPC
]) = newval
;
138 case 4 : /* ??? unspecified, but apparently available */
139 case 5 : /* ??? unspecified, but apparently available */
140 CPU (h_cr
[cr
]) = newval
;
148 /* Cover fns to access h-psw. */
151 m32rxf_h_psw_get_handler (SIM_CPU
*current_cpu
)
153 return (CPU (h_psw
) & 0xfe) | (CPU (h_cond
) & 1);
157 m32rxf_h_psw_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
159 CPU (h_psw
) = newval
;
160 CPU (h_cond
) = newval
& 1;
163 /* Cover fns to access h-accum. */
166 m32rxf_h_accum_get_handler (SIM_CPU
*current_cpu
)
168 /* Sign extend the top 8 bits. */
170 r
= ANDDI (CPU (h_accum
), MAKEDI (0xffffff, 0xffffffff));
171 r
= XORDI (r
, MAKEDI (0x800000, 0));
172 r
= SUBDI (r
, MAKEDI (0x800000, 0));
177 m32rxf_h_accum_set_handler (SIM_CPU
*current_cpu
, DI newval
)
179 CPU (h_accum
) = newval
;
182 /* Cover fns to access h-accums. */
185 m32rxf_h_accums_get_handler (SIM_CPU
*current_cpu
, UINT regno
)
187 /* FIXME: Yes, this is just a quick hack. */
192 r
= CPU (h_accums
[1]);
193 /* Sign extend the top 8 bits. */
194 r
= ANDDI (r
, MAKEDI (0xffffff, 0xffffffff));
195 r
= XORDI (r
, MAKEDI (0x800000, 0));
196 r
= SUBDI (r
, MAKEDI (0x800000, 0));
201 m32rxf_h_accums_set_handler (SIM_CPU
*current_cpu
, UINT regno
, DI newval
)
203 /* FIXME: Yes, this is just a quick hack. */
205 CPU (h_accum
) = newval
;
207 CPU (h_accums
[1]) = newval
;
210 #if WITH_PROFILE_MODEL_P
212 /* Initialize cycle counting for an insn.
213 FIRST_P is non-zero if this is the first insn in a set of parallel
217 m32rxf_model_insn_before (SIM_CPU
*cpu
, int first_p
)
219 m32rbf_model_insn_before (cpu
, first_p
);
222 /* Record the cycles computed for an insn.
223 LAST_P is non-zero if this is the last insn in a set of parallel insns,
224 and we update the total cycle count.
225 CYCLES is the cycle count of the insn. */
228 m32rxf_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
230 m32rbf_model_insn_after (cpu
, last_p
, cycles
);
234 check_load_stall (SIM_CPU
*cpu
, int regno
)
236 UINT h_gr
= CPU_M32R_MISC_PROFILE (cpu
)->load_regs
;
239 && (h_gr
& (1 << regno
)) != 0)
241 CPU_M32R_MISC_PROFILE (cpu
)->load_stall
+= 2;
242 if (TRACE_INSN_P (cpu
))
243 cgen_trace_printf (cpu
, " ; Load stall of 2 cycles.");
248 m32rxf_model_m32rx_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
249 int unit_num
, int referenced
,
250 INT sr
, INT sr2
, INT dr
)
252 check_load_stall (cpu
, sr
);
253 check_load_stall (cpu
, sr2
);
254 return idesc
->timing
->units
[unit_num
].done
;
258 m32rxf_model_m32rx_u_cmp (SIM_CPU
*cpu
, const IDESC
*idesc
,
259 int unit_num
, int referenced
,
262 check_load_stall (cpu
, src1
);
263 check_load_stall (cpu
, src2
);
264 return idesc
->timing
->units
[unit_num
].done
;
268 m32rxf_model_m32rx_u_mac (SIM_CPU
*cpu
, const IDESC
*idesc
,
269 int unit_num
, int referenced
,
272 check_load_stall (cpu
, src1
);
273 check_load_stall (cpu
, src2
);
274 return idesc
->timing
->units
[unit_num
].done
;
278 m32rxf_model_m32rx_u_cti (SIM_CPU
*cpu
, const IDESC
*idesc
,
279 int unit_num
, int referenced
,
282 PROFILE_DATA
*profile
= CPU_PROFILE_DATA (cpu
);
283 int taken_p
= (referenced
& (1 << 1)) != 0;
285 check_load_stall (cpu
, sr
);
288 CPU_M32R_MISC_PROFILE (cpu
)->cti_stall
+= 2;
289 PROFILE_MODEL_TAKEN_COUNT (profile
) += 1;
292 PROFILE_MODEL_UNTAKEN_COUNT (profile
) += 1;
293 return idesc
->timing
->units
[unit_num
].done
;
297 m32rxf_model_m32rx_u_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
298 int unit_num
, int referenced
,
301 CPU_M32R_MISC_PROFILE (cpu
)->load_regs_pending
|= (1 << dr
);
302 return idesc
->timing
->units
[unit_num
].done
;
306 m32rxf_model_m32rx_u_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
307 int unit_num
, int referenced
,
310 return idesc
->timing
->units
[unit_num
].done
;
313 #endif /* WITH_PROFILE_MODEL_P */