sim/m32r/readx.c

   1 /* Simulator instruction operand reader for m32r.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifdef DEFINE_LABELS
  26 #undef DEFINE_LABELS
  27
  28   /* The labels have the case they have because the enum of insn types
  29      is all uppercase and in the non-stdc case the fmt symbol is built
  30      into the enum name.  */
  31
  32   static struct {
  33     int index;
  34     void *label;
  35   } labels[] = {
  36     { M32RX_XINSN_ILLEGAL, && case_read_READ_ILLEGAL },
  37     { M32RX_XINSN_ADD, && case_read_READ_FMT_ADD },
  38     { M32RX_XINSN_ADD3, && case_read_READ_FMT_ADD3 },
  39     { M32RX_XINSN_AND, && case_read_READ_FMT_ADD },
  40     { M32RX_XINSN_AND3, && case_read_READ_FMT_AND3 },
  41     { M32RX_XINSN_OR, && case_read_READ_FMT_ADD },
  42     { M32RX_XINSN_OR3, && case_read_READ_FMT_OR3 },
  43     { M32RX_XINSN_XOR, && case_read_READ_FMT_ADD },
  44     { M32RX_XINSN_XOR3, && case_read_READ_FMT_AND3 },
  45     { M32RX_XINSN_ADDI, && case_read_READ_FMT_ADDI },
  46     { M32RX_XINSN_ADDV, && case_read_READ_FMT_ADDV },
  47     { M32RX_XINSN_ADDV3, && case_read_READ_FMT_ADDV3 },
  48     { M32RX_XINSN_ADDX, && case_read_READ_FMT_ADDX },
  49     { M32RX_XINSN_BC8, && case_read_READ_FMT_BC8 },
  50     { M32RX_XINSN_BC24, && case_read_READ_FMT_BC24 },
  51     { M32RX_XINSN_BEQ, && case_read_READ_FMT_BEQ },
  52     { M32RX_XINSN_BEQZ, && case_read_READ_FMT_BEQZ },
  53     { M32RX_XINSN_BGEZ, && case_read_READ_FMT_BEQZ },
  54     { M32RX_XINSN_BGTZ, && case_read_READ_FMT_BEQZ },
  55     { M32RX_XINSN_BLEZ, && case_read_READ_FMT_BEQZ },
  56     { M32RX_XINSN_BLTZ, && case_read_READ_FMT_BEQZ },
  57     { M32RX_XINSN_BNEZ, && case_read_READ_FMT_BEQZ },
  58     { M32RX_XINSN_BL8, && case_read_READ_FMT_BL8 },
  59     { M32RX_XINSN_BL24, && case_read_READ_FMT_BL24 },
  60     { M32RX_XINSN_BCL8, && case_read_READ_FMT_BCL8 },
  61     { M32RX_XINSN_BCL24, && case_read_READ_FMT_BCL24 },
  62     { M32RX_XINSN_BNC8, && case_read_READ_FMT_BC8 },
  63     { M32RX_XINSN_BNC24, && case_read_READ_FMT_BC24 },
  64     { M32RX_XINSN_BNE, && case_read_READ_FMT_BEQ },
  65     { M32RX_XINSN_BRA8, && case_read_READ_FMT_BRA8 },
  66     { M32RX_XINSN_BRA24, && case_read_READ_FMT_BRA24 },
  67     { M32RX_XINSN_BNCL8, && case_read_READ_FMT_BCL8 },
  68     { M32RX_XINSN_BNCL24, && case_read_READ_FMT_BCL24 },
  69     { M32RX_XINSN_CMP, && case_read_READ_FMT_CMP },
  70     { M32RX_XINSN_CMPI, && case_read_READ_FMT_CMPI },
  71     { M32RX_XINSN_CMPU, && case_read_READ_FMT_CMP },
  72     { M32RX_XINSN_CMPUI, && case_read_READ_FMT_CMPI },
  73     { M32RX_XINSN_CMPEQ, && case_read_READ_FMT_CMP },
  74     { M32RX_XINSN_CMPZ, && case_read_READ_FMT_CMPZ },
  75     { M32RX_XINSN_DIV, && case_read_READ_FMT_DIV },
  76     { M32RX_XINSN_DIVU, && case_read_READ_FMT_DIV },
  77     { M32RX_XINSN_REM, && case_read_READ_FMT_DIV },
  78     { M32RX_XINSN_REMU, && case_read_READ_FMT_DIV },
  79     { M32RX_XINSN_DIVH, && case_read_READ_FMT_DIV },
  80     { M32RX_XINSN_JC, && case_read_READ_FMT_JC },
  81     { M32RX_XINSN_JNC, && case_read_READ_FMT_JC },
  82     { M32RX_XINSN_JL, && case_read_READ_FMT_JL },
  83     { M32RX_XINSN_JMP, && case_read_READ_FMT_JMP },
  84     { M32RX_XINSN_LD, && case_read_READ_FMT_LD },
  85     { M32RX_XINSN_LD_D, && case_read_READ_FMT_LD_D },
  86     { M32RX_XINSN_LDB, && case_read_READ_FMT_LDB },
  87     { M32RX_XINSN_LDB_D, && case_read_READ_FMT_LDB_D },
  88     { M32RX_XINSN_LDH, && case_read_READ_FMT_LDH },
  89     { M32RX_XINSN_LDH_D, && case_read_READ_FMT_LDH_D },
  90     { M32RX_XINSN_LDUB, && case_read_READ_FMT_LDB },
  91     { M32RX_XINSN_LDUB_D, && case_read_READ_FMT_LDB_D },
  92     { M32RX_XINSN_LDUH, && case_read_READ_FMT_LDH },
  93     { M32RX_XINSN_LDUH_D, && case_read_READ_FMT_LDH_D },
  94     { M32RX_XINSN_LD_PLUS, && case_read_READ_FMT_LD_PLUS },
  95     { M32RX_XINSN_LD24, && case_read_READ_FMT_LD24 },
  96     { M32RX_XINSN_LDI8, && case_read_READ_FMT_LDI8 },
  97     { M32RX_XINSN_LDI16, && case_read_READ_FMT_LDI16 },
  98     { M32RX_XINSN_LOCK, && case_read_READ_FMT_LOCK },
  99     { M32RX_XINSN_MACHI_A, && case_read_READ_FMT_MACHI_A },
 100     { M32RX_XINSN_MACLO_A, && case_read_READ_FMT_MACHI_A },
 101     { M32RX_XINSN_MACWHI, && case_read_READ_FMT_MACWHI },
 102     { M32RX_XINSN_MACWLO, && case_read_READ_FMT_MACWHI },
 103     { M32RX_XINSN_MUL, && case_read_READ_FMT_ADD },
 104     { M32RX_XINSN_MULHI_A, && case_read_READ_FMT_MULHI_A },
 105     { M32RX_XINSN_MULLO_A, && case_read_READ_FMT_MULHI_A },
 106     { M32RX_XINSN_MULWHI, && case_read_READ_FMT_MULWHI },
 107     { M32RX_XINSN_MULWLO, && case_read_READ_FMT_MULWHI },
 108     { M32RX_XINSN_MV, && case_read_READ_FMT_MV },
 109     { M32RX_XINSN_MVFACHI_A, && case_read_READ_FMT_MVFACHI_A },
 110     { M32RX_XINSN_MVFACLO_A, && case_read_READ_FMT_MVFACHI_A },
 111     { M32RX_XINSN_MVFACMI_A, && case_read_READ_FMT_MVFACHI_A },
 112     { M32RX_XINSN_MVFC, && case_read_READ_FMT_MVFC },
 113     { M32RX_XINSN_MVTACHI_A, && case_read_READ_FMT_MVTACHI_A },
 114     { M32RX_XINSN_MVTACLO_A, && case_read_READ_FMT_MVTACHI_A },
 115     { M32RX_XINSN_MVTC, && case_read_READ_FMT_MVTC },
 116     { M32RX_XINSN_NEG, && case_read_READ_FMT_MV },
 117     { M32RX_XINSN_NOP, && case_read_READ_FMT_NOP },
 118     { M32RX_XINSN_NOT, && case_read_READ_FMT_MV },
 119     { M32RX_XINSN_RAC_DSI, && case_read_READ_FMT_RAC_DSI },
 120     { M32RX_XINSN_RACH_DSI, && case_read_READ_FMT_RAC_DSI },
 121     { M32RX_XINSN_RTE, && case_read_READ_FMT_RTE },
 122     { M32RX_XINSN_SETH, && case_read_READ_FMT_SETH },
 123     { M32RX_XINSN_SLL, && case_read_READ_FMT_ADD },
 124     { M32RX_XINSN_SLL3, && case_read_READ_FMT_SLL3 },
 125     { M32RX_XINSN_SLLI, && case_read_READ_FMT_SLLI },
 126     { M32RX_XINSN_SRA, && case_read_READ_FMT_ADD },
 127     { M32RX_XINSN_SRA3, && case_read_READ_FMT_SLL3 },
 128     { M32RX_XINSN_SRAI, && case_read_READ_FMT_SLLI },
 129     { M32RX_XINSN_SRL, && case_read_READ_FMT_ADD },
 130     { M32RX_XINSN_SRL3, && case_read_READ_FMT_SLL3 },
 131     { M32RX_XINSN_SRLI, && case_read_READ_FMT_SLLI },
 132     { M32RX_XINSN_ST, && case_read_READ_FMT_ST },
 133     { M32RX_XINSN_ST_D, && case_read_READ_FMT_ST_D },
 134     { M32RX_XINSN_STB, && case_read_READ_FMT_STB },
 135     { M32RX_XINSN_STB_D, && case_read_READ_FMT_STB_D },
 136     { M32RX_XINSN_STH, && case_read_READ_FMT_STH },
 137     { M32RX_XINSN_STH_D, && case_read_READ_FMT_STH_D },
 138     { M32RX_XINSN_ST_PLUS, && case_read_READ_FMT_ST_PLUS },
 139     { M32RX_XINSN_ST_MINUS, && case_read_READ_FMT_ST_PLUS },
 140     { M32RX_XINSN_SUB, && case_read_READ_FMT_ADD },
 141     { M32RX_XINSN_SUBV, && case_read_READ_FMT_ADDV },
 142     { M32RX_XINSN_SUBX, && case_read_READ_FMT_ADDX },
 143     { M32RX_XINSN_TRAP, && case_read_READ_FMT_TRAP },
 144     { M32RX_XINSN_UNLOCK, && case_read_READ_FMT_UNLOCK },
 145     { M32RX_XINSN_SATB, && case_read_READ_FMT_SATB },
 146     { M32RX_XINSN_SATH, && case_read_READ_FMT_SATB },
 147     { M32RX_XINSN_SAT, && case_read_READ_FMT_SAT },
 148     { M32RX_XINSN_PCMPBZ, && case_read_READ_FMT_CMPZ },
 149     { M32RX_XINSN_SADD, && case_read_READ_FMT_SADD },
 150     { M32RX_XINSN_MACWU1, && case_read_READ_FMT_MACWU1 },
 151     { M32RX_XINSN_MSBLO, && case_read_READ_FMT_MACWHI },
 152     { M32RX_XINSN_MULWU1, && case_read_READ_FMT_MULWU1 },
 153     { M32RX_XINSN_MACLH1, && case_read_READ_FMT_MACWU1 },
 154     { M32RX_XINSN_SC, && case_read_READ_FMT_SC },
 155     { M32RX_XINSN_SNC, && case_read_READ_FMT_SC },
 156     { 0, 0 }
 157   };
 158   int i;
 159
 160   for (i = 0; labels[i].label != 0; ++i)
 161     CPU_IDESC (current_cpu) [labels[i].index].read = labels[i].label;
 162
 163 #endif /* DEFINE_LABELS */
 164
 165 #ifdef DEFINE_SWITCH
 166 #undef DEFINE_SWITCH
 167
 168 {
 169   SWITCH (read, decode->read)
 170     {
 171
 172     CASE (read, READ_ILLEGAL) :
 173     {
 174       sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
 175     }
 176     BREAK (read);
 177
 178     CASE (read, READ_FMT_ADD) : /* e.g. add $dr,$sr */
 179     {
 180 #define OPRND(f) par_exec->operands.fmt_add.f
 181   EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 182   EXTRACT_FMT_ADD_CODE
 183
 184       /* Fetch the input operands for the semantic handler.  */
 185       OPRND (dr) = CPU (h_gr[f_r1]);
 186       OPRND (sr) = CPU (h_gr[f_r2]);
 187 #undef OPRND
 188     }
 189     BREAK (read);
 190
 191     CASE (read, READ_FMT_ADD3) : /* e.g. add3 $dr,$sr,$hash$slo16 */
 192     {
 193 #define OPRND(f) par_exec->operands.fmt_add3.f
 194   EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 195   EXTRACT_FMT_ADD3_CODE
 196
 197       /* Fetch the input operands for the semantic handler.  */
 198       OPRND (sr) = CPU (h_gr[f_r2]);
 199       OPRND (slo16) = f_simm16;
 200 #undef OPRND
 201     }
 202     BREAK (read);
 203
 204     CASE (read, READ_FMT_AND3) : /* e.g. and3 $dr,$sr,$uimm16 */
 205     {
 206 #define OPRND(f) par_exec->operands.fmt_and3.f
 207   EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 208   EXTRACT_FMT_AND3_CODE
 209
 210       /* Fetch the input operands for the semantic handler.  */
 211       OPRND (sr) = CPU (h_gr[f_r2]);
 212       OPRND (uimm16) = f_uimm16;
 213 #undef OPRND
 214     }
 215     BREAK (read);
 216
 217     CASE (read, READ_FMT_OR3) : /* e.g. or3 $dr,$sr,$hash$ulo16 */
 218     {
 219 #define OPRND(f) par_exec->operands.fmt_or3.f
 220   EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 221   EXTRACT_FMT_OR3_CODE
 222
 223       /* Fetch the input operands for the semantic handler.  */
 224       OPRND (sr) = CPU (h_gr[f_r2]);
 225       OPRND (ulo16) = f_uimm16;
 226 #undef OPRND
 227     }
 228     BREAK (read);
 229
 230     CASE (read, READ_FMT_ADDI) : /* e.g. addi $dr,$simm8 */
 231     {
 232 #define OPRND(f) par_exec->operands.fmt_addi.f
 233   EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
 234   EXTRACT_FMT_ADDI_CODE
 235
 236       /* Fetch the input operands for the semantic handler.  */
 237       OPRND (dr) = CPU (h_gr[f_r1]);
 238       OPRND (simm8) = f_simm8;
 239 #undef OPRND
 240     }
 241     BREAK (read);
 242
 243     CASE (read, READ_FMT_ADDV) : /* e.g. addv $dr,$sr */
 244     {
 245 #define OPRND(f) par_exec->operands.fmt_addv.f
 246   EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 247   EXTRACT_FMT_ADDV_CODE
 248
 249       /* Fetch the input operands for the semantic handler.  */
 250       OPRND (dr) = CPU (h_gr[f_r1]);
 251       OPRND (sr) = CPU (h_gr[f_r2]);
 252 #undef OPRND
 253     }
 254     BREAK (read);
 255
 256     CASE (read, READ_FMT_ADDV3) : /* e.g. addv3 $dr,$sr,$simm16 */
 257     {
 258 #define OPRND(f) par_exec->operands.fmt_addv3.f
 259   EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 260   EXTRACT_FMT_ADDV3_CODE
 261
 262       /* Fetch the input operands for the semantic handler.  */
 263       OPRND (sr) = CPU (h_gr[f_r2]);
 264       OPRND (simm16) = f_simm16;
 265 #undef OPRND
 266     }
 267     BREAK (read);
 268
 269     CASE (read, READ_FMT_ADDX) : /* e.g. addx $dr,$sr */
 270     {
 271 #define OPRND(f) par_exec->operands.fmt_addx.f
 272   EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
 273   EXTRACT_FMT_ADDX_CODE
 274
 275       /* Fetch the input operands for the semantic handler.  */
 276       OPRND (dr) = CPU (h_gr[f_r1]);
 277       OPRND (sr) = CPU (h_gr[f_r2]);
 278       OPRND (condbit) = CPU (h_cond);
 279 #undef OPRND
 280     }
 281     BREAK (read);
 282
 283     CASE (read, READ_FMT_BC8) : /* e.g. bc.s $disp8 */
 284     {
 285 #define OPRND(f) par_exec->operands.fmt_bc8.f
 286   EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
 287   EXTRACT_FMT_BC8_CODE
 288
 289       /* Fetch the input operands for the semantic handler.  */
 290       OPRND (condbit) = CPU (h_cond);
 291       RECORD_IADDR (OPRND (disp8), (pc & -4L) + f_disp8);
 292 #undef OPRND
 293     }
 294     BREAK (read);
 295
 296     CASE (read, READ_FMT_BC24) : /* e.g. bc.l $disp24 */
 297     {
 298 #define OPRND(f) par_exec->operands.fmt_bc24.f
 299   EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
 300   EXTRACT_FMT_BC24_CODE
 301
 302       /* Fetch the input operands for the semantic handler.  */
 303       OPRND (condbit) = CPU (h_cond);
 304       OPRND (disp24) = pc + f_disp24;
 305 #undef OPRND
 306     }
 307     BREAK (read);
 308
 309     CASE (read, READ_FMT_BEQ) : /* e.g. beq $src1,$src2,$disp16 */
 310     {
 311 #define OPRND(f) par_exec->operands.fmt_beq.f
 312   EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 313   EXTRACT_FMT_BEQ_CODE
 314
 315       /* Fetch the input operands for the semantic handler.  */
 316       OPRND (src1) = CPU (h_gr[f_r1]);
 317       OPRND (src2) = CPU (h_gr[f_r2]);
 318       OPRND (disp16) = pc + f_disp16;
 319 #undef OPRND
 320     }
 321     BREAK (read);
 322
 323     CASE (read, READ_FMT_BEQZ) : /* e.g. beqz $src2,$disp16 */
 324     {
 325 #define OPRND(f) par_exec->operands.fmt_beqz.f
 326   EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 327   EXTRACT_FMT_BEQZ_CODE
 328
 329       /* Fetch the input operands for the semantic handler.  */
 330       OPRND (src2) = CPU (h_gr[f_r2]);
 331       OPRND (disp16) = pc + f_disp16;
 332 #undef OPRND
 333     }
 334     BREAK (read);
 335
 336     CASE (read, READ_FMT_BL8) : /* e.g. bl.s $disp8 */
 337     {
 338 #define OPRND(f) par_exec->operands.fmt_bl8.f
 339   EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
 340   EXTRACT_FMT_BL8_CODE
 341
 342       /* Fetch the input operands for the semantic handler.  */
 343       OPRND (pc) = CPU (h_pc);
 344       RECORD_IADDR (OPRND (disp8), (pc & -4L) + f_disp8);
 345 #undef OPRND
 346     }
 347     BREAK (read);
 348
 349     CASE (read, READ_FMT_BL24) : /* e.g. bl.l $disp24 */
 350     {
 351 #define OPRND(f) par_exec->operands.fmt_bl24.f
 352   EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
 353   EXTRACT_FMT_BL24_CODE
 354
 355       /* Fetch the input operands for the semantic handler.  */
 356       OPRND (pc) = CPU (h_pc);
 357       OPRND (disp24) = pc + f_disp24;
 358 #undef OPRND
 359     }
 360     BREAK (read);
 361
 362     CASE (read, READ_FMT_BCL8) : /* e.g. bcl.s $disp8 */
 363     {
 364 #define OPRND(f) par_exec->operands.fmt_bcl8.f
 365   EXTRACT_FMT_BCL8_VARS /* f-op1 f-r1 f-disp8 */
 366   EXTRACT_FMT_BCL8_CODE
 367
 368       /* Fetch the input operands for the semantic handler.  */
 369       OPRND (condbit) = CPU (h_cond);
 370       OPRND (pc) = CPU (h_pc);
 371       RECORD_IADDR (OPRND (disp8), (pc & -4L) + f_disp8);
 372 #undef OPRND
 373     }
 374     BREAK (read);
 375
 376     CASE (read, READ_FMT_BCL24) : /* e.g. bcl.l $disp24 */
 377     {
 378 #define OPRND(f) par_exec->operands.fmt_bcl24.f
 379   EXTRACT_FMT_BCL24_VARS /* f-op1 f-r1 f-disp24 */
 380   EXTRACT_FMT_BCL24_CODE
 381
 382       /* Fetch the input operands for the semantic handler.  */
 383       OPRND (condbit) = CPU (h_cond);
 384       OPRND (pc) = CPU (h_pc);
 385       OPRND (disp24) = pc + f_disp24;
 386 #undef OPRND
 387     }
 388     BREAK (read);
 389
 390     CASE (read, READ_FMT_BRA8) : /* e.g. bra.s $disp8 */
 391     {
 392 #define OPRND(f) par_exec->operands.fmt_bra8.f
 393   EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
 394   EXTRACT_FMT_BRA8_CODE
 395
 396       /* Fetch the input operands for the semantic handler.  */
 397       RECORD_IADDR (OPRND (disp8), (pc & -4L) + f_disp8);
 398 #undef OPRND
 399     }
 400     BREAK (read);
 401
 402     CASE (read, READ_FMT_BRA24) : /* e.g. bra.l $disp24 */
 403     {
 404 #define OPRND(f) par_exec->operands.fmt_bra24.f
 405   EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
 406   EXTRACT_FMT_BRA24_CODE
 407
 408       /* Fetch the input operands for the semantic handler.  */
 409       OPRND (disp24) = pc + f_disp24;
 410 #undef OPRND
 411     }
 412     BREAK (read);
 413
 414     CASE (read, READ_FMT_CMP) : /* e.g. cmp $src1,$src2 */
 415     {
 416 #define OPRND(f) par_exec->operands.fmt_cmp.f
 417   EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 418   EXTRACT_FMT_CMP_CODE
 419
 420       /* Fetch the input operands for the semantic handler.  */
 421       OPRND (src1) = CPU (h_gr[f_r1]);
 422       OPRND (src2) = CPU (h_gr[f_r2]);
 423 #undef OPRND
 424     }
 425     BREAK (read);
 426
 427     CASE (read, READ_FMT_CMPI) : /* e.g. cmpi $src2,$simm16 */
 428     {
 429 #define OPRND(f) par_exec->operands.fmt_cmpi.f
 430   EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 431   EXTRACT_FMT_CMPI_CODE
 432
 433       /* Fetch the input operands for the semantic handler.  */
 434       OPRND (src2) = CPU (h_gr[f_r2]);
 435       OPRND (simm16) = f_simm16;
 436 #undef OPRND
 437     }
 438     BREAK (read);
 439
 440     CASE (read, READ_FMT_CMPZ) : /* e.g. cmpz $src2 */
 441     {
 442 #define OPRND(f) par_exec->operands.fmt_cmpz.f
 443   EXTRACT_FMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
 444   EXTRACT_FMT_CMPZ_CODE
 445
 446       /* Fetch the input operands for the semantic handler.  */
 447       OPRND (src2) = CPU (h_gr[f_r2]);
 448 #undef OPRND
 449     }
 450     BREAK (read);
 451
 452     CASE (read, READ_FMT_DIV) : /* e.g. div $dr,$sr */
 453     {
 454 #define OPRND(f) par_exec->operands.fmt_div.f
 455   EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 456   EXTRACT_FMT_DIV_CODE
 457
 458       /* Fetch the input operands for the semantic handler.  */
 459       OPRND (dr) = CPU (h_gr[f_r1]);
 460       OPRND (sr) = CPU (h_gr[f_r2]);
 461 #undef OPRND
 462     }
 463     BREAK (read);
 464
 465     CASE (read, READ_FMT_JC) : /* e.g. jc $sr */
 466     {
 467 #define OPRND(f) par_exec->operands.fmt_jc.f
 468   EXTRACT_FMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 469   EXTRACT_FMT_JC_CODE
 470
 471       /* Fetch the input operands for the semantic handler.  */
 472       OPRND (condbit) = CPU (h_cond);
 473       OPRND (sr) = CPU (h_gr[f_r2]);
 474 #undef OPRND
 475     }
 476     BREAK (read);
 477
 478     CASE (read, READ_FMT_JL) : /* e.g. jl $sr */
 479     {
 480 #define OPRND(f) par_exec->operands.fmt_jl.f
 481   EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
 482   EXTRACT_FMT_JL_CODE
 483
 484       /* Fetch the input operands for the semantic handler.  */
 485       OPRND (pc) = CPU (h_pc);
 486       OPRND (sr) = CPU (h_gr[f_r2]);
 487 #undef OPRND
 488     }
 489     BREAK (read);
 490
 491     CASE (read, READ_FMT_JMP) : /* e.g. jmp $sr */
 492     {
 493 #define OPRND(f) par_exec->operands.fmt_jmp.f
 494   EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 495   EXTRACT_FMT_JMP_CODE
 496
 497       /* Fetch the input operands for the semantic handler.  */
 498       OPRND (sr) = CPU (h_gr[f_r2]);
 499 #undef OPRND
 500     }
 501     BREAK (read);
 502
 503     CASE (read, READ_FMT_LD) : /* e.g. ld $dr,@$sr */
 504     {
 505 #define OPRND(f) par_exec->operands.fmt_ld.f
 506   EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 507   EXTRACT_FMT_LD_CODE
 508
 509       /* Fetch the input operands for the semantic handler.  */
 510       OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
 511       OPRND (sr) = CPU (h_gr[f_r2]);
 512 #undef OPRND
 513     }
 514     BREAK (read);
 515
 516     CASE (read, READ_FMT_LD_D) : /* e.g. ld $dr,@($slo16,$sr) */
 517     {
 518 #define OPRND(f) par_exec->operands.fmt_ld_d.f
 519   EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 520   EXTRACT_FMT_LD_D_CODE
 521
 522       /* Fetch the input operands for the semantic handler.  */
 523       OPRND (h_memory_add__VM_sr_slo16) = GETMEMSI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 524       OPRND (sr) = CPU (h_gr[f_r2]);
 525       OPRND (slo16) = f_simm16;
 526 #undef OPRND
 527     }
 528     BREAK (read);
 529
 530     CASE (read, READ_FMT_LDB) : /* e.g. ldb $dr,@$sr */
 531     {
 532 #define OPRND(f) par_exec->operands.fmt_ldb.f
 533   EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
 534   EXTRACT_FMT_LDB_CODE
 535
 536       /* Fetch the input operands for the semantic handler.  */
 537       OPRND (h_memory_sr) = GETMEMQI (current_cpu, CPU (h_gr[f_r2]));
 538       OPRND (sr) = CPU (h_gr[f_r2]);
 539 #undef OPRND
 540     }
 541     BREAK (read);
 542
 543     CASE (read, READ_FMT_LDB_D) : /* e.g. ldb $dr,@($slo16,$sr) */
 544     {
 545 #define OPRND(f) par_exec->operands.fmt_ldb_d.f
 546   EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 547   EXTRACT_FMT_LDB_D_CODE
 548
 549       /* Fetch the input operands for the semantic handler.  */
 550       OPRND (h_memory_add__VM_sr_slo16) = GETMEMQI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 551       OPRND (sr) = CPU (h_gr[f_r2]);
 552       OPRND (slo16) = f_simm16;
 553 #undef OPRND
 554     }
 555     BREAK (read);
 556
 557     CASE (read, READ_FMT_LDH) : /* e.g. ldh $dr,@$sr */
 558     {
 559 #define OPRND(f) par_exec->operands.fmt_ldh.f
 560   EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
 561   EXTRACT_FMT_LDH_CODE
 562
 563       /* Fetch the input operands for the semantic handler.  */
 564       OPRND (h_memory_sr) = GETMEMHI (current_cpu, CPU (h_gr[f_r2]));
 565       OPRND (sr) = CPU (h_gr[f_r2]);
 566 #undef OPRND
 567     }
 568     BREAK (read);
 569
 570     CASE (read, READ_FMT_LDH_D) : /* e.g. ldh $dr,@($slo16,$sr) */
 571     {
 572 #define OPRND(f) par_exec->operands.fmt_ldh_d.f
 573   EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 574   EXTRACT_FMT_LDH_D_CODE
 575
 576       /* Fetch the input operands for the semantic handler.  */
 577       OPRND (h_memory_add__VM_sr_slo16) = GETMEMHI (current_cpu, ADDSI (CPU (h_gr[f_r2]), f_simm16));
 578       OPRND (sr) = CPU (h_gr[f_r2]);
 579       OPRND (slo16) = f_simm16;
 580 #undef OPRND
 581     }
 582     BREAK (read);
 583
 584     CASE (read, READ_FMT_LD_PLUS) : /* e.g. ld $dr,@$sr+ */
 585     {
 586 #define OPRND(f) par_exec->operands.fmt_ld_plus.f
 587   EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
 588   EXTRACT_FMT_LD_PLUS_CODE
 589
 590       /* Fetch the input operands for the semantic handler.  */
 591       OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
 592       OPRND (sr) = CPU (h_gr[f_r2]);
 593 #undef OPRND
 594     }
 595     BREAK (read);
 596
 597     CASE (read, READ_FMT_LD24) : /* e.g. ld24 $dr,$uimm24 */
 598     {
 599 #define OPRND(f) par_exec->operands.fmt_ld24.f
 600   EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
 601   EXTRACT_FMT_LD24_CODE
 602
 603       /* Fetch the input operands for the semantic handler.  */
 604       OPRND (uimm24) = f_uimm24;
 605 #undef OPRND
 606     }
 607     BREAK (read);
 608
 609     CASE (read, READ_FMT_LDI8) : /* e.g. ldi8 $dr,$simm8 */
 610     {
 611 #define OPRND(f) par_exec->operands.fmt_ldi8.f
 612   EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
 613   EXTRACT_FMT_LDI8_CODE
 614
 615       /* Fetch the input operands for the semantic handler.  */
 616       OPRND (simm8) = f_simm8;
 617 #undef OPRND
 618     }
 619     BREAK (read);
 620
 621     CASE (read, READ_FMT_LDI16) : /* e.g. ldi16 $dr,$hash$slo16 */
 622     {
 623 #define OPRND(f) par_exec->operands.fmt_ldi16.f
 624   EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 625   EXTRACT_FMT_LDI16_CODE
 626
 627       /* Fetch the input operands for the semantic handler.  */
 628       OPRND (slo16) = f_simm16;
 629 #undef OPRND
 630     }
 631     BREAK (read);
 632
 633     CASE (read, READ_FMT_LOCK) : /* e.g. lock $dr,@$sr */
 634     {
 635 #define OPRND(f) par_exec->operands.fmt_lock.f
 636   EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
 637   EXTRACT_FMT_LOCK_CODE
 638
 639       /* Fetch the input operands for the semantic handler.  */
 640       OPRND (h_memory_sr) = GETMEMSI (current_cpu, CPU (h_gr[f_r2]));
 641       OPRND (sr) = CPU (h_gr[f_r2]);
 642 #undef OPRND
 643     }
 644     BREAK (read);
 645
 646     CASE (read, READ_FMT_MACHI_A) : /* e.g. machi $src1,$src2,$acc */
 647     {
 648 #define OPRND(f) par_exec->operands.fmt_machi_a.f
 649   EXTRACT_FMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
 650   EXTRACT_FMT_MACHI_A_CODE
 651
 652       /* Fetch the input operands for the semantic handler.  */
 653       OPRND (acc) = m32rx_h_accums_get (current_cpu, f_acc);
 654       OPRND (src1) = CPU (h_gr[f_r1]);
 655       OPRND (src2) = CPU (h_gr[f_r2]);
 656 #undef OPRND
 657     }
 658     BREAK (read);
 659
 660     CASE (read, READ_FMT_MACWHI) : /* e.g. macwhi $src1,$src2 */
 661     {
 662 #define OPRND(f) par_exec->operands.fmt_macwhi.f
 663   EXTRACT_FMT_MACWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
 664   EXTRACT_FMT_MACWHI_CODE
 665
 666       /* Fetch the input operands for the semantic handler.  */
 667       OPRND (accum) = m32rx_h_accum_get (current_cpu);
 668       OPRND (src1) = CPU (h_gr[f_r1]);
 669       OPRND (src2) = CPU (h_gr[f_r2]);
 670 #undef OPRND
 671     }
 672     BREAK (read);
 673
 674     CASE (read, READ_FMT_MULHI_A) : /* e.g. mulhi $src1,$src2,$acc */
 675     {
 676 #define OPRND(f) par_exec->operands.fmt_mulhi_a.f
 677   EXTRACT_FMT_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
 678   EXTRACT_FMT_MULHI_A_CODE
 679
 680       /* Fetch the input operands for the semantic handler.  */
 681       OPRND (src1) = CPU (h_gr[f_r1]);
 682       OPRND (src2) = CPU (h_gr[f_r2]);
 683 #undef OPRND
 684     }
 685     BREAK (read);
 686
 687     CASE (read, READ_FMT_MULWHI) : /* e.g. mulwhi $src1,$src2 */
 688     {
 689 #define OPRND(f) par_exec->operands.fmt_mulwhi.f
 690   EXTRACT_FMT_MULWHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
 691   EXTRACT_FMT_MULWHI_CODE
 692
 693       /* Fetch the input operands for the semantic handler.  */
 694       OPRND (src1) = CPU (h_gr[f_r1]);
 695       OPRND (src2) = CPU (h_gr[f_r2]);
 696 #undef OPRND
 697     }
 698     BREAK (read);
 699
 700     CASE (read, READ_FMT_MV) : /* e.g. mv $dr,$sr */
 701     {
 702 #define OPRND(f) par_exec->operands.fmt_mv.f
 703   EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 704   EXTRACT_FMT_MV_CODE
 705
 706       /* Fetch the input operands for the semantic handler.  */
 707       OPRND (sr) = CPU (h_gr[f_r2]);
 708 #undef OPRND
 709     }
 710     BREAK (read);
 711
 712     CASE (read, READ_FMT_MVFACHI_A) : /* e.g. mvfachi $dr,$accs */
 713     {
 714 #define OPRND(f) par_exec->operands.fmt_mvfachi_a.f
 715   EXTRACT_FMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
 716   EXTRACT_FMT_MVFACHI_A_CODE
 717
 718       /* Fetch the input operands for the semantic handler.  */
 719       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 720 #undef OPRND
 721     }
 722     BREAK (read);
 723
 724     CASE (read, READ_FMT_MVFC) : /* e.g. mvfc $dr,$scr */
 725     {
 726 #define OPRND(f) par_exec->operands.fmt_mvfc.f
 727   EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 728   EXTRACT_FMT_MVFC_CODE
 729
 730       /* Fetch the input operands for the semantic handler.  */
 731       OPRND (scr) = m32rx_h_cr_get (current_cpu, f_r2);
 732 #undef OPRND
 733     }
 734     BREAK (read);
 735
 736     CASE (read, READ_FMT_MVTACHI_A) : /* e.g. mvtachi $src1,$accs */
 737     {
 738 #define OPRND(f) par_exec->operands.fmt_mvtachi_a.f
 739   EXTRACT_FMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
 740   EXTRACT_FMT_MVTACHI_A_CODE
 741
 742       /* Fetch the input operands for the semantic handler.  */
 743       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 744       OPRND (src1) = CPU (h_gr[f_r1]);
 745 #undef OPRND
 746     }
 747     BREAK (read);
 748
 749     CASE (read, READ_FMT_MVTC) : /* e.g. mvtc $sr,$dcr */
 750     {
 751 #define OPRND(f) par_exec->operands.fmt_mvtc.f
 752   EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
 753   EXTRACT_FMT_MVTC_CODE
 754
 755       /* Fetch the input operands for the semantic handler.  */
 756       OPRND (sr) = CPU (h_gr[f_r2]);
 757 #undef OPRND
 758     }
 759     BREAK (read);
 760
 761     CASE (read, READ_FMT_NOP) : /* e.g. nop */
 762     {
 763 #define OPRND(f) par_exec->operands.fmt_nop.f
 764   EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 765   EXTRACT_FMT_NOP_CODE
 766
 767       /* Fetch the input operands for the semantic handler.  */
 768 #undef OPRND
 769     }
 770     BREAK (read);
 771
 772     CASE (read, READ_FMT_RAC_DSI) : /* e.g. rac $accd,$accs,$imm1 */
 773     {
 774 #define OPRND(f) par_exec->operands.fmt_rac_dsi.f
 775   EXTRACT_FMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
 776   EXTRACT_FMT_RAC_DSI_CODE
 777
 778       /* Fetch the input operands for the semantic handler.  */
 779       OPRND (accs) = m32rx_h_accums_get (current_cpu, f_accs);
 780       OPRND (imm1) = f_imm1;
 781 #undef OPRND
 782     }
 783     BREAK (read);
 784
 785     CASE (read, READ_FMT_RTE) : /* e.g. rte */
 786     {
 787 #define OPRND(f) par_exec->operands.fmt_rte.f
 788   EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
 789   EXTRACT_FMT_RTE_CODE
 790
 791       /* Fetch the input operands for the semantic handler.  */
 792       OPRND (h_bsm_0) = CPU (h_bsm);
 793       OPRND (h_bie_0) = CPU (h_bie);
 794       OPRND (h_bcond_0) = CPU (h_bcond);
 795       OPRND (h_bpc_0) = CPU (h_bpc);
 796 #undef OPRND
 797     }
 798     BREAK (read);
 799
 800     CASE (read, READ_FMT_SETH) : /* e.g. seth $dr,$hash$hi16 */
 801     {
 802 #define OPRND(f) par_exec->operands.fmt_seth.f
 803   EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
 804   EXTRACT_FMT_SETH_CODE
 805
 806       /* Fetch the input operands for the semantic handler.  */
 807       OPRND (hi16) = f_hi16;
 808 #undef OPRND
 809     }
 810     BREAK (read);
 811
 812     CASE (read, READ_FMT_SLL3) : /* e.g. sll3 $dr,$sr,$simm16 */
 813     {
 814 #define OPRND(f) par_exec->operands.fmt_sll3.f
 815   EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 816   EXTRACT_FMT_SLL3_CODE
 817
 818       /* Fetch the input operands for the semantic handler.  */
 819       OPRND (sr) = CPU (h_gr[f_r2]);
 820       OPRND (simm16) = f_simm16;
 821 #undef OPRND
 822     }
 823     BREAK (read);
 824
 825     CASE (read, READ_FMT_SLLI) : /* e.g. slli $dr,$uimm5 */
 826     {
 827 #define OPRND(f) par_exec->operands.fmt_slli.f
 828   EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
 829   EXTRACT_FMT_SLLI_CODE
 830
 831       /* Fetch the input operands for the semantic handler.  */
 832       OPRND (dr) = CPU (h_gr[f_r1]);
 833       OPRND (uimm5) = f_uimm5;
 834 #undef OPRND
 835     }
 836     BREAK (read);
 837
 838     CASE (read, READ_FMT_ST) : /* e.g. st $src1,@$src2 */
 839     {
 840 #define OPRND(f) par_exec->operands.fmt_st.f
 841   EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
 842   EXTRACT_FMT_ST_CODE
 843
 844       /* Fetch the input operands for the semantic handler.  */
 845       OPRND (src2) = CPU (h_gr[f_r2]);
 846       OPRND (src1) = CPU (h_gr[f_r1]);
 847 #undef OPRND
 848     }
 849     BREAK (read);
 850
 851     CASE (read, READ_FMT_ST_D) : /* e.g. st $src1,@($slo16,$src2) */
 852     {
 853 #define OPRND(f) par_exec->operands.fmt_st_d.f
 854   EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 855   EXTRACT_FMT_ST_D_CODE
 856
 857       /* Fetch the input operands for the semantic handler.  */
 858       OPRND (src2) = CPU (h_gr[f_r2]);
 859       OPRND (slo16) = f_simm16;
 860       OPRND (src1) = CPU (h_gr[f_r1]);
 861 #undef OPRND
 862     }
 863     BREAK (read);
 864
 865     CASE (read, READ_FMT_STB) : /* e.g. stb $src1,@$src2 */
 866     {
 867 #define OPRND(f) par_exec->operands.fmt_stb.f
 868   EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
 869   EXTRACT_FMT_STB_CODE
 870
 871       /* Fetch the input operands for the semantic handler.  */
 872       OPRND (src2) = CPU (h_gr[f_r2]);
 873       OPRND (src1) = CPU (h_gr[f_r1]);
 874 #undef OPRND
 875     }
 876     BREAK (read);
 877
 878     CASE (read, READ_FMT_STB_D) : /* e.g. stb $src1,@($slo16,$src2) */
 879     {
 880 #define OPRND(f) par_exec->operands.fmt_stb_d.f
 881   EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 882   EXTRACT_FMT_STB_D_CODE
 883
 884       /* Fetch the input operands for the semantic handler.  */
 885       OPRND (src2) = CPU (h_gr[f_r2]);
 886       OPRND (slo16) = f_simm16;
 887       OPRND (src1) = CPU (h_gr[f_r1]);
 888 #undef OPRND
 889     }
 890     BREAK (read);
 891
 892     CASE (read, READ_FMT_STH) : /* e.g. sth $src1,@$src2 */
 893     {
 894 #define OPRND(f) par_exec->operands.fmt_sth.f
 895   EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
 896   EXTRACT_FMT_STH_CODE
 897
 898       /* Fetch the input operands for the semantic handler.  */
 899       OPRND (src2) = CPU (h_gr[f_r2]);
 900       OPRND (src1) = CPU (h_gr[f_r1]);
 901 #undef OPRND
 902     }
 903     BREAK (read);
 904
 905     CASE (read, READ_FMT_STH_D) : /* e.g. sth $src1,@($slo16,$src2) */
 906     {
 907 #define OPRND(f) par_exec->operands.fmt_sth_d.f
 908   EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 909   EXTRACT_FMT_STH_D_CODE
 910
 911       /* Fetch the input operands for the semantic handler.  */
 912       OPRND (src2) = CPU (h_gr[f_r2]);
 913       OPRND (slo16) = f_simm16;
 914       OPRND (src1) = CPU (h_gr[f_r1]);
 915 #undef OPRND
 916     }
 917     BREAK (read);
 918
 919     CASE (read, READ_FMT_ST_PLUS) : /* e.g. st $src1,@+$src2 */
 920     {
 921 #define OPRND(f) par_exec->operands.fmt_st_plus.f
 922   EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
 923   EXTRACT_FMT_ST_PLUS_CODE
 924
 925       /* Fetch the input operands for the semantic handler.  */
 926       OPRND (src2) = CPU (h_gr[f_r2]);
 927       OPRND (src1) = CPU (h_gr[f_r1]);
 928 #undef OPRND
 929     }
 930     BREAK (read);
 931
 932     CASE (read, READ_FMT_TRAP) : /* e.g. trap $uimm4 */
 933     {
 934 #define OPRND(f) par_exec->operands.fmt_trap.f
 935   EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
 936   EXTRACT_FMT_TRAP_CODE
 937
 938       /* Fetch the input operands for the semantic handler.  */
 939       OPRND (pc) = CPU (h_pc);
 940       OPRND (h_cr_0) = m32rx_h_cr_get (current_cpu, 0);
 941       OPRND (uimm4) = f_uimm4;
 942 #undef OPRND
 943     }
 944     BREAK (read);
 945
 946     CASE (read, READ_FMT_UNLOCK) : /* e.g. unlock $src1,@$src2 */
 947     {
 948 #define OPRND(f) par_exec->operands.fmt_unlock.f
 949   EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
 950   EXTRACT_FMT_UNLOCK_CODE
 951
 952       /* Fetch the input operands for the semantic handler.  */
 953       OPRND (h_lock_0) = CPU (h_lock);
 954       OPRND (src2) = CPU (h_gr[f_r2]);
 955       OPRND (src1) = CPU (h_gr[f_r1]);
 956 #undef OPRND
 957     }
 958     BREAK (read);
 959
 960     CASE (read, READ_FMT_SATB) : /* e.g. satb $dr,$sr */
 961     {
 962 #define OPRND(f) par_exec->operands.fmt_satb.f
 963   EXTRACT_FMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 964   EXTRACT_FMT_SATB_CODE
 965
 966       /* Fetch the input operands for the semantic handler.  */
 967       OPRND (sr) = CPU (h_gr[f_r2]);
 968 #undef OPRND
 969     }
 970     BREAK (read);
 971
 972     CASE (read, READ_FMT_SAT) : /* e.g. sat $dr,$sr */
 973     {
 974 #define OPRND(f) par_exec->operands.fmt_sat.f
 975   EXTRACT_FMT_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 976   EXTRACT_FMT_SAT_CODE
 977
 978       /* Fetch the input operands for the semantic handler.  */
 979       OPRND (condbit) = CPU (h_cond);
 980       OPRND (sr) = CPU (h_gr[f_r2]);
 981 #undef OPRND
 982     }
 983     BREAK (read);
 984
 985     CASE (read, READ_FMT_SADD) : /* e.g. sadd */
 986     {
 987 #define OPRND(f) par_exec->operands.fmt_sadd.f
 988   EXTRACT_FMT_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 989   EXTRACT_FMT_SADD_CODE
 990
 991       /* Fetch the input operands for the semantic handler.  */
 992       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
 993       OPRND (h_accums_0) = m32rx_h_accums_get (current_cpu, 0);
 994 #undef OPRND
 995     }
 996     BREAK (read);
 997
 998     CASE (read, READ_FMT_MACWU1) : /* e.g. macwu1 $src1,$src2 */
 999     {
1000 #define OPRND(f) par_exec->operands.fmt_macwu1.f
1001   EXTRACT_FMT_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
1002   EXTRACT_FMT_MACWU1_CODE
1003
1004       /* Fetch the input operands for the semantic handler.  */
1005       OPRND (h_accums_1) = m32rx_h_accums_get (current_cpu, 1);
1006       OPRND (src1) = CPU (h_gr[f_r1]);
1007       OPRND (src2) = CPU (h_gr[f_r2]);
1008 #undef OPRND
1009     }
1010     BREAK (read);
1011
1012     CASE (read, READ_FMT_MULWU1) : /* e.g. mulwu1 $src1,$src2 */
1013     {
1014 #define OPRND(f) par_exec->operands.fmt_mulwu1.f
1015   EXTRACT_FMT_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
1016   EXTRACT_FMT_MULWU1_CODE
1017
1018       /* Fetch the input operands for the semantic handler.  */
1019       OPRND (src1) = CPU (h_gr[f_r1]);
1020       OPRND (src2) = CPU (h_gr[f_r2]);
1021 #undef OPRND
1022     }
1023     BREAK (read);
1024
1025     CASE (read, READ_FMT_SC) : /* e.g. sc */
1026     {
1027 #define OPRND(f) par_exec->operands.fmt_sc.f
1028   EXTRACT_FMT_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1029   EXTRACT_FMT_SC_CODE
1030
1031       /* Fetch the input operands for the semantic handler.  */
1032       OPRND (condbit) = CPU (h_cond);
1033 #undef OPRND
1034     }
1035     BREAK (read);
1036
1037     }
1038   ENDSWITCH (read) /* End of read switch.  */
1039 }
1040
1041 #endif /* DEFINE_SWITCH */