1 /* Main simulator entry points specific to the M32R.
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "sim-options.h"
22 #include "libiberty.h"
36 #include "dv-m32r_uart.h"
38 static void free_state (SIM_DESC
);
39 static void print_m32r_misc_cpu (SIM_CPU
*cpu
, int verbose
);
41 /* Cover function of sim_state_free to free the cpu buffers as well. */
44 free_state (SIM_DESC sd
)
46 if (STATE_MODULES (sd
) != NULL
)
47 sim_module_uninstall (sd
);
48 sim_cpu_free_all (sd
);
52 /* Create an instance of the simulator. */
55 sim_open (kind
, callback
, abfd
, argv
)
57 host_callback
*callback
;
61 SIM_DESC sd
= sim_state_alloc (kind
, callback
);
65 /* The cpu data is kept in a separately allocated chunk of memory. */
66 if (sim_cpu_alloc_all (sd
, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK
)
72 #if 0 /* FIXME: pc is in mach-specific struct */
73 /* FIXME: watchpoints code shouldn't need this */
75 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
76 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
77 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
81 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
87 /* getopt will print the error message so we just have to exit if this fails.
88 FIXME: Hmmm... in the case of gdb we need getopt to call
90 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
96 /* Allocate a handler for the control registers and other devices
97 if no memory for that range has been allocated by the user.
98 All are allocated in one chunk to keep things from being
99 unnecessarily complicated.
100 TODO: Move these to the sim-model framework. */
101 sim_hw_parse (sd
, "/core/%s/reg %#x %i", "m32r_uart", UART_BASE_ADDR
, 0x100);
102 sim_hw_parse (sd
, "/core/%s/reg %#x %i", "m32r_cache", 0xfffffff0, 0x10);
104 /* Allocate core managed memory if none specified by user.
105 Use address 4 here in case the user wanted address 0 unmapped. */
106 if (sim_core_read_buffer (sd
, NULL
, read_map
, &c
, 4, 1) == 0)
107 sim_do_commandf (sd
, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE
);
109 /* check for/establish the reference program image */
110 if (sim_analyze_program (sd
,
111 (STATE_PROG_ARGV (sd
) != NULL
112 ? *STATE_PROG_ARGV (sd
)
120 /* Establish any remaining configuration options. */
121 if (sim_config (sd
) != SIM_RC_OK
)
127 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
133 /* Open a copy of the cpu descriptor table. */
135 CGEN_CPU_DESC cd
= m32r_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd
)->printable_name
,
137 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
139 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
140 CPU_CPU_DESC (cpu
) = cd
;
141 CPU_DISASSEMBLER (cpu
) = sim_cgen_disassemble_insn
;
143 m32r_cgen_init_dis (cd
);
146 /* Initialize various cgen things not done by common framework.
147 Must be done after m32r_cgen_cpu_open. */
150 for (c
= 0; c
< MAX_NR_PROCESSORS
; ++c
)
152 /* Only needed for profiling, but the structure member is small. */
153 memset (CPU_M32R_MISC_PROFILE (STATE_CPU (sd
, i
)), 0,
154 sizeof (* CPU_M32R_MISC_PROFILE (STATE_CPU (sd
, i
))));
155 /* Hook in callback for reporting these stats */
156 PROFILE_INFO_CPU_CALLBACK (CPU_PROFILE_DATA (STATE_CPU (sd
, i
)))
157 = print_m32r_misc_cpu
;
164 sim_create_inferior (sd
, abfd
, argv
, envp
)
170 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
174 addr
= bfd_get_start_address (abfd
);
177 sim_pc_set (current_cpu
, addr
);
180 m32rbf_h_cr_set (current_cpu
,
181 m32r_decode_gdb_ctrl_regnum(SPI_REGNUM
), 0x1f00000);
182 m32rbf_h_cr_set (current_cpu
,
183 m32r_decode_gdb_ctrl_regnum(SPU_REGNUM
), 0x1f00000);
186 /* Standalone mode (i.e. `run`) will take care of the argv for us in
187 sim_open() -> sim_parse_args(). But in debug mode (i.e. 'target sim'
188 with `gdb`), we need to handle it because the user can change the
189 argv on the fly via gdb's 'run'. */
190 if (STATE_PROG_ARGV (sd
) != argv
)
192 freeargv (STATE_PROG_ARGV (sd
));
193 STATE_PROG_ARGV (sd
) = dupargv (argv
);
199 /* PROFILE_CPU_CALLBACK */
202 print_m32r_misc_cpu (SIM_CPU
*cpu
, int verbose
)
204 SIM_DESC sd
= CPU_STATE (cpu
);
207 if (CPU_PROFILE_FLAGS (cpu
) [PROFILE_INSN_IDX
])
209 sim_io_printf (sd
, "Miscellaneous Statistics\n\n");
210 sim_io_printf (sd
, " %-*s %s\n\n",
211 PROFILE_LABEL_WIDTH
, "Fill nops:",
212 sim_add_commas (buf
, sizeof (buf
),
213 CPU_M32R_MISC_PROFILE (cpu
)->fillnop_count
));
214 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_m32rx
)
215 sim_io_printf (sd
, " %-*s %s\n\n",
216 PROFILE_LABEL_WIDTH
, "Parallel insns:",
217 sim_add_commas (buf
, sizeof (buf
),
218 CPU_M32R_MISC_PROFILE (cpu
)->parallel_count
));
219 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_m32r2
)
220 sim_io_printf (sd
, " %-*s %s\n\n",
221 PROFILE_LABEL_WIDTH
, "Parallel insns:",
222 sim_add_commas (buf
, sizeof (buf
),
223 CPU_M32R_MISC_PROFILE (cpu
)->parallel_count
));