sim/m32r/traps.c

   1 /* m32r exception, interrupt, and trap (EIT) support
   2    Copyright (C) 1998-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "sim-main.h"
  21 #include "sim-syscall.h"
  22 #include "targ-vals.h"
  23 #include <stdlib.h>
  24
  25 #define TRAP_FLUSH_CACHE 12
  26 /* The semantic code invokes this for invalid (unrecognized) instructions.  */
  27
  28 SEM_PC
  29 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
  30 {
  31   SIM_DESC sd = CPU_STATE (current_cpu);
  32
  33 #if 0
  34   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  35     {
  36       h_bsm_set (current_cpu, h_sm_get (current_cpu));
  37       h_bie_set (current_cpu, h_ie_get (current_cpu));
  38       h_bcond_set (current_cpu, h_cond_get (current_cpu));
  39       /* sm not changed */
  40       h_ie_set (current_cpu, 0);
  41       h_cond_set (current_cpu, 0);
  42
  43       h_bpc_set (current_cpu, cia);
  44
  45       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  46                           EIT_RSVD_INSN_ADDR);
  47     }
  48   else
  49 #endif
  50     sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
  51
  52   return pc;
  53 }
  54
  55 /* Process an address exception.  */
  56
  57 void
  58 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
  59                   unsigned int map, int nr_bytes, address_word addr,
  60                   transfer_type transfer, sim_core_signals sig)
  61 {
  62   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  63     {
  64       m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
  65                        m32rbf_h_cr_get (current_cpu, H_CR_BPC));
  66       switch (MACH_NUM (CPU_MACH (current_cpu)))
  67         {
  68         case MACH_M32R:
  69           m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
  70           /* sm not changed.  */
  71           m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
  72           break;
  73         case MACH_M32RX:
  74           m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
  75           /* sm not changed.  */
  76           m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
  77           break;
  78         case MACH_M32R2:
  79           m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
  80           /* sm not changed.  */
  81           m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
  82           break;
  83         default:
  84           abort ();
  85         }
  86
  87       m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
  88
  89       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  90                           EIT_ADDR_EXCP_ADDR);
  91     }
  92   else
  93     sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
  94                      transfer, sig);
  95 }
  96 \f
  97 /* Trap support.
  98    The result is the pc address to continue at.
  99    Preprocessing like saving the various registers has already been done.  */
 100
 101 USI
 102 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
 103 {
 104   SIM_DESC sd = CPU_STATE (current_cpu);
 105   host_callback *cb = STATE_CALLBACK (sd);
 106
 107   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
 108     {
 109       /* The new pc is the trap vector entry.
 110          We assume there's a branch there to some handler.
 111          Use cr5 as EVB (EIT Vector Base) register.  */
 112       /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 113       USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 114       return new_pc;
 115     }
 116
 117   switch (num)
 118     {
 119     case TRAP_SYSCALL :
 120       {
 121         long result, result2;
 122         int errcode;
 123
 124         sim_syscall_multi (current_cpu,
 125                            m32rbf_h_gr_get (current_cpu, 0),
 126                            m32rbf_h_gr_get (current_cpu, 1),
 127                            m32rbf_h_gr_get (current_cpu, 2),
 128                            m32rbf_h_gr_get (current_cpu, 3),
 129                            m32rbf_h_gr_get (current_cpu, 4),
 130                            &result, &result2, &errcode);
 131
 132         m32rbf_h_gr_set (current_cpu, 2, errcode);
 133         m32rbf_h_gr_set (current_cpu, 0, result);
 134         m32rbf_h_gr_set (current_cpu, 1, result2);
 135         break;
 136       }
 137
 138     case TRAP_BREAKPOINT:
 139       sim_engine_halt (sd, current_cpu, NULL, pc,
 140                        sim_stopped, SIM_SIGTRAP);
 141       break;
 142
 143     case TRAP_FLUSH_CACHE:
 144       /* Do nothing.  */
 145       break;
 146
 147     default :
 148       {
 149         /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 150         /* Use cr5 as EVB (EIT Vector Base) register.  */
 151         USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 152         return new_pc;
 153       }
 154     }
 155
 156   /* Fake an "rte" insn.  */
 157   /* FIXME: Should duplicate all of rte processing.  */
 158   return (pc & -4) + 4;
 159 }