sim/m32r/traps.c

   1 /* m32r exception, interrupt, and trap (EIT) support
   2    Copyright (C) 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #include "sim-main.h"
  22 #include "targ-vals.h"
  23
  24 #define TRAP_FLUSH_CACHE 12
  25 /* The semantic code invokes this for invalid (unrecognized) instructions.
  26    CIA is the address with the invalid insn.
  27    VPC is the virtual pc of the following insn.  */
  28
  29 SEM_PC
  30 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
  31 {
  32   SIM_DESC sd = CPU_STATE (current_cpu);
  33
  34 #if 0
  35   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  36     {
  37       h_bsm_set (current_cpu, h_sm_get (current_cpu));
  38       h_bie_set (current_cpu, h_ie_get (current_cpu));
  39       h_bcond_set (current_cpu, h_cond_get (current_cpu));
  40       /* sm not changed */
  41       h_ie_set (current_cpu, 0);
  42       h_cond_set (current_cpu, 0);
  43
  44       h_bpc_set (current_cpu, cia);
  45
  46       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  47                           EIT_RSVD_INSN_ADDR);
  48     }
  49   else
  50 #endif
  51     sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
  52   return vpc;
  53 }
  54
  55 /* Process an address exception.  */
  56
  57 void
  58 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
  59                   unsigned int map, int nr_bytes, address_word addr,
  60                   transfer_type transfer, sim_core_signals sig)
  61 {
  62   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  63     {
  64       a_m32r_h_cr_set (current_cpu, H_CR_BBPC,
  65                        a_m32r_h_cr_get (current_cpu, H_CR_BPC));
  66       if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32R)
  67         {
  68           m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
  69           /* sm not changed */
  70           m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
  71         }
  72       else if (MACH_NUM (CPU_MACH (current_cpu)) == MACH_M32RX)
  73         {
  74           m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
  75           /* sm not changed */
  76           m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
  77         }
  78       else
  79         {
  80           m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
  81           /* sm not changed */
  82           m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
  83         }
  84       a_m32r_h_cr_set (current_cpu, H_CR_BPC, cia);
  85
  86       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  87                           EIT_ADDR_EXCP_ADDR);
  88     }
  89   else
  90     sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
  91                      transfer, sig);
  92 }
  93 \f
  94 /* Read/write functions for system call interface.  */
  95
  96 static int
  97 syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
  98                   unsigned long taddr, char *buf, int bytes)
  99 {
 100   SIM_DESC sd = (SIM_DESC) sc->p1;
 101   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
 102
 103   return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
 104 }
 105
 106 static int
 107 syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
 108                    unsigned long taddr, const char *buf, int bytes)
 109 {
 110   SIM_DESC sd = (SIM_DESC) sc->p1;
 111   SIM_CPU *cpu = (SIM_CPU *) sc->p2;
 112
 113   return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
 114 }
 115
 116 /* Trap support.
 117    The result is the pc address to continue at.
 118    Preprocessing like saving the various registers has already been done.  */
 119
 120 USI
 121 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
 122 {
 123   SIM_DESC sd = CPU_STATE (current_cpu);
 124   host_callback *cb = STATE_CALLBACK (sd);
 125
 126 #ifdef SIM_HAVE_BREAKPOINTS
 127   /* Check for breakpoints "owned" by the simulator first, regardless
 128      of --environment.  */
 129   if (num == TRAP_BREAKPOINT)
 130     {
 131       /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
 132          it doesn't return.  Otherwise it returns and let's us try.  */
 133       sim_handle_breakpoint (sd, current_cpu, pc);
 134       /* Fall through.  */
 135     }
 136 #endif
 137
 138   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
 139     {
 140       /* The new pc is the trap vector entry.
 141          We assume there's a branch there to some handler.
 142          Use cr5 as EVB (EIT Vector Base) register.  */
 143       /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 144       USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 145       return new_pc;
 146     }
 147
 148   switch (num)
 149     {
 150     case TRAP_SYSCALL :
 151       {
 152         CB_SYSCALL s;
 153
 154         CB_SYSCALL_INIT (&s);
 155         s.func = a_m32r_h_gr_get (current_cpu, 0);
 156         s.arg1 = a_m32r_h_gr_get (current_cpu, 1);
 157         s.arg2 = a_m32r_h_gr_get (current_cpu, 2);
 158         s.arg3 = a_m32r_h_gr_get (current_cpu, 3);
 159
 160         if (s.func == TARGET_SYS_exit)
 161           {
 162             sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
 163           }
 164
 165         s.p1 = (PTR) sd;
 166         s.p2 = (PTR) current_cpu;
 167         s.read_mem = syscall_read_mem;
 168         s.write_mem = syscall_write_mem;
 169         cb_syscall (cb, &s);
 170         a_m32r_h_gr_set (current_cpu, 2, s.errcode);
 171         a_m32r_h_gr_set (current_cpu, 0, s.result);
 172         a_m32r_h_gr_set (current_cpu, 1, s.result2);
 173         break;
 174       }
 175
 176     case TRAP_BREAKPOINT:
 177       sim_engine_halt (sd, current_cpu, NULL, pc,
 178                        sim_stopped, SIM_SIGTRAP);
 179       break;
 180
 181     case TRAP_FLUSH_CACHE:
 182       /* Do nothing.  */
 183       break;
 184
 185     default :
 186       {
 187         /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 188         /* Use cr5 as EVB (EIT Vector Base) register.  */
 189         USI new_pc = a_m32r_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 190         return new_pc;
 191       }
 192     }
 193
 194   /* Fake an "rte" insn.  */
 195   /* FIXME: Should duplicate all of rte processing.  */
 196   return (pc & -4) + 4;
 197 }