sim/m32r/traps.c

   1 /* m32r exception, interrupt, and trap (EIT) support
   2    Copyright (C) 1998-2021 Free Software Foundation, Inc.
   3    Contributed by Cygnus Solutions.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 /* This must come before any other includes.  */
  21 #include "defs.h"
  22
  23 #include "sim-main.h"
  24 #include "sim-syscall.h"
  25 #include "targ-vals.h"
  26 #include <stdlib.h>
  27
  28 #define TRAP_FLUSH_CACHE 12
  29 /* The semantic code invokes this for invalid (unrecognized) instructions.  */
  30
  31 SEM_PC
  32 sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC pc)
  33 {
  34   SIM_DESC sd = CPU_STATE (current_cpu);
  35
  36 #if 0
  37   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  38     {
  39       h_bsm_set (current_cpu, h_sm_get (current_cpu));
  40       h_bie_set (current_cpu, h_ie_get (current_cpu));
  41       h_bcond_set (current_cpu, h_cond_get (current_cpu));
  42       /* sm not changed */
  43       h_ie_set (current_cpu, 0);
  44       h_cond_set (current_cpu, 0);
  45
  46       h_bpc_set (current_cpu, cia);
  47
  48       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  49                           EIT_RSVD_INSN_ADDR);
  50     }
  51   else
  52 #endif
  53     sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
  54
  55   return pc;
  56 }
  57
  58 /* Process an address exception.  */
  59
  60 void
  61 m32r_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
  62                   unsigned int map, int nr_bytes, address_word addr,
  63                   transfer_type transfer, sim_core_signals sig)
  64 {
  65   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
  66     {
  67       m32rbf_h_cr_set (current_cpu, H_CR_BBPC,
  68                        m32rbf_h_cr_get (current_cpu, H_CR_BPC));
  69       switch (MACH_NUM (CPU_MACH (current_cpu)))
  70         {
  71         case MACH_M32R:
  72           m32rbf_h_bpsw_set (current_cpu, m32rbf_h_psw_get (current_cpu));
  73           /* sm not changed.  */
  74           m32rbf_h_psw_set (current_cpu, m32rbf_h_psw_get (current_cpu) & 0x80);
  75           break;
  76         case MACH_M32RX:
  77           m32rxf_h_bpsw_set (current_cpu, m32rxf_h_psw_get (current_cpu));
  78           /* sm not changed.  */
  79           m32rxf_h_psw_set (current_cpu, m32rxf_h_psw_get (current_cpu) & 0x80);
  80           break;
  81         case MACH_M32R2:
  82           m32r2f_h_bpsw_set (current_cpu, m32r2f_h_psw_get (current_cpu));
  83           /* sm not changed.  */
  84           m32r2f_h_psw_set (current_cpu, m32r2f_h_psw_get (current_cpu) & 0x80);
  85           break;
  86         default:
  87           abort ();
  88         }
  89
  90       m32rbf_h_cr_set (current_cpu, H_CR_BPC, cia);
  91
  92       sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
  93                           EIT_ADDR_EXCP_ADDR);
  94     }
  95   else
  96     sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
  97                      transfer, sig);
  98 }
  99 \f
 100 /* Trap support.
 101    The result is the pc address to continue at.
 102    Preprocessing like saving the various registers has already been done.  */
 103
 104 USI
 105 m32r_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
 106 {
 107   SIM_DESC sd = CPU_STATE (current_cpu);
 108   host_callback *cb = STATE_CALLBACK (sd);
 109
 110   if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
 111     {
 112       /* The new pc is the trap vector entry.
 113          We assume there's a branch there to some handler.
 114          Use cr5 as EVB (EIT Vector Base) register.  */
 115       /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 116       USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 117       return new_pc;
 118     }
 119
 120   switch (num)
 121     {
 122     case TRAP_SYSCALL :
 123       {
 124         long result, result2;
 125         int errcode;
 126
 127         sim_syscall_multi (current_cpu,
 128                            m32rbf_h_gr_get (current_cpu, 0),
 129                            m32rbf_h_gr_get (current_cpu, 1),
 130                            m32rbf_h_gr_get (current_cpu, 2),
 131                            m32rbf_h_gr_get (current_cpu, 3),
 132                            m32rbf_h_gr_get (current_cpu, 4),
 133                            &result, &result2, &errcode);
 134
 135         m32rbf_h_gr_set (current_cpu, 2, errcode);
 136         m32rbf_h_gr_set (current_cpu, 0, result);
 137         m32rbf_h_gr_set (current_cpu, 1, result2);
 138         break;
 139       }
 140
 141     case TRAP_BREAKPOINT:
 142       sim_engine_halt (sd, current_cpu, NULL, pc,
 143                        sim_stopped, SIM_SIGTRAP);
 144       break;
 145
 146     case TRAP_FLUSH_CACHE:
 147       /* Do nothing.  */
 148       break;
 149
 150     default :
 151       {
 152         /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
 153         /* Use cr5 as EVB (EIT Vector Base) register.  */
 154         USI new_pc = m32rbf_h_cr_get (current_cpu, 5) + 0x40 + num * 4;
 155         return new_pc;
 156       }
 157     }
 158
 159   /* Fake an "rte" insn.  */
 160   /* FIXME: Should duplicate all of rte processing.  */
 161   return (pc & -4) + 4;
 162 }