1 /* dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
2 Copyright (C) 2000 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include "dv-sockser.h"
28 #include "sim-assert.h"
33 m68hc11spi - m68hc11 SPI interface
38 Implements the m68hc11 Synchronous Serial Peripheral Interface
39 described in the m68hc11 user guide (Chapter 8 in pink book).
40 The SPI I/O controller is directly connected to the CPU
41 interrupt. The simulator implements:
45 - Write collision detection
57 Reset port. This port is only used to simulate a reset of the SPI
58 I/O controller. It should be connected to the RESET output of the cpu.
72 static const struct hw_port_descriptor m68hc11spi_ports
[] =
74 { "reset", RESET_PORT
, 0, input_port
, },
82 /* Information about next character to be transmited. */
83 unsigned char tx_char
;
87 unsigned char rx_char
;
88 unsigned char rx_clear_scsr
;
89 unsigned char clk_pin
;
91 /* SPI clock rate (twice the real clock). */
94 /* Periodic SPI event. */
95 struct hw_event
* spi_event
;
100 /* Finish off the partially created hw device. Attach our local
101 callbacks. Wire up our port names etc */
103 static hw_io_read_buffer_method m68hc11spi_io_read_buffer
;
104 static hw_io_write_buffer_method m68hc11spi_io_write_buffer
;
105 static hw_port_event_method m68hc11spi_port_event
;
106 static hw_ioctl_method m68hc11spi_ioctl
;
108 #define M6811_SPI_FIRST_REG (M6811_SPCR)
109 #define M6811_SPI_LAST_REG (M6811_SPDR)
113 attach_m68hc11spi_regs (struct hw
*me
,
114 struct m68hc11spi
*controller
)
116 hw_attach_address (hw_parent (me
), M6811_IO_LEVEL
, io_map
,
118 M6811_SPI_LAST_REG
- M6811_SPI_FIRST_REG
+ 1,
123 m68hc11spi_finish (struct hw
*me
)
125 struct m68hc11spi
*controller
;
127 controller
= HW_ZALLOC (me
, struct m68hc11spi
);
128 set_hw_data (me
, controller
);
129 set_hw_io_read_buffer (me
, m68hc11spi_io_read_buffer
);
130 set_hw_io_write_buffer (me
, m68hc11spi_io_write_buffer
);
131 set_hw_ports (me
, m68hc11spi_ports
);
132 set_hw_port_event (me
, m68hc11spi_port_event
);
134 set_hw_ioctl (me
, m68hc11spi_ioctl
);
136 me
->to_ioctl
= m68hc11spi_ioctl
;
139 /* Attach ourself to our parent bus. */
140 attach_m68hc11spi_regs (me
, controller
);
142 /* Initialize to reset state. */
143 controller
->spi_event
= NULL
;
144 controller
->rx_clear_scsr
= 0;
149 /* An event arrives on an interrupt port */
152 m68hc11spi_port_event (struct hw
*me
,
159 struct m68hc11spi
*controller
;
163 controller
= hw_data (me
);
165 cpu
= STATE_CPU (sd
, 0);
170 HW_TRACE ((me
, "SPI reset"));
172 /* Reset the state of SPI registers. */
173 controller
->rx_clear_scsr
= 0;
174 if (controller
->spi_event
)
176 hw_event_queue_deschedule (me
, controller
->spi_event
);
177 controller
->spi_event
= 0;
181 m68hc11spi_io_write_buffer (me
, &val
, io_map
,
182 (unsigned_word
) M6811_SPCR
, 1);
187 hw_abort (me
, "Event on unknown port %d", my_port
);
193 set_bit_port (struct hw
*me
, sim_cpu
*cpu
, int port
, int mask
, int value
)
195 /* TODO: Post an event to inform other devices that pin 'port' changes.
196 This has only a sense if we provide some device that is logically
197 connected to these pin ports (SCLK and MOSI) and that handles
200 cpu
->ios
[port
] |= mask
;
202 cpu
->ios
[port
] &= ~mask
;
206 /* When a character is sent/received by the SPI, the PD2..PD5 line
207 are driven by the following signals:
210 -----+---------+--------+---/-+-------
212 MISO +---------+--------+---/-+
214 CLK _______/ \____/ \__ CPOL=0, CPHA=0
216 \____/ \___/ CPOL=1, CPHA=0
218 __/ \____/ \___/ CPOL=0, CPHA=1
220 \____/ \____/ \__ CPOL=1, CPHA=1
223 \__________________________//___/
232 #define SPI_START_BIT 0
233 #define SPI_MIDDLE_BIT 1
236 m68hc11spi_clock (struct hw
*me
, void *data
)
239 struct m68hc11spi
* controller
;
241 int check_interrupt
= 0;
243 controller
= hw_data (me
);
245 cpu
= STATE_CPU (sd
, 0);
247 /* Cleanup current event. */
248 if (controller
->spi_event
)
250 hw_event_queue_deschedule (me
, controller
->spi_event
);
251 controller
->spi_event
= 0;
254 /* Change a bit of data at each two SPI event. */
255 if (controller
->mode
== SPI_START_BIT
)
257 /* Reflect the bit value on bit 2 of port D. */
258 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 2),
259 (controller
->tx_char
& (1 << controller
->tx_bit
)));
260 controller
->tx_bit
--;
261 controller
->mode
= SPI_MIDDLE_BIT
;
265 controller
->mode
= SPI_START_BIT
;
268 /* Change the SPI clock at each event on bit 4 of port D. */
269 controller
->clk_pin
= ~controller
->clk_pin
;
270 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 4), controller
->clk_pin
);
272 /* Transmit is now complete for this byte. */
273 if (controller
->mode
== SPI_START_BIT
&& controller
->tx_bit
< 0)
275 controller
->rx_clear_scsr
= 0;
276 cpu
->ios
[M6811_SPSR
] |= M6811_SPIF
;
277 if (cpu
->ios
[M6811_SPCR
] & M6811_SPIE
)
282 controller
->spi_event
= hw_event_queue_schedule (me
, controller
->clock
,
288 interrupts_update_pending (&cpu
->cpu_interrupts
);
291 /* Flags of the SPCR register. */
292 io_reg_desc spcr_desc
[] = {
293 { M6811_SPIE
, "SPIE ", "Serial Peripheral Interrupt Enable" },
294 { M6811_SPE
, "SPE ", "Serial Peripheral System Enable" },
295 { M6811_DWOM
, "DWOM ", "Port D Wire-OR mode option" },
296 { M6811_MSTR
, "MSTR ", "Master Mode Select" },
297 { M6811_CPOL
, "CPOL ", "Clock Polarity" },
298 { M6811_CPHA
, "CPHA ", "Clock Phase" },
299 { M6811_SPR1
, "SPR1 ", "SPI Clock Rate Select" },
300 { M6811_SPR0
, "SPR0 ", "SPI Clock Rate Select" },
305 /* Flags of the SPSR register. */
306 io_reg_desc spsr_desc
[] = {
307 { M6811_SPIF
, "SPIF ", "SPI Transfer Complete flag" },
308 { M6811_WCOL
, "WCOL ", "Write Collision" },
309 { M6811_MODF
, "MODF ", "Mode Fault" },
314 m68hc11spi_info (struct hw
*me
)
319 struct m68hc11spi
*controller
;
323 cpu
= STATE_CPU (sd
, 0);
324 controller
= hw_data (me
);
326 sim_io_printf (sd
, "M68HC11 SPI:\n");
328 base
= cpu_get_io_base (cpu
);
330 val
= cpu
->ios
[M6811_SPCR
];
331 print_io_byte (sd
, "SPCR", spcr_desc
, val
, base
+ M6811_SPCR
);
332 sim_io_printf (sd
, "\n");
334 val
= cpu
->ios
[M6811_SPSR
];
335 print_io_byte (sd
, "SPSR", spsr_desc
, val
, base
+ M6811_SPSR
);
336 sim_io_printf (sd
, "\n");
338 if (controller
->spi_event
)
342 t
= hw_event_remain_time (me
, controller
->spi_event
);
343 sim_io_printf (sd
, " SPI operation finished in %ld cycles\n",
349 m68hc11spi_ioctl (struct hw
*me
,
350 hw_ioctl_request request
,
353 m68hc11spi_info (me
);
357 /* generic read/write */
360 m68hc11spi_io_read_buffer (struct hw
*me
,
367 struct m68hc11spi
*controller
;
371 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
374 cpu
= STATE_CPU (sd
, 0);
375 controller
= hw_data (me
);
380 controller
->rx_clear_scsr
= cpu
->ios
[M6811_SCSR
]
381 & (M6811_SPIF
| M6811_WCOL
| M6811_MODF
);
384 val
= cpu
->ios
[base
];
388 if (controller
->rx_clear_scsr
)
390 cpu
->ios
[M6811_SPSR
] &= ~controller
->rx_clear_scsr
;
391 controller
->rx_clear_scsr
= 0;
393 val
= controller
->rx_char
;
399 *((unsigned8
*) dest
) = val
;
404 m68hc11spi_io_write_buffer (struct hw
*me
,
411 struct m68hc11spi
*controller
;
415 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
418 cpu
= STATE_CPU (sd
, 0);
419 controller
= hw_data (me
);
421 val
= *((const unsigned8
*) source
);
425 cpu
->ios
[M6811_SPCR
] = val
;
427 /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
428 We have to drive the clock pin and need a 2x faster clock. */
429 switch (val
& (M6811_SPR1
| M6811_SPR0
))
432 controller
->clock
= 1;
436 controller
->clock
= 2;
440 controller
->clock
= 8;
444 controller
->clock
= 16;
448 /* Set the clock pin. */
449 if ((val
& M6811_CPOL
)
450 && (controller
->spi_event
== 0
451 || ((val
& M6811_CPHA
) && controller
->mode
== 1)))
452 controller
->clk_pin
= 1;
454 controller
->clk_pin
= 0;
456 set_bit_port (me
, cpu
, M6811_PORTD
, (1 << 4), controller
->clk_pin
);
459 /* Can't write to SPSR. */
464 if (!(cpu
->ios
[M6811_SPCR
] & M6811_SPE
))
469 /* If transfer is taking place, a write to SPDR
470 generates a collision. */
471 if (controller
->spi_event
)
473 cpu
->ios
[M6811_SPSR
] |= M6811_WCOL
;
477 /* Refuse the write if there was no read of SPSR. */
480 /* Prepare to send a byte. */
481 controller
->tx_char
= val
;
482 controller
->tx_bit
= 7;
483 controller
->mode
= 0;
485 /* Toggle clock pin internal value when CPHA is 0 so that
486 it will really change in the middle of a bit. */
487 if (!(cpu
->ios
[M6811_SPCR
] & M6811_CPHA
))
488 controller
->clk_pin
= ~controller
->clk_pin
;
490 cpu
->ios
[M6811_SPDR
] = val
;
492 /* Activate transmission. */
493 m68hc11spi_clock (me
, NULL
);
503 const struct hw_descriptor dv_m68hc11spi_descriptor
[] = {
504 { "m68hc11spi", m68hc11spi_finish
, },