sim/m68hc11/dv-m68hc11spi.c

   1 /*  dv-m68hc11spi.c -- Simulation of the 68HC11 SPI
   2     Copyright (C) 2000-2023 Free Software Foundation, Inc.
   3     Written by Stephane Carrez (stcarrez@nerim.fr)
   4     (From a driver model Contributed by Cygnus Solutions.)
   5
   6     This file is part of the program GDB, the GNU debugger.
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 3 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20
  21     */
  22
  23 /* This must come before any other includes.  */
  24 #include "defs.h"
  25
  26 #include "sim-main.h"
  27 #include "hw-main.h"
  28 #include "dv-sockser.h"
  29 #include "sim-assert.h"
  30
  31 #include "m68hc11-sim.h"
  32
  33 /* DEVICE
  34
  35         m68hc11spi - m68hc11 SPI interface
  36
  37
  38    DESCRIPTION
  39
  40         Implements the m68hc11 Synchronous Serial Peripheral Interface
  41         described in the m68hc11 user guide (Chapter 8 in pink book).
  42         The SPI I/O controller is directly connected to the CPU
  43         interrupt.  The simulator implements:
  44
  45             - SPI clock emulation
  46             - Data transfer
  47             - Write collision detection
  48
  49
  50    PROPERTIES
  51
  52         None
  53
  54
  55    PORTS
  56
  57    reset (input)
  58
  59         Reset port. This port is only used to simulate a reset of the SPI
  60         I/O controller. It should be connected to the RESET output of the cpu.
  61
  62    */
  63
  64
  65
  66 /* port ID's */
  67
  68 enum
  69 {
  70   RESET_PORT
  71 };
  72
  73
  74 static const struct hw_port_descriptor m68hc11spi_ports[] =
  75 {
  76   { "reset", RESET_PORT, 0, input_port, },
  77   { NULL, },
  78 };
  79
  80
  81 /* SPI */
  82 struct m68hc11spi
  83 {
  84   /* Information about next character to be transmited.  */
  85   unsigned char tx_char;
  86   int           tx_bit;
  87   unsigned char mode;
  88
  89   unsigned char rx_char;
  90   unsigned char rx_clear_scsr;
  91   unsigned char clk_pin;
  92
  93   /* SPI clock rate (twice the real clock).  */
  94   unsigned int clock;
  95
  96   /* Periodic SPI event.  */
  97   struct hw_event* spi_event;
  98 };
  99
 100
 101
 102 /* Finish off the partially created hw device.  Attach our local
 103    callbacks.  Wire up our port names etc */
 104
 105 static hw_io_read_buffer_method m68hc11spi_io_read_buffer;
 106 static hw_io_write_buffer_method m68hc11spi_io_write_buffer;
 107 static hw_port_event_method m68hc11spi_port_event;
 108 static hw_ioctl_method m68hc11spi_ioctl;
 109
 110 #define M6811_SPI_FIRST_REG (M6811_SPCR)
 111 #define M6811_SPI_LAST_REG  (M6811_SPDR)
 112
 113
 114 static void
 115 attach_m68hc11spi_regs (struct hw *me,
 116                         struct m68hc11spi *controller)
 117 {
 118   hw_attach_address (hw_parent (me), M6811_IO_LEVEL, io_map,
 119                      M6811_SPI_FIRST_REG,
 120                      M6811_SPI_LAST_REG - M6811_SPI_FIRST_REG + 1,
 121                      me);
 122 }
 123
 124 static void
 125 m68hc11spi_finish (struct hw *me)
 126 {
 127   struct m68hc11spi *controller;
 128
 129   controller = HW_ZALLOC (me, struct m68hc11spi);
 130   set_hw_data (me, controller);
 131   set_hw_io_read_buffer (me, m68hc11spi_io_read_buffer);
 132   set_hw_io_write_buffer (me, m68hc11spi_io_write_buffer);
 133   set_hw_ports (me, m68hc11spi_ports);
 134   set_hw_port_event (me, m68hc11spi_port_event);
 135 #ifdef set_hw_ioctl
 136   set_hw_ioctl (me, m68hc11spi_ioctl);
 137 #else
 138   me->to_ioctl = m68hc11spi_ioctl;
 139 #endif
 140
 141   /* Attach ourself to our parent bus.  */
 142   attach_m68hc11spi_regs (me, controller);
 143
 144   /* Initialize to reset state.  */
 145   controller->spi_event = NULL;
 146   controller->rx_clear_scsr = 0;
 147 }
 148
 149
 150
 151 /* An event arrives on an interrupt port */
 152
 153 static void
 154 m68hc11spi_port_event (struct hw *me,
 155                        int my_port,
 156                        struct hw *source,
 157                        int source_port,
 158                        int level)
 159 {
 160   SIM_DESC sd;
 161   struct m68hc11spi *controller;
 162   sim_cpu *cpu;
 163   uint8_t val;
 164
 165   controller = hw_data (me);
 166   sd         = hw_system (me);
 167   cpu        = STATE_CPU (sd, 0);
 168   switch (my_port)
 169     {
 170     case RESET_PORT:
 171       {
 172         HW_TRACE ((me, "SPI reset"));
 173
 174         /* Reset the state of SPI registers.  */
 175         controller->rx_clear_scsr = 0;
 176         if (controller->spi_event)
 177           {
 178             hw_event_queue_deschedule (me, controller->spi_event);
 179             controller->spi_event = 0;
 180           }
 181
 182         val = 0;
 183         m68hc11spi_io_write_buffer (me, &val, io_map,
 184                                     (unsigned_word) M6811_SPCR, 1);
 185         break;
 186       }
 187
 188     default:
 189       hw_abort (me, "Event on unknown port %d", my_port);
 190       break;
 191     }
 192 }
 193
 194 static void
 195 set_bit_port (struct hw *me, sim_cpu *cpu, int port, int mask, int value)
 196 {
 197   struct m68hc11_sim_cpu *m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 198   uint8_t val;
 199
 200   if (value)
 201     val = m68hc11_cpu->ios[port] | mask;
 202   else
 203     val = m68hc11_cpu->ios[port] & ~mask;
 204
 205   /* Set the new value and post an event to inform other devices
 206      that pin 'port' changed.  */
 207   m68hc11cpu_set_port (me, cpu, port, val);
 208 }
 209
 210
 211 /* When a character is sent/received by the SPI, the PD2..PD5 line
 212    are driven by the following signals:
 213
 214               B7        B6
 215       -----+---------+--------+---/-+-------
 216  MOSI      |    |    |   |    |     |
 217  MISO      +---------+--------+---/-+
 218                 ____      ___
 219  CLK    _______/    \____/   \__                CPOL=0, CPHA=0
 220         _______      ____     __
 221                \____/    \___/                  CPOL=1, CPHA=0
 222            ____      ____     __
 223         __/    \____/    \___/                  CPOL=0, CPHA=1
 224         __      ____      ___
 225           \____/    \____/   \__                CPOL=1, CPHA=1
 226
 227  SS ___                                 ____
 228        \__________________________//___/
 229
 230  MISO = PD2
 231  MOSI = PD3
 232  SCK  = PD4
 233  SS   = PD5
 234
 235 */
 236
 237 #define SPI_START_BYTE 0
 238 #define SPI_START_BIT  1
 239 #define SPI_MIDDLE_BIT 2
 240
 241 static void
 242 m68hc11spi_clock (struct hw *me, void *data)
 243 {
 244   SIM_DESC sd;
 245   struct m68hc11spi* controller;
 246   sim_cpu *cpu;
 247   struct m68hc11_sim_cpu *m68hc11_cpu;
 248   int check_interrupt = 0;
 249
 250   controller = hw_data (me);
 251   sd         = hw_system (me);
 252   cpu        = STATE_CPU (sd, 0);
 253   m68hc11_cpu  = M68HC11_SIM_CPU (cpu);
 254
 255   /* Cleanup current event.  */
 256   if (controller->spi_event)
 257     {
 258       hw_event_queue_deschedule (me, controller->spi_event);
 259       controller->spi_event = 0;
 260     }
 261
 262   /* Change a bit of data at each two SPI event.  */
 263   if (controller->mode == SPI_START_BIT)
 264     {
 265       /* Reflect the bit value on bit 2 of port D.  */
 266       set_bit_port (me, cpu, M6811_PORTD, (1 << 2),
 267                     (controller->tx_char & (1 << controller->tx_bit)));
 268       controller->tx_bit--;
 269       controller->mode = SPI_MIDDLE_BIT;
 270     }
 271   else if (controller->mode == SPI_MIDDLE_BIT)
 272     {
 273       controller->mode = SPI_START_BIT;
 274     }
 275
 276   if (controller->mode == SPI_START_BYTE)
 277     {
 278       /* Start a new SPI transfer.  */
 279
 280       /* TBD: clear SS output.  */
 281       controller->mode = SPI_START_BIT;
 282       controller->tx_bit = 7;
 283       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), ~controller->clk_pin);
 284     }
 285   else
 286     {
 287       /* Change the SPI clock at each event on bit 4 of port D.  */
 288       controller->clk_pin = ~controller->clk_pin;
 289       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
 290     }
 291
 292   /* Transmit is now complete for this byte.  */
 293   if (controller->mode == SPI_START_BIT && controller->tx_bit < 0)
 294     {
 295       controller->rx_clear_scsr = 0;
 296       m68hc11_cpu->ios[M6811_SPSR] |= M6811_SPIF;
 297       if (m68hc11_cpu->ios[M6811_SPCR] & M6811_SPIE)
 298         check_interrupt = 1;
 299     }
 300   else
 301     {
 302       controller->spi_event = hw_event_queue_schedule (me, controller->clock,
 303                                                        m68hc11spi_clock,
 304                                                        NULL);
 305     }
 306
 307   if (check_interrupt)
 308     interrupts_update_pending (&m68hc11_cpu->cpu_interrupts);
 309 }
 310
 311 /* Flags of the SPCR register.  */
 312 io_reg_desc spcr_desc[] = {
 313   { M6811_SPIE, "SPIE ", "Serial Peripheral Interrupt Enable" },
 314   { M6811_SPE,  "SPE  ",  "Serial Peripheral System Enable" },
 315   { M6811_DWOM, "DWOM ", "Port D Wire-OR mode option" },
 316   { M6811_MSTR, "MSTR ", "Master Mode Select" },
 317   { M6811_CPOL, "CPOL ", "Clock Polarity" },
 318   { M6811_CPHA, "CPHA ", "Clock Phase" },
 319   { M6811_SPR1, "SPR1 ", "SPI Clock Rate Select" },
 320   { M6811_SPR0, "SPR0 ", "SPI Clock Rate Select" },
 321   { 0,  0, 0 }
 322 };
 323
 324
 325 /* Flags of the SPSR register.  */
 326 io_reg_desc spsr_desc[] = {
 327   { M6811_SPIF, "SPIF ", "SPI Transfer Complete flag" },
 328   { M6811_WCOL, "WCOL ", "Write Collision" },
 329   { M6811_MODF, "MODF ", "Mode Fault" },
 330   { 0,  0, 0 }
 331 };
 332
 333 static void
 334 m68hc11spi_info (struct hw *me)
 335 {
 336   SIM_DESC sd;
 337   uint16_t base = 0;
 338   sim_cpu *cpu;
 339   struct m68hc11_sim_cpu *m68hc11_cpu;
 340   struct m68hc11spi *controller;
 341   uint8_t val;
 342
 343   sd = hw_system (me);
 344   cpu = STATE_CPU (sd, 0);
 345   m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 346   controller = hw_data (me);
 347
 348   sim_io_printf (sd, "M68HC11 SPI:\n");
 349
 350   base = cpu_get_io_base (cpu);
 351
 352   val = m68hc11_cpu->ios[M6811_SPCR];
 353   print_io_byte (sd, "SPCR", spcr_desc, val, base + M6811_SPCR);
 354   sim_io_printf (sd, "\n");
 355
 356   val = m68hc11_cpu->ios[M6811_SPSR];
 357   print_io_byte (sd, "SPSR", spsr_desc, val, base + M6811_SPSR);
 358   sim_io_printf (sd, "\n");
 359
 360   if (controller->spi_event)
 361     {
 362       int64_t t;
 363
 364       sim_io_printf (sd, "  SPI has %d bits to send\n",
 365                      controller->tx_bit + 1);
 366       t = hw_event_remain_time (me, controller->spi_event);
 367       sim_io_printf (sd, "  SPI current bit-cycle finished in %s\n",
 368                      cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
 369
 370       t += (controller->tx_bit + 1) * 2 * controller->clock;
 371       sim_io_printf (sd, "  SPI operation finished in %s\n",
 372                      cycle_to_string (cpu, t, PRINT_TIME | PRINT_CYCLE));
 373     }
 374 }
 375
 376 static int
 377 m68hc11spi_ioctl (struct hw *me,
 378                   hw_ioctl_request request,
 379                   va_list ap)
 380 {
 381   m68hc11spi_info (me);
 382   return 0;
 383 }
 384
 385 /* generic read/write */
 386
 387 static unsigned
 388 m68hc11spi_io_read_buffer (struct hw *me,
 389                            void *dest,
 390                            int space,
 391                            unsigned_word base,
 392                            unsigned nr_bytes)
 393 {
 394   SIM_DESC sd;
 395   struct m68hc11spi *controller;
 396   sim_cpu *cpu;
 397   struct m68hc11_sim_cpu *m68hc11_cpu;
 398   uint8_t val;
 399
 400   HW_TRACE ((me, "read 0x%08lx %d", (long) base, (int) nr_bytes));
 401
 402   sd  = hw_system (me);
 403   cpu = STATE_CPU (sd, 0);
 404   m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 405   controller = hw_data (me);
 406
 407   switch (base)
 408     {
 409     case M6811_SPSR:
 410       controller->rx_clear_scsr = m68hc11_cpu->ios[M6811_SCSR]
 411         & (M6811_SPIF | M6811_WCOL | M6811_MODF);
 412
 413     case M6811_SPCR:
 414       val = m68hc11_cpu->ios[base];
 415       break;
 416
 417     case M6811_SPDR:
 418       if (controller->rx_clear_scsr)
 419         {
 420           m68hc11_cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
 421           controller->rx_clear_scsr = 0;
 422           interrupts_update_pending (&m68hc11_cpu->cpu_interrupts);
 423         }
 424       val = controller->rx_char;
 425       break;
 426
 427     default:
 428       return 0;
 429     }
 430   *((uint8_t*) dest) = val;
 431   return 1;
 432 }
 433
 434 static unsigned
 435 m68hc11spi_io_write_buffer (struct hw *me,
 436                             const void *source,
 437                             int space,
 438                             unsigned_word base,
 439                             unsigned nr_bytes)
 440 {
 441   SIM_DESC sd;
 442   struct m68hc11spi *controller;
 443   sim_cpu *cpu;
 444   struct m68hc11_sim_cpu *m68hc11_cpu;
 445   uint8_t val;
 446
 447   HW_TRACE ((me, "write 0x%08lx %d", (long) base, (int) nr_bytes));
 448
 449   sd  = hw_system (me);
 450   cpu = STATE_CPU (sd, 0);
 451   m68hc11_cpu = M68HC11_SIM_CPU (cpu);
 452   controller = hw_data (me);
 453
 454   val = *((const uint8_t*) source);
 455   switch (base)
 456     {
 457     case M6811_SPCR:
 458       m68hc11_cpu->ios[M6811_SPCR] = val;
 459
 460       /* The SPI clock rate is 2, 4, 16, 32 of the internal CPU clock.
 461          We have to drive the clock pin and need a 2x faster clock.  */
 462       switch (val & (M6811_SPR1 | M6811_SPR0))
 463         {
 464         case 0:
 465           controller->clock = 1;
 466           break;
 467
 468         case 1:
 469           controller->clock = 2;
 470           break;
 471
 472         case 2:
 473           controller->clock = 8;
 474           break;
 475
 476         default:
 477           controller->clock = 16;
 478           break;
 479         }
 480
 481       /* Set the clock pin.  */
 482       if ((val & M6811_CPOL)
 483           && (controller->spi_event == 0
 484               || ((val & M6811_CPHA) && controller->mode == 1)))
 485         controller->clk_pin = 1;
 486       else
 487         controller->clk_pin = 0;
 488
 489       set_bit_port (me, cpu, M6811_PORTD, (1 << 4), controller->clk_pin);
 490       break;
 491
 492       /* Can't write to SPSR.  */
 493     case M6811_SPSR:
 494       break;
 495
 496     case M6811_SPDR:
 497       if (!(m68hc11_cpu->ios[M6811_SPCR] & M6811_SPE))
 498         {
 499           return 0;
 500         }
 501
 502       if (controller->rx_clear_scsr)
 503         {
 504           m68hc11_cpu->ios[M6811_SPSR] &= ~controller->rx_clear_scsr;
 505           controller->rx_clear_scsr = 0;
 506           interrupts_update_pending (&m68hc11_cpu->cpu_interrupts);
 507         }
 508
 509       /* If transfer is taking place, a write to SPDR
 510          generates a collision.  */
 511       if (controller->spi_event)
 512         {
 513           m68hc11_cpu->ios[M6811_SPSR] |= M6811_WCOL;
 514           break;
 515         }
 516
 517       /* Refuse the write if there was no read of SPSR.  */
 518       /* ???? TBD. */
 519
 520       /* Prepare to send a byte.  */
 521       controller->tx_char = val;
 522       controller->mode   = SPI_START_BYTE;
 523
 524       /* Toggle clock pin internal value when CPHA is 0 so that
 525          it will really change in the middle of a bit.  */
 526       if (!(m68hc11_cpu->ios[M6811_SPCR] & M6811_CPHA))
 527         controller->clk_pin = ~controller->clk_pin;
 528
 529       m68hc11_cpu->ios[M6811_SPDR] = val;
 530
 531       /* Activate transmission.  */
 532       m68hc11spi_clock (me, NULL);
 533       break;
 534
 535     default:
 536       return 0;
 537     }
 538   return nr_bytes;
 539 }
 540
 541
 542 const struct hw_descriptor dv_m68hc11spi_descriptor[] = {
 543   { "m68hc11spi", m68hc11spi_finish },
 544   { "m68hc12spi", m68hc11spi_finish },
 545   { NULL },
 546 };
 547