1 /* dv-m68hc11tim.c -- Simulation of the 68HC11 timer devices.
2 Copyright (C) 1999, 2000, 2002, 2003, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
4 Written by Stephane Carrez (stcarrez@nerim.fr)
5 (From a driver model Contributed by Cygnus Solutions.)
7 This file is part of the program GDB, the GNU debugger.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>.
27 #include "sim-assert.h"
32 m68hc11tim - m68hc11 timer devices
37 Implements the m68hc11 timer as described in Chapter 10
50 Reset the timer device. This port must be connected to
51 the cpu-reset output port.
55 Input capture. This port must be connected to the input
56 captures. It latches the current TCNT free running counter
57 into one of the three input capture registers.
72 static const struct hw_port_descriptor m68hc11tim_ports
[] =
74 { "reset", RESET_PORT
, 0, input_port
, },
75 { "capture", CAPTURE
, 0, input_port
, },
80 /* Timer Controller information. */
83 unsigned long cop_delay
;
84 unsigned long rti_delay
;
85 unsigned long ovf_delay
;
86 signed64 clock_prescaler
;
88 signed64 cop_prev_interrupt
;
89 signed64 rti_prev_interrupt
;
91 /* Periodic timers. */
92 struct hw_event
*rti_timer_event
;
93 struct hw_event
*cop_timer_event
;
94 struct hw_event
*tof_timer_event
;
95 struct hw_event
*cmp_timer_event
;
100 /* Finish off the partially created hw device. Attach our local
101 callbacks. Wire up our port names etc. */
103 static hw_io_read_buffer_method m68hc11tim_io_read_buffer
;
104 static hw_io_write_buffer_method m68hc11tim_io_write_buffer
;
105 static hw_port_event_method m68hc11tim_port_event
;
106 static hw_ioctl_method m68hc11tim_ioctl
;
108 #define M6811_TIMER_FIRST_REG (M6811_TCTN)
109 #define M6811_TIMER_LAST_REG (M6811_PACNT)
113 attach_m68hc11tim_regs (struct hw
*me
,
114 struct m68hc11tim
*controller
)
116 hw_attach_address (hw_parent (me
), M6811_IO_LEVEL
, io_map
,
117 M6811_TIMER_FIRST_REG
,
118 M6811_TIMER_LAST_REG
- M6811_TIMER_FIRST_REG
+ 1,
123 m68hc11tim_finish (struct hw
*me
)
125 struct m68hc11tim
*controller
;
127 controller
= HW_ZALLOC (me
, struct m68hc11tim
);
128 set_hw_data (me
, controller
);
129 set_hw_io_read_buffer (me
, m68hc11tim_io_read_buffer
);
130 set_hw_io_write_buffer (me
, m68hc11tim_io_write_buffer
);
131 set_hw_ports (me
, m68hc11tim_ports
);
132 set_hw_port_event (me
, m68hc11tim_port_event
);
134 set_hw_ioctl (me
, m68hc11tim_ioctl
);
136 me
->to_ioctl
= m68hc11tim_ioctl
;
139 /* Preset defaults. */
140 controller
->clock_prescaler
= 1;
141 controller
->tcnt_adjust
= 0;
143 /* Attach ourself to our parent bus. */
144 attach_m68hc11tim_regs (me
, controller
);
148 /* An event arrives on an interrupt port. */
151 m68hc11tim_port_event (struct hw
*me
,
158 struct m68hc11tim
*controller
;
163 controller
= hw_data (me
);
165 cpu
= STATE_CPU (sd
, 0);
170 HW_TRACE ((me
, "Timer reset"));
172 /* Cancel all timer events. */
173 if (controller
->rti_timer_event
)
175 hw_event_queue_deschedule (me
, controller
->rti_timer_event
);
176 controller
->rti_timer_event
= 0;
177 controller
->rti_prev_interrupt
= 0;
179 if (controller
->cop_timer_event
)
181 hw_event_queue_deschedule (me
, controller
->cop_timer_event
);
182 controller
->cop_timer_event
= 0;
183 controller
->cop_prev_interrupt
= 0;
185 if (controller
->tof_timer_event
)
187 hw_event_queue_deschedule (me
, controller
->tof_timer_event
);
188 controller
->tof_timer_event
= 0;
190 if (controller
->cmp_timer_event
)
192 hw_event_queue_deschedule (me
, controller
->cmp_timer_event
);
193 controller
->cmp_timer_event
= 0;
196 /* Reset the state of Timer registers. This also restarts
197 the timer events (overflow and RTI clock). The pending
198 flags (TFLG2) must be cleared explicitly here. */
200 cpu
->ios
[M6811_TFLG2
] = 0;
201 m68hc11tim_io_write_buffer (me
, &val
, io_map
,
202 (unsigned_word
) M6811_TMSK2
, 1);
203 m68hc11tim_io_write_buffer (me
, &val
, io_map
,
204 (unsigned_word
) M6811_PACTL
, 1);
209 tcnt
= (uint16
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
210 / controller
->clock_prescaler
);
216 cpu
->ios
[level
] = tcnt
>> 8;
217 cpu
->ios
[level
+ 1] = tcnt
;
221 hw_abort (me
, "Invalid event parameter %d", level
);
227 hw_abort (me
, "Event on unknown port %d", my_port
);
241 m68hc11tim_timer_event (struct hw
*me
, void *data
)
244 struct m68hc11tim
*controller
;
246 enum event_type type
;
248 struct hw_event
**eventp
;
249 int check_interrupt
= 0;
252 unsigned long tcnt_internal
;
253 unsigned long tcnt
, tcnt_prev
;
254 signed64 tcnt_insn_end
;
255 signed64 tcnt_insn_start
;
259 controller
= hw_data (me
);
261 cpu
= STATE_CPU (sd
, 0);
262 type
= (enum event_type
) ((long) data
) & 0x0FF;
263 events
= STATE_EVENTS (sd
);
269 eventp
= &controller
->cop_timer_event
;
270 delay
= controller
->cop_delay
;
271 delay
= controller
->cop_prev_interrupt
+ controller
->cop_delay
;
272 controller
->cop_prev_interrupt
= delay
;
273 delay
= delay
- cpu
->cpu_absolute_cycle
;
275 delay
+= events
->nr_ticks_to_process
;
279 eventp
= &controller
->rti_timer_event
;
280 delay
= controller
->rti_prev_interrupt
+ controller
->rti_delay
;
282 if (((long) (data
) & 0x0100) == 0)
284 cpu
->ios
[M6811_TFLG2
] |= M6811_RTIF
;
286 controller
->rti_prev_interrupt
= delay
;
287 delay
+= controller
->rti_delay
;
289 delay
= delay
- cpu
->cpu_absolute_cycle
;
290 delay
+= events
->nr_ticks_to_process
;
294 /* Compute the 68HC11 internal free running counter. */
295 tcnt_internal
= (cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
);
297 /* We must take into account the prescaler that comes
298 before the counter (it's a power of 2). */
299 tcnt_internal
&= 0x0ffff * controller
->clock_prescaler
;
301 /* Compute the time when the overflow will occur. It occurs when
302 the counter increments from 0x0ffff to 0x10000 (and thus resets). */
303 delay
= (0x10000 * controller
->clock_prescaler
) - tcnt_internal
;
305 /* The 'nr_ticks_to_process' will be subtracted when the event
307 delay
+= events
->nr_ticks_to_process
;
309 eventp
= &controller
->tof_timer_event
;
310 if (((long) (data
) & 0x100) == 0)
312 cpu
->ios
[M6811_TFLG2
] |= M6811_TOF
;
318 /* Compute value of TCNT register (64-bit precision) at beginning
319 and end of instruction. */
320 tcnt_insn_end
= (cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
);
321 tcnt_insn_start
= (tcnt_insn_end
- cpu
->cpu_current_cycle
);
323 /* TCNT value at beginning of current instruction. */
324 tcnt_prev
= (tcnt_insn_start
/ controller
->clock_prescaler
) & 0x0ffff;
326 /* TCNT value at end of current instruction. */
327 tcnt
= (tcnt_insn_end
/ controller
->clock_prescaler
) & 0x0ffff;
329 /* We must take into account the prescaler that comes
330 before the counter (it's a power of 2). */
331 tcnt_internal
= tcnt_insn_end
;
332 tcnt_internal
&= 0x0ffff * controller
->clock_prescaler
;
334 flags
= cpu
->ios
[M6811_TMSK1
];
336 delay
= 65536 * controller
->clock_prescaler
;
338 /* Scan each output compare register to see if one matches
339 the free running counter. Set the corresponding OCi flag
340 if the output compare is enabled. */
341 for (i
= M6811_TOC1
; i
<= M6811_TOC5
; i
+= 2, mask
>>= 1)
343 unsigned long compare
;
345 compare
= (cpu
->ios
[i
] << 8) + cpu
->ios
[i
+ 1];
347 /* See if compare is reached; handle wrap arround. */
348 if ((compare
>= tcnt_prev
&& compare
<= tcnt
&& tcnt_prev
< tcnt
)
349 || (compare
>= tcnt_prev
&& tcnt_prev
> tcnt
)
350 || (compare
< tcnt
&& tcnt_prev
> tcnt
))
355 dt
= 0x10000 - compare
- tcnt
;
359 cpu
->ios
[M6811_TFLG1
] |= mask
;
361 /* Raise interrupt now at the correct CPU cycle so that
362 we can find the interrupt latency. */
363 cpu
->cpu_absolute_cycle
-= dt
;
364 interrupts_update_pending (&cpu
->cpu_interrupts
);
365 cpu
->cpu_absolute_cycle
+= dt
;
368 /* Compute how many times for the next match.
369 Use the internal counter value to take into account the
370 prescaler accurately. */
371 compare
= compare
* controller
->clock_prescaler
;
372 if (compare
> tcnt_internal
)
373 compare
= compare
- tcnt_internal
;
375 compare
= compare
- tcnt_internal
376 + 65536 * controller
->clock_prescaler
;
382 /* Deactivate the compare timer if no output compare is enabled. */
383 if ((flags
& 0xF8) == 0)
386 delay
+= events
->nr_ticks_to_process
;
388 eventp
= &controller
->cmp_timer_event
;
398 hw_event_queue_deschedule (me
, *eventp
);
404 *eventp
= hw_event_queue_schedule (me
, delay
,
405 m68hc11tim_timer_event
,
410 interrupts_update_pending (&cpu
->cpu_interrupts
);
414 /* Descriptions of the Timer I/O ports. These descriptions are only used to
415 give information of the Timer device under GDB. */
416 io_reg_desc tmsk1_desc
[] = {
417 { M6811_OC1I
, "OC1I ", "Timer Output Compare 1 Interrupt Enable" },
418 { M6811_OC2I
, "OC2I ", "Timer Output Compare 2 Interrupt Enable" },
419 { M6811_OC3I
, "OC3I ", "Timer Output Compare 3 Interrupt Enable" },
420 { M6811_OC4I
, "OC4I ", "Timer Output Compare 4 Interrupt Enable" },
421 { M6811_OC5I
, "OC5I ", "Timer Input Capture 4 / Output Compare 5 Enable" },
422 { M6811_IC1I
, "IC1I ", "Timer Input Capture 1 Interrupt Enable" },
423 { M6811_IC2I
, "IC2I ", "Timer Input Capture 2 Interrupt Enable" },
424 { M6811_IC3I
, "IC3I ", "Timer Input Capture 3 Interrupt Enable" },
428 io_reg_desc tflg1_desc
[] = {
429 { M6811_OC1F
, "OC1F ", "Timer Output Compare 1 Interrupt Flag" },
430 { M6811_OC2F
, "OC2F ", "Timer Output Compare 2 Interrupt Flag" },
431 { M6811_OC3F
, "OC3F ", "Timer Output Compare 3 Interrupt Flag" },
432 { M6811_OC4F
, "OC4F ", "Timer Output Compare 4 Interrupt Flag" },
433 { M6811_OC5F
, "OC5F ", "Timer Input Capture 4 / Output Compare 5 Flag" },
434 { M6811_IC1F
, "IC1F ", "Timer Input Capture 1 Interrupt Flag" },
435 { M6811_IC2F
, "IC2F ", "Timer Input Capture 2 Interrupt Flag" },
436 { M6811_IC3F
, "IC3F ", "Timer Input Capture 3 Interrupt Flag" },
440 io_reg_desc tmsk2_desc
[] = {
441 { M6811_TOI
, "TOI ", "Timer Overflow Interrupt Enable" },
442 { M6811_RTII
, "RTII ", "RTI Interrupt Enable" },
443 { M6811_PAOVI
, "PAOVI ", "Pulse Accumulator Overflow Interrupt Enable" },
444 { M6811_PAII
, "PAII ", "Pulse Accumulator Interrupt Enable" },
445 { M6811_PR1
, "PR1 ", "Timer prescaler (PR1)" },
446 { M6811_PR0
, "PR0 ", "Timer prescaler (PR0)" },
447 { M6811_TPR_1
, "TPR_1 ", "Timer prescaler div 1" },
448 { M6811_TPR_4
, "TPR_4 ", "Timer prescaler div 4" },
449 { M6811_TPR_8
, "TPR_8 ", "Timer prescaler div 8" },
450 { M6811_TPR_16
, "TPR_16", "Timer prescaler div 16" },
454 io_reg_desc tflg2_desc
[] = {
455 { M6811_TOF
, "TOF ", "Timer Overflow Bit" },
456 { M6811_RTIF
, "RTIF ", "Read Time Interrupt Flag" },
457 { M6811_PAOVF
, "PAOVF ", "Pulse Accumulator Overflow Interrupt Flag" },
458 { M6811_PAIF
, "PAIF ", "Pulse Accumulator Input Edge" },
462 io_reg_desc pactl_desc
[] = {
463 { M6811_DDRA7
, "DDRA7 ", "Data Direction for Port A bit-7" },
464 { M6811_PAEN
, "PAEN ", "Pulse Accumulator System Enable" },
465 { M6811_PAMOD
, "PAMOD ", "Pulse Accumulator Mode" },
466 { M6811_PEDGE
, "PEDGE ", "Pulse Accumulator Edge Control" },
467 { M6811_RTR1
, "RTR1 ", "RTI Interrupt rate select (RTR1)" },
468 { M6811_RTR0
, "RTR0 ", "RTI Interrupt rate select (RTR0)" },
473 to_realtime (sim_cpu
*cpu
, signed64 t
)
475 return (double) (t
) / (double) (cpu
->cpu_frequency
/ 4);
479 cycle_to_string (sim_cpu
*cpu
, signed64 t
, int flags
)
487 if (flags
& PRINT_TIME
)
491 dt
= to_realtime (cpu
, t
);
493 sprintf (time_buf
, " (%3.1f us)", dt
* 1000000.0);
495 sprintf (time_buf
, " (%3.1f ms)", dt
* 1000.0);
497 sprintf (time_buf
, " (%3.1f s)", dt
);
500 if (flags
& PRINT_CYCLE
)
501 sprintf (cycle_buf
, " cycle%s",
505 sprintf (buf
, "%9lu%s%s", (unsigned long) t
, cycle_buf
, time_buf
);
507 sprintf (buf
, "%llu%s%s", t
, cycle_buf
, time_buf
);
512 m68hc11tim_print_timer (struct hw
*me
, const char *name
,
513 struct hw_event
*event
)
520 sim_io_printf (sd
, " No %s interrupt will be raised.\n", name
);
527 cpu
= STATE_CPU (sd
, 0);
529 t
= hw_event_remain_time (me
, event
);
530 sim_io_printf (sd
, " Next %s interrupt in %s\n",
531 name
, cycle_to_string (cpu
, t
, PRINT_TIME
| PRINT_CYCLE
));
536 m68hc11tim_info (struct hw
*me
)
541 struct m68hc11tim
*controller
;
546 cpu
= STATE_CPU (sd
, 0);
547 controller
= hw_data (me
);
549 sim_io_printf (sd
, "M68HC11 Timer:\n");
551 base
= cpu_get_io_base (cpu
);
554 val16
= (cpu
->ios
[M6811_TIC1_H
] << 8) + cpu
->ios
[M6811_TIC1_L
];
555 print_io_word (sd
, "TIC1 ", 0, val16
, base
+ M6811_TIC1
);
556 sim_io_printf (sd
, "\n");
559 val16
= (cpu
->ios
[M6811_TIC2_H
] << 8) + cpu
->ios
[M6811_TIC2_L
];
560 print_io_word (sd
, "TIC2 ", 0, val16
, base
+ M6811_TIC2
);
561 sim_io_printf (sd
, "\n");
564 val16
= (cpu
->ios
[M6811_TIC3_H
] << 8) + cpu
->ios
[M6811_TIC3_L
];
565 print_io_word (sd
, "TIC3 ", 0, val16
, base
+ M6811_TIC3
);
566 sim_io_printf (sd
, "\n");
569 val16
= (cpu
->ios
[M6811_TOC1_H
] << 8) + cpu
->ios
[M6811_TOC1_L
];
570 print_io_word (sd
, "TOC1 ", 0, val16
, base
+ M6811_TOC1
);
571 sim_io_printf (sd
, "\n");
574 val16
= (cpu
->ios
[M6811_TOC2_H
] << 8) + cpu
->ios
[M6811_TOC2_L
];
575 print_io_word (sd
, "TOC2 ", 0, val16
, base
+ M6811_TOC2
);
576 sim_io_printf (sd
, "\n");
579 val16
= (cpu
->ios
[M6811_TOC3_H
] << 8) + cpu
->ios
[M6811_TOC3_L
];
580 print_io_word (sd
, "TOC3 ", 0, val16
, base
+ M6811_TOC3
);
581 sim_io_printf (sd
, "\n");
584 val16
= (cpu
->ios
[M6811_TOC4_H
] << 8) + cpu
->ios
[M6811_TOC4_L
];
585 print_io_word (sd
, "TOC4 ", 0, val16
, base
+ M6811_TOC4
);
586 sim_io_printf (sd
, "\n");
589 val16
= (cpu
->ios
[M6811_TOC5_H
] << 8) + cpu
->ios
[M6811_TOC5_L
];
590 print_io_word (sd
, "TOC5 ", 0, val16
, base
+ M6811_TOC5
);
591 sim_io_printf (sd
, "\n");
594 val
= cpu
->ios
[M6811_TMSK1
];
595 print_io_byte (sd
, "TMSK1 ", tmsk1_desc
, val
, base
+ M6811_TMSK1
);
596 sim_io_printf (sd
, "\n");
599 val
= cpu
->ios
[M6811_TFLG1
];
600 print_io_byte (sd
, "TFLG1", tflg1_desc
, val
, base
+ M6811_TFLG1
);
601 sim_io_printf (sd
, "\n");
603 val
= cpu
->ios
[M6811_TMSK2
];
604 print_io_byte (sd
, "TMSK2 ", tmsk2_desc
, val
, base
+ M6811_TMSK2
);
605 sim_io_printf (sd
, "\n");
607 val
= cpu
->ios
[M6811_TFLG2
];
608 print_io_byte (sd
, "TFLG2", tflg2_desc
, val
, base
+ M6811_TFLG2
);
609 sim_io_printf (sd
, "\n");
611 val
= cpu
->ios
[M6811_PACTL
];
612 print_io_byte (sd
, "PACTL", pactl_desc
, val
, base
+ M6811_PACTL
);
613 sim_io_printf (sd
, "\n");
615 val
= cpu
->ios
[M6811_PACNT
];
616 print_io_byte (sd
, "PACNT", 0, val
, base
+ M6811_PACNT
);
617 sim_io_printf (sd
, "\n");
619 /* Give info about the next timer interrupts. */
620 m68hc11tim_print_timer (me
, "RTI", controller
->rti_timer_event
);
621 m68hc11tim_print_timer (me
, "COP", controller
->cop_timer_event
);
622 m68hc11tim_print_timer (me
, "OVERFLOW", controller
->tof_timer_event
);
623 m68hc11tim_print_timer (me
, "COMPARE", controller
->cmp_timer_event
);
627 m68hc11tim_ioctl (struct hw
*me
,
628 hw_ioctl_request request
,
631 m68hc11tim_info (me
);
635 /* generic read/write */
638 m68hc11tim_io_read_buffer (struct hw
*me
,
645 struct m68hc11tim
*controller
;
650 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
653 cpu
= STATE_CPU (sd
, 0);
654 controller
= hw_data (me
);
660 /* The cpu_absolute_cycle is updated after each instruction.
661 Reading in a 16-bit register will be split in two accesses
662 but this will be atomic within the simulator. */
664 val
= (uint8
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
665 / (controller
->clock_prescaler
* 256));
669 val
= (uint8
) ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
670 / controller
->clock_prescaler
);
674 val
= cpu
->ios
[base
];
677 *((unsigned8
*) dest
) = val
;
678 dest
= (char*) dest
+ 1;
687 m68hc11tim_io_write_buffer (struct hw
*me
,
694 struct m68hc11tim
*controller
;
698 int reset_compare
= 0;
699 int reset_overflow
= 0;
702 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
705 cpu
= STATE_CPU (sd
, 0);
706 controller
= hw_data (me
);
710 val
= *((const unsigned8
*) source
);
713 /* Set the timer counter low part, trying to preserve the low part.
714 We compute the absolute cycle adjustment that we have to apply
715 to obtain the timer current value. Computation must be made
716 in 64-bit to avoid overflow problems. */
718 adj
= ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
719 / (controller
->clock_prescaler
* (signed64
) 256)) & 0x0FF;
720 adj
= cpu
->cpu_absolute_cycle
721 - (adj
* controller
->clock_prescaler
* (signed64
) 256)
722 - ((signed64
) adj
* controller
->clock_prescaler
);
723 controller
->tcnt_adjust
= adj
;
729 adj
= ((cpu
->cpu_absolute_cycle
- controller
->tcnt_adjust
)
730 / controller
->clock_prescaler
) & 0x0ff;
731 adj
= cpu
->cpu_absolute_cycle
732 - ((signed64
) val
* controller
->clock_prescaler
* (signed64
) 256)
733 - (adj
* controller
->clock_prescaler
);
734 controller
->tcnt_adjust
= adj
;
741 /* Timer prescaler cannot be changed after 64 bus cycles. */
742 if (cpu
->cpu_absolute_cycle
>= 64)
744 val
&= ~(M6811_PR1
| M6811_PR0
);
745 val
|= cpu
->ios
[M6811_TMSK2
] & (M6811_PR1
| M6811_PR0
);
747 switch (val
& (M6811_PR1
| M6811_PR0
))
759 case M6811_PR1
| M6811_PR0
:
763 if (cpu
->cpu_absolute_cycle
< 64)
766 controller
->clock_prescaler
= n
;
768 cpu
->ios
[base
] = val
;
769 interrupts_update_pending (&cpu
->cpu_interrupts
);
773 n
= (1 << ((val
& (M6811_RTR1
| M6811_RTR0
))));
774 cpu
->ios
[base
] = val
;
776 controller
->rti_delay
= (long) (n
) * 8192;
777 m68hc11tim_timer_event (me
, (void*) (RTI_EVENT
| 0x100));
781 val
&= cpu
->ios
[M6811_TFLG2
];
782 cpu
->ios
[M6811_TFLG2
] &= ~val
;
783 interrupts_update_pending (&cpu
->cpu_interrupts
);
787 cpu
->ios
[M6811_TMSK1
] = val
;
788 interrupts_update_pending (&cpu
->cpu_interrupts
);
793 val
&= cpu
->ios
[M6811_TFLG1
];
794 cpu
->ios
[M6811_TFLG1
] &= ~val
;
795 interrupts_update_pending (&cpu
->cpu_interrupts
);
803 cpu
->ios
[base
] = val
;
809 cpu
->ios
[base
] = val
;
813 cpu
->ios
[base
] = val
;
820 source
= (char*) source
+ 1;
823 /* Re-compute the next timer compare event. */
826 m68hc11tim_timer_event (me
, (void*) (COMPARE_EVENT
));
830 m68hc11tim_timer_event (me
, (void*) (OVERFLOW_EVENT
| 0x100));
836 const struct hw_descriptor dv_m68hc11tim_descriptor
[] = {
837 { "m68hc11tim", m68hc11tim_finish
},
838 { "m68hc12tim", m68hc11tim_finish
},