1 /* interp.c -- Simulator for Motorola 68HC11/68HC12
2 Copyright (C) 1999-2022 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
24 #include "sim-assert.h"
26 #include "sim-options.h"
28 #include "hw-device.h"
30 #include "elf32-m68hc1x.h"
33 # define MONITOR_BASE (0x0C000)
34 # define MONITOR_SIZE (0x04000)
37 static void sim_get_info (SIM_DESC sd
, char *cmd
);
45 struct sim_info_list dev_list_68hc11
[] = {
47 {"timer", "/m68hc11/m68hc11tim"},
48 {"sio", "/m68hc11/m68hc11sio"},
49 {"spi", "/m68hc11/m68hc11spi"},
50 {"eeprom", "/m68hc11/m68hc11eepr"},
54 struct sim_info_list dev_list_68hc12
[] = {
56 {"timer", "/m68hc12/m68hc12tim"},
57 {"sio", "/m68hc12/m68hc12sio"},
58 {"spi", "/m68hc12/m68hc12spi"},
59 {"eeprom", "/m68hc12/m68hc12eepr"},
63 /* Cover function of sim_state_free to free the cpu buffers as well. */
66 free_state (SIM_DESC sd
)
68 if (STATE_MODULES (sd
) != NULL
)
69 sim_module_uninstall (sd
);
74 /* Give some information about the simulator. */
76 sim_get_info (SIM_DESC sd
, char *cmd
)
80 cpu
= STATE_CPU (sd
, 0);
81 if (cmd
!= 0 && (cmd
[0] == ' ' || cmd
[0] == '-'))
85 struct sim_info_list
*dev_list
;
86 const struct bfd_arch_info
*arch
;
88 arch
= STATE_ARCHITECTURE (sd
);
91 if (arch
->arch
== bfd_arch_m68hc11
)
92 dev_list
= dev_list_68hc11
;
94 dev_list
= dev_list_68hc12
;
96 for (i
= 0; dev_list
[i
].name
; i
++)
97 if (strcmp (cmd
, dev_list
[i
].name
) == 0)
100 if (dev_list
[i
].name
== 0)
102 sim_io_eprintf (sd
, "Device '%s' not found.\n", cmd
);
103 sim_io_eprintf (sd
, "Valid devices: cpu timer sio eeprom\n");
106 hw_dev
= sim_hw_parse (sd
, "%s", dev_list
[i
].device
);
109 sim_io_eprintf (sd
, "Device '%s' not found\n", dev_list
[i
].device
);
112 hw_ioctl (hw_dev
, 23, 0);
117 interrupts_info (sd
, &cpu
->cpu_interrupts
);
122 sim_board_reset (SIM_DESC sd
)
126 const struct bfd_arch_info
*arch
;
127 const char *cpu_type
;
129 cpu
= STATE_CPU (sd
, 0);
130 arch
= STATE_ARCHITECTURE (sd
);
132 /* hw_cpu = sim_hw_parse (sd, "/"); */
133 if (arch
->arch
== bfd_arch_m68hc11
)
135 cpu
->cpu_type
= CPU_M6811
;
136 cpu_type
= "/m68hc11";
140 cpu
->cpu_type
= CPU_M6812
;
141 cpu_type
= "/m68hc12";
144 hw_cpu
= sim_hw_parse (sd
, "%s", cpu_type
);
147 sim_io_eprintf (sd
, "%s cpu not found in device tree.", cpu_type
);
152 hw_port_event (hw_cpu
, 3, 0);
157 sim_hw_configure (SIM_DESC sd
)
159 const struct bfd_arch_info
*arch
;
160 struct hw
*device_tree
;
163 arch
= STATE_ARCHITECTURE (sd
);
167 cpu
= STATE_CPU (sd
, 0);
168 cpu
->cpu_configured_arch
= arch
;
169 device_tree
= sim_hw_parse (sd
, "/");
170 if (arch
->arch
== bfd_arch_m68hc11
)
172 cpu
->cpu_interpretor
= cpu_interp_m6811
;
173 if (hw_tree_find_property (device_tree
, "/m68hc11/reg") == 0)
175 /* Allocate core managed memory */
178 sim_do_commandf (sd
, "memory region 0x%x@%d,0x%x",
179 /* MONITOR_BASE, MONITOR_SIZE */
180 0x8000, M6811_RAM_LEVEL
, 0x8000);
181 sim_do_commandf (sd
, "memory region 0x000@%d,0x8000",
183 sim_hw_parse (sd
, "/m68hc11/reg 0x1000 0x03F");
184 if (cpu
->bank_start
< cpu
->bank_end
)
186 sim_do_commandf (sd
, "memory region 0x%x@%d,0x100000",
187 cpu
->bank_virtual
, M6811_RAM_LEVEL
);
188 sim_hw_parse (sd
, "/m68hc11/use_bank 1");
191 if (cpu
->cpu_start_mode
)
193 sim_hw_parse (sd
, "/m68hc11/mode %s", cpu
->cpu_start_mode
);
195 if (hw_tree_find_property (device_tree
, "/m68hc11/m68hc11sio/reg") == 0)
197 sim_hw_parse (sd
, "/m68hc11/m68hc11sio/reg 0x2b 0x5");
198 sim_hw_parse (sd
, "/m68hc11/m68hc11sio/backend stdio");
199 sim_hw_parse (sd
, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11sio");
201 if (hw_tree_find_property (device_tree
, "/m68hc11/m68hc11tim/reg") == 0)
203 /* M68hc11 Timer configuration. */
204 sim_hw_parse (sd
, "/m68hc11/m68hc11tim/reg 0x1b 0x5");
205 sim_hw_parse (sd
, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11tim");
206 sim_hw_parse (sd
, "/m68hc11 > capture capture /m68hc11/m68hc11tim");
209 /* Create the SPI device. */
210 if (hw_tree_find_property (device_tree
, "/m68hc11/m68hc11spi/reg") == 0)
212 sim_hw_parse (sd
, "/m68hc11/m68hc11spi/reg 0x28 0x3");
213 sim_hw_parse (sd
, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11spi");
215 if (hw_tree_find_property (device_tree
, "/m68hc11/nvram/reg") == 0)
217 /* M68hc11 persistent ram configuration. */
218 sim_hw_parse (sd
, "/m68hc11/nvram/reg 0x0 256");
219 sim_hw_parse (sd
, "/m68hc11/nvram/file m68hc11.ram");
220 sim_hw_parse (sd
, "/m68hc11/nvram/mode save-modified");
221 /*sim_hw_parse (sd, "/m68hc11 > cpu-reset reset /m68hc11/pram"); */
223 if (hw_tree_find_property (device_tree
, "/m68hc11/m68hc11eepr/reg") == 0)
225 sim_hw_parse (sd
, "/m68hc11/m68hc11eepr/reg 0xb000 512");
226 sim_hw_parse (sd
, "/m68hc11 > cpu-reset reset /m68hc11/m68hc11eepr");
228 sim_hw_parse (sd
, "/m68hc11 > port-a cpu-write-port /m68hc11");
229 sim_hw_parse (sd
, "/m68hc11 > port-b cpu-write-port /m68hc11");
230 sim_hw_parse (sd
, "/m68hc11 > port-c cpu-write-port /m68hc11");
231 sim_hw_parse (sd
, "/m68hc11 > port-d cpu-write-port /m68hc11");
232 cpu
->hw_cpu
= sim_hw_parse (sd
, "/m68hc11");
236 cpu
->cpu_interpretor
= cpu_interp_m6812
;
237 if (hw_tree_find_property (device_tree
, "/m68hc12/reg") == 0)
239 /* Allocate core external memory. */
240 sim_do_commandf (sd
, "memory region 0x%x@%d,0x%x",
241 0x8000, M6811_RAM_LEVEL
, 0x8000);
242 sim_do_commandf (sd
, "memory region 0x000@%d,0x8000",
244 if (cpu
->bank_start
< cpu
->bank_end
)
246 sim_do_commandf (sd
, "memory region 0x%x@%d,0x100000",
247 cpu
->bank_virtual
, M6811_RAM_LEVEL
);
248 sim_hw_parse (sd
, "/m68hc12/use_bank 1");
250 sim_hw_parse (sd
, "/m68hc12/reg 0x0 0x3FF");
253 if (!hw_tree_find_property (device_tree
, "/m68hc12/m68hc12sio@1/reg"))
255 sim_hw_parse (sd
, "/m68hc12/m68hc12sio@1/reg 0xC0 0x8");
256 sim_hw_parse (sd
, "/m68hc12/m68hc12sio@1/backend stdio");
257 sim_hw_parse (sd
, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12sio@1");
259 if (hw_tree_find_property (device_tree
, "/m68hc12/m68hc12tim/reg") == 0)
261 /* M68hc11 Timer configuration. */
262 sim_hw_parse (sd
, "/m68hc12/m68hc12tim/reg 0x1b 0x5");
263 sim_hw_parse (sd
, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12tim");
264 sim_hw_parse (sd
, "/m68hc12 > capture capture /m68hc12/m68hc12tim");
267 /* Create the SPI device. */
268 if (hw_tree_find_property (device_tree
, "/m68hc12/m68hc12spi/reg") == 0)
270 sim_hw_parse (sd
, "/m68hc12/m68hc12spi/reg 0x28 0x3");
271 sim_hw_parse (sd
, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12spi");
273 if (hw_tree_find_property (device_tree
, "/m68hc12/nvram/reg") == 0)
275 /* M68hc11 persistent ram configuration. */
276 sim_hw_parse (sd
, "/m68hc12/nvram/reg 0x2000 8192");
277 sim_hw_parse (sd
, "/m68hc12/nvram/file m68hc12.ram");
278 sim_hw_parse (sd
, "/m68hc12/nvram/mode save-modified");
280 if (hw_tree_find_property (device_tree
, "/m68hc12/m68hc12eepr/reg") == 0)
282 sim_hw_parse (sd
, "/m68hc12/m68hc12eepr/reg 0x0800 2048");
283 sim_hw_parse (sd
, "/m68hc12 > cpu-reset reset /m68hc12/m68hc12eepr");
286 sim_hw_parse (sd
, "/m68hc12 > port-a cpu-write-port /m68hc12");
287 sim_hw_parse (sd
, "/m68hc12 > port-b cpu-write-port /m68hc12");
288 sim_hw_parse (sd
, "/m68hc12 > port-c cpu-write-port /m68hc12");
289 sim_hw_parse (sd
, "/m68hc12 > port-d cpu-write-port /m68hc12");
290 cpu
->hw_cpu
= sim_hw_parse (sd
, "/m68hc12");
295 /* Get the memory bank parameters by looking at the global symbols
296 defined by the linker. */
298 sim_get_bank_parameters (SIM_DESC sd
)
304 cpu
= STATE_CPU (sd
, 0);
306 addr
= trace_sym_value (sd
, BFD_M68HC11_BANK_START_NAME
);
308 cpu
->bank_start
= addr
;
310 size
= trace_sym_value (sd
, BFD_M68HC11_BANK_SIZE_NAME
);
314 addr
= trace_sym_value (sd
, BFD_M68HC11_BANK_VIRTUAL_NAME
);
316 cpu
->bank_virtual
= addr
;
318 cpu
->bank_end
= cpu
->bank_start
+ size
;
320 for (; size
> 1; size
>>= 1)
327 sim_prepare_for_program (SIM_DESC sd
, bfd
* abfd
)
332 cpu
= STATE_CPU (sd
, 0);
338 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
)
339 elf_flags
= elf_elfheader (abfd
)->e_flags
;
341 cpu
->cpu_elf_start
= bfd_get_start_address (abfd
);
342 /* See if any section sets the reset address */
343 cpu
->cpu_use_elf_start
= 1;
344 for (s
= abfd
->sections
; s
&& cpu
->cpu_use_elf_start
; s
= s
->next
)
346 if (s
->flags
& SEC_LOAD
)
350 size
= bfd_section_size (s
);
355 if (STATE_LOAD_AT_LMA_P (sd
))
356 lma
= bfd_section_lma (s
);
358 lma
= bfd_section_vma (s
);
360 if (lma
<= 0xFFFE && lma
+size
>= 0x10000)
361 cpu
->cpu_use_elf_start
= 0;
366 if (elf_flags
& E_M68HC12_BANKS
)
368 if (sim_get_bank_parameters (sd
) != 0)
369 sim_io_eprintf (sd
, "Memory bank parameters are not initialized\n");
373 if (!sim_hw_configure (sd
))
376 /* reset all state information */
377 sim_board_reset (sd
);
383 m68hc11_pc_get (sim_cpu
*cpu
)
385 return cpu_get_pc (cpu
);
389 m68hc11_pc_set (sim_cpu
*cpu
, sim_cia pc
)
391 cpu_set_pc (cpu
, pc
);
394 static int m68hc11_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
395 static int m68hc11_reg_store (SIM_CPU
*, int, unsigned char *, int);
398 sim_open (SIM_OPEN_KIND kind
, host_callback
*callback
,
399 bfd
*abfd
, char * const *argv
)
405 sd
= sim_state_alloc (kind
, callback
);
407 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
409 /* Set default options before parsing user options. */
410 current_target_byte_order
= BFD_ENDIAN_BIG
;
412 /* The cpu data is kept in a separately allocated chunk of memory. */
413 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
419 cpu
= STATE_CPU (sd
, 0);
421 cpu_initialize (sd
, cpu
);
423 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
429 /* The parser will print an error message for us, so we silently return. */
430 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
432 /* Uninstall the modules to avoid memory leaks,
433 file descriptor leaks, etc. */
438 /* Check for/establish the a reference program image. */
439 if (sim_analyze_program (sd
, STATE_PROG_FILE (sd
), abfd
) != SIM_RC_OK
)
445 /* Establish any remaining configuration options. */
446 if (sim_config (sd
) != SIM_RC_OK
)
452 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
454 /* Uninstall the modules to avoid memory leaks,
455 file descriptor leaks, etc. */
459 if (sim_prepare_for_program (sd
, abfd
) != SIM_RC_OK
)
465 /* CPU specific initialization. */
466 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
468 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
470 CPU_REG_FETCH (cpu
) = m68hc11_reg_fetch
;
471 CPU_REG_STORE (cpu
) = m68hc11_reg_store
;
472 CPU_PC_FETCH (cpu
) = m68hc11_pc_get
;
473 CPU_PC_STORE (cpu
) = m68hc11_pc_set
;
479 /* Generic implementation of sim_engine_run that works within the
480 sim_engine setjmp/longjmp framework. */
483 sim_engine_run (SIM_DESC sd
,
484 int next_cpu_nr
, /* ignore */
485 int nr_cpus
, /* ignore */
486 int siggnal
) /* ignore */
490 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
491 cpu
= STATE_CPU (sd
, 0);
494 cpu_single_step (cpu
);
496 /* process any events */
497 if (sim_events_tickn (sd
, cpu
->cpu_current_cycle
))
499 sim_events_process (sd
);
505 sim_info (SIM_DESC sd
, int verbose
)
507 const char *cpu_type
;
508 const struct bfd_arch_info
*arch
;
510 /* Nothing to do if there is no verbose flag set. */
511 if (verbose
== 0 && STATE_VERBOSE_P (sd
) == 0)
514 arch
= STATE_ARCHITECTURE (sd
);
515 if (arch
->arch
== bfd_arch_m68hc11
)
520 sim_io_eprintf (sd
, "Simulator info:\n");
521 sim_io_eprintf (sd
, " CPU Motorola %s\n", cpu_type
);
522 sim_get_info (sd
, 0);
523 sim_module_info (sd
, verbose
|| STATE_VERBOSE_P (sd
));
527 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
,
528 char * const *argv
, char * const *env
)
530 return sim_prepare_for_program (sd
, abfd
);
534 m68hc11_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
542 val
= cpu_get_a (cpu
);
547 val
= cpu_get_b (cpu
);
552 val
= cpu_get_d (cpu
);
556 val
= cpu_get_x (cpu
);
560 val
= cpu_get_y (cpu
);
564 val
= cpu_get_sp (cpu
);
568 val
= cpu_get_pc (cpu
);
572 val
= cpu_get_ccr (cpu
);
577 val
= cpu_get_page (cpu
);
591 memory
[0] = val
>> 8;
592 memory
[1] = val
& 0x0FF;
598 m68hc11_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
604 val
= (val
<< 8) | *memory
;
609 cpu_set_d (cpu
, val
);
613 cpu_set_a (cpu
, val
);
617 cpu_set_b (cpu
, val
);
621 cpu_set_x (cpu
, val
);
625 cpu_set_y (cpu
, val
);
629 cpu_set_sp (cpu
, val
);
633 cpu_set_pc (cpu
, val
);
637 cpu_set_ccr (cpu
, val
);
641 cpu_set_page (cpu
, val
);