1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@nerim.fr)
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #define WITH_MODULO_MEMORY 1
24 #define WITH_WATCHPOINTS 1
25 #define SIM_HANDLES_LMA 1
27 #include "sim-basics.h"
29 typedef struct _sim_cpu SIM_CPU
;
31 #include "sim-signal.h"
36 #include "opcode/m68hc11.h"
38 #include "gdb/callback.h"
39 #include "gdb/remote-sim.h"
40 #include "opcode/m68hc11.h"
41 #include "sim-types.h"
43 typedef unsigned8 uint8
;
44 typedef unsigned16 uint16
;
45 typedef signed16 int16
;
46 typedef unsigned32 uint32
;
47 typedef signed32 int32
;
48 typedef unsigned64 uint64
;
49 typedef signed64 int64
;
53 #include "interrupts.h"
56 /* Specifies the level of mapping for the IO, EEprom, nvram and external
57 RAM. IO registers are mapped over everything and the external RAM
58 is last (ie, it can be hidden by everything above it in the list). */
59 enum m68hc11_map_level
84 typedef struct m6811_regs
{
95 /* Description of 68HC11 IO registers. Such description is only provided
96 for the info command to display the current setting of IO registers
101 const char *short_name
;
102 const char *long_name
;
104 typedef struct io_reg_desc io_reg_desc
;
106 extern void print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
,
108 extern void print_io_byte (SIM_DESC sd
, const char *name
,
109 io_reg_desc
*desc
, uint8 val
, uint16 addr
);
110 extern void print_io_word (SIM_DESC sd
, const char *name
,
111 io_reg_desc
*desc
, uint16 val
, uint16 addr
);
114 /* List of special 68HC11&68HC12 instructions that are not handled by the
115 'gencode.c' generator. These complex instructions are implemented
119 /* 68HC11 instructions. */
129 /* 68HC12 instructions. */
148 #define M6811_MAX_PORTS (0x03f+1)
149 #define M6812_MAX_PORTS (0x3ff+1)
150 #define MAX_PORTS (M6812_MAX_PORTS)
154 typedef void (* cpu_interp
) (struct _sim_cpu
*);
158 struct m6811_regs cpu_regs
;
160 /* CPU interrupts. */
161 struct interrupts cpu_interrupts
;
163 /* Pointer to the interpretor routine. */
164 cpu_interp cpu_interpretor
;
166 /* Pointer to the architecture currently configured in the simulator. */
167 const struct bfd_arch_info
*cpu_configured_arch
;
169 /* CPU absolute cycle time. The cycle time is updated after
170 each instruction, by the number of cycles taken by the instruction.
171 It is cleared only when reset occurs. */
172 signed64 cpu_absolute_cycle
;
174 /* Number of cycles to increment after the current instruction.
175 This is also the number of ticks for the generic event scheduler. */
176 uint8 cpu_current_cycle
;
177 int cpu_emul_syscall
;
178 int cpu_is_initialized
;
180 int cpu_check_memory
;
181 int cpu_stop_on_interrupt
;
183 /* When this is set, start execution of program at address specified
184 in the ELF header. This is used for testing some programs that do not
185 have an interrupt table linked with them. Programs created during the
186 GCC validation are like this. A normal 68HC11 does not behave like
187 this (unless there is some OS or downloadable feature). */
188 int cpu_use_elf_start
;
190 /* The starting address specified in ELF header. */
195 /* CPU frequency. This is the quartz frequency. It is divided by 4 to
196 get the cycle time. This is used for the timer rate and for the baud
198 unsigned long cpu_frequency
;
200 /* The mode in which the CPU is configured (MODA and MODB pins). */
201 unsigned int cpu_mode
;
202 const char* cpu_start_mode
;
204 /* The cpu being configured. */
205 enum cpu_type cpu_type
;
207 /* Initial value of the CONFIG register. */
209 uint8 cpu_use_local_config
;
211 uint8 ios
[MAX_PORTS
];
213 /* Memory bank parameters which describe how the memory bank window
214 is mapped in memory and how to convert it in virtual address. */
217 address_word bank_virtual
;
223 /* ... base type ... */
227 /* Returns the cpu absolute cycle time (A virtual counter incremented
228 at each 68HC11 E clock). */
229 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
230 #define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
231 #define cpu_is_running(PROC) ((PROC)->cpu_running)
233 /* Get the IO/RAM base addresses depending on the M6811_INIT register. */
234 #define cpu_get_io_base(PROC) \
235 (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
236 #define cpu_get_reg_base(PROC) \
237 (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
239 /* Returns the different CPU registers. */
240 #define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
241 #define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
242 #define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
243 #define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
244 #define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
245 #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
246 #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
247 #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
248 #define cpu_get_page(PROC) ((PROC)->cpu_regs.page)
250 /* 68HC12 specific and Motorola internal registers. */
251 #define cpu_get_tmp3(PROC) (0)
252 #define cpu_get_tmp2(PROC) (0)
254 #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
255 #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
256 #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
257 #define cpu_set_page(PROC,VAL) (((PROC)->cpu_regs.page) = (VAL))
259 /* 68HC12 specific and Motorola internal registers. */
260 #define cpu_set_tmp3(PROC,VAL) (0)
261 #define cpu_set_tmp2(PROC,VAL) (void) (0)
264 /* This is a function in m68hc11_sim.c to keep track of the frame. */
265 #define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
268 #define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
270 #define cpu_set_a(PROC,VAL) \
271 cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
272 #define cpu_set_b(PROC,VAL) \
273 cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
275 #define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
276 #define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
277 #define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
278 #define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
279 #define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
280 #define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
281 #define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
282 #define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
283 #define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
285 #define cpu_set_ccr_flag(S,B,V) \
286 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
288 #define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
289 #define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
290 #define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
291 #define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
292 #define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
293 #define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
294 #define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
295 #define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
298 #define inline static __inline__
300 extern void cpu_memory_exception (struct _sim_cpu
*proc
,
303 const char *message
);
306 phys_to_virt (sim_cpu
*cpu
, address_word addr
)
308 if (addr
>= cpu
->bank_start
&& addr
< cpu
->bank_end
)
309 return ((address_word
) (addr
- cpu
->bank_start
)
310 + (((address_word
) cpu
->cpu_regs
.page
) << cpu
->bank_shift
)
311 + cpu
->bank_virtual
);
313 return (address_word
) (addr
);
317 memory_read8 (sim_cpu
*cpu
, uint16 addr
)
321 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
323 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
330 memory_write8 (sim_cpu
*cpu
, uint16 addr
, uint8 val
)
332 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
334 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
340 memory_read16 (sim_cpu
*cpu
, uint16 addr
)
344 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
346 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
349 return (((uint16
) (b
[0])) << 8) | ((uint16
) b
[1]);
353 memory_write16 (sim_cpu
*cpu
, uint16 addr
, uint16 val
)
359 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
361 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
366 cpu_ccr_update_tst8 (sim_cpu
*proc
, uint8 val
);
369 cpu_ccr_update_tst16 (sim_cpu
*proc
, uint16 val
)
371 cpu_set_ccr_V (proc
, 0);
372 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
373 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
377 cpu_ccr_update_shift8 (sim_cpu
*proc
, uint8 val
)
379 cpu_set_ccr_N (proc
, val
& 0x80 ? 1 : 0);
380 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
381 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
385 cpu_ccr_update_shift16 (sim_cpu
*proc
, uint16 val
)
387 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
388 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
389 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
393 cpu_ccr_update_add8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
395 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x80 ? 1 : 0);
396 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80 ? 1 : 0);
397 cpu_set_ccr_Z (proc
, r
== 0);
398 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
403 cpu_ccr_update_sub8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
405 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x80 ? 1 : 0);
406 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80 ? 1 : 0);
407 cpu_set_ccr_Z (proc
, r
== 0);
408 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
412 cpu_ccr_update_add16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
414 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x8000 ? 1 : 0);
415 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x8000 ? 1 : 0);
416 cpu_set_ccr_Z (proc
, r
== 0);
417 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
421 cpu_ccr_update_sub16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
423 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x8000 ? 1 : 0);
424 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x8000 ? 1 : 0);
425 cpu_set_ccr_Z (proc
, r
== 0);
426 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
429 /* Push and pop instructions for 68HC11 (next-available stack mode). */
431 cpu_m68hc11_push_uint8 (sim_cpu
*proc
, uint8 val
)
433 uint16 addr
= proc
->cpu_regs
.sp
;
435 memory_write8 (proc
, addr
, val
);
436 proc
->cpu_regs
.sp
= addr
- 1;
440 cpu_m68hc11_push_uint16 (sim_cpu
*proc
, uint16 val
)
442 uint16 addr
= proc
->cpu_regs
.sp
- 1;
444 memory_write16 (proc
, addr
, val
);
445 proc
->cpu_regs
.sp
= addr
- 1;
449 cpu_m68hc11_pop_uint8 (sim_cpu
*proc
)
451 uint16 addr
= proc
->cpu_regs
.sp
;
454 val
= memory_read8 (proc
, addr
+ 1);
455 proc
->cpu_regs
.sp
= addr
+ 1;
460 cpu_m68hc11_pop_uint16 (sim_cpu
*proc
)
462 uint16 addr
= proc
->cpu_regs
.sp
;
465 val
= memory_read16 (proc
, addr
+ 1);
466 proc
->cpu_regs
.sp
= addr
+ 2;
470 /* Push and pop instructions for 68HC12 (last-used stack mode). */
472 cpu_m68hc12_push_uint8 (sim_cpu
*proc
, uint8 val
)
474 uint16 addr
= proc
->cpu_regs
.sp
;
477 memory_write8 (proc
, addr
, val
);
478 proc
->cpu_regs
.sp
= addr
;
482 cpu_m68hc12_push_uint16 (sim_cpu
*proc
, uint16 val
)
484 uint16 addr
= proc
->cpu_regs
.sp
;
487 memory_write16 (proc
, addr
, val
);
488 proc
->cpu_regs
.sp
= addr
;
492 cpu_m68hc12_pop_uint8 (sim_cpu
*proc
)
494 uint16 addr
= proc
->cpu_regs
.sp
;
497 val
= memory_read8 (proc
, addr
);
498 proc
->cpu_regs
.sp
= addr
+ 1;
503 cpu_m68hc12_pop_uint16 (sim_cpu
*proc
)
505 uint16 addr
= proc
->cpu_regs
.sp
;
508 val
= memory_read16 (proc
, addr
);
509 proc
->cpu_regs
.sp
= addr
+ 2;
513 /* Fetch a 8/16 bit value and update the PC. */
515 cpu_fetch8 (sim_cpu
*proc
)
517 uint16 addr
= proc
->cpu_regs
.pc
;
520 val
= memory_read8 (proc
, addr
);
521 proc
->cpu_regs
.pc
= addr
+ 1;
526 cpu_fetch16 (sim_cpu
*proc
)
528 uint16 addr
= proc
->cpu_regs
.pc
;
531 val
= memory_read16 (proc
, addr
);
532 proc
->cpu_regs
.pc
= addr
+ 2;
536 extern void cpu_call (sim_cpu
* proc
, uint16 addr
);
537 extern void cpu_exg (sim_cpu
* proc
, uint8 code
);
538 extern void cpu_dbcc (sim_cpu
* proc
);
539 extern void cpu_special (sim_cpu
*proc
, enum M6811_Special special
);
540 extern void cpu_move8 (sim_cpu
*proc
, uint8 op
);
541 extern void cpu_move16 (sim_cpu
*proc
, uint8 op
);
543 extern uint16
cpu_fetch_relbranch (sim_cpu
*proc
);
544 extern uint16
cpu_fetch_relbranch16 (sim_cpu
*proc
);
545 extern void cpu_push_all (sim_cpu
*proc
);
546 extern void cpu_single_step (sim_cpu
*proc
);
548 extern void cpu_info (SIM_DESC sd
, sim_cpu
*proc
);
550 extern int cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
);
552 /* Returns the address of a 68HC12 indexed operand.
553 Pre and post modifications are handled on the source register. */
554 extern uint16
cpu_get_indexed_operand_addr (sim_cpu
*cpu
, int restricted
);
556 extern void cpu_return (sim_cpu
*cpu
);
557 extern void cpu_set_sp (sim_cpu
*cpu
, uint16 val
);
558 extern int cpu_reset (sim_cpu
*cpu
);
559 extern int cpu_restart (sim_cpu
*cpu
);
560 extern void sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
561 uint16 addr
, const char *message
, ...);
562 extern void emul_os (int op
, sim_cpu
*cpu
);
563 extern void cpu_interp_m6811 (sim_cpu
*cpu
);
564 extern void cpu_interp_m6812 (sim_cpu
*cpu
);
566 extern int m68hc11cpu_set_oscillator (SIM_DESC sd
, const char *port
,
567 double ton
, double toff
,
569 extern int m68hc11cpu_clear_oscillator (SIM_DESC sd
, const char *port
);
570 extern void m68hc11cpu_set_port (struct hw
*me
, sim_cpu
*cpu
,
571 unsigned addr
, uint8 val
);
573 /* The current state of the processor; registers, memory, etc. */
576 sim_cpu
*cpu
[MAX_NR_PROCESSORS
];
581 extern void sim_board_reset (SIM_DESC sd
);
583 #define PRINT_TIME 0x01
584 #define PRINT_CYCLE 0x02
585 extern const char *cycle_to_string (sim_cpu
*cpu
, signed64 t
, int flags
);