sim/m68hc11/sim-main.h

   1 /* sim-main.h -- Simulator for Motorola 68HC11
   2    Copyright (C) 1999, 2000 Free Software Foundation, Inc.
   3    Written by Stephane Carrez (stcarrez@worldnet.fr)
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef _SIM_MAIN_H
  22 #define _SIM_MAIN_H
  23
  24 #define WITH_MODULO_MEMORY 1
  25 #define WITH_WATCHPOINTS 1
  26 #define SIM_HANDLES_LMA 1
  27
  28 #include "sim-basics.h"
  29
  30 typedef address_word sim_cia;
  31
  32 #include "sim-signal.h"
  33 #include "sim-base.h"
  34
  35 #include "bfd.h"
  36
  37 #include "opcode/m68hc11.h"
  38
  39 #include "callback.h"
  40 #include "remote-sim.h"
  41 #include "opcode/m68hc11.h"
  42 #include "sim-types.h"
  43
  44 typedef unsigned8 uint8;
  45 typedef unsigned16 uint16;
  46 typedef signed16 int16;
  47 typedef unsigned32 uint32;
  48 typedef signed32 int32;
  49 typedef unsigned64 uint64;
  50 typedef signed64 int64;
  51
  52 struct _sim_cpu;
  53
  54 #include "interrupts.h"
  55 #include <setjmp.h>
  56
  57 /* Specifies the level of mapping for the IO, EEprom, nvram and external
  58    RAM.  IO registers are mapped over everything and the external RAM
  59    is last (ie, it can be hidden by everything above it in the list).  */
  60 enum m68hc11_map_level
  61 {
  62   M6811_IO_LEVEL,
  63   M6811_EEPROM_LEVEL,
  64   M6811_NVRAM_LEVEL,
  65   M6811_RAM_LEVEL
  66 };
  67
  68
  69 #define X_REGNUM        0
  70 #define D_REGNUM        1
  71 #define Y_REGNUM        2
  72 #define SP_REGNUM       3
  73 #define PC_REGNUM       4
  74 #define A_REGNUM        5
  75 #define B_REGNUM        6
  76 #define PSW_REGNUM      7
  77 #define Z_REGNUM        8
  78
  79 typedef struct m6811_regs {
  80     unsigned short      d;
  81     unsigned short      ix;
  82     unsigned short      iy;
  83     unsigned short      sp;
  84     unsigned short      pc;
  85     unsigned char       ccr;
  86 } m6811_regs;
  87
  88
  89 /* Description of 68HC11 IO registers.  Such description is only provided
  90    for the info command to display the current setting of IO registers
  91    from GDB.  */
  92 struct io_reg_desc
  93 {
  94   int        mask;
  95   const char *short_name;
  96   const char *long_name;
  97 };
  98 typedef struct io_reg_desc io_reg_desc;
  99
 100 extern void print_io_reg_desc (SIM_DESC sd, io_reg_desc *desc, int val,
 101                                int mode);
 102 extern void print_io_byte (SIM_DESC sd, const char *name,
 103                            io_reg_desc *desc, uint8 val, uint16 addr);
 104
 105
 106 /* List of special 68HC11 instructions that are not handled by the
 107    'gencode.c' generator.  These complex instructions are implemented
 108    by 'cpu_special'.  */
 109 enum M6811_Special
 110 {
 111   M6811_RTI,
 112   M6811_WAI,
 113   M6811_SWI,
 114   M6811_TEST,
 115   M6811_ILLEGAL,
 116   M6811_EMUL_SYSCALL
 117 };
 118
 119 #define CPU_POP 1
 120 #define CPU_PUSH 2
 121
 122 #define MAX_PORTS 0x40
 123
 124 /* Tentative to keep track of the stack frame.
 125    The frame is updated each time a call or a return are made.
 126    We also have to take into account changes of stack pointer
 127    (either thread switch or longjmp).  */
 128 struct cpu_frame
 129 {
 130   struct cpu_frame *up;
 131   uint16 pc;
 132   uint16 sp_low;
 133   uint16 sp_high;
 134 };
 135
 136 /* Represents a list of frames (or a thread).  */
 137 struct cpu_frame_list
 138 {
 139   struct cpu_frame_list *next;
 140   struct cpu_frame_list *prev;
 141   struct cpu_frame      *frame;
 142 };
 143
 144 struct _sim_cpu {
 145   /* CPU registers.  */
 146   struct m6811_regs     cpu_regs;
 147
 148   /* CPU interrupts.  */
 149   struct interrupts     cpu_interrupts;
 150
 151   struct cpu_frame_list *cpu_frames;
 152   struct cpu_frame_list *cpu_current_frame;
 153   int                   cpu_need_update_frame;
 154
 155   /* CPU absolute cycle time.  The cycle time is updated after
 156      each instruction, by the number of cycles taken by the instruction.
 157      It is cleared only when reset occurs.  */
 158   signed64              cpu_absolute_cycle;
 159
 160   /* Number of cycles to increment after the current instruction.
 161      This is also the number of ticks for the generic event scheduler.  */
 162   uint8                 cpu_current_cycle;
 163   int                   cpu_emul_syscall;
 164   int                   cpu_is_initialized;
 165   int                   cpu_running;
 166   int                   cpu_check_memory;
 167   int                   cpu_stop_on_interrupt;
 168
 169   /* When this is set, start execution of program at address specified
 170      in the ELF header.  This is used for testing some programs that do not
 171      have an interrupt table linked with them.  Programs created during the
 172      GCC validation are like this. A normal 68HC11 does not behave like
 173      this (unless there is some OS or downloadable feature).  */
 174   int                   cpu_use_elf_start;
 175
 176   /* The starting address specified in ELF header.  */
 177   int                   cpu_elf_start;
 178
 179   uint16                cpu_insn_pc;
 180
 181   /* CPU frequency.  This is the quartz frequency.  It is divided by 4 to
 182      get the cycle time.  This is used for the timer rate and for the baud
 183      rate generation.  */
 184   unsigned long         cpu_frequency;
 185
 186   /* The mode in which the CPU is configured (MODA and MODB pins).  */
 187   unsigned int          cpu_mode;
 188
 189   /* Initial value of the CONFIG register.  */
 190   uint8                 cpu_config;
 191   uint8                 cpu_use_local_config;
 192
 193   uint8 ios[0x3F];
 194
 195   /* ... base type ... */
 196   sim_cpu_base base;
 197 };
 198
 199 /* Returns the cpu absolute cycle time (A virtual counter incremented
 200    at each 68HC11 E clock).  */
 201 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
 202 #define cpu_add_cycles(PROC,T)  ((PROC)->cpu_current_cycle += (signed64) (T))
 203 #define cpu_is_running(PROC)    ((PROC)->cpu_running)
 204
 205 /* Get the IO/RAM base addresses depending on the M6811_INIT register.  */
 206 #define cpu_get_io_base(PROC) \
 207         (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
 208 #define cpu_get_reg_base(PROC) \
 209         (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
 210
 211 /* Returns the different CPU registers.  */
 212 #define cpu_get_ccr(PROC)          ((PROC)->cpu_regs.ccr)
 213 #define cpu_get_pc(PROC)           ((PROC)->cpu_regs.pc)
 214 #define cpu_get_d(PROC)            ((PROC)->cpu_regs.d)
 215 #define cpu_get_x(PROC)            ((PROC)->cpu_regs.ix)
 216 #define cpu_get_y(PROC)            ((PROC)->cpu_regs.iy)
 217 #define cpu_get_sp(PROC)           ((PROC)->cpu_regs.sp)
 218 #define cpu_get_a(PROC)            ((PROC->cpu_regs.d >> 8) & 0x0FF)
 219 #define cpu_get_b(PROC)            ((PROC->cpu_regs.d) & 0x0FF)
 220
 221 #define cpu_set_d(PROC,VAL)        (((PROC)->cpu_regs.d) = (VAL))
 222 #define cpu_set_x(PROC,VAL)        (((PROC)->cpu_regs.ix) = (VAL))
 223 #define cpu_set_y(PROC,VAL)        (((PROC)->cpu_regs.iy) = (VAL))
 224
 225 #if 0
 226 /* This is a function in m68hc11_sim.c to keep track of the frame.  */
 227 #define cpu_set_sp(PROC,VAL)       (((PROC)->cpu_regs.sp) = (VAL))
 228 #endif
 229
 230 #define cpu_set_pc(PROC,VAL)       (((PROC)->cpu_regs.pc) = (VAL))
 231
 232 #define cpu_set_a(PROC,VAL)  \
 233       cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
 234 #define cpu_set_b(PROC,VAL)  \
 235       cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
 236
 237 #define cpu_set_ccr(PROC,VAL)      ((PROC)->cpu_regs.ccr = (VAL))
 238 #define cpu_get_ccr_H(PROC)        ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
 239 #define cpu_get_ccr_X(PROC)        ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
 240 #define cpu_get_ccr_S(PROC)        ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
 241 #define cpu_get_ccr_N(PROC)        ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
 242 #define cpu_get_ccr_V(PROC)        ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
 243 #define cpu_get_ccr_C(PROC)        ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
 244 #define cpu_get_ccr_Z(PROC)        ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
 245 #define cpu_get_ccr_I(PROC)        ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
 246
 247 #define cpu_set_ccr_flag(S,B,V) \
 248 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
 249
 250 #define cpu_set_ccr_H(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
 251 #define cpu_set_ccr_X(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
 252 #define cpu_set_ccr_S(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
 253 #define cpu_set_ccr_N(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
 254 #define cpu_set_ccr_V(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
 255 #define cpu_set_ccr_C(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
 256 #define cpu_set_ccr_Z(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
 257 #define cpu_set_ccr_I(PROC,VAL)    cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
 258
 259 #undef inline
 260 #define inline static __inline__
 261
 262 extern void cpu_memory_exception (struct _sim_cpu *proc,
 263                                   SIM_SIGNAL excep,
 264                                   uint16 addr,
 265                                   const char *message);
 266
 267 inline uint8
 268 memory_read8 (sim_cpu *cpu, uint16 addr)
 269 {
 270   uint8 val;
 271
 272   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 273     {
 274       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 275                             "Read error");
 276     }
 277   return val;
 278 }
 279
 280 inline void
 281 memory_write8 (sim_cpu *cpu, uint16 addr, uint8 val)
 282 {
 283   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, &val, addr, 1) != 1)
 284     {
 285       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 286                             "Write error");
 287     }
 288 }
 289
 290 inline uint16
 291 memory_read16 (sim_cpu *cpu, uint16 addr)
 292 {
 293   uint8 b[2];
 294
 295   if (sim_core_read_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 296     {
 297       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 298                             "Read error");
 299     }
 300   return (((uint16) (b[0])) << 8) | ((uint16) b[1]);
 301 }
 302
 303 inline void
 304 memory_write16 (sim_cpu *cpu, uint16 addr, uint16 val)
 305 {
 306   uint8 b[2];
 307
 308   b[0] = val >> 8;
 309   b[1] = val;
 310   if (sim_core_write_buffer (CPU_STATE (cpu), cpu, 0, b, addr, 2) != 2)
 311     {
 312       cpu_memory_exception (cpu, SIM_SIGSEGV, addr,
 313                             "Write error");
 314     }
 315 }
 316 extern void
 317 cpu_ccr_update_tst8 (sim_cpu *proc, uint8 val);
 318
 319      inline void
 320 cpu_ccr_update_tst16 (sim_cpu *proc, uint16 val)
 321 {
 322   cpu_set_ccr_V (proc, 0);
 323   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 324   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 325 }
 326
 327      inline void
 328 cpu_ccr_update_shift8 (sim_cpu *proc, uint8 val)
 329 {
 330   cpu_set_ccr_N (proc, val & 0x80 ? 1 : 0);
 331   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 332   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 333 }
 334
 335      inline void
 336 cpu_ccr_update_shift16 (sim_cpu *proc, uint16 val)
 337 {
 338   cpu_set_ccr_N (proc, val & 0x8000 ? 1 : 0);
 339   cpu_set_ccr_Z (proc, val == 0 ? 1 : 0);
 340   cpu_set_ccr_V (proc, cpu_get_ccr_N (proc) ^ cpu_get_ccr_C (proc));
 341 }
 342
 343 inline void
 344 cpu_ccr_update_add8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 345 {
 346   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x80 ? 1 : 0);
 347   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x80 ? 1 : 0);
 348   cpu_set_ccr_Z (proc, r == 0);
 349   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 350 }
 351
 352
 353 inline void
 354 cpu_ccr_update_sub8 (sim_cpu *proc, uint8 r, uint8 a, uint8 b)
 355 {
 356   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x80 ? 1 : 0);
 357   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x80 ? 1 : 0);
 358   cpu_set_ccr_Z (proc, r == 0);
 359   cpu_set_ccr_N (proc, r & 0x80 ? 1 : 0);
 360 }
 361
 362 inline void
 363 cpu_ccr_update_add16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 364 {
 365   cpu_set_ccr_C (proc, ((a & b) | (b & ~r) | (a & ~r)) & 0x8000 ? 1 : 0);
 366   cpu_set_ccr_V (proc, ((a & b & ~r) | (~a & ~b & r)) & 0x8000 ? 1 : 0);
 367   cpu_set_ccr_Z (proc, r == 0);
 368   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 369 }
 370
 371 inline void
 372 cpu_ccr_update_sub16 (sim_cpu *proc, uint16 r, uint16 a, uint16 b)
 373 {
 374   cpu_set_ccr_C (proc, ((~a & b) | (b & r) | (~a & r)) & 0x8000 ? 1 : 0);
 375   cpu_set_ccr_V (proc, ((a & ~b & ~r) | (~a & b & r)) & 0x8000 ? 1 : 0);
 376   cpu_set_ccr_Z (proc, r == 0);
 377   cpu_set_ccr_N (proc, r & 0x8000 ? 1 : 0);
 378 }
 379
 380
 381 inline void
 382 cpu_push_uint8 (sim_cpu *proc, uint8 val)
 383 {
 384   uint16 addr = proc->cpu_regs.sp;
 385
 386   memory_write8 (proc, addr, val);
 387   proc->cpu_regs.sp = addr - 1;
 388   proc->cpu_need_update_frame |= CPU_PUSH;
 389 }
 390
 391 inline void
 392 cpu_push_uint16 (sim_cpu *proc, uint16 val)
 393 {
 394   uint16 addr = proc->cpu_regs.sp - 1;
 395
 396   memory_write16 (proc, addr, val);
 397   proc->cpu_regs.sp = addr - 1;
 398   proc->cpu_need_update_frame |= CPU_PUSH;
 399 }
 400
 401 inline uint8
 402 cpu_pop_uint8 (sim_cpu *proc)
 403 {
 404   uint16 addr = proc->cpu_regs.sp;
 405   uint8 val;
 406
 407   val = memory_read8 (proc, addr + 1);
 408   proc->cpu_regs.sp = addr + 1;
 409   proc->cpu_need_update_frame |= CPU_POP;
 410   return val;
 411 }
 412
 413 inline uint16
 414 cpu_pop_uint16 (sim_cpu *proc)
 415 {
 416   uint16 addr = proc->cpu_regs.sp;
 417   uint16 val;
 418
 419   val = memory_read16 (proc, addr + 1);
 420   proc->cpu_regs.sp = addr + 2;
 421   proc->cpu_need_update_frame |= CPU_POP;
 422   return val;
 423 }
 424
 425 inline uint8
 426 cpu_fetch8 (sim_cpu *proc)
 427 {
 428   uint16 addr = proc->cpu_regs.pc;
 429   uint8 val;
 430
 431   val = memory_read8 (proc, addr);
 432   proc->cpu_regs.pc = addr + 1;
 433   return val;
 434 }
 435
 436 inline uint16
 437 cpu_fetch16 (sim_cpu *proc)
 438 {
 439   uint16 addr = proc->cpu_regs.pc;
 440   uint16 val;
 441
 442   val = memory_read16 (proc, addr);
 443   proc->cpu_regs.pc = addr + 2;
 444   return val;
 445 }
 446
 447 extern void cpu_call (sim_cpu* proc, uint16 addr);
 448 extern void cpu_special (sim_cpu *proc, enum M6811_Special special);
 449
 450 extern uint16 cpu_fetch_relbranch (sim_cpu *proc);
 451 extern void cpu_push_all (sim_cpu *proc);
 452 extern void cpu_single_step (sim_cpu *proc);
 453
 454 extern void cpu_info (SIM_DESC sd, sim_cpu *proc);
 455
 456 extern int cpu_initialize (SIM_DESC sd, sim_cpu *cpu);
 457
 458 extern void cpu_print_frame (SIM_DESC sd, sim_cpu *cpu);
 459 extern void cpu_set_sp (sim_cpu *cpu, uint16 val);
 460 extern uint16 cpu_frame_reg (sim_cpu *cpu, uint16 rn);
 461 extern int cpu_reset (sim_cpu *cpu);
 462 extern int cpu_restart (sim_cpu *cpu);
 463 extern void sim_memory_error (sim_cpu *cpu, SIM_SIGNAL excep,
 464                               uint16 addr, const char *message, ...);
 465 extern void emul_os (int op, sim_cpu *cpu);
 466 extern void cpu_interp (sim_cpu *cpu);
 467
 468 /* The current state of the processor; registers, memory, etc.  */
 469
 470 #define CIA_GET(CPU)      (cpu_get_pc (CPU))
 471 #define CIA_SET(CPU,VAL)  (cpu_set_pc ((CPU), (VAL)))
 472
 473 #if (WITH_SMP)
 474 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 475 #else
 476 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 477 #endif
 478
 479 struct sim_state {
 480   sim_cpu        cpu[MAX_NR_PROCESSORS];
 481   device         *devices;
 482   sim_state_base base;
 483 };
 484
 485 extern void sim_set_profile (int n);
 486 extern void sim_set_profile_size (int n);
 487 extern void sim_board_reset (SIM_DESC sd);
 488
 489 extern const char *cycle_to_string (sim_cpu *cpu, signed64 t);
 490
 491 #endif
 492
 493