1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2021 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* This must come before any other includes. */
26 #include <sys/param.h>
29 #include "sim/callback.h"
30 #include "libiberty.h"
35 #include "sim-signal.h"
36 #include "sim-syscall.h"
37 #include "sim-options.h"
39 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
43 mcore_extract_unsigned_integer (unsigned char *addr
, int len
)
47 unsigned char * startaddr
= (unsigned char *)addr
;
48 unsigned char * endaddr
= startaddr
+ len
;
50 if (len
> (int) sizeof (unsigned long))
51 printf ("That operation is not available on integers of more than %zu bytes.",
52 sizeof (unsigned long));
54 /* Start at the most significant end of the integer, and work towards
55 the least significant. */
58 if (! target_big_endian
)
60 for (p
= endaddr
; p
> startaddr
;)
61 retval
= (retval
<< 8) | * -- p
;
65 for (p
= startaddr
; p
< endaddr
;)
66 retval
= (retval
<< 8) | * p
++;
73 mcore_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
76 unsigned char * startaddr
= (unsigned char *)addr
;
77 unsigned char * endaddr
= startaddr
+ len
;
79 if (! target_big_endian
)
81 for (p
= startaddr
; p
< endaddr
;)
89 for (p
= endaddr
; p
> startaddr
;)
97 static int memcycles
= 1;
99 #define gr cpu->active_gregs
100 #define cr cpu->regs.cregs
115 /* maniuplate the carry bit */
116 #define C_ON() (sr & 1)
117 #define C_VALUE() (sr & 1)
118 #define C_OFF() ((sr & 1) == 0)
119 #define SET_C() {sr |= 1;}
120 #define CLR_C() {sr &= 0xfffffffe;}
121 #define NEW_C(v) {CLR_C(); sr |= ((v) & 1);}
123 #define SR_AF() ((sr >> 1) & 1)
124 static void set_active_regs (SIM_CPU
*cpu
)
127 cpu
->active_gregs
= cpu
->regs
.alt_gregs
;
129 cpu
->active_gregs
= cpu
->regs
.gregs
;
132 #define TRAPCODE 1 /* r1 holds which function we want */
133 #define PARM1 2 /* first parameter */
137 #define RET1 2 /* register for return values. */
139 /* Default to a 8 Mbyte (== 2^23) memory space. */
140 #define DEFAULT_MEMORY_SIZE 0x800000
143 set_initial_gprs (SIM_CPU
*cpu
)
145 /* Set up machine just out of reset. */
149 /* Clean out the GPRs and alternate GPRs. */
150 memset (&cpu
->regs
.gregs
, 0, sizeof(cpu
->regs
.gregs
));
151 memset (&cpu
->regs
.alt_gregs
, 0, sizeof(cpu
->regs
.alt_gregs
));
153 /* Make our register set point to the right place. */
154 set_active_regs (cpu
);
156 /* ABI specifies initial values for these registers. */
157 gr
[0] = DEFAULT_MEMORY_SIZE
- 4;
159 /* dac fix, the stack address must be 8-byte aligned! */
160 gr
[0] = gr
[0] - gr
[0] % 8;
167 /* Simulate a monitor trap. */
170 handle_trap1 (SIM_DESC sd
, SIM_CPU
*cpu
)
172 /* XXX: We don't pass back the actual errno value. */
173 gr
[RET1
] = sim_syscall (cpu
, gr
[TRAPCODE
], gr
[PARM1
], gr
[PARM2
], gr
[PARM3
],
178 process_stub (SIM_DESC sd
, SIM_CPU
*cpu
, int what
)
180 /* These values should match those in libgloss/mcore/syscalls.s. */
187 case 10: /* _unlink */
188 case 19: /* _lseek */
189 case 43: /* _times */
191 handle_trap1 (sd
, cpu
);
195 if (STATE_VERBOSE_P (sd
))
196 fprintf (stderr
, "Unhandled stub opcode: %d\n", what
);
202 util (SIM_DESC sd
, SIM_CPU
*cpu
, unsigned what
)
207 sim_engine_halt (sd
, cpu
, NULL
, cpu
->regs
.pc
, sim_exited
, gr
[PARM1
]);
211 if (STATE_VERBOSE_P (sd
))
212 fprintf (stderr
, "WARNING: printf unimplemented\n");
216 if (STATE_VERBOSE_P (sd
))
217 fprintf (stderr
, "WARNING: scanf unimplemented\n");
221 gr
[RET1
] = cpu
->insts
;
225 process_stub (sd
, cpu
, gr
[1]);
229 if (STATE_VERBOSE_P (sd
))
230 fprintf (stderr
, "Unhandled util code: %x\n", what
);
235 /* For figuring out whether we carried; addc/subc use this. */
237 iu_carry (unsigned long a
, unsigned long b
, int cin
)
241 x
= (a
& 0xffff) + (b
& 0xffff) + cin
;
242 x
= (x
>> 16) + (a
>> 16) + (b
>> 16);
248 /* TODO: Convert to common watchpoints. */
249 #undef WATCHFUNCTIONS
250 #ifdef WATCHFUNCTIONS
267 #define RD (inst & 0xF)
268 #define RS ((inst >> 4) & 0xF)
269 #define RX ((inst >> 8) & 0xF)
270 #define IMM5 ((inst >> 4) & 0x1F)
271 #define IMM4 ((inst) & 0xF)
273 #define rbat(X) sim_core_read_1 (cpu, 0, read_map, X)
274 #define rhat(X) sim_core_read_2 (cpu, 0, read_map, X)
275 #define rlat(X) sim_core_read_4 (cpu, 0, read_map, X)
276 #define wbat(X, D) sim_core_write_1 (cpu, 0, write_map, X, D)
277 #define what(X, D) sim_core_write_2 (cpu, 0, write_map, X, D)
278 #define wlat(X, D) sim_core_write_4 (cpu, 0, write_map, X, D)
280 static int tracing
= 0;
283 sim_engine_halt (sd, cpu, NULL, pc, sim_stopped, SIM_SIGILL)
286 step_once (SIM_DESC sd
, SIM_CPU
*cpu
)
297 #ifdef WATCHFUNCTIONS
301 pc
= CPU_PC_GET (cpu
);
303 /* Fetch the initial instructions that we'll decode. */
304 ibuf
= rlat (pc
& 0xFFFFFFFC);
311 /* make our register set point to the right place */
312 set_active_regs (cpu
);
314 #ifdef WATCHFUNCTIONS
315 /* make a hash to speed exec loop, hope it's nonzero */
318 for (w
= 1; w
<= ENDWL
; w
++)
319 WLhash
= WLhash
& WL
[w
];
322 /* TODO: Unindent this block. */
330 if (! target_big_endian
)
333 inst
= ibuf
& 0xFFFF;
338 if (! target_big_endian
)
339 inst
= ibuf
& 0xFFFF;
344 #ifdef WATCHFUNCTIONS
345 /* now scan list of watch addresses, if match, count it and
346 note return address and count cycles until pc=return address */
348 if ((WLincyc
== 1) && (pc
== WLendpc
))
350 cycs
= (cpu
->cycles
+ (insts
+ bonus_cycles
+
351 (memops
* memcycles
)) - WLbcyc
);
353 if (WLcnts
[WLW
] == 1)
360 if (cycs
> WLmax
[WLW
])
365 if (cycs
< WLmin
[WLW
])
375 /* Optimize with a hash to speed loop. */
378 if ((WLhash
== 0) || ((WLhash
& pc
) != 0))
380 for (w
=1; w
<= ENDWL
; w
++)
385 WLbcyc
= cpu
->cycles
+ insts
386 + bonus_cycles
+ (memops
* memcycles
);
398 fprintf (stderr
, "%.4lx: inst = %.4x ", pc
, inst
);
414 sim_engine_halt (sd
, cpu
, NULL
, pc
- 2,
415 sim_stopped
, SIM_SIGTRAP
);
426 set_active_regs (cpu
);
434 set_active_regs (cpu
);
438 if (STATE_VERBOSE_P (sd
))
439 fprintf (stderr
, "WARNING: stop unimplemented\n");
443 if (STATE_VERBOSE_P (sd
))
444 fprintf (stderr
, "WARNING: wait unimplemented\n");
448 if (STATE_VERBOSE_P (sd
))
449 fprintf (stderr
, "WARNING: doze unimplemented\n");
453 ILLEGAL (); /* illegal */
456 case 0x8: /* trap 0 */
457 case 0xA: /* trap 2 */
458 case 0xB: /* trap 3 */
459 sim_engine_halt (sd
, cpu
, NULL
, pc
,
460 sim_stopped
, SIM_SIGTRAP
);
463 case 0xC: /* trap 4 */
464 case 0xD: /* trap 5 */
465 case 0xE: /* trap 6 */
466 ILLEGAL (); /* illegal */
469 case 0xF: /* trap 7 */
470 sim_engine_halt (sd
, cpu
, NULL
, pc
, /* integer div-by-0 */
471 sim_stopped
, SIM_SIGTRAP
);
474 case 0x9: /* trap 1 */
475 handle_trap1 (sd
, cpu
);
481 ILLEGAL (); /* illegal */
493 int regno
= 4; /* always r4-r7 */
499 gr
[regno
] = rlat (addr
);
503 while ((regno
&0x3) != 0);
509 int regno
= 4; /* always r4-r7 */
515 wlat (addr
, gr
[regno
]);
519 while ((regno
& 0x3) != 0);
527 /* bonus cycle is really only needed if
528 the next insn shifts the last reg loaded.
535 gr
[regno
] = rlat (addr
);
546 /* this should be removed! */
547 /* bonus_cycles ++; */
549 memops
+= 16 - regno
;
552 wlat (addr
, gr
[regno
]);
573 if (tracing
&& RD
== 15)
574 fprintf (stderr
, "Func return, r2 = %lxx, r3 = %lx\n",
589 for (i
= 0; !(tmp
& 0x80000000) && i
< 32; i
++)
598 tmp
= ((tmp
& 0xaaaaaaaa) >> 1) | ((tmp
& 0x55555555) << 1);
599 tmp
= ((tmp
& 0xcccccccc) >> 2) | ((tmp
& 0x33333333) << 2);
600 tmp
= ((tmp
& 0xf0f0f0f0) >> 4) | ((tmp
& 0x0f0f0f0f) << 4);
601 tmp
= ((tmp
& 0xff00ff00) >> 8) | ((tmp
& 0x00ff00ff) << 8);
602 gr
[RD
] = ((tmp
& 0xffff0000) >> 16) | ((tmp
& 0x0000ffff) << 16);
610 case 0x0: /* xtrb3 */
611 gr
[1] = (gr
[RD
]) & 0xFF;
614 case 0x1: /* xtrb2 */
615 gr
[1] = (gr
[RD
]>>8) & 0xFF;
618 case 0x2: /* xtrb1 */
619 gr
[1] = (gr
[RD
]>>16) & 0xFF;
622 case 0x3: /* xtrb0 */
623 gr
[1] = (gr
[RD
]>>24) & 0xFF;
626 case 0x4: /* zextb */
627 gr
[RD
] &= 0x000000FF;
629 case 0x5: /* sextb */
638 case 0x6: /* zexth */
639 gr
[RD
] &= 0x0000FFFF;
641 case 0x7: /* sexth */
650 case 0x8: /* declt */
652 NEW_C ((long)gr
[RD
] < 0);
654 case 0x9: /* tstnbz */
657 NEW_C ((tmp
& 0xFF000000) != 0 &&
658 (tmp
& 0x00FF0000) != 0 && (tmp
& 0x0000FF00) != 0 &&
659 (tmp
& 0x000000FF) != 0);
662 case 0xA: /* decgt */
664 NEW_C ((long)gr
[RD
] > 0);
666 case 0xB: /* decne */
668 NEW_C ((long)gr
[RD
] != 0);
679 if (gr
[RD
] & 0x80000000)
680 gr
[RD
] = ~gr
[RD
] + 1;
687 case 0x02: /* movt */
691 case 0x03: /* mult */
692 /* consume 2 bits per cycle from rs, until rs is 0 */
694 unsigned int t
= gr
[RS
];
696 for (ticks
= 0; t
!= 0 ; t
>>= 2)
698 bonus_cycles
+= ticks
;
700 bonus_cycles
+= 2; /* min. is 3, so add 2, plus ticks above */
702 fprintf (stderr
, " mult %lx by %lx to give %lx",
703 gr
[RD
], gr
[RS
], gr
[RD
] * gr
[RS
]);
704 gr
[RD
] = gr
[RD
] * gr
[RS
];
706 case 0x04: /* loopt */
709 pc
+= (IMM4
<< 1) - 32;
713 --gr
[RS
]; /* not RD! */
714 NEW_C (((long)gr
[RS
]) > 0);
716 case 0x05: /* subu */
719 case 0x06: /* addc */
721 unsigned long tmp
, a
, b
;
724 gr
[RD
] = a
+ b
+ C_VALUE ();
725 tmp
= iu_carry (a
, b
, C_VALUE ());
729 case 0x07: /* subc */
731 unsigned long tmp
, a
, b
;
734 gr
[RD
] = a
- b
+ C_VALUE () - 1;
735 tmp
= iu_carry (a
,~b
, C_VALUE ());
739 case 0x08: /* illegal */
740 case 0x09: /* illegal*/
743 case 0x0A: /* movf */
749 unsigned long dst
, src
;
752 /* We must not rely solely upon the native shift operations, since they
753 may not match the M*Core's behaviour on boundary conditions. */
754 dst
= src
> 31 ? 0 : dst
>> src
;
758 case 0x0C: /* cmphs */
759 NEW_C ((unsigned long )gr
[RD
] >=
760 (unsigned long)gr
[RS
]);
762 case 0x0D: /* cmplt */
763 NEW_C ((long)gr
[RD
] < (long)gr
[RS
]);
766 NEW_C ((gr
[RD
] & gr
[RS
]) != 0);
768 case 0x0F: /* cmpne */
769 NEW_C (gr
[RD
] != gr
[RS
]);
771 case 0x10: case 0x11: /* mfcr */
775 if (r
<= LAST_VALID_CREG
)
785 fprintf (stderr
, "MOV %lx into reg %d", gr
[RD
], RD
);
788 case 0x13: /* bgenr */
792 gr
[RD
] = 1 << (gr
[RS
] & 0x1F);
795 case 0x14: /* rsub */
796 gr
[RD
] = gr
[RS
] - gr
[RD
];
811 case 0x18: case 0x19: /* mtcr */
815 if (r
<= LAST_VALID_CREG
)
820 /* we might have changed register sets... */
821 set_active_regs (cpu
);
826 /* We must not rely solely upon the native shift operations, since they
827 may not match the M*Core's behaviour on boundary conditions. */
829 gr
[RD
] = ((long) gr
[RD
]) < 0 ? -1 : 0;
831 gr
[RD
] = (long) gr
[RD
] >> gr
[RS
];
835 /* We must not rely solely upon the native shift operations, since they
836 may not match the M*Core's behaviour on boundary conditions. */
837 gr
[RD
] = gr
[RS
] > 31 ? 0 : gr
[RD
] << gr
[RS
];
840 case 0x1C: /* addu */
845 gr
[RD
] += gr
[RS
] << 1;
852 case 0x1F: /* andn */
855 case 0x20: case 0x21: /* addi */
859 case 0x22: case 0x23: /* cmplti */
861 int tmp
= (IMM5
+ 1);
872 case 0x24: case 0x25: /* subi */
876 case 0x26: case 0x27: /* illegal */
879 case 0x28: case 0x29: /* rsubi */
883 case 0x2A: case 0x2B: /* cmpnei */
894 case 0x2C: case 0x2D: /* bmaski, divu */
908 /* unsigned divide */
909 gr
[RD
] = (word
) ((unsigned int) gr
[RD
] / (unsigned int)gr
[1] );
911 /* compute bonus_cycles for divu */
912 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32); r1nlz
++)
915 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32); rxnlz
++)
921 exe
+= 5 + r1nlz
- rxnlz
;
923 if (exe
>= (2 * memcycles
- 1))
925 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
928 else if (imm
== 0 || imm
>= 8)
934 gr
[RD
] = (1 << imm
) - 1;
943 case 0x2E: case 0x2F: /* andi */
944 gr
[RD
] = gr
[RD
] & IMM5
;
946 case 0x30: case 0x31: /* bclri */
947 gr
[RD
] = gr
[RD
] & ~(1<<IMM5
);
949 case 0x32: case 0x33: /* bgeni, divs */
958 /* compute bonus_cycles for divu */
963 if (((rx
< 0) && (r1
> 0)) || ((rx
>= 0) && (r1
< 0)))
971 /* signed divide, general registers are of type int, so / op is OK */
972 gr
[RD
] = gr
[RD
] / gr
[1];
974 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32) ; r1nlz
++ )
977 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32) ; rxnlz
++ )
983 exe
+= 6 + r1nlz
- rxnlz
+ sc
;
985 if (exe
>= (2 * memcycles
- 1))
987 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
993 gr
[RD
] = (1 << IMM5
);
1002 case 0x34: case 0x35: /* bseti */
1003 gr
[RD
] = gr
[RD
] | (1 << IMM5
);
1005 case 0x36: case 0x37: /* btsti */
1006 NEW_C (gr
[RD
] >> IMM5
);
1008 case 0x38: case 0x39: /* xsr, rotli */
1010 unsigned imm
= IMM5
;
1011 unsigned long tmp
= gr
[RD
];
1017 gr
[RD
] = (cbit
<< 31) | (tmp
>> 1);
1020 gr
[RD
] = (tmp
<< imm
) | (tmp
>> (32 - imm
));
1023 case 0x3A: case 0x3B: /* asrc, asri */
1025 unsigned imm
= IMM5
;
1033 gr
[RD
] = tmp
>> imm
;
1036 case 0x3C: case 0x3D: /* lslc, lsli */
1038 unsigned imm
= IMM5
;
1039 unsigned long tmp
= gr
[RD
];
1046 gr
[RD
] = tmp
<< imm
;
1049 case 0x3E: case 0x3F: /* lsrc, lsri */
1051 unsigned imm
= IMM5
;
1052 unsigned long tmp
= gr
[RD
];
1059 gr
[RD
] = tmp
>> imm
;
1062 case 0x40: case 0x41: case 0x42: case 0x43:
1063 case 0x44: case 0x45: case 0x46: case 0x47:
1064 case 0x48: case 0x49: case 0x4A: case 0x4B:
1065 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1069 util (sd
, cpu
, inst
& 0xFF);
1071 case 0x51: case 0x52: case 0x53:
1072 case 0x54: case 0x55: case 0x56: case 0x57:
1073 case 0x58: case 0x59: case 0x5A: case 0x5B:
1074 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1077 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1078 case 0x64: case 0x65: case 0x66: case 0x67:
1079 gr
[RD
] = (inst
>> 4) & 0x7F;
1081 case 0x68: case 0x69: case 0x6A: case 0x6B:
1082 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1085 case 0x71: case 0x72: case 0x73:
1086 case 0x74: case 0x75: case 0x76: case 0x77:
1087 case 0x78: case 0x79: case 0x7A: case 0x7B:
1088 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1089 gr
[RX
] = rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1091 fprintf (stderr
, "LRW of 0x%x from 0x%lx to reg %d",
1092 rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC),
1093 (pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC, RX
);
1096 case 0x7F: /* jsri */
1100 "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n",
1101 gr
[2], gr
[3], gr
[4], gr
[5], gr
[6], gr
[7]);
1102 case 0x70: /* jmpi */
1103 pc
= rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1109 case 0x80: case 0x81: case 0x82: case 0x83:
1110 case 0x84: case 0x85: case 0x86: case 0x87:
1111 case 0x88: case 0x89: case 0x8A: case 0x8B:
1112 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1113 gr
[RX
] = rlat (gr
[RD
] + ((inst
>> 2) & 0x003C));
1115 fprintf (stderr
, "load reg %d from 0x%lx with 0x%lx",
1117 gr
[RD
] + ((inst
>> 2) & 0x003C), gr
[RX
]);
1120 case 0x90: case 0x91: case 0x92: case 0x93:
1121 case 0x94: case 0x95: case 0x96: case 0x97:
1122 case 0x98: case 0x99: case 0x9A: case 0x9B:
1123 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1124 wlat (gr
[RD
] + ((inst
>> 2) & 0x003C), gr
[RX
]);
1126 fprintf (stderr
, "store reg %d (containing 0x%lx) to 0x%lx",
1128 gr
[RD
] + ((inst
>> 2) & 0x003C));
1131 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1132 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1133 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1134 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1135 gr
[RX
] = rbat (gr
[RD
] + RS
);
1138 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1139 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1140 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1141 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1142 wbat (gr
[RD
] + RS
, gr
[RX
]);
1145 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1146 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1147 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1148 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1149 gr
[RX
] = rhat (gr
[RD
] + ((inst
>> 3) & 0x001E));
1152 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1153 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1154 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1155 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1156 what (gr
[RD
] + ((inst
>> 3) & 0x001E), gr
[RX
]);
1159 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1160 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1164 disp
= inst
& 0x03FF;
1172 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1173 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1177 disp
= inst
& 0x03FF;
1186 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1187 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1189 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1190 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1193 disp
= inst
& 0x03FF;
1205 fprintf (stderr
, "\n");
1209 ibuf
= rlat (pc
& 0xFFFFFFFC);
1214 /* Hide away the things we've cached while executing. */
1215 CPU_PC_SET (cpu
, pc
);
1216 cpu
->insts
+= insts
; /* instructions done ... */
1217 cpu
->cycles
+= insts
; /* and each takes a cycle */
1218 cpu
->cycles
+= bonus_cycles
; /* and extra cycles for branches */
1219 cpu
->cycles
+= memops
* memcycles
; /* and memop cycle delays */
1223 sim_engine_run (SIM_DESC sd
,
1224 int next_cpu_nr
, /* ignore */
1225 int nr_cpus
, /* ignore */
1226 int siggnal
) /* ignore */
1230 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1232 cpu
= STATE_CPU (sd
, 0);
1236 step_once (sd
, cpu
);
1237 if (sim_events_tick (sd
))
1238 sim_events_process (sd
);
1243 mcore_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1245 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1251 /* misalignment safe */
1252 ival
= mcore_extract_unsigned_integer (memory
, 4);
1253 cpu
->asints
[rn
] = ival
;
1263 mcore_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
1265 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1269 long ival
= cpu
->asints
[rn
];
1271 /* misalignment-safe */
1272 mcore_store_unsigned_integer (memory
, 4, ival
);
1282 sim_info (SIM_DESC sd
, int verbose
)
1284 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1285 #ifdef WATCHFUNCTIONS
1288 double virttime
= cpu
->cycles
/ 36.0e6
;
1289 host_callback
*callback
= STATE_CALLBACK (sd
);
1291 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1293 callback
->printf_filtered (callback
, "# cycles %10d\n",
1295 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
1297 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
1300 #ifdef WATCHFUNCTIONS
1301 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
1306 for (w
= 1; w
<= ENDWL
; w
++)
1308 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
1309 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
1310 WLcnts
[w
],WLcyc
[w
]);
1313 callback
->printf_filtered (callback
,
1314 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1315 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
1319 callback
->printf_filtered (callback
,
1320 "Total cycles for watched functions: %d\n",wcyc
);
1325 mcore_pc_get (sim_cpu
*cpu
)
1327 return cpu
->regs
.pc
;
1331 mcore_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1337 free_state (SIM_DESC sd
)
1339 if (STATE_MODULES (sd
) != NULL
)
1340 sim_module_uninstall (sd
);
1341 sim_cpu_free_all (sd
);
1342 sim_state_free (sd
);
1346 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
,
1347 struct bfd
*abfd
, char * const *argv
)
1350 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1351 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1353 /* The cpu data is kept in a separately allocated chunk of memory. */
1354 if (sim_cpu_alloc_all (sd
, 1) != SIM_RC_OK
)
1360 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1366 /* The parser will print an error message for us, so we silently return. */
1367 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1373 /* Check for/establish the a reference program image. */
1374 if (sim_analyze_program (sd
,
1375 (STATE_PROG_ARGV (sd
) != NULL
1376 ? *STATE_PROG_ARGV (sd
)
1377 : NULL
), abfd
) != SIM_RC_OK
)
1383 /* Configure/verify the target byte order and other runtime
1384 configuration options. */
1385 if (sim_config (sd
) != SIM_RC_OK
)
1387 sim_module_uninstall (sd
);
1391 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1393 /* Uninstall the modules to avoid memory leaks,
1394 file descriptor leaks, etc. */
1395 sim_module_uninstall (sd
);
1399 /* CPU specific initialization. */
1400 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1402 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1404 CPU_REG_FETCH (cpu
) = mcore_reg_fetch
;
1405 CPU_REG_STORE (cpu
) = mcore_reg_store
;
1406 CPU_PC_FETCH (cpu
) = mcore_pc_get
;
1407 CPU_PC_STORE (cpu
) = mcore_pc_set
;
1409 set_initial_gprs (cpu
); /* Reset the GPR registers. */
1412 /* Default to a 8 Mbyte (== 2^23) memory space. */
1413 sim_do_commandf (sd
, "memory-size %#x", DEFAULT_MEMORY_SIZE
);
1419 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
,
1420 char * const *argv
, char * const *env
)
1422 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1428 unsigned long strings
;
1429 unsigned long pointers
;
1430 unsigned long hi_stack
;
1433 /* Set the initial register set. */
1434 set_initial_gprs (cpu
);
1436 hi_stack
= DEFAULT_MEMORY_SIZE
- 4;
1437 CPU_PC_SET (cpu
, bfd_get_start_address (prog_bfd
));
1439 /* Calculate the argument and environment strings. */
1445 l
= strlen (*avp
) + 1; /* include the null */
1446 s_length
+= (l
+ 3) & ~3; /* make it a 4 byte boundary */
1454 l
= strlen (*avp
) + 1; /* include the null */
1455 s_length
+= (l
+ 3) & ~ 3;/* make it a 4 byte boundary */
1459 /* Claim some memory for the pointers and strings. */
1460 pointers
= hi_stack
- sizeof(word
) * (nenv
+1+nargs
+1);
1461 pointers
&= ~3; /* must be 4-byte aligned */
1464 strings
= gr
[0] - s_length
;
1465 strings
&= ~3; /* want to make it 4-byte aligned */
1467 /* dac fix, the stack address must be 8-byte aligned! */
1468 gr
[0] = gr
[0] - gr
[0] % 8;
1470 /* Loop through the arguments and fill them in. */
1474 /* No strings to fill in. */
1479 gr
[PARM2
] = pointers
;
1483 /* Save where we're putting it. */
1484 wlat (pointers
, strings
);
1486 /* Copy the string. */
1487 l
= strlen (* avp
) + 1;
1488 sim_core_write_buffer (sd
, cpu
, write_map
, *avp
, strings
, l
);
1490 /* Bump the pointers. */
1496 /* A null to finish the list. */
1501 /* Now do the environment pointers. */
1504 /* No strings to fill in. */
1509 gr
[PARM3
] = pointers
;
1514 /* Save where we're putting it. */
1515 wlat (pointers
, strings
);
1517 /* Copy the string. */
1518 l
= strlen (* avp
) + 1;
1519 sim_core_write_buffer (sd
, cpu
, write_map
, *avp
, strings
, l
);
1521 /* Bump the pointers. */
1527 /* A null to finish the list. */