1 2003-01-14 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
5 2003-01-14 Chris Demetriou <cgd@broadcom.com>
7 * mips.igen (EI, DI): Remove.
9 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
11 * Makefile.in (tmp-run-multi): Fix mips16 filter.
13 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
14 Andrew Cagney <ac131313@redhat.com>
15 Gavin Romig-Koch <gavin@redhat.com>
16 Graydon Hoare <graydon@redhat.com>
17 Aldy Hernandez <aldyh@redhat.com>
18 Dave Brolley <brolley@redhat.com>
19 Chris Demetriou <cgd@broadcom.com>
21 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
22 (sim_mach_default): New variable.
23 (mips64vr-*-*, mips64vrel-*-*): New configurations.
24 Add a new simulator generator, MULTI.
25 * configure: Regenerate.
26 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
27 (multi-run.o): New dependency.
28 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
29 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
30 (tmp-multi): Combine them.
31 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
32 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
33 (distclean-extra): New rule.
34 * sim-main.h: Include bfd.h.
35 (MIPS_MACH): New macro.
36 * mips.igen (vr4120, vr5400, vr5500): New models.
37 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
38 * vr.igen: Replace with new version.
40 2003-01-04 Chris Demetriou <cgd@broadcom.com>
42 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
43 * configure: Regenerate.
45 2002-12-31 Chris Demetriou <cgd@broadcom.com>
47 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
48 * mips.igen: Remove all invocations of check_branch_bug and
51 2002-12-16 Chris Demetriou <cgd@broadcom.com>
53 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
55 2002-07-30 Chris Demetriou <cgd@broadcom.com>
57 * mips.igen (do_load_double, do_store_double): New functions.
58 (LDC1, SDC1): Rename to...
59 (LDC1b, SDC1b): respectively.
60 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
62 2002-07-29 Michael Snyder <msnyder@redhat.com>
64 * cp1.c (fp_recip2): Modify initialization expression so that
65 GCC will recognize it as constant.
67 2002-06-18 Chris Demetriou <cgd@broadcom.com>
69 * mdmx.c (SD_): Delete.
70 (Unpredictable): Re-define, for now, to directly invoke
71 unpredictable_action().
72 (mdmx_acc_op): Fix error in .ob immediate handling.
74 2002-06-18 Andrew Cagney <cagney@redhat.com>
76 * interp.c (sim_firmware_command): Initialize `address'.
78 2002-06-16 Andrew Cagney <ac131313@redhat.com>
80 * configure: Regenerated to track ../common/aclocal.m4 changes.
82 2002-06-14 Chris Demetriou <cgd@broadcom.com>
83 Ed Satterthwaite <ehs@broadcom.com>
85 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
86 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
87 * mips.igen: Include mips3d.igen.
88 (mips3d): New model name for MIPS-3D ASE instructions.
89 (CVT.W.fmt): Don't use this instruction for word (source) format
91 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
92 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
93 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
94 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
95 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
96 (RSquareRoot1, RSquareRoot2): New macros.
97 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
98 (fp_rsqrt2): New functions.
99 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
100 * configure: Regenerate.
102 2002-06-13 Chris Demetriou <cgd@broadcom.com>
103 Ed Satterthwaite <ehs@broadcom.com>
105 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
106 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
107 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
108 (convert): Note that this function is not used for paired-single
110 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
111 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
112 (check_fmt_p): Enable paired-single support.
113 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
114 (PUU.PS): New instructions.
115 (CVT.S.fmt): Don't use this instruction for paired-single format
117 * sim-main.h (FP_formats): New value 'fmt_ps.'
118 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
119 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
121 2002-06-12 Chris Demetriou <cgd@broadcom.com>
123 * mips.igen: Fix formatting of function calls in
126 2002-06-12 Chris Demetriou <cgd@broadcom.com>
128 * mips.igen (MOVN, MOVZ): Trace result.
129 (TNEI): Print "tnei" as the opcode name in traces.
130 (CEIL.W): Add disassembly string for traces.
131 (RSQRT.fmt): Make location of disassembly string consistent
132 with other instructions.
134 2002-06-12 Chris Demetriou <cgd@broadcom.com>
136 * mips.igen (X): Delete unused function.
138 2002-06-08 Andrew Cagney <cagney@redhat.com>
140 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
142 2002-06-07 Chris Demetriou <cgd@broadcom.com>
143 Ed Satterthwaite <ehs@broadcom.com>
145 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
146 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
147 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
148 (fp_nmsub): New prototypes.
149 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
150 (NegMultiplySub): New defines.
151 * mips.igen (RSQRT.fmt): Use RSquareRoot().
152 (MADD.D, MADD.S): Replace with...
153 (MADD.fmt): New instruction.
154 (MSUB.D, MSUB.S): Replace with...
155 (MSUB.fmt): New instruction.
156 (NMADD.D, NMADD.S): Replace with...
157 (NMADD.fmt): New instruction.
158 (NMSUB.D, MSUB.S): Replace with...
159 (NMSUB.fmt): New instruction.
161 2002-06-07 Chris Demetriou <cgd@broadcom.com>
162 Ed Satterthwaite <ehs@broadcom.com>
164 * cp1.c: Fix more comment spelling and formatting.
165 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
166 (denorm_mode): New function.
167 (fpu_unary, fpu_binary): Round results after operation, collect
168 status from rounding operations, and update the FCSR.
169 (convert): Collect status from integer conversions and rounding
170 operations, and update the FCSR. Adjust NaN values that result
171 from conversions. Convert to use sim_io_eprintf rather than
172 fprintf, and remove some debugging code.
173 * cp1.h (fenr_FS): New define.
175 2002-06-07 Chris Demetriou <cgd@broadcom.com>
177 * cp1.c (convert): Remove unusable debugging code, and move MIPS
178 rounding mode to sim FP rounding mode flag conversion code into...
179 (rounding_mode): New function.
181 2002-06-07 Chris Demetriou <cgd@broadcom.com>
183 * cp1.c: Clean up formatting of a few comments.
184 (value_fpr): Reformat switch statement.
186 2002-06-06 Chris Demetriou <cgd@broadcom.com>
187 Ed Satterthwaite <ehs@broadcom.com>
190 * sim-main.h: Include cp1.h.
191 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
192 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
193 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
194 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
195 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
196 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
197 * cp1.c: Don't include sim-fpu.h; already included by
198 sim-main.h. Clean up formatting of some comments.
199 (NaN, Equal, Less): Remove.
200 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
201 (fp_cmp): New functions.
202 * mips.igen (do_c_cond_fmt): Remove.
203 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
204 Compare. Add result tracing.
205 (CxC1): Remove, replace with...
206 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
207 (DMxC1): Remove, replace with...
208 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
209 (MxC1): Remove, replace with...
210 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
212 2002-06-04 Chris Demetriou <cgd@broadcom.com>
214 * sim-main.h (FGRIDX): Remove, replace all uses with...
215 (FGR_BASE): New macro.
216 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
217 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
218 (NR_FGR, FGR): Likewise.
219 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
220 * mips.igen: Likewise.
222 2002-06-04 Chris Demetriou <cgd@broadcom.com>
224 * cp1.c: Add an FSF Copyright notice to this file.
226 2002-06-04 Chris Demetriou <cgd@broadcom.com>
227 Ed Satterthwaite <ehs@broadcom.com>
229 * cp1.c (Infinity): Remove.
230 * sim-main.h (Infinity): Likewise.
232 * cp1.c (fp_unary, fp_binary): New functions.
233 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
234 (fp_sqrt): New functions, implemented in terms of the above.
235 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
236 (Recip, SquareRoot): Remove (replaced by functions above).
237 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
238 (fp_recip, fp_sqrt): New prototypes.
239 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
240 (Recip, SquareRoot): Replace prototypes with #defines which
241 invoke the functions above.
243 2002-06-03 Chris Demetriou <cgd@broadcom.com>
245 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
246 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
247 file, remove PARAMS from prototypes.
248 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
249 simulator state arguments.
250 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
251 pass simulator state arguments.
252 * cp1.c (SD): Redefine as CPU_STATE(cpu).
253 (store_fpr, convert): Remove 'sd' argument.
254 (value_fpr): Likewise. Convert to use 'SD' instead.
256 2002-06-03 Chris Demetriou <cgd@broadcom.com>
258 * cp1.c (Min, Max): Remove #if 0'd functions.
259 * sim-main.h (Min, Max): Remove.
261 2002-06-03 Chris Demetriou <cgd@broadcom.com>
263 * cp1.c: fix formatting of switch case and default labels.
264 * interp.c: Likewise.
265 * sim-main.c: Likewise.
267 2002-06-03 Chris Demetriou <cgd@broadcom.com>
269 * cp1.c: Clean up comments which describe FP formats.
270 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
272 2002-06-03 Chris Demetriou <cgd@broadcom.com>
273 Ed Satterthwaite <ehs@broadcom.com>
275 * configure.in (mipsisa64sb1*-*-*): New target for supporting
276 Broadcom SiByte SB-1 processor configurations.
277 * configure: Regenerate.
278 * sb1.igen: New file.
279 * mips.igen: Include sb1.igen.
281 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
282 * mdmx.igen: Add "sb1" model to all appropriate functions and
284 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
285 (ob_func, ob_acc): Reference the above.
286 (qh_acc): Adjust to keep the same size as ob_acc.
287 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
288 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
290 2002-06-03 Chris Demetriou <cgd@broadcom.com>
292 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
294 2002-06-02 Chris Demetriou <cgd@broadcom.com>
295 Ed Satterthwaite <ehs@broadcom.com>
297 * mips.igen (mdmx): New (pseudo-)model.
298 * mdmx.c, mdmx.igen: New files.
299 * Makefile.in (SIM_OBJS): Add mdmx.o.
300 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
302 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
303 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
304 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
305 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
306 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
307 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
308 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
309 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
310 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
311 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
312 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
313 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
314 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
315 (qh_fmtsel): New macros.
316 (_sim_cpu): New member "acc".
317 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
318 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
320 2002-05-01 Chris Demetriou <cgd@broadcom.com>
322 * interp.c: Use 'deprecated' rather than 'depreciated.'
323 * sim-main.h: Likewise.
325 2002-05-01 Chris Demetriou <cgd@broadcom.com>
327 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
328 which wouldn't compile anyway.
329 * sim-main.h (unpredictable_action): New function prototype.
330 (Unpredictable): Define to call igen function unpredictable().
331 (NotWordValue): New macro to call igen function not_word_value().
332 (UndefinedResult): Remove.
333 * interp.c (undefined_result): Remove.
334 (unpredictable_action): New function.
335 * mips.igen (not_word_value, unpredictable): New functions.
336 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
337 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
338 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
339 NotWordValue() to check for unpredictable inputs, then
340 Unpredictable() to handle them.
342 2002-02-24 Chris Demetriou <cgd@broadcom.com>
344 * mips.igen: Fix formatting of calls to Unpredictable().
346 2002-04-20 Andrew Cagney <ac131313@redhat.com>
348 * interp.c (sim_open): Revert previous change.
350 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
352 * interp.c (sim_open): Disable chunk of code that wrote code in
353 vector table entries.
355 2002-03-19 Chris Demetriou <cgd@broadcom.com>
357 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
358 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
361 2002-03-19 Chris Demetriou <cgd@broadcom.com>
363 * cp1.c: Fix many formatting issues.
365 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
367 * cp1.c (fpu_format_name): New function to replace...
368 (DOFMT): This. Delete, and update all callers.
369 (fpu_rounding_mode_name): New function to replace...
370 (RMMODE): This. Delete, and update all callers.
372 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
374 * interp.c: Move FPU support routines from here to...
375 * cp1.c: Here. New file.
376 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
379 2002-03-12 Chris Demetriou <cgd@broadcom.com>
381 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
382 * mips.igen (mips32, mips64): New models, add to all instructions
383 and functions as appropriate.
384 (loadstore_ea, check_u64): New variant for model mips64.
385 (check_fmt_p): New variant for models mipsV and mips64, remove
386 mipsV model marking fro other variant.
389 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
390 for mips32 and mips64.
391 (DCLO, DCLZ): New instructions for mips64.
393 2002-03-07 Chris Demetriou <cgd@broadcom.com>
395 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
396 immediate or code as a hex value with the "%#lx" format.
397 (ANDI): Likewise, and fix printed instruction name.
399 2002-03-05 Chris Demetriou <cgd@broadcom.com>
401 * sim-main.h (UndefinedResult, Unpredictable): New macros
402 which currently do nothing.
404 2002-03-05 Chris Demetriou <cgd@broadcom.com>
406 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
407 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
408 (status_CU3): New definitions.
410 * sim-main.h (ExceptionCause): Add new values for MIPS32
411 and MIPS64: MDMX, MCheck, CacheErr. Update comments
412 for DebugBreakPoint and NMIReset to note their status in
414 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
415 (SignalExceptionCacheErr): New exception macros.
417 2002-03-05 Chris Demetriou <cgd@broadcom.com>
419 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
420 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
422 (SignalExceptionCoProcessorUnusable): Take as argument the
423 unusable coprocessor number.
425 2002-03-05 Chris Demetriou <cgd@broadcom.com>
427 * mips.igen: Fix formatting of all SignalException calls.
429 2002-03-05 Chris Demetriou <cgd@broadcom.com>
431 * sim-main.h (SIGNEXTEND): Remove.
433 2002-03-04 Chris Demetriou <cgd@broadcom.com>
435 * mips.igen: Remove gencode comment from top of file, fix
436 spelling in another comment.
438 2002-03-04 Chris Demetriou <cgd@broadcom.com>
440 * mips.igen (check_fmt, check_fmt_p): New functions to check
441 whether specific floating point formats are usable.
442 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
443 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
444 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
445 Use the new functions.
446 (do_c_cond_fmt): Remove format checks...
447 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
449 2002-03-03 Chris Demetriou <cgd@broadcom.com>
451 * mips.igen: Fix formatting of check_fpu calls.
453 2002-03-03 Chris Demetriou <cgd@broadcom.com>
455 * mips.igen (FLOOR.L.fmt): Store correct destination register.
457 2002-03-03 Chris Demetriou <cgd@broadcom.com>
459 * mips.igen: Remove whitespace at end of lines.
461 2002-03-02 Chris Demetriou <cgd@broadcom.com>
463 * mips.igen (loadstore_ea): New function to do effective
464 address calculations.
465 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
466 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
467 CACHE): Use loadstore_ea to do effective address computations.
469 2002-03-02 Chris Demetriou <cgd@broadcom.com>
471 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
472 * mips.igen (LL, CxC1, MxC1): Likewise.
474 2002-03-02 Chris Demetriou <cgd@broadcom.com>
476 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
477 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
478 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
479 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
480 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
481 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
482 Don't split opcode fields by hand, use the opcode field values
485 2002-03-01 Chris Demetriou <cgd@broadcom.com>
487 * mips.igen (do_divu): Fix spacing.
489 * mips.igen (do_dsllv): Move to be right before DSLLV,
490 to match the rest of the do_<shift> functions.
492 2002-03-01 Chris Demetriou <cgd@broadcom.com>
494 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
495 DSRL32, do_dsrlv): Trace inputs and results.
497 2002-03-01 Chris Demetriou <cgd@broadcom.com>
499 * mips.igen (CACHE): Provide instruction-printing string.
501 * interp.c (signal_exception): Comment tokens after #endif.
503 2002-02-28 Chris Demetriou <cgd@broadcom.com>
505 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
506 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
507 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
508 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
509 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
510 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
511 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
512 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
514 2002-02-28 Chris Demetriou <cgd@broadcom.com>
516 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
517 instruction-printing string.
518 (LWU): Use '64' as the filter flag.
520 2002-02-28 Chris Demetriou <cgd@broadcom.com>
522 * mips.igen (SDXC1): Fix instruction-printing string.
524 2002-02-28 Chris Demetriou <cgd@broadcom.com>
526 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
529 2002-02-27 Chris Demetriou <cgd@broadcom.com>
531 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
534 2002-02-27 Chris Demetriou <cgd@broadcom.com>
536 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
537 add a comma) so that it more closely match the MIPS ISA
538 documentation opcode partitioning.
539 (PREF): Put useful names on opcode fields, and include
540 instruction-printing string.
542 2002-02-27 Chris Demetriou <cgd@broadcom.com>
544 * mips.igen (check_u64): New function which in the future will
545 check whether 64-bit instructions are usable and signal an
546 exception if not. Currently a no-op.
547 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
548 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
549 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
550 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
552 * mips.igen (check_fpu): New function which in the future will
553 check whether FPU instructions are usable and signal an exception
554 if not. Currently a no-op.
555 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
556 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
557 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
558 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
559 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
560 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
561 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
562 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
564 2002-02-27 Chris Demetriou <cgd@broadcom.com>
566 * mips.igen (do_load_left, do_load_right): Move to be immediately
568 (do_store_left, do_store_right): Move to be immediately following
571 2002-02-27 Chris Demetriou <cgd@broadcom.com>
573 * mips.igen (mipsV): New model name. Also, add it to
574 all instructions and functions where it is appropriate.
576 2002-02-18 Chris Demetriou <cgd@broadcom.com>
578 * mips.igen: For all functions and instructions, list model
579 names that support that instruction one per line.
581 2002-02-11 Chris Demetriou <cgd@broadcom.com>
583 * mips.igen: Add some additional comments about supported
584 models, and about which instructions go where.
585 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
586 order as is used in the rest of the file.
588 2002-02-11 Chris Demetriou <cgd@broadcom.com>
590 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
591 indicating that ALU32_END or ALU64_END are there to check
593 (DADD): Likewise, but also remove previous comment about
596 2002-02-10 Chris Demetriou <cgd@broadcom.com>
598 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
599 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
600 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
601 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
602 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
603 fields (i.e., add and move commas) so that they more closely
604 match the MIPS ISA documentation opcode partitioning.
606 2002-02-10 Chris Demetriou <cgd@broadcom.com>
608 * mips.igen (ADDI): Print immediate value.
610 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
611 (SLL): Print "nop" specially, and don't run the code
612 that does the shift for the "nop" case.
614 2001-11-17 Fred Fish <fnf@redhat.com>
616 * sim-main.h (float_operation): Move enum declaration outside
617 of _sim_cpu struct declaration.
619 2001-04-12 Jim Blandy <jimb@redhat.com>
621 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
622 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
624 * sim-main.h (COCIDX): Remove definition; this isn't supported by
625 PENDING_FILL, and you can get the intended effect gracefully by
626 calling PENDING_SCHED directly.
628 2001-02-23 Ben Elliston <bje@redhat.com>
630 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
631 already defined elsewhere.
633 2001-02-19 Ben Elliston <bje@redhat.com>
635 * sim-main.h (sim_monitor): Return an int.
636 * interp.c (sim_monitor): Add return values.
637 (signal_exception): Handle error conditions from sim_monitor.
639 2001-02-08 Ben Elliston <bje@redhat.com>
641 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
642 (store_memory): Likewise, pass cia to sim_core_write*.
644 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
646 On advice from Chris G. Demetriou <cgd@sibyte.com>:
647 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
649 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
651 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
652 * Makefile.in: Don't delete *.igen when cleaning directory.
654 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
656 * m16.igen (break): Call SignalException not sim_engine_halt.
658 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
661 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
663 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
665 * mips.igen (MxC1, DMxC1): Fix printf formatting.
667 2000-05-24 Michael Hayes <mhayes@cygnus.com>
669 * mips.igen (do_dmultx): Fix typo.
671 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
673 * configure: Regenerated to track ../common/aclocal.m4 changes.
675 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
677 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
679 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
681 * sim-main.h (GPR_CLEAR): Define macro.
683 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
685 * interp.c (decode_coproc): Output long using %lx and not %s.
687 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
689 * interp.c (sim_open): Sort & extend dummy memory regions for
690 --board=jmr3904 for eCos.
692 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
694 * configure: Regenerated.
696 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
698 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
699 calls, conditional on the simulator being in verbose mode.
701 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
703 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
704 cache don't get ReservedInstruction traps.
706 1999-11-29 Mark Salter <msalter@cygnus.com>
708 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
709 to clear status bits in sdisr register. This is how the hardware works.
711 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
712 being used by cygmon.
714 1999-11-11 Andrew Haley <aph@cygnus.com>
716 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
719 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
721 * mips.igen (MULT): Correct previous mis-applied patch.
723 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
725 * mips.igen (delayslot32): Handle sequence like
726 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
727 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
728 (MULT): Actually pass the third register...
730 1999-09-03 Mark Salter <msalter@cygnus.com>
732 * interp.c (sim_open): Added more memory aliases for additional
733 hardware being touched by cygmon on jmr3904 board.
735 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
737 * configure: Regenerated to track ../common/aclocal.m4 changes.
739 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
741 * interp.c (sim_store_register): Handle case where client - GDB -
742 specifies that a 4 byte register is 8 bytes in size.
743 (sim_fetch_register): Ditto.
745 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
747 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
748 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
749 (idt_monitor_base): Base address for IDT monitor traps.
750 (pmon_monitor_base): Ditto for PMON.
751 (lsipmon_monitor_base): Ditto for LSI PMON.
752 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
753 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
754 (sim_firmware_command): New function.
755 (mips_option_handler): Call it for OPTION_FIRMWARE.
756 (sim_open): Allocate memory for idt_monitor region. If "--board"
757 option was given, add no monitor by default. Add BREAK hooks only if
758 monitors are also there.
760 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
762 * interp.c (sim_monitor): Flush output before reading input.
764 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
766 * tconfig.in (SIM_HANDLES_LMA): Always define.
768 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
770 From Mark Salter <msalter@cygnus.com>:
771 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
772 (sim_open): Add setup for BSP board.
774 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
776 * mips.igen (MULT, MULTU): Add syntax for two operand version.
777 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
778 them as unimplemented.
780 1999-05-08 Felix Lee <flee@cygnus.com>
782 * configure: Regenerated to track ../common/aclocal.m4 changes.
784 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
786 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
788 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
790 * configure.in: Any mips64vr5*-*-* target should have
791 -DTARGET_ENABLE_FR=1.
792 (default_endian): Any mips64vr*el-*-* target should default to
794 * configure: Re-generate.
796 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
798 * mips.igen (ldl): Extend from _16_, not 32.
800 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
802 * interp.c (sim_store_register): Force registers written to by GDB
803 into an un-interpreted state.
805 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
807 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
808 CPU, start periodic background I/O polls.
809 (tx3904sio_poll): New function: periodic I/O poller.
811 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
813 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
815 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
817 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
820 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
822 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
823 (load_word): Call SIM_CORE_SIGNAL hook on error.
824 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
825 starting. For exception dispatching, pass PC instead of NULL_CIA.
826 (decode_coproc): Use COP0_BADVADDR to store faulting address.
827 * sim-main.h (COP0_BADVADDR): Define.
828 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
829 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
830 (_sim_cpu): Add exc_* fields to store register value snapshots.
831 * mips.igen (*): Replace memory-related SignalException* calls
832 with references to SIM_CORE_SIGNAL hook.
834 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
836 * sim-main.c (*): Minor warning cleanups.
838 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
840 * m16.igen (DADDIU5): Correct type-o.
842 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
844 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
847 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
849 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
851 (interp.o): Add dependency on itable.h
852 (oengine.c, gencode): Delete remaining references.
853 (BUILT_SRC_FROM_GEN): Clean up.
855 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
858 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
859 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
861 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
862 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
863 Drop the "64" qualifier to get the HACK generator working.
864 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
865 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
866 qualifier to get the hack generator working.
867 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
869 (DSLLV): Use do_dsllv.
872 (DSRLV): Use do_dsrlv.
873 (BC1): Move *vr4100 to get the HACK generator working.
874 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
875 get the HACK generator working.
876 (MACC) Rename to get the HACK generator working.
877 (DMACC,MACCS,DMACCS): Add the 64.
879 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
881 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
882 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
884 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
886 * mips/interp.c (DEBUG): Cleanups.
888 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
890 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
891 (tx3904sio_tickle): fflush after a stdout character output.
893 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
895 * interp.c (sim_close): Uninstall modules.
897 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
899 * sim-main.h, interp.c (sim_monitor): Change to global
902 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
904 * configure.in (vr4100): Only include vr4100 instructions in
906 * configure: Re-generate.
907 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
909 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
911 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
912 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
915 * configure.in (sim_default_gen, sim_use_gen): Replace with
917 (--enable-sim-igen): Delete config option. Always using IGEN.
918 * configure: Re-generate.
920 * Makefile.in (gencode): Kill, kill, kill.
923 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
925 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
926 bit mips16 igen simulator.
927 * configure: Re-generate.
929 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
930 as part of vr4100 ISA.
931 * vr.igen: Mark all instructions as 64 bit only.
933 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
935 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
938 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
940 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
941 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
942 * configure: Re-generate.
944 * m16.igen (BREAK): Define breakpoint instruction.
945 (JALX32): Mark instruction as mips16 and not r3900.
946 * mips.igen (C.cond.fmt): Fix typo in instruction format.
948 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
950 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
952 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
953 insn as a debug breakpoint.
955 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
957 (PENDING_SCHED): Clean up trace statement.
958 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
959 (PENDING_FILL): Delay write by only one cycle.
960 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
962 * sim-main.c (pending_tick): Clean up trace statements. Add trace
964 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
966 (pending_tick): Move incrementing of index to FOR statement.
967 (pending_tick): Only update PENDING_OUT after a write has occured.
969 * configure.in: Add explicit mips-lsi-* target. Use gencode to
971 * configure: Re-generate.
973 * interp.c (sim_engine_run OLD): Delete explicit call to
974 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
976 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
978 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
979 interrupt level number to match changed SignalExceptionInterrupt
982 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
984 * interp.c: #include "itable.h" if WITH_IGEN.
985 (get_insn_name): New function.
986 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
987 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
989 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
991 * configure: Rebuilt to inhale new common/aclocal.m4.
993 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
995 * dv-tx3904sio.c: Include sim-assert.h.
997 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
999 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1000 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1001 Reorganize target-specific sim-hardware checks.
1002 * configure: rebuilt.
1003 * interp.c (sim_open): For tx39 target boards, set
1004 OPERATING_ENVIRONMENT, add tx3904sio devices.
1005 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1006 ROM executables. Install dv-sockser into sim-modules list.
1008 * dv-tx3904irc.c: Compiler warning clean-up.
1009 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1010 frequent hw-trace messages.
1012 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1014 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1016 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1018 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1020 * vr.igen: New file.
1021 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1022 * mips.igen: Define vr4100 model. Include vr.igen.
1023 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1025 * mips.igen (check_mf_hilo): Correct check.
1027 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1029 * sim-main.h (interrupt_event): Add prototype.
1031 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1032 register_ptr, register_value.
1033 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1035 * sim-main.h (tracefh): Make extern.
1037 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1039 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1040 Reduce unnecessarily high timer event frequency.
1041 * dv-tx3904cpu.c: Ditto for interrupt event.
1043 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1045 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1047 (interrupt_event): Made non-static.
1049 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1050 interchange of configuration values for external vs. internal
1053 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1055 * mips.igen (BREAK): Moved code to here for
1056 simulator-reserved break instructions.
1057 * gencode.c (build_instruction): Ditto.
1058 * interp.c (signal_exception): Code moved from here. Non-
1059 reserved instructions now use exception vector, rather
1061 * sim-main.h: Moved magic constants to here.
1063 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1065 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1066 register upon non-zero interrupt event level, clear upon zero
1068 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1069 by passing zero event value.
1070 (*_io_{read,write}_buffer): Endianness fixes.
1071 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1072 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1074 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1075 serial I/O and timer module at base address 0xFFFF0000.
1077 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1079 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1082 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1084 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1086 * configure: Update.
1088 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1090 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1091 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1092 * configure.in: Include tx3904tmr in hw_device list.
1093 * configure: Rebuilt.
1094 * interp.c (sim_open): Instantiate three timer instances.
1095 Fix address typo of tx3904irc instance.
1097 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1099 * interp.c (signal_exception): SystemCall exception now uses
1100 the exception vector.
1102 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1104 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1107 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1111 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1115 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1116 sim-main.h. Declare a struct hw_descriptor instead of struct
1117 hw_device_descriptor.
1119 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1121 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1122 right bits and then re-align left hand bytes to correct byte
1123 lanes. Fix incorrect computation in do_store_left when loading
1124 bytes from second word.
1126 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1128 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1129 * interp.c (sim_open): Only create a device tree when HW is
1132 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1133 * interp.c (signal_exception): Ditto.
1135 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1137 * gencode.c: Mark BEGEZALL as LIKELY.
1139 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1142 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1144 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1146 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1147 modules. Recognize TX39 target with "mips*tx39" pattern.
1148 * configure: Rebuilt.
1149 * sim-main.h (*): Added many macros defining bits in
1150 TX39 control registers.
1151 (SignalInterrupt): Send actual PC instead of NULL.
1152 (SignalNMIReset): New exception type.
1153 * interp.c (board): New variable for future use to identify
1154 a particular board being simulated.
1155 (mips_option_handler,mips_options): Added "--board" option.
1156 (interrupt_event): Send actual PC.
1157 (sim_open): Make memory layout conditional on board setting.
1158 (signal_exception): Initial implementation of hardware interrupt
1159 handling. Accept another break instruction variant for simulator
1161 (decode_coproc): Implement RFE instruction for TX39.
1162 (mips.igen): Decode RFE instruction as such.
1163 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1164 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1165 bbegin to implement memory map.
1166 * dv-tx3904cpu.c: New file.
1167 * dv-tx3904irc.c: New file.
1169 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1171 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1173 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1175 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1176 with calls to check_div_hilo.
1178 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1180 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1181 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1182 Add special r3900 version of do_mult_hilo.
1183 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1184 with calls to check_mult_hilo.
1185 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1186 with calls to check_div_hilo.
1188 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1190 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1191 Document a replacement.
1193 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1195 * interp.c (sim_monitor): Make mon_printf work.
1197 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1199 * sim-main.h (INSN_NAME): New arg `cpu'.
1201 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1203 * configure: Regenerated to track ../common/aclocal.m4 changes.
1205 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1207 * configure: Regenerated to track ../common/aclocal.m4 changes.
1210 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1212 * acconfig.h: New file.
1213 * configure.in: Reverted change of Apr 24; use sinclude again.
1215 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1217 * configure: Regenerated to track ../common/aclocal.m4 changes.
1220 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1222 * configure.in: Don't call sinclude.
1224 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1226 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1228 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230 * mips.igen (ERET): Implement.
1232 * interp.c (decode_coproc): Return sign-extended EPC.
1234 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1236 * interp.c (signal_exception): Do not ignore Trap.
1237 (signal_exception): On TRAP, restart at exception address.
1238 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1239 (signal_exception): Update.
1240 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1241 so that TRAP instructions are caught.
1243 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1245 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1246 contains HI/LO access history.
1247 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1248 (HIACCESS, LOACCESS): Delete, replace with
1249 (HIHISTORY, LOHISTORY): New macros.
1250 (CHECKHILO): Delete all, moved to mips.igen
1252 * gencode.c (build_instruction): Do not generate checks for
1253 correct HI/LO register usage.
1255 * interp.c (old_engine_run): Delete checks for correct HI/LO
1258 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1259 check_mf_cycles): New functions.
1260 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1261 do_divu, domultx, do_mult, do_multu): Use.
1263 * tx.igen ("madd", "maddu"): Use.
1265 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1267 * mips.igen (DSRAV): Use function do_dsrav.
1268 (SRAV): Use new function do_srav.
1270 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1271 (B): Sign extend 11 bit immediate.
1272 (EXT-B*): Shift 16 bit immediate left by 1.
1273 (ADDIU*): Don't sign extend immediate value.
1275 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1277 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1279 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1282 * mips.igen (delayslot32, nullify_next_insn): New functions.
1283 (m16.igen): Always include.
1284 (do_*): Add more tracing.
1286 * m16.igen (delayslot16): Add NIA argument, could be called by a
1287 32 bit MIPS16 instruction.
1289 * interp.c (ifetch16): Move function from here.
1290 * sim-main.c (ifetch16): To here.
1292 * sim-main.c (ifetch16, ifetch32): Update to match current
1293 implementations of LH, LW.
1294 (signal_exception): Don't print out incorrect hex value of illegal
1297 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1302 * m16.igen: Implement MIPS16 instructions.
1304 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1305 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1306 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1307 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1308 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1309 bodies of corresponding code from 32 bit insn to these. Also used
1310 by MIPS16 versions of functions.
1312 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1313 (IMEM16): Drop NR argument from macro.
1315 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317 * Makefile.in (SIM_OBJS): Add sim-main.o.
1319 * sim-main.h (address_translation, load_memory, store_memory,
1320 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1322 (pr_addr, pr_uword64): Declare.
1323 (sim-main.c): Include when H_REVEALS_MODULE_P.
1325 * interp.c (address_translation, load_memory, store_memory,
1326 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1328 * sim-main.c: To here. Fix compilation problems.
1330 * configure.in: Enable inlining.
1331 * configure: Re-config.
1333 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1335 * configure: Regenerated to track ../common/aclocal.m4 changes.
1337 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1339 * mips.igen: Include tx.igen.
1340 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1341 * tx.igen: New file, contains MADD and MADDU.
1343 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1344 the hardwired constant `7'.
1345 (store_memory): Ditto.
1346 (LOADDRMASK): Move definition to sim-main.h.
1348 mips.igen (MTC0): Enable for r3900.
1351 mips.igen (do_load_byte): Delete.
1352 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1353 do_store_right): New functions.
1354 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1356 configure.in: Let the tx39 use igen again.
1359 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1362 not an address sized quantity. Return zero for cache sizes.
1364 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1366 * mips.igen (r3900): r3900 does not support 64 bit integer
1369 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1371 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1373 * configure : Rebuild.
1375 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1377 * configure: Regenerated to track ../common/aclocal.m4 changes.
1379 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1383 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1385 * configure: Regenerated to track ../common/aclocal.m4 changes.
1386 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1388 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390 * configure: Regenerated to track ../common/aclocal.m4 changes.
1392 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394 * interp.c (Max, Min): Comment out functions. Not yet used.
1396 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1400 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1402 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1403 configurable settings for stand-alone simulator.
1405 * configure.in: Added X11 search, just in case.
1407 * configure: Regenerated.
1409 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411 * interp.c (sim_write, sim_read, load_memory, store_memory):
1412 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1414 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416 * sim-main.h (GETFCC): Return an unsigned value.
1418 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1421 (DADD): Result destination is RD not RT.
1423 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1425 * sim-main.h (HIACCESS, LOACCESS): Always define.
1427 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1429 * interp.c (sim_info): Delete.
1431 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1433 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1434 (mips_option_handler): New argument `cpu'.
1435 (sim_open): Update call to sim_add_option_table.
1437 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1439 * mips.igen (CxC1): Add tracing.
1441 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443 * sim-main.h (Max, Min): Declare.
1445 * interp.c (Max, Min): New functions.
1447 * mips.igen (BC1): Add tracing.
1449 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1451 * interp.c Added memory map for stack in vr4100
1453 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1455 * interp.c (load_memory): Add missing "break"'s.
1457 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459 * interp.c (sim_store_register, sim_fetch_register): Pass in
1460 length parameter. Return -1.
1462 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1464 * interp.c: Added hardware init hook, fixed warnings.
1466 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1468 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1470 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472 * interp.c (ifetch16): New function.
1474 * sim-main.h (IMEM32): Rename IMEM.
1475 (IMEM16_IMMED): Define.
1477 (DELAY_SLOT): Update.
1479 * m16run.c (sim_engine_run): New file.
1481 * m16.igen: All instructions except LB.
1482 (LB): Call do_load_byte.
1483 * mips.igen (do_load_byte): New function.
1484 (LB): Call do_load_byte.
1486 * mips.igen: Move spec for insn bit size and high bit from here.
1487 * Makefile.in (tmp-igen, tmp-m16): To here.
1489 * m16.dc: New file, decode mips16 instructions.
1491 * Makefile.in (SIM_NO_ALL): Define.
1492 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1494 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1496 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1497 point unit to 32 bit registers.
1498 * configure: Re-generate.
1500 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1502 * configure.in (sim_use_gen): Make IGEN the default simulator
1503 generator for generic 32 and 64 bit mips targets.
1504 * configure: Re-generate.
1506 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1511 * interp.c (sim_fetch_register, sim_store_register): Read/write
1512 FGR from correct location.
1513 (sim_open): Set size of FGR's according to
1514 WITH_TARGET_FLOATING_POINT_BITSIZE.
1516 * sim-main.h (FGR): Store floating point registers in a separate
1519 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1521 * configure: Regenerated to track ../common/aclocal.m4 changes.
1523 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1525 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1527 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1529 * interp.c (pending_tick): New function. Deliver pending writes.
1531 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1532 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1533 it can handle mixed sized quantites and single bits.
1535 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1537 * interp.c (oengine.h): Do not include when building with IGEN.
1538 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1539 (sim_info): Ditto for PROCESSOR_64BIT.
1540 (sim_monitor): Replace ut_reg with unsigned_word.
1541 (*): Ditto for t_reg.
1542 (LOADDRMASK): Define.
1543 (sim_open): Remove defunct check that host FP is IEEE compliant,
1544 using software to emulate floating point.
1545 (value_fpr, ...): Always compile, was conditional on HASFPU.
1547 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1552 * interp.c (SD, CPU): Define.
1553 (mips_option_handler): Set flags in each CPU.
1554 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1555 (sim_close): Do not clear STATE, deleted anyway.
1556 (sim_write, sim_read): Assume CPU zero's vm should be used for
1558 (sim_create_inferior): Set the PC for all processors.
1559 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1561 (mips16_entry): Pass correct nr of args to store_word, load_word.
1562 (ColdReset): Cold reset all cpu's.
1563 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1564 (sim_monitor, load_memory, store_memory, signal_exception): Use
1565 `CPU' instead of STATE_CPU.
1568 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1571 * sim-main.h (signal_exception): Add sim_cpu arg.
1572 (SignalException*): Pass both SD and CPU to signal_exception.
1573 * interp.c (signal_exception): Update.
1575 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1577 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1578 address_translation): Ditto
1579 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1581 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1583 * configure: Regenerated to track ../common/aclocal.m4 changes.
1585 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1587 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1589 * mips.igen (model): Map processor names onto BFD name.
1591 * sim-main.h (CPU_CIA): Delete.
1592 (SET_CIA, GET_CIA): Define
1594 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1596 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1599 * configure.in (default_endian): Configure a big-endian simulator
1601 * configure: Re-generate.
1603 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1605 * configure: Regenerated to track ../common/aclocal.m4 changes.
1607 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1609 * interp.c (sim_monitor): Handle Densan monitor outbyte
1610 and inbyte functions.
1612 1997-12-29 Felix Lee <flee@cygnus.com>
1614 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1616 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1618 * Makefile.in (tmp-igen): Arrange for $zero to always be
1619 reset to zero after every instruction.
1621 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623 * configure: Regenerated to track ../common/aclocal.m4 changes.
1626 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1628 * mips.igen (MSUB): Fix to work like MADD.
1629 * gencode.c (MSUB): Similarly.
1631 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1633 * configure: Regenerated to track ../common/aclocal.m4 changes.
1635 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1639 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * sim-main.h (sim-fpu.h): Include.
1643 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1644 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1645 using host independant sim_fpu module.
1647 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649 * interp.c (signal_exception): Report internal errors with SIGABRT
1652 * sim-main.h (C0_CONFIG): New register.
1653 (signal.h): No longer include.
1655 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1657 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1659 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1661 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * mips.igen: Tag vr5000 instructions.
1664 (ANDI): Was missing mipsIV model, fix assembler syntax.
1665 (do_c_cond_fmt): New function.
1666 (C.cond.fmt): Handle mips I-III which do not support CC field
1668 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1669 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1671 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1672 vr5000 which saves LO in a GPR separatly.
1674 * configure.in (enable-sim-igen): For vr5000, select vr5000
1675 specific instructions.
1676 * configure: Re-generate.
1678 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1682 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1683 fmt_uninterpreted_64 bit cases to switch. Convert to
1686 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1688 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1689 as specified in IV3.2 spec.
1690 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1692 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1694 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1695 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1696 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1697 PENDING_FILL versions of instructions. Simplify.
1699 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1701 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1703 (MTHI, MFHI): Disable code checking HI-LO.
1705 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1707 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1709 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711 * gencode.c (build_mips16_operands): Replace IPC with cia.
1713 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1714 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1716 (UndefinedResult): Replace function with macro/function
1718 (sim_engine_run): Don't save PC in IPC.
1720 * sim-main.h (IPC): Delete.
1723 * interp.c (signal_exception, store_word, load_word,
1724 address_translation, load_memory, store_memory, cache_op,
1725 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1726 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1727 current instruction address - cia - argument.
1728 (sim_read, sim_write): Call address_translation directly.
1729 (sim_engine_run): Rename variable vaddr to cia.
1730 (signal_exception): Pass cia to sim_monitor
1732 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1733 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1734 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1736 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1737 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1740 * interp.c (signal_exception): Pass restart address to
1743 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1744 idecode.o): Add dependency.
1746 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1748 (DELAY_SLOT): Update NIA not PC with branch address.
1749 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1751 * mips.igen: Use CIA not PC in branch calculations.
1752 (illegal): Call SignalException.
1753 (BEQ, ADDIU): Fix assembler.
1755 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757 * m16.igen (JALX): Was missing.
1759 * configure.in (enable-sim-igen): New configuration option.
1760 * configure: Re-generate.
1762 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1764 * interp.c (load_memory, store_memory): Delete parameter RAW.
1765 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1766 bypassing {load,store}_memory.
1768 * sim-main.h (ByteSwapMem): Delete definition.
1770 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1772 * interp.c (sim_do_command, sim_commands): Delete mips specific
1773 commands. Handled by module sim-options.
1775 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1776 (WITH_MODULO_MEMORY): Define.
1778 * interp.c (sim_info): Delete code printing memory size.
1780 * interp.c (mips_size): Nee sim_size, delete function.
1782 (monitor, monitor_base, monitor_size): Delete global variables.
1783 (sim_open, sim_close): Delete code creating monitor and other
1784 memory regions. Use sim-memopts module, via sim_do_commandf, to
1785 manage memory regions.
1786 (load_memory, store_memory): Use sim-core for memory model.
1788 * interp.c (address_translation): Delete all memory map code
1789 except line forcing 32 bit addresses.
1791 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1796 * interp.c (logfh, logfile): Delete globals.
1797 (sim_open, sim_close): Delete code opening & closing log file.
1798 (mips_option_handler): Delete -l and -n options.
1799 (OPTION mips_options): Ditto.
1801 * interp.c (OPTION mips_options): Rename option trace to dinero.
1802 (mips_option_handler): Update.
1804 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1806 * interp.c (fetch_str): New function.
1807 (sim_monitor): Rewrite using sim_read & sim_write.
1808 (sim_open): Check magic number.
1809 (sim_open): Write monitor vectors into memory using sim_write.
1810 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1811 (sim_read, sim_write): Simplify - transfer data one byte at a
1813 (load_memory, store_memory): Clarify meaning of parameter RAW.
1815 * sim-main.h (isHOST): Defete definition.
1816 (isTARGET): Mark as depreciated.
1817 (address_translation): Delete parameter HOST.
1819 * interp.c (address_translation): Delete parameter HOST.
1821 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1826 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1828 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1830 * mips.igen: Add model filter field to records.
1832 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1834 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1836 interp.c (sim_engine_run): Do not compile function sim_engine_run
1837 when WITH_IGEN == 1.
1839 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1840 target architecture.
1842 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1843 igen. Replace with configuration variables sim_igen_flags /
1846 * m16.igen: New file. Copy mips16 insns here.
1847 * mips.igen: From here.
1849 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1851 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1853 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1855 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1857 * gencode.c (build_instruction): Follow sim_write's lead in using
1858 BigEndianMem instead of !ByteSwapMem.
1860 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1862 * configure.in (sim_gen): Dependent on target, select type of
1863 generator. Always select old style generator.
1865 configure: Re-generate.
1867 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1869 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1870 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1871 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1872 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1873 SIM_@sim_gen@_*, set by autoconf.
1875 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1877 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1879 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1880 CURRENT_FLOATING_POINT instead.
1882 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1883 (address_translation): Raise exception InstructionFetch when
1884 translation fails and isINSTRUCTION.
1886 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1887 sim_engine_run): Change type of of vaddr and paddr to
1889 (address_translation, prefetch, load_memory, store_memory,
1890 cache_op): Change type of vAddr and pAddr to address_word.
1892 * gencode.c (build_instruction): Change type of vaddr and paddr to
1895 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1898 macro to obtain result of ALU op.
1900 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * interp.c (sim_info): Call profile_print.
1904 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1906 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1908 * sim-main.h (WITH_PROFILE): Do not define, defined in
1909 common/sim-config.h. Use sim-profile module.
1910 (simPROFILE): Delete defintion.
1912 * interp.c (PROFILE): Delete definition.
1913 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1914 (sim_close): Delete code writing profile histogram.
1915 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1917 (sim_engine_run): Delete code profiling the PC.
1919 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1921 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1923 * interp.c (sim_monitor): Make register pointers of type
1926 * sim-main.h: Make registers of type unsigned_word not
1929 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1931 * interp.c (sync_operation): Rename from SyncOperation, make
1932 global, add SD argument.
1933 (prefetch): Rename from Prefetch, make global, add SD argument.
1934 (decode_coproc): Make global.
1936 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1938 * gencode.c (build_instruction): Generate DecodeCoproc not
1939 decode_coproc calls.
1941 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1942 (SizeFGR): Move to sim-main.h
1943 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1944 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1945 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1947 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1948 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1949 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1950 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1951 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1952 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1954 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1956 (sim-alu.h): Include.
1957 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1958 (sim_cia): Typedef to instruction_address.
1960 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1962 * Makefile.in (interp.o): Rename generated file engine.c to
1967 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1971 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973 * gencode.c (build_instruction): For "FPSQRT", output correct
1974 number of arguments to Recip.
1976 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1978 * Makefile.in (interp.o): Depends on sim-main.h
1980 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1982 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1983 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1984 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1985 STATE, DSSTATE): Define
1986 (GPR, FGRIDX, ..): Define.
1988 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1989 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1990 (GPR, FGRIDX, ...): Delete macros.
1992 * interp.c: Update names to match defines from sim-main.h
1994 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996 * interp.c (sim_monitor): Add SD argument.
1997 (sim_warning): Delete. Replace calls with calls to
1999 (sim_error): Delete. Replace calls with sim_io_error.
2000 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2001 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2002 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2004 (mips_size): Rename from sim_size. Add SD argument.
2006 * interp.c (simulator): Delete global variable.
2007 (callback): Delete global variable.
2008 (mips_option_handler, sim_open, sim_write, sim_read,
2009 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2010 sim_size,sim_monitor): Use sim_io_* not callback->*.
2011 (sim_open): ZALLOC simulator struct.
2012 (PROFILE): Do not define.
2014 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2016 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2017 support.h with corresponding code.
2019 * sim-main.h (word64, uword64), support.h: Move definition to
2021 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2024 * Makefile.in: Update dependencies
2025 * interp.c: Do not include.
2027 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * interp.c (address_translation, load_memory, store_memory,
2030 cache_op): Rename to from AddressTranslation et.al., make global,
2033 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2036 * interp.c (SignalException): Rename to signal_exception, make
2039 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2041 * sim-main.h (SignalException, SignalExceptionInterrupt,
2042 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2043 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2044 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2047 * interp.c, support.h: Use.
2049 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2052 to value_fpr / store_fpr. Add SD argument.
2053 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2054 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2056 * sim-main.h (ValueFPR, StoreFPR): Define.
2058 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2060 * interp.c (sim_engine_run): Check consistency between configure
2061 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2064 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2065 (mips_fpu): Configure WITH_FLOATING_POINT.
2066 (mips_endian): Configure WITH_TARGET_ENDIAN.
2067 * configure: Update.
2069 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071 * configure: Regenerated to track ../common/aclocal.m4 changes.
2073 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2075 * configure: Regenerated.
2077 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2079 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2081 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2083 * gencode.c (print_igen_insn_models): Assume certain architectures
2084 include all mips* instructions.
2085 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2088 * Makefile.in (tmp.igen): Add target. Generate igen input from
2091 * gencode.c (FEATURE_IGEN): Define.
2092 (main): Add --igen option. Generate output in igen format.
2093 (process_instructions): Format output according to igen option.
2094 (print_igen_insn_format): New function.
2095 (print_igen_insn_models): New function.
2096 (process_instructions): Only issue warnings and ignore
2097 instructions when no FEATURE_IGEN.
2099 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2104 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106 * configure: Regenerated to track ../common/aclocal.m4 changes.
2108 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2111 SIM_RESERVED_BITS): Delete, moved to common.
2112 (SIM_EXTRA_CFLAGS): Update.
2114 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * configure.in: Configure non-strict memory alignment.
2117 * configure: Regenerated to track ../common/aclocal.m4 changes.
2119 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121 * configure: Regenerated to track ../common/aclocal.m4 changes.
2123 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2125 * gencode.c (SDBBP,DERET): Added (3900) insns.
2126 (RFE): Turn on for 3900.
2127 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2128 (dsstate): Made global.
2129 (SUBTARGET_R3900): Added.
2130 (CANCELDELAYSLOT): New.
2131 (SignalException): Ignore SystemCall rather than ignore and
2132 terminate. Add DebugBreakPoint handling.
2133 (decode_coproc): New insns RFE, DERET; and new registers Debug
2134 and DEPC protected by SUBTARGET_R3900.
2135 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2137 * Makefile.in,configure.in: Add mips subtarget option.
2138 * configure: Update.
2140 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2142 * gencode.c: Add r3900 (tx39).
2145 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2147 * gencode.c (build_instruction): Don't need to subtract 4 for
2150 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2152 * interp.c: Correct some HASFPU problems.
2154 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2156 * configure: Regenerated to track ../common/aclocal.m4 changes.
2158 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160 * interp.c (mips_options): Fix samples option short form, should
2163 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165 * interp.c (sim_info): Enable info code. Was just returning.
2167 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2172 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2176 (build_instruction): Ditto for LL.
2178 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184 * configure: Regenerated to track ../common/aclocal.m4 changes.
2187 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189 * interp.c (sim_open): Add call to sim_analyze_program, update
2192 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2194 * interp.c (sim_kill): Delete.
2195 (sim_create_inferior): Add ABFD argument. Set PC from same.
2196 (sim_load): Move code initializing trap handlers from here.
2197 (sim_open): To here.
2198 (sim_load): Delete, use sim-hload.c.
2200 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2202 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204 * configure: Regenerated to track ../common/aclocal.m4 changes.
2207 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209 * interp.c (sim_open): Add ABFD argument.
2210 (sim_load): Move call to sim_config from here.
2211 (sim_open): To here. Check return status.
2213 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2215 * gencode.c (build_instruction): Two arg MADD should
2216 not assign result to $0.
2218 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2220 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2221 * sim/mips/configure.in: Regenerate.
2223 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2225 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2226 signed8, unsigned8 et.al. types.
2228 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2229 hosts when selecting subreg.
2231 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2233 * interp.c (sim_engine_run): Reset the ZERO register to zero
2234 regardless of FEATURE_WARN_ZERO.
2235 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2237 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2239 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2240 (SignalException): For BreakPoints ignore any mode bits and just
2242 (SignalException): Always set the CAUSE register.
2244 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2246 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2247 exception has been taken.
2249 * interp.c: Implement the ERET and mt/f sr instructions.
2251 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253 * interp.c (SignalException): Don't bother restarting an
2256 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258 * interp.c (SignalException): Really take an interrupt.
2259 (interrupt_event): Only deliver interrupts when enabled.
2261 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * interp.c (sim_info): Only print info when verbose.
2264 (sim_info) Use sim_io_printf for output.
2266 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2271 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2273 * interp.c (sim_do_command): Check for common commands if a
2274 simulator specific command fails.
2276 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2278 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2279 and simBE when DEBUG is defined.
2281 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2283 * interp.c (interrupt_event): New function. Pass exception event
2284 onto exception handler.
2286 * configure.in: Check for stdlib.h.
2287 * configure: Regenerate.
2289 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2290 variable declaration.
2291 (build_instruction): Initialize memval1.
2292 (build_instruction): Add UNUSED attribute to byte, bigend,
2294 (build_operands): Ditto.
2296 * interp.c: Fix GCC warnings.
2297 (sim_get_quit_code): Delete.
2299 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2300 * Makefile.in: Ditto.
2301 * configure: Re-generate.
2303 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2305 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2307 * interp.c (mips_option_handler): New function parse argumes using
2309 (myname): Replace with STATE_MY_NAME.
2310 (sim_open): Delete check for host endianness - performed by
2312 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2313 (sim_open): Move much of the initialization from here.
2314 (sim_load): To here. After the image has been loaded and
2316 (sim_open): Move ColdReset from here.
2317 (sim_create_inferior): To here.
2318 (sim_open): Make FP check less dependant on host endianness.
2320 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2322 * interp.c (sim_set_callbacks): Delete.
2324 * interp.c (membank, membank_base, membank_size): Replace with
2325 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2326 (sim_open): Remove call to callback->init. gdb/run do this.
2330 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2332 * interp.c (big_endian_p): Delete, replaced by
2333 current_target_byte_order.
2335 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * interp.c (host_read_long, host_read_word, host_swap_word,
2338 host_swap_long): Delete. Using common sim-endian.
2339 (sim_fetch_register, sim_store_register): Use H2T.
2340 (pipeline_ticks): Delete. Handled by sim-events.
2342 (sim_engine_run): Update.
2344 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2348 (SignalException): To here. Signal using sim_engine_halt.
2349 (sim_stop_reason): Delete, moved to common.
2351 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2353 * interp.c (sim_open): Add callback argument.
2354 (sim_set_callbacks): Delete SIM_DESC argument.
2357 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2359 * Makefile.in (SIM_OBJS): Add common modules.
2361 * interp.c (sim_set_callbacks): Also set SD callback.
2362 (set_endianness, xfer_*, swap_*): Delete.
2363 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2364 Change to functions using sim-endian macros.
2365 (control_c, sim_stop): Delete, use common version.
2366 (simulate): Convert into.
2367 (sim_engine_run): This function.
2368 (sim_resume): Delete.
2370 * interp.c (simulation): New variable - the simulator object.
2371 (sim_kind): Delete global - merged into simulation.
2372 (sim_load): Cleanup. Move PC assignment from here.
2373 (sim_create_inferior): To here.
2375 * sim-main.h: New file.
2376 * interp.c (sim-main.h): Include.
2378 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2380 * configure: Regenerated to track ../common/aclocal.m4 changes.
2382 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2384 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2386 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2388 * gencode.c (build_instruction): DIV instructions: check
2389 for division by zero and integer overflow before using
2390 host's division operation.
2392 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2394 * Makefile.in (SIM_OBJS): Add sim-load.o.
2395 * interp.c: #include bfd.h.
2396 (target_byte_order): Delete.
2397 (sim_kind, myname, big_endian_p): New static locals.
2398 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2399 after argument parsing. Recognize -E arg, set endianness accordingly.
2400 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2401 load file into simulator. Set PC from bfd.
2402 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2403 (set_endianness): Use big_endian_p instead of target_byte_order.
2405 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2407 * interp.c (sim_size): Delete prototype - conflicts with
2408 definition in remote-sim.h. Correct definition.
2410 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2412 * configure: Regenerated to track ../common/aclocal.m4 changes.
2415 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2417 * interp.c (sim_open): New arg `kind'.
2419 * configure: Regenerated to track ../common/aclocal.m4 changes.
2421 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2423 * configure: Regenerated to track ../common/aclocal.m4 changes.
2425 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2427 * interp.c (sim_open): Set optind to 0 before calling getopt.
2429 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2431 * configure: Regenerated to track ../common/aclocal.m4 changes.
2433 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2435 * interp.c : Replace uses of pr_addr with pr_uword64
2436 where the bit length is always 64 independent of SIM_ADDR.
2437 (pr_uword64) : added.
2439 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2441 * configure: Re-generate.
2443 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2445 * configure: Regenerate to track ../common/aclocal.m4 changes.
2447 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2449 * interp.c (sim_open): New SIM_DESC result. Argument is now
2451 (other sim_*): New SIM_DESC argument.
2453 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2455 * interp.c: Fix printing of addresses for non-64-bit targets.
2456 (pr_addr): Add function to print address based on size.
2458 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2460 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2462 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2464 * gencode.c (build_mips16_operands): Correct computation of base
2465 address for extended PC relative instruction.
2467 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2469 * interp.c (mips16_entry): Add support for floating point cases.
2470 (SignalException): Pass floating point cases to mips16_entry.
2471 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2473 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2475 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2476 and then set the state to fmt_uninterpreted.
2477 (COP_SW): Temporarily set the state to fmt_word while calling
2480 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2482 * gencode.c (build_instruction): The high order may be set in the
2483 comparison flags at any ISA level, not just ISA 4.
2485 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2487 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2488 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2489 * configure.in: sinclude ../common/aclocal.m4.
2490 * configure: Regenerated.
2492 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2494 * configure: Rebuild after change to aclocal.m4.
2496 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2498 * configure configure.in Makefile.in: Update to new configure
2499 scheme which is more compatible with WinGDB builds.
2500 * configure.in: Improve comment on how to run autoconf.
2501 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2502 * Makefile.in: Use autoconf substitution to install common
2505 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2507 * gencode.c (build_instruction): Use BigEndianCPU instead of
2510 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2512 * interp.c (sim_monitor): Make output to stdout visible in
2513 wingdb's I/O log window.
2515 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2517 * support.h: Undo previous change to SIGTRAP
2520 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2522 * interp.c (store_word, load_word): New static functions.
2523 (mips16_entry): New static function.
2524 (SignalException): Look for mips16 entry and exit instructions.
2525 (simulate): Use the correct index when setting fpr_state after
2526 doing a pending move.
2528 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2530 * interp.c: Fix byte-swapping code throughout to work on
2531 both little- and big-endian hosts.
2533 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2535 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2536 with gdb/config/i386/xm-windows.h.
2538 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2540 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2541 that messes up arithmetic shifts.
2543 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2545 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2546 SIGTRAP and SIGQUIT for _WIN32.
2548 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2550 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2551 force a 64 bit multiplication.
2552 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2553 destination register is 0, since that is the default mips16 nop
2556 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2558 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2559 (build_endian_shift): Don't check proc64.
2560 (build_instruction): Always set memval to uword64. Cast op2 to
2561 uword64 when shifting it left in memory instructions. Always use
2562 the same code for stores--don't special case proc64.
2564 * gencode.c (build_mips16_operands): Fix base PC value for PC
2566 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2568 * interp.c (simJALDELAYSLOT): Define.
2569 (JALDELAYSLOT): Define.
2570 (INDELAYSLOT, INJALDELAYSLOT): Define.
2571 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2573 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2575 * interp.c (sim_open): add flush_cache as a PMON routine
2576 (sim_monitor): handle flush_cache by ignoring it
2578 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2580 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2582 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2583 (BigEndianMem): Rename to ByteSwapMem and change sense.
2584 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2585 BigEndianMem references to !ByteSwapMem.
2586 (set_endianness): New function, with prototype.
2587 (sim_open): Call set_endianness.
2588 (sim_info): Use simBE instead of BigEndianMem.
2589 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2590 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2591 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2592 ifdefs, keeping the prototype declaration.
2593 (swap_word): Rewrite correctly.
2594 (ColdReset): Delete references to CONFIG. Delete endianness related
2595 code; moved to set_endianness.
2597 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2599 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2600 * interp.c (CHECKHILO): Define away.
2601 (simSIGINT): New macro.
2602 (membank_size): Increase from 1MB to 2MB.
2603 (control_c): New function.
2604 (sim_resume): Rename parameter signal to signal_number. Add local
2605 variable prev. Call signal before and after simulate.
2606 (sim_stop_reason): Add simSIGINT support.
2607 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2609 (sim_warning): Delete call to SignalException. Do call printf_filtered
2611 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2612 a call to sim_warning.
2614 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2616 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2617 16 bit instructions.
2619 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2621 Add support for mips16 (16 bit MIPS implementation):
2622 * gencode.c (inst_type): Add mips16 instruction encoding types.
2623 (GETDATASIZEINSN): Define.
2624 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2625 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2627 (MIPS16_DECODE): New table, for mips16 instructions.
2628 (bitmap_val): New static function.
2629 (struct mips16_op): Define.
2630 (mips16_op_table): New table, for mips16 operands.
2631 (build_mips16_operands): New static function.
2632 (process_instructions): If PC is odd, decode a mips16
2633 instruction. Break out instruction handling into new
2634 build_instruction function.
2635 (build_instruction): New static function, broken out of
2636 process_instructions. Check modifiers rather than flags for SHIFT
2637 bit count and m[ft]{hi,lo} direction.
2638 (usage): Pass program name to fprintf.
2639 (main): Remove unused variable this_option_optind. Change
2640 ``*loptarg++'' to ``loptarg++''.
2641 (my_strtoul): Parenthesize && within ||.
2642 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2643 (simulate): If PC is odd, fetch a 16 bit instruction, and
2644 increment PC by 2 rather than 4.
2645 * configure.in: Add case for mips16*-*-*.
2646 * configure: Rebuild.
2648 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2650 * interp.c: Allow -t to enable tracing in standalone simulator.
2651 Fix garbage output in trace file and error messages.
2653 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2655 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2656 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2657 * configure.in: Simplify using macros in ../common/aclocal.m4.
2658 * configure: Regenerated.
2659 * tconfig.in: New file.
2661 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2663 * interp.c: Fix bugs in 64-bit port.
2664 Use ansi function declarations for msvc compiler.
2665 Initialize and test file pointer in trace code.
2666 Prevent duplicate definition of LAST_EMED_REGNUM.
2668 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2670 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2672 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2674 * interp.c (SignalException): Check for explicit terminating
2676 * gencode.c: Pass instruction value through SignalException()
2677 calls for Trap, Breakpoint and Syscall.
2679 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2681 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2682 only used on those hosts that provide it.
2683 * configure.in: Add sqrt() to list of functions to be checked for.
2684 * config.in: Re-generated.
2685 * configure: Re-generated.
2687 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2689 * gencode.c (process_instructions): Call build_endian_shift when
2690 expanding STORE RIGHT, to fix swr.
2691 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2692 clear the high bits.
2693 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2694 Fix float to int conversions to produce signed values.
2696 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2698 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2699 (process_instructions): Correct handling of nor instruction.
2700 Correct shift count for 32 bit shift instructions. Correct sign
2701 extension for arithmetic shifts to not shift the number of bits in
2702 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2703 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2705 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2706 It's OK to have a mult follow a mult. What's not OK is to have a
2707 mult follow an mfhi.
2708 (Convert): Comment out incorrect rounding code.
2710 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2712 * interp.c (sim_monitor): Improved monitor printf
2713 simulation. Tidied up simulator warnings, and added "--log" option
2714 for directing warning message output.
2715 * gencode.c: Use sim_warning() rather than WARNING macro.
2717 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2719 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2720 getopt1.o, rather than on gencode.c. Link objects together.
2721 Don't link against -liberty.
2722 (gencode.o, getopt.o, getopt1.o): New targets.
2723 * gencode.c: Include <ctype.h> and "ansidecl.h".
2724 (AND): Undefine after including "ansidecl.h".
2725 (ULONG_MAX): Define if not defined.
2726 (OP_*): Don't define macros; now defined in opcode/mips.h.
2727 (main): Call my_strtoul rather than strtoul.
2728 (my_strtoul): New static function.
2730 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2732 * gencode.c (process_instructions): Generate word64 and uword64
2733 instead of `long long' and `unsigned long long' data types.
2734 * interp.c: #include sysdep.h to get signals, and define default
2736 * (Convert): Work around for Visual-C++ compiler bug with type
2738 * support.h: Make things compile under Visual-C++ by using
2739 __int64 instead of `long long'. Change many refs to long long
2740 into word64/uword64 typedefs.
2742 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2744 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2745 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2747 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2748 (AC_PROG_INSTALL): Added.
2749 (AC_PROG_CC): Moved to before configure.host call.
2750 * configure: Rebuilt.
2752 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2754 * configure.in: Define @SIMCONF@ depending on mips target.
2755 * configure: Rebuild.
2756 * Makefile.in (run): Add @SIMCONF@ to control simulator
2758 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2759 * interp.c: Remove some debugging, provide more detailed error
2760 messages, update memory accesses to use LOADDRMASK.
2762 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2764 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2765 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2767 * configure: Rebuild.
2768 * config.in: New file, generated by autoheader.
2769 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2770 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2771 HAVE_ANINT and HAVE_AINT, as appropriate.
2772 * Makefile.in (run): Use @LIBS@ rather than -lm.
2773 (interp.o): Depend upon config.h.
2774 (Makefile): Just rebuild Makefile.
2775 (clean): Remove stamp-h.
2776 (mostlyclean): Make the same as clean, not as distclean.
2777 (config.h, stamp-h): New targets.
2779 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2781 * interp.c (ColdReset): Fix boolean test. Make all simulator
2784 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2786 * interp.c (xfer_direct_word, xfer_direct_long,
2787 swap_direct_word, swap_direct_long, xfer_big_word,
2788 xfer_big_long, xfer_little_word, xfer_little_long,
2789 swap_word,swap_long): Added.
2790 * interp.c (ColdReset): Provide function indirection to
2791 host<->simulated_target transfer routines.
2792 * interp.c (sim_store_register, sim_fetch_register): Updated to
2793 make use of indirected transfer routines.
2795 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2797 * gencode.c (process_instructions): Ensure FP ABS instruction
2799 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2800 system call support.
2802 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2804 * interp.c (sim_do_command): Complain if callback structure not
2807 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2809 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2810 support for Sun hosts.
2811 * Makefile.in (gencode): Ensure the host compiler and libraries
2812 used for cross-hosted build.
2814 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2816 * interp.c, gencode.c: Some more (TODO) tidying.
2818 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2820 * gencode.c, interp.c: Replaced explicit long long references with
2821 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2822 * support.h (SET64LO, SET64HI): Macros added.
2824 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2826 * configure: Regenerate with autoconf 2.7.
2828 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2830 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2831 * support.h: Remove superfluous "1" from #if.
2832 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2834 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2836 * interp.c (StoreFPR): Control UndefinedResult() call on
2837 WARN_RESULT manifest.
2839 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2841 * gencode.c: Tidied instruction decoding, and added FP instruction
2844 * interp.c: Added dineroIII, and BSD profiling support. Also
2845 run-time FP handling.
2847 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2849 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2850 gencode.c, interp.c, support.h: created.