1 2006-08-29 Thiemo Seufer <ths@mips.com>
2 David Ung <davidu@mips.com>
4 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
6 * configure: Regenerate.
7 * mips.igen (model): Add smartmips.
8 (MADDU): Increment ACX if carry.
10 (ROR,RORV): Add smartmips.
11 (include): Include smartmips.igen.
12 * sim-main.h (ACX): Set to REGISTERS[89].
13 * smartmips.igen: New file.
15 2006-08-29 Thiemo Seufer <ths@mips.com>
16 David Ung <davidu@mips.com>
18 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
19 mips3264r2.igen. Add missing dependency rules.
20 * m16e.igen: Support for mips16e save/restore instructions.
22 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
24 * configure: Regenerated.
26 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
28 * configure: Regenerated.
30 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
32 * configure: Regenerated.
34 2006-05-15 Chao-ying Fu <fu@mips.com>
36 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
38 2006-04-18 Nick Clifton <nickc@redhat.com>
40 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
43 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
45 * configure: Regenerate.
47 2005-12-14 Chao-ying Fu <fu@mips.com>
49 * Makefile.in (SIM_OBJS): Add dsp.o.
50 (dsp.o): New dependency.
51 (IGEN_INCLUDE): Add dsp.igen.
52 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
53 mipsisa64*-*-*): Add dsp to sim_igen_machine.
54 * configure: Regenerate.
55 * mips.igen: Add dsp model and include dsp.igen.
56 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
57 because these instructions are extended in DSP ASE.
58 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
59 adding 6 DSP accumulator registers and 1 DSP control register.
60 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
61 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
62 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
63 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
64 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
65 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
66 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
67 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
68 DSPCR_CCOND_SMASK): New define.
69 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
70 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
72 2005-07-08 Ian Lance Taylor <ian@airs.com>
74 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
76 2005-06-16 David Ung <davidu@mips.com>
77 Nigel Stephens <nigel@mips.com>
79 * mips.igen: New mips16e model and include m16e.igen.
80 (check_u64): Add mips16e tag.
81 * m16e.igen: New file for MIPS16e instructions.
82 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
83 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
85 * configure: Regenerate.
87 2005-05-26 David Ung <davidu@mips.com>
89 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
90 tags to all instructions which are applicable to the new ISAs.
91 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
93 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
95 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
97 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
98 * configure: Regenerate.
100 2005-03-23 Mark Kettenis <kettenis@gnu.org>
102 * configure: Regenerate.
104 2005-01-14 Andrew Cagney <cagney@gnu.org>
106 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
107 explicit call to AC_CONFIG_HEADER.
108 * configure: Regenerate.
110 2005-01-12 Andrew Cagney <cagney@gnu.org>
112 * configure.ac: Update to use ../common/common.m4.
113 * configure: Re-generate.
115 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
117 * configure: Regenerated to track ../common/aclocal.m4 changes.
119 2005-01-07 Andrew Cagney <cagney@gnu.org>
121 * configure.ac: Rename configure.in, require autoconf 2.59.
122 * configure: Re-generate.
124 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
126 * configure: Regenerate for ../common/aclocal.m4 update.
128 2004-09-24 Monika Chaddha <monika@acmet.com>
130 Committed by Andrew Cagney.
131 * m16.igen (CMP, CMPI): Fix assembler.
133 2004-08-18 Chris Demetriou <cgd@broadcom.com>
135 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
136 * configure: Regenerate.
138 2004-06-25 Chris Demetriou <cgd@broadcom.com>
140 * configure.in (sim_m16_machine): Include mipsIII.
141 * configure: Regenerate.
143 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
145 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
147 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
149 2004-04-10 Chris Demetriou <cgd@broadcom.com>
151 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
153 2004-04-09 Chris Demetriou <cgd@broadcom.com>
155 * mips.igen (check_fmt): Remove.
156 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
157 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
158 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
159 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
160 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
161 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
162 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
163 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
164 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
165 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
167 2004-04-09 Chris Demetriou <cgd@broadcom.com>
169 * sb1.igen (check_sbx): New function.
170 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
172 2004-03-29 Chris Demetriou <cgd@broadcom.com>
173 Richard Sandiford <rsandifo@redhat.com>
175 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
176 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
177 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
178 separate implementations for mipsIV and mipsV. Use new macros to
179 determine whether the restrictions apply.
181 2004-01-19 Chris Demetriou <cgd@broadcom.com>
183 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
184 (check_mult_hilo): Improve comments.
185 (check_div_hilo): Likewise. Also, fork off a new version
186 to handle mips32/mips64 (since there are no hazards to check
189 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
191 * mips.igen (do_dmultx): Fix check for negative operands.
193 2003-05-16 Ian Lance Taylor <ian@airs.com>
195 * Makefile.in (SHELL): Make sure this is defined.
196 (various): Use $(SHELL) whenever we invoke move-if-change.
198 2003-05-03 Chris Demetriou <cgd@broadcom.com>
200 * cp1.c: Tweak attribution slightly.
203 * mdmx.igen: Likewise.
204 * mips3d.igen: Likewise.
205 * sb1.igen: Likewise.
207 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
209 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
212 2003-02-27 Andrew Cagney <cagney@redhat.com>
214 * interp.c (sim_open): Rename _bfd to bfd.
215 (sim_create_inferior): Ditto.
217 2003-01-14 Chris Demetriou <cgd@broadcom.com>
219 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
221 2003-01-14 Chris Demetriou <cgd@broadcom.com>
223 * mips.igen (EI, DI): Remove.
225 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
227 * Makefile.in (tmp-run-multi): Fix mips16 filter.
229 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
230 Andrew Cagney <ac131313@redhat.com>
231 Gavin Romig-Koch <gavin@redhat.com>
232 Graydon Hoare <graydon@redhat.com>
233 Aldy Hernandez <aldyh@redhat.com>
234 Dave Brolley <brolley@redhat.com>
235 Chris Demetriou <cgd@broadcom.com>
237 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
238 (sim_mach_default): New variable.
239 (mips64vr-*-*, mips64vrel-*-*): New configurations.
240 Add a new simulator generator, MULTI.
241 * configure: Regenerate.
242 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
243 (multi-run.o): New dependency.
244 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
245 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
246 (tmp-multi): Combine them.
247 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
248 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
249 (distclean-extra): New rule.
250 * sim-main.h: Include bfd.h.
251 (MIPS_MACH): New macro.
252 * mips.igen (vr4120, vr5400, vr5500): New models.
253 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
254 * vr.igen: Replace with new version.
256 2003-01-04 Chris Demetriou <cgd@broadcom.com>
258 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
259 * configure: Regenerate.
261 2002-12-31 Chris Demetriou <cgd@broadcom.com>
263 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
264 * mips.igen: Remove all invocations of check_branch_bug and
267 2002-12-16 Chris Demetriou <cgd@broadcom.com>
269 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
271 2002-07-30 Chris Demetriou <cgd@broadcom.com>
273 * mips.igen (do_load_double, do_store_double): New functions.
274 (LDC1, SDC1): Rename to...
275 (LDC1b, SDC1b): respectively.
276 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
278 2002-07-29 Michael Snyder <msnyder@redhat.com>
280 * cp1.c (fp_recip2): Modify initialization expression so that
281 GCC will recognize it as constant.
283 2002-06-18 Chris Demetriou <cgd@broadcom.com>
285 * mdmx.c (SD_): Delete.
286 (Unpredictable): Re-define, for now, to directly invoke
287 unpredictable_action().
288 (mdmx_acc_op): Fix error in .ob immediate handling.
290 2002-06-18 Andrew Cagney <cagney@redhat.com>
292 * interp.c (sim_firmware_command): Initialize `address'.
294 2002-06-16 Andrew Cagney <ac131313@redhat.com>
296 * configure: Regenerated to track ../common/aclocal.m4 changes.
298 2002-06-14 Chris Demetriou <cgd@broadcom.com>
299 Ed Satterthwaite <ehs@broadcom.com>
301 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
302 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
303 * mips.igen: Include mips3d.igen.
304 (mips3d): New model name for MIPS-3D ASE instructions.
305 (CVT.W.fmt): Don't use this instruction for word (source) format
307 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
308 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
309 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
310 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
311 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
312 (RSquareRoot1, RSquareRoot2): New macros.
313 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
314 (fp_rsqrt2): New functions.
315 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
316 * configure: Regenerate.
318 2002-06-13 Chris Demetriou <cgd@broadcom.com>
319 Ed Satterthwaite <ehs@broadcom.com>
321 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
322 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
323 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
324 (convert): Note that this function is not used for paired-single
326 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
327 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
328 (check_fmt_p): Enable paired-single support.
329 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
330 (PUU.PS): New instructions.
331 (CVT.S.fmt): Don't use this instruction for paired-single format
333 * sim-main.h (FP_formats): New value 'fmt_ps.'
334 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
335 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
337 2002-06-12 Chris Demetriou <cgd@broadcom.com>
339 * mips.igen: Fix formatting of function calls in
342 2002-06-12 Chris Demetriou <cgd@broadcom.com>
344 * mips.igen (MOVN, MOVZ): Trace result.
345 (TNEI): Print "tnei" as the opcode name in traces.
346 (CEIL.W): Add disassembly string for traces.
347 (RSQRT.fmt): Make location of disassembly string consistent
348 with other instructions.
350 2002-06-12 Chris Demetriou <cgd@broadcom.com>
352 * mips.igen (X): Delete unused function.
354 2002-06-08 Andrew Cagney <cagney@redhat.com>
356 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
358 2002-06-07 Chris Demetriou <cgd@broadcom.com>
359 Ed Satterthwaite <ehs@broadcom.com>
361 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
362 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
363 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
364 (fp_nmsub): New prototypes.
365 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
366 (NegMultiplySub): New defines.
367 * mips.igen (RSQRT.fmt): Use RSquareRoot().
368 (MADD.D, MADD.S): Replace with...
369 (MADD.fmt): New instruction.
370 (MSUB.D, MSUB.S): Replace with...
371 (MSUB.fmt): New instruction.
372 (NMADD.D, NMADD.S): Replace with...
373 (NMADD.fmt): New instruction.
374 (NMSUB.D, MSUB.S): Replace with...
375 (NMSUB.fmt): New instruction.
377 2002-06-07 Chris Demetriou <cgd@broadcom.com>
378 Ed Satterthwaite <ehs@broadcom.com>
380 * cp1.c: Fix more comment spelling and formatting.
381 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
382 (denorm_mode): New function.
383 (fpu_unary, fpu_binary): Round results after operation, collect
384 status from rounding operations, and update the FCSR.
385 (convert): Collect status from integer conversions and rounding
386 operations, and update the FCSR. Adjust NaN values that result
387 from conversions. Convert to use sim_io_eprintf rather than
388 fprintf, and remove some debugging code.
389 * cp1.h (fenr_FS): New define.
391 2002-06-07 Chris Demetriou <cgd@broadcom.com>
393 * cp1.c (convert): Remove unusable debugging code, and move MIPS
394 rounding mode to sim FP rounding mode flag conversion code into...
395 (rounding_mode): New function.
397 2002-06-07 Chris Demetriou <cgd@broadcom.com>
399 * cp1.c: Clean up formatting of a few comments.
400 (value_fpr): Reformat switch statement.
402 2002-06-06 Chris Demetriou <cgd@broadcom.com>
403 Ed Satterthwaite <ehs@broadcom.com>
406 * sim-main.h: Include cp1.h.
407 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
408 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
409 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
410 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
411 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
412 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
413 * cp1.c: Don't include sim-fpu.h; already included by
414 sim-main.h. Clean up formatting of some comments.
415 (NaN, Equal, Less): Remove.
416 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
417 (fp_cmp): New functions.
418 * mips.igen (do_c_cond_fmt): Remove.
419 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
420 Compare. Add result tracing.
421 (CxC1): Remove, replace with...
422 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
423 (DMxC1): Remove, replace with...
424 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
425 (MxC1): Remove, replace with...
426 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
428 2002-06-04 Chris Demetriou <cgd@broadcom.com>
430 * sim-main.h (FGRIDX): Remove, replace all uses with...
431 (FGR_BASE): New macro.
432 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
433 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
434 (NR_FGR, FGR): Likewise.
435 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
436 * mips.igen: Likewise.
438 2002-06-04 Chris Demetriou <cgd@broadcom.com>
440 * cp1.c: Add an FSF Copyright notice to this file.
442 2002-06-04 Chris Demetriou <cgd@broadcom.com>
443 Ed Satterthwaite <ehs@broadcom.com>
445 * cp1.c (Infinity): Remove.
446 * sim-main.h (Infinity): Likewise.
448 * cp1.c (fp_unary, fp_binary): New functions.
449 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
450 (fp_sqrt): New functions, implemented in terms of the above.
451 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
452 (Recip, SquareRoot): Remove (replaced by functions above).
453 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
454 (fp_recip, fp_sqrt): New prototypes.
455 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
456 (Recip, SquareRoot): Replace prototypes with #defines which
457 invoke the functions above.
459 2002-06-03 Chris Demetriou <cgd@broadcom.com>
461 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
462 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
463 file, remove PARAMS from prototypes.
464 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
465 simulator state arguments.
466 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
467 pass simulator state arguments.
468 * cp1.c (SD): Redefine as CPU_STATE(cpu).
469 (store_fpr, convert): Remove 'sd' argument.
470 (value_fpr): Likewise. Convert to use 'SD' instead.
472 2002-06-03 Chris Demetriou <cgd@broadcom.com>
474 * cp1.c (Min, Max): Remove #if 0'd functions.
475 * sim-main.h (Min, Max): Remove.
477 2002-06-03 Chris Demetriou <cgd@broadcom.com>
479 * cp1.c: fix formatting of switch case and default labels.
480 * interp.c: Likewise.
481 * sim-main.c: Likewise.
483 2002-06-03 Chris Demetriou <cgd@broadcom.com>
485 * cp1.c: Clean up comments which describe FP formats.
486 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
488 2002-06-03 Chris Demetriou <cgd@broadcom.com>
489 Ed Satterthwaite <ehs@broadcom.com>
491 * configure.in (mipsisa64sb1*-*-*): New target for supporting
492 Broadcom SiByte SB-1 processor configurations.
493 * configure: Regenerate.
494 * sb1.igen: New file.
495 * mips.igen: Include sb1.igen.
497 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
498 * mdmx.igen: Add "sb1" model to all appropriate functions and
500 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
501 (ob_func, ob_acc): Reference the above.
502 (qh_acc): Adjust to keep the same size as ob_acc.
503 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
504 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
506 2002-06-03 Chris Demetriou <cgd@broadcom.com>
508 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
510 2002-06-02 Chris Demetriou <cgd@broadcom.com>
511 Ed Satterthwaite <ehs@broadcom.com>
513 * mips.igen (mdmx): New (pseudo-)model.
514 * mdmx.c, mdmx.igen: New files.
515 * Makefile.in (SIM_OBJS): Add mdmx.o.
516 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
518 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
519 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
520 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
521 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
522 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
523 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
524 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
525 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
526 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
527 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
528 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
529 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
530 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
531 (qh_fmtsel): New macros.
532 (_sim_cpu): New member "acc".
533 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
534 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
536 2002-05-01 Chris Demetriou <cgd@broadcom.com>
538 * interp.c: Use 'deprecated' rather than 'depreciated.'
539 * sim-main.h: Likewise.
541 2002-05-01 Chris Demetriou <cgd@broadcom.com>
543 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
544 which wouldn't compile anyway.
545 * sim-main.h (unpredictable_action): New function prototype.
546 (Unpredictable): Define to call igen function unpredictable().
547 (NotWordValue): New macro to call igen function not_word_value().
548 (UndefinedResult): Remove.
549 * interp.c (undefined_result): Remove.
550 (unpredictable_action): New function.
551 * mips.igen (not_word_value, unpredictable): New functions.
552 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
553 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
554 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
555 NotWordValue() to check for unpredictable inputs, then
556 Unpredictable() to handle them.
558 2002-02-24 Chris Demetriou <cgd@broadcom.com>
560 * mips.igen: Fix formatting of calls to Unpredictable().
562 2002-04-20 Andrew Cagney <ac131313@redhat.com>
564 * interp.c (sim_open): Revert previous change.
566 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
568 * interp.c (sim_open): Disable chunk of code that wrote code in
569 vector table entries.
571 2002-03-19 Chris Demetriou <cgd@broadcom.com>
573 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
574 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
577 2002-03-19 Chris Demetriou <cgd@broadcom.com>
579 * cp1.c: Fix many formatting issues.
581 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
583 * cp1.c (fpu_format_name): New function to replace...
584 (DOFMT): This. Delete, and update all callers.
585 (fpu_rounding_mode_name): New function to replace...
586 (RMMODE): This. Delete, and update all callers.
588 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
590 * interp.c: Move FPU support routines from here to...
591 * cp1.c: Here. New file.
592 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
595 2002-03-12 Chris Demetriou <cgd@broadcom.com>
597 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
598 * mips.igen (mips32, mips64): New models, add to all instructions
599 and functions as appropriate.
600 (loadstore_ea, check_u64): New variant for model mips64.
601 (check_fmt_p): New variant for models mipsV and mips64, remove
602 mipsV model marking fro other variant.
605 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
606 for mips32 and mips64.
607 (DCLO, DCLZ): New instructions for mips64.
609 2002-03-07 Chris Demetriou <cgd@broadcom.com>
611 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
612 immediate or code as a hex value with the "%#lx" format.
613 (ANDI): Likewise, and fix printed instruction name.
615 2002-03-05 Chris Demetriou <cgd@broadcom.com>
617 * sim-main.h (UndefinedResult, Unpredictable): New macros
618 which currently do nothing.
620 2002-03-05 Chris Demetriou <cgd@broadcom.com>
622 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
623 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
624 (status_CU3): New definitions.
626 * sim-main.h (ExceptionCause): Add new values for MIPS32
627 and MIPS64: MDMX, MCheck, CacheErr. Update comments
628 for DebugBreakPoint and NMIReset to note their status in
630 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
631 (SignalExceptionCacheErr): New exception macros.
633 2002-03-05 Chris Demetriou <cgd@broadcom.com>
635 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
636 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
638 (SignalExceptionCoProcessorUnusable): Take as argument the
639 unusable coprocessor number.
641 2002-03-05 Chris Demetriou <cgd@broadcom.com>
643 * mips.igen: Fix formatting of all SignalException calls.
645 2002-03-05 Chris Demetriou <cgd@broadcom.com>
647 * sim-main.h (SIGNEXTEND): Remove.
649 2002-03-04 Chris Demetriou <cgd@broadcom.com>
651 * mips.igen: Remove gencode comment from top of file, fix
652 spelling in another comment.
654 2002-03-04 Chris Demetriou <cgd@broadcom.com>
656 * mips.igen (check_fmt, check_fmt_p): New functions to check
657 whether specific floating point formats are usable.
658 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
659 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
660 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
661 Use the new functions.
662 (do_c_cond_fmt): Remove format checks...
663 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
665 2002-03-03 Chris Demetriou <cgd@broadcom.com>
667 * mips.igen: Fix formatting of check_fpu calls.
669 2002-03-03 Chris Demetriou <cgd@broadcom.com>
671 * mips.igen (FLOOR.L.fmt): Store correct destination register.
673 2002-03-03 Chris Demetriou <cgd@broadcom.com>
675 * mips.igen: Remove whitespace at end of lines.
677 2002-03-02 Chris Demetriou <cgd@broadcom.com>
679 * mips.igen (loadstore_ea): New function to do effective
680 address calculations.
681 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
682 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
683 CACHE): Use loadstore_ea to do effective address computations.
685 2002-03-02 Chris Demetriou <cgd@broadcom.com>
687 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
688 * mips.igen (LL, CxC1, MxC1): Likewise.
690 2002-03-02 Chris Demetriou <cgd@broadcom.com>
692 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
693 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
694 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
695 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
696 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
697 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
698 Don't split opcode fields by hand, use the opcode field values
701 2002-03-01 Chris Demetriou <cgd@broadcom.com>
703 * mips.igen (do_divu): Fix spacing.
705 * mips.igen (do_dsllv): Move to be right before DSLLV,
706 to match the rest of the do_<shift> functions.
708 2002-03-01 Chris Demetriou <cgd@broadcom.com>
710 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
711 DSRL32, do_dsrlv): Trace inputs and results.
713 2002-03-01 Chris Demetriou <cgd@broadcom.com>
715 * mips.igen (CACHE): Provide instruction-printing string.
717 * interp.c (signal_exception): Comment tokens after #endif.
719 2002-02-28 Chris Demetriou <cgd@broadcom.com>
721 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
722 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
723 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
724 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
725 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
726 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
727 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
728 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
730 2002-02-28 Chris Demetriou <cgd@broadcom.com>
732 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
733 instruction-printing string.
734 (LWU): Use '64' as the filter flag.
736 2002-02-28 Chris Demetriou <cgd@broadcom.com>
738 * mips.igen (SDXC1): Fix instruction-printing string.
740 2002-02-28 Chris Demetriou <cgd@broadcom.com>
742 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
745 2002-02-27 Chris Demetriou <cgd@broadcom.com>
747 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
750 2002-02-27 Chris Demetriou <cgd@broadcom.com>
752 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
753 add a comma) so that it more closely match the MIPS ISA
754 documentation opcode partitioning.
755 (PREF): Put useful names on opcode fields, and include
756 instruction-printing string.
758 2002-02-27 Chris Demetriou <cgd@broadcom.com>
760 * mips.igen (check_u64): New function which in the future will
761 check whether 64-bit instructions are usable and signal an
762 exception if not. Currently a no-op.
763 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
764 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
765 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
766 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
768 * mips.igen (check_fpu): New function which in the future will
769 check whether FPU instructions are usable and signal an exception
770 if not. Currently a no-op.
771 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
772 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
773 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
774 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
775 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
776 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
777 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
778 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
780 2002-02-27 Chris Demetriou <cgd@broadcom.com>
782 * mips.igen (do_load_left, do_load_right): Move to be immediately
784 (do_store_left, do_store_right): Move to be immediately following
787 2002-02-27 Chris Demetriou <cgd@broadcom.com>
789 * mips.igen (mipsV): New model name. Also, add it to
790 all instructions and functions where it is appropriate.
792 2002-02-18 Chris Demetriou <cgd@broadcom.com>
794 * mips.igen: For all functions and instructions, list model
795 names that support that instruction one per line.
797 2002-02-11 Chris Demetriou <cgd@broadcom.com>
799 * mips.igen: Add some additional comments about supported
800 models, and about which instructions go where.
801 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
802 order as is used in the rest of the file.
804 2002-02-11 Chris Demetriou <cgd@broadcom.com>
806 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
807 indicating that ALU32_END or ALU64_END are there to check
809 (DADD): Likewise, but also remove previous comment about
812 2002-02-10 Chris Demetriou <cgd@broadcom.com>
814 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
815 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
816 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
817 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
818 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
819 fields (i.e., add and move commas) so that they more closely
820 match the MIPS ISA documentation opcode partitioning.
822 2002-02-10 Chris Demetriou <cgd@broadcom.com>
824 * mips.igen (ADDI): Print immediate value.
826 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
827 (SLL): Print "nop" specially, and don't run the code
828 that does the shift for the "nop" case.
830 2001-11-17 Fred Fish <fnf@redhat.com>
832 * sim-main.h (float_operation): Move enum declaration outside
833 of _sim_cpu struct declaration.
835 2001-04-12 Jim Blandy <jimb@redhat.com>
837 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
838 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
840 * sim-main.h (COCIDX): Remove definition; this isn't supported by
841 PENDING_FILL, and you can get the intended effect gracefully by
842 calling PENDING_SCHED directly.
844 2001-02-23 Ben Elliston <bje@redhat.com>
846 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
847 already defined elsewhere.
849 2001-02-19 Ben Elliston <bje@redhat.com>
851 * sim-main.h (sim_monitor): Return an int.
852 * interp.c (sim_monitor): Add return values.
853 (signal_exception): Handle error conditions from sim_monitor.
855 2001-02-08 Ben Elliston <bje@redhat.com>
857 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
858 (store_memory): Likewise, pass cia to sim_core_write*.
860 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
862 On advice from Chris G. Demetriou <cgd@sibyte.com>:
863 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
865 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
867 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
868 * Makefile.in: Don't delete *.igen when cleaning directory.
870 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
872 * m16.igen (break): Call SignalException not sim_engine_halt.
874 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
877 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
879 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
881 * mips.igen (MxC1, DMxC1): Fix printf formatting.
883 2000-05-24 Michael Hayes <mhayes@cygnus.com>
885 * mips.igen (do_dmultx): Fix typo.
887 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
889 * configure: Regenerated to track ../common/aclocal.m4 changes.
891 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
893 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
895 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
897 * sim-main.h (GPR_CLEAR): Define macro.
899 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
901 * interp.c (decode_coproc): Output long using %lx and not %s.
903 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
905 * interp.c (sim_open): Sort & extend dummy memory regions for
906 --board=jmr3904 for eCos.
908 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
910 * configure: Regenerated.
912 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
914 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
915 calls, conditional on the simulator being in verbose mode.
917 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
919 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
920 cache don't get ReservedInstruction traps.
922 1999-11-29 Mark Salter <msalter@cygnus.com>
924 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
925 to clear status bits in sdisr register. This is how the hardware works.
927 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
928 being used by cygmon.
930 1999-11-11 Andrew Haley <aph@cygnus.com>
932 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
935 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
937 * mips.igen (MULT): Correct previous mis-applied patch.
939 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
941 * mips.igen (delayslot32): Handle sequence like
942 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
943 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
944 (MULT): Actually pass the third register...
946 1999-09-03 Mark Salter <msalter@cygnus.com>
948 * interp.c (sim_open): Added more memory aliases for additional
949 hardware being touched by cygmon on jmr3904 board.
951 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
953 * configure: Regenerated to track ../common/aclocal.m4 changes.
955 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
957 * interp.c (sim_store_register): Handle case where client - GDB -
958 specifies that a 4 byte register is 8 bytes in size.
959 (sim_fetch_register): Ditto.
961 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
963 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
964 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
965 (idt_monitor_base): Base address for IDT monitor traps.
966 (pmon_monitor_base): Ditto for PMON.
967 (lsipmon_monitor_base): Ditto for LSI PMON.
968 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
969 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
970 (sim_firmware_command): New function.
971 (mips_option_handler): Call it for OPTION_FIRMWARE.
972 (sim_open): Allocate memory for idt_monitor region. If "--board"
973 option was given, add no monitor by default. Add BREAK hooks only if
974 monitors are also there.
976 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
978 * interp.c (sim_monitor): Flush output before reading input.
980 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
982 * tconfig.in (SIM_HANDLES_LMA): Always define.
984 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
986 From Mark Salter <msalter@cygnus.com>:
987 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
988 (sim_open): Add setup for BSP board.
990 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
992 * mips.igen (MULT, MULTU): Add syntax for two operand version.
993 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
994 them as unimplemented.
996 1999-05-08 Felix Lee <flee@cygnus.com>
998 * configure: Regenerated to track ../common/aclocal.m4 changes.
1000 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1002 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1004 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1006 * configure.in: Any mips64vr5*-*-* target should have
1007 -DTARGET_ENABLE_FR=1.
1008 (default_endian): Any mips64vr*el-*-* target should default to
1010 * configure: Re-generate.
1012 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1014 * mips.igen (ldl): Extend from _16_, not 32.
1016 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1018 * interp.c (sim_store_register): Force registers written to by GDB
1019 into an un-interpreted state.
1021 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1023 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1024 CPU, start periodic background I/O polls.
1025 (tx3904sio_poll): New function: periodic I/O poller.
1027 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1029 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1031 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1033 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1036 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1038 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1039 (load_word): Call SIM_CORE_SIGNAL hook on error.
1040 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1041 starting. For exception dispatching, pass PC instead of NULL_CIA.
1042 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1043 * sim-main.h (COP0_BADVADDR): Define.
1044 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1045 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1046 (_sim_cpu): Add exc_* fields to store register value snapshots.
1047 * mips.igen (*): Replace memory-related SignalException* calls
1048 with references to SIM_CORE_SIGNAL hook.
1050 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1052 * sim-main.c (*): Minor warning cleanups.
1054 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1056 * m16.igen (DADDIU5): Correct type-o.
1058 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1060 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1063 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1065 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1067 (interp.o): Add dependency on itable.h
1068 (oengine.c, gencode): Delete remaining references.
1069 (BUILT_SRC_FROM_GEN): Clean up.
1071 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1074 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1075 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1076 tmp-run-hack) : New.
1077 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1078 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1079 Drop the "64" qualifier to get the HACK generator working.
1080 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1081 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1082 qualifier to get the hack generator working.
1083 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1084 (DSLL): Use do_dsll.
1085 (DSLLV): Use do_dsllv.
1086 (DSRA): Use do_dsra.
1087 (DSRL): Use do_dsrl.
1088 (DSRLV): Use do_dsrlv.
1089 (BC1): Move *vr4100 to get the HACK generator working.
1090 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1091 get the HACK generator working.
1092 (MACC) Rename to get the HACK generator working.
1093 (DMACC,MACCS,DMACCS): Add the 64.
1095 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1097 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1098 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1100 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1102 * mips/interp.c (DEBUG): Cleanups.
1104 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1106 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1107 (tx3904sio_tickle): fflush after a stdout character output.
1109 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1111 * interp.c (sim_close): Uninstall modules.
1113 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1115 * sim-main.h, interp.c (sim_monitor): Change to global
1118 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1120 * configure.in (vr4100): Only include vr4100 instructions in
1122 * configure: Re-generate.
1123 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1125 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1128 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1131 * configure.in (sim_default_gen, sim_use_gen): Replace with
1133 (--enable-sim-igen): Delete config option. Always using IGEN.
1134 * configure: Re-generate.
1136 * Makefile.in (gencode): Kill, kill, kill.
1139 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1141 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1142 bit mips16 igen simulator.
1143 * configure: Re-generate.
1145 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1146 as part of vr4100 ISA.
1147 * vr.igen: Mark all instructions as 64 bit only.
1149 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1151 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1154 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1156 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1157 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1158 * configure: Re-generate.
1160 * m16.igen (BREAK): Define breakpoint instruction.
1161 (JALX32): Mark instruction as mips16 and not r3900.
1162 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1164 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1166 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1168 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1169 insn as a debug breakpoint.
1171 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1173 (PENDING_SCHED): Clean up trace statement.
1174 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1175 (PENDING_FILL): Delay write by only one cycle.
1176 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1178 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1180 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1182 (pending_tick): Move incrementing of index to FOR statement.
1183 (pending_tick): Only update PENDING_OUT after a write has occured.
1185 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1187 * configure: Re-generate.
1189 * interp.c (sim_engine_run OLD): Delete explicit call to
1190 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1192 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1194 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1195 interrupt level number to match changed SignalExceptionInterrupt
1198 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1200 * interp.c: #include "itable.h" if WITH_IGEN.
1201 (get_insn_name): New function.
1202 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1203 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1205 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1207 * configure: Rebuilt to inhale new common/aclocal.m4.
1209 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1211 * dv-tx3904sio.c: Include sim-assert.h.
1213 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1215 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1216 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1217 Reorganize target-specific sim-hardware checks.
1218 * configure: rebuilt.
1219 * interp.c (sim_open): For tx39 target boards, set
1220 OPERATING_ENVIRONMENT, add tx3904sio devices.
1221 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1222 ROM executables. Install dv-sockser into sim-modules list.
1224 * dv-tx3904irc.c: Compiler warning clean-up.
1225 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1226 frequent hw-trace messages.
1228 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1232 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1234 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1236 * vr.igen: New file.
1237 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1238 * mips.igen: Define vr4100 model. Include vr.igen.
1239 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1241 * mips.igen (check_mf_hilo): Correct check.
1243 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1245 * sim-main.h (interrupt_event): Add prototype.
1247 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1248 register_ptr, register_value.
1249 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1251 * sim-main.h (tracefh): Make extern.
1253 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1255 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1256 Reduce unnecessarily high timer event frequency.
1257 * dv-tx3904cpu.c: Ditto for interrupt event.
1259 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1261 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1263 (interrupt_event): Made non-static.
1265 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1266 interchange of configuration values for external vs. internal
1269 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1271 * mips.igen (BREAK): Moved code to here for
1272 simulator-reserved break instructions.
1273 * gencode.c (build_instruction): Ditto.
1274 * interp.c (signal_exception): Code moved from here. Non-
1275 reserved instructions now use exception vector, rather
1277 * sim-main.h: Moved magic constants to here.
1279 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1281 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1282 register upon non-zero interrupt event level, clear upon zero
1284 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1285 by passing zero event value.
1286 (*_io_{read,write}_buffer): Endianness fixes.
1287 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1288 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1290 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1291 serial I/O and timer module at base address 0xFFFF0000.
1293 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1295 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1298 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1300 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1302 * configure: Update.
1304 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1306 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1307 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1308 * configure.in: Include tx3904tmr in hw_device list.
1309 * configure: Rebuilt.
1310 * interp.c (sim_open): Instantiate three timer instances.
1311 Fix address typo of tx3904irc instance.
1313 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1315 * interp.c (signal_exception): SystemCall exception now uses
1316 the exception vector.
1318 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1320 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1323 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1325 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1327 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1329 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1331 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1332 sim-main.h. Declare a struct hw_descriptor instead of struct
1333 hw_device_descriptor.
1335 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1337 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1338 right bits and then re-align left hand bytes to correct byte
1339 lanes. Fix incorrect computation in do_store_left when loading
1340 bytes from second word.
1342 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1345 * interp.c (sim_open): Only create a device tree when HW is
1348 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1349 * interp.c (signal_exception): Ditto.
1351 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1353 * gencode.c: Mark BEGEZALL as LIKELY.
1355 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1358 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1360 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1362 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1363 modules. Recognize TX39 target with "mips*tx39" pattern.
1364 * configure: Rebuilt.
1365 * sim-main.h (*): Added many macros defining bits in
1366 TX39 control registers.
1367 (SignalInterrupt): Send actual PC instead of NULL.
1368 (SignalNMIReset): New exception type.
1369 * interp.c (board): New variable for future use to identify
1370 a particular board being simulated.
1371 (mips_option_handler,mips_options): Added "--board" option.
1372 (interrupt_event): Send actual PC.
1373 (sim_open): Make memory layout conditional on board setting.
1374 (signal_exception): Initial implementation of hardware interrupt
1375 handling. Accept another break instruction variant for simulator
1377 (decode_coproc): Implement RFE instruction for TX39.
1378 (mips.igen): Decode RFE instruction as such.
1379 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1380 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1381 bbegin to implement memory map.
1382 * dv-tx3904cpu.c: New file.
1383 * dv-tx3904irc.c: New file.
1385 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1387 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1389 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1391 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1392 with calls to check_div_hilo.
1394 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1396 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1397 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1398 Add special r3900 version of do_mult_hilo.
1399 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1400 with calls to check_mult_hilo.
1401 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1402 with calls to check_div_hilo.
1404 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1407 Document a replacement.
1409 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1411 * interp.c (sim_monitor): Make mon_printf work.
1413 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1415 * sim-main.h (INSN_NAME): New arg `cpu'.
1417 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1419 * configure: Regenerated to track ../common/aclocal.m4 changes.
1421 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1423 * configure: Regenerated to track ../common/aclocal.m4 changes.
1426 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1428 * acconfig.h: New file.
1429 * configure.in: Reverted change of Apr 24; use sinclude again.
1431 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1433 * configure: Regenerated to track ../common/aclocal.m4 changes.
1436 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1438 * configure.in: Don't call sinclude.
1440 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1442 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1444 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446 * mips.igen (ERET): Implement.
1448 * interp.c (decode_coproc): Return sign-extended EPC.
1450 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1452 * interp.c (signal_exception): Do not ignore Trap.
1453 (signal_exception): On TRAP, restart at exception address.
1454 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1455 (signal_exception): Update.
1456 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1457 so that TRAP instructions are caught.
1459 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1462 contains HI/LO access history.
1463 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1464 (HIACCESS, LOACCESS): Delete, replace with
1465 (HIHISTORY, LOHISTORY): New macros.
1466 (CHECKHILO): Delete all, moved to mips.igen
1468 * gencode.c (build_instruction): Do not generate checks for
1469 correct HI/LO register usage.
1471 * interp.c (old_engine_run): Delete checks for correct HI/LO
1474 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1475 check_mf_cycles): New functions.
1476 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1477 do_divu, domultx, do_mult, do_multu): Use.
1479 * tx.igen ("madd", "maddu"): Use.
1481 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483 * mips.igen (DSRAV): Use function do_dsrav.
1484 (SRAV): Use new function do_srav.
1486 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1487 (B): Sign extend 11 bit immediate.
1488 (EXT-B*): Shift 16 bit immediate left by 1.
1489 (ADDIU*): Don't sign extend immediate value.
1491 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1495 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1498 * mips.igen (delayslot32, nullify_next_insn): New functions.
1499 (m16.igen): Always include.
1500 (do_*): Add more tracing.
1502 * m16.igen (delayslot16): Add NIA argument, could be called by a
1503 32 bit MIPS16 instruction.
1505 * interp.c (ifetch16): Move function from here.
1506 * sim-main.c (ifetch16): To here.
1508 * sim-main.c (ifetch16, ifetch32): Update to match current
1509 implementations of LH, LW.
1510 (signal_exception): Don't print out incorrect hex value of illegal
1513 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1515 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1518 * m16.igen: Implement MIPS16 instructions.
1520 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1521 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1522 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1523 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1524 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1525 bodies of corresponding code from 32 bit insn to these. Also used
1526 by MIPS16 versions of functions.
1528 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1529 (IMEM16): Drop NR argument from macro.
1531 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1533 * Makefile.in (SIM_OBJS): Add sim-main.o.
1535 * sim-main.h (address_translation, load_memory, store_memory,
1536 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1538 (pr_addr, pr_uword64): Declare.
1539 (sim-main.c): Include when H_REVEALS_MODULE_P.
1541 * interp.c (address_translation, load_memory, store_memory,
1542 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1544 * sim-main.c: To here. Fix compilation problems.
1546 * configure.in: Enable inlining.
1547 * configure: Re-config.
1549 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551 * configure: Regenerated to track ../common/aclocal.m4 changes.
1553 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1555 * mips.igen: Include tx.igen.
1556 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1557 * tx.igen: New file, contains MADD and MADDU.
1559 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1560 the hardwired constant `7'.
1561 (store_memory): Ditto.
1562 (LOADDRMASK): Move definition to sim-main.h.
1564 mips.igen (MTC0): Enable for r3900.
1567 mips.igen (do_load_byte): Delete.
1568 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1569 do_store_right): New functions.
1570 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1572 configure.in: Let the tx39 use igen again.
1575 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1577 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1578 not an address sized quantity. Return zero for cache sizes.
1580 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582 * mips.igen (r3900): r3900 does not support 64 bit integer
1585 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1587 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1589 * configure : Rebuild.
1591 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1595 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1597 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1599 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1601 * configure: Regenerated to track ../common/aclocal.m4 changes.
1602 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1604 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1606 * configure: Regenerated to track ../common/aclocal.m4 changes.
1608 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1610 * interp.c (Max, Min): Comment out functions. Not yet used.
1612 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1614 * configure: Regenerated to track ../common/aclocal.m4 changes.
1616 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1618 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1619 configurable settings for stand-alone simulator.
1621 * configure.in: Added X11 search, just in case.
1623 * configure: Regenerated.
1625 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1627 * interp.c (sim_write, sim_read, load_memory, store_memory):
1628 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1630 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1632 * sim-main.h (GETFCC): Return an unsigned value.
1634 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1636 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1637 (DADD): Result destination is RD not RT.
1639 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641 * sim-main.h (HIACCESS, LOACCESS): Always define.
1643 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1645 * interp.c (sim_info): Delete.
1647 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1649 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1650 (mips_option_handler): New argument `cpu'.
1651 (sim_open): Update call to sim_add_option_table.
1653 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1655 * mips.igen (CxC1): Add tracing.
1657 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659 * sim-main.h (Max, Min): Declare.
1661 * interp.c (Max, Min): New functions.
1663 * mips.igen (BC1): Add tracing.
1665 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1667 * interp.c Added memory map for stack in vr4100
1669 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1671 * interp.c (load_memory): Add missing "break"'s.
1673 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1675 * interp.c (sim_store_register, sim_fetch_register): Pass in
1676 length parameter. Return -1.
1678 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1680 * interp.c: Added hardware init hook, fixed warnings.
1682 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1684 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1686 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1688 * interp.c (ifetch16): New function.
1690 * sim-main.h (IMEM32): Rename IMEM.
1691 (IMEM16_IMMED): Define.
1693 (DELAY_SLOT): Update.
1695 * m16run.c (sim_engine_run): New file.
1697 * m16.igen: All instructions except LB.
1698 (LB): Call do_load_byte.
1699 * mips.igen (do_load_byte): New function.
1700 (LB): Call do_load_byte.
1702 * mips.igen: Move spec for insn bit size and high bit from here.
1703 * Makefile.in (tmp-igen, tmp-m16): To here.
1705 * m16.dc: New file, decode mips16 instructions.
1707 * Makefile.in (SIM_NO_ALL): Define.
1708 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1710 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1712 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1713 point unit to 32 bit registers.
1714 * configure: Re-generate.
1716 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1718 * configure.in (sim_use_gen): Make IGEN the default simulator
1719 generator for generic 32 and 64 bit mips targets.
1720 * configure: Re-generate.
1722 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1724 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1727 * interp.c (sim_fetch_register, sim_store_register): Read/write
1728 FGR from correct location.
1729 (sim_open): Set size of FGR's according to
1730 WITH_TARGET_FLOATING_POINT_BITSIZE.
1732 * sim-main.h (FGR): Store floating point registers in a separate
1735 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1739 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1741 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1743 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1745 * interp.c (pending_tick): New function. Deliver pending writes.
1747 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1748 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1749 it can handle mixed sized quantites and single bits.
1751 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1753 * interp.c (oengine.h): Do not include when building with IGEN.
1754 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1755 (sim_info): Ditto for PROCESSOR_64BIT.
1756 (sim_monitor): Replace ut_reg with unsigned_word.
1757 (*): Ditto for t_reg.
1758 (LOADDRMASK): Define.
1759 (sim_open): Remove defunct check that host FP is IEEE compliant,
1760 using software to emulate floating point.
1761 (value_fpr, ...): Always compile, was conditional on HASFPU.
1763 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1768 * interp.c (SD, CPU): Define.
1769 (mips_option_handler): Set flags in each CPU.
1770 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1771 (sim_close): Do not clear STATE, deleted anyway.
1772 (sim_write, sim_read): Assume CPU zero's vm should be used for
1774 (sim_create_inferior): Set the PC for all processors.
1775 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1777 (mips16_entry): Pass correct nr of args to store_word, load_word.
1778 (ColdReset): Cold reset all cpu's.
1779 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1780 (sim_monitor, load_memory, store_memory, signal_exception): Use
1781 `CPU' instead of STATE_CPU.
1784 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1787 * sim-main.h (signal_exception): Add sim_cpu arg.
1788 (SignalException*): Pass both SD and CPU to signal_exception.
1789 * interp.c (signal_exception): Update.
1791 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1793 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1794 address_translation): Ditto
1795 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1797 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799 * configure: Regenerated to track ../common/aclocal.m4 changes.
1801 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1803 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1805 * mips.igen (model): Map processor names onto BFD name.
1807 * sim-main.h (CPU_CIA): Delete.
1808 (SET_CIA, GET_CIA): Define
1810 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1815 * configure.in (default_endian): Configure a big-endian simulator
1817 * configure: Re-generate.
1819 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1821 * configure: Regenerated to track ../common/aclocal.m4 changes.
1823 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1825 * interp.c (sim_monitor): Handle Densan monitor outbyte
1826 and inbyte functions.
1828 1997-12-29 Felix Lee <flee@cygnus.com>
1830 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1832 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1834 * Makefile.in (tmp-igen): Arrange for $zero to always be
1835 reset to zero after every instruction.
1837 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839 * configure: Regenerated to track ../common/aclocal.m4 changes.
1842 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1844 * mips.igen (MSUB): Fix to work like MADD.
1845 * gencode.c (MSUB): Similarly.
1847 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1849 * configure: Regenerated to track ../common/aclocal.m4 changes.
1851 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1853 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1855 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857 * sim-main.h (sim-fpu.h): Include.
1859 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1860 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1861 using host independant sim_fpu module.
1863 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1865 * interp.c (signal_exception): Report internal errors with SIGABRT
1868 * sim-main.h (C0_CONFIG): New register.
1869 (signal.h): No longer include.
1871 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1873 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1875 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1877 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879 * mips.igen: Tag vr5000 instructions.
1880 (ANDI): Was missing mipsIV model, fix assembler syntax.
1881 (do_c_cond_fmt): New function.
1882 (C.cond.fmt): Handle mips I-III which do not support CC field
1884 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1885 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1887 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1888 vr5000 which saves LO in a GPR separatly.
1890 * configure.in (enable-sim-igen): For vr5000, select vr5000
1891 specific instructions.
1892 * configure: Re-generate.
1894 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1898 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1899 fmt_uninterpreted_64 bit cases to switch. Convert to
1902 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1904 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1905 as specified in IV3.2 spec.
1906 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1908 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1910 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1911 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1912 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1913 PENDING_FILL versions of instructions. Simplify.
1915 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1917 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1919 (MTHI, MFHI): Disable code checking HI-LO.
1921 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1923 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1925 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * gencode.c (build_mips16_operands): Replace IPC with cia.
1929 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1930 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1932 (UndefinedResult): Replace function with macro/function
1934 (sim_engine_run): Don't save PC in IPC.
1936 * sim-main.h (IPC): Delete.
1939 * interp.c (signal_exception, store_word, load_word,
1940 address_translation, load_memory, store_memory, cache_op,
1941 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1942 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1943 current instruction address - cia - argument.
1944 (sim_read, sim_write): Call address_translation directly.
1945 (sim_engine_run): Rename variable vaddr to cia.
1946 (signal_exception): Pass cia to sim_monitor
1948 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1949 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1950 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1952 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1953 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1956 * interp.c (signal_exception): Pass restart address to
1959 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1960 idecode.o): Add dependency.
1962 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1964 (DELAY_SLOT): Update NIA not PC with branch address.
1965 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1967 * mips.igen: Use CIA not PC in branch calculations.
1968 (illegal): Call SignalException.
1969 (BEQ, ADDIU): Fix assembler.
1971 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973 * m16.igen (JALX): Was missing.
1975 * configure.in (enable-sim-igen): New configuration option.
1976 * configure: Re-generate.
1978 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1980 * interp.c (load_memory, store_memory): Delete parameter RAW.
1981 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1982 bypassing {load,store}_memory.
1984 * sim-main.h (ByteSwapMem): Delete definition.
1986 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1988 * interp.c (sim_do_command, sim_commands): Delete mips specific
1989 commands. Handled by module sim-options.
1991 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1992 (WITH_MODULO_MEMORY): Define.
1994 * interp.c (sim_info): Delete code printing memory size.
1996 * interp.c (mips_size): Nee sim_size, delete function.
1998 (monitor, monitor_base, monitor_size): Delete global variables.
1999 (sim_open, sim_close): Delete code creating monitor and other
2000 memory regions. Use sim-memopts module, via sim_do_commandf, to
2001 manage memory regions.
2002 (load_memory, store_memory): Use sim-core for memory model.
2004 * interp.c (address_translation): Delete all memory map code
2005 except line forcing 32 bit addresses.
2007 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2012 * interp.c (logfh, logfile): Delete globals.
2013 (sim_open, sim_close): Delete code opening & closing log file.
2014 (mips_option_handler): Delete -l and -n options.
2015 (OPTION mips_options): Ditto.
2017 * interp.c (OPTION mips_options): Rename option trace to dinero.
2018 (mips_option_handler): Update.
2020 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2022 * interp.c (fetch_str): New function.
2023 (sim_monitor): Rewrite using sim_read & sim_write.
2024 (sim_open): Check magic number.
2025 (sim_open): Write monitor vectors into memory using sim_write.
2026 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2027 (sim_read, sim_write): Simplify - transfer data one byte at a
2029 (load_memory, store_memory): Clarify meaning of parameter RAW.
2031 * sim-main.h (isHOST): Defete definition.
2032 (isTARGET): Mark as depreciated.
2033 (address_translation): Delete parameter HOST.
2035 * interp.c (address_translation): Delete parameter HOST.
2037 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2042 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2044 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046 * mips.igen: Add model filter field to records.
2048 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2050 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2052 interp.c (sim_engine_run): Do not compile function sim_engine_run
2053 when WITH_IGEN == 1.
2055 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2056 target architecture.
2058 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2059 igen. Replace with configuration variables sim_igen_flags /
2062 * m16.igen: New file. Copy mips16 insns here.
2063 * mips.igen: From here.
2065 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2067 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2069 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2071 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2073 * gencode.c (build_instruction): Follow sim_write's lead in using
2074 BigEndianMem instead of !ByteSwapMem.
2076 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078 * configure.in (sim_gen): Dependent on target, select type of
2079 generator. Always select old style generator.
2081 configure: Re-generate.
2083 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2085 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2086 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2087 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2088 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2089 SIM_@sim_gen@_*, set by autoconf.
2091 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2095 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2096 CURRENT_FLOATING_POINT instead.
2098 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2099 (address_translation): Raise exception InstructionFetch when
2100 translation fails and isINSTRUCTION.
2102 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2103 sim_engine_run): Change type of of vaddr and paddr to
2105 (address_translation, prefetch, load_memory, store_memory,
2106 cache_op): Change type of vAddr and pAddr to address_word.
2108 * gencode.c (build_instruction): Change type of vaddr and paddr to
2111 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2113 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2114 macro to obtain result of ALU op.
2116 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * interp.c (sim_info): Call profile_print.
2120 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2122 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2124 * sim-main.h (WITH_PROFILE): Do not define, defined in
2125 common/sim-config.h. Use sim-profile module.
2126 (simPROFILE): Delete defintion.
2128 * interp.c (PROFILE): Delete definition.
2129 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2130 (sim_close): Delete code writing profile histogram.
2131 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2133 (sim_engine_run): Delete code profiling the PC.
2135 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2139 * interp.c (sim_monitor): Make register pointers of type
2142 * sim-main.h: Make registers of type unsigned_word not
2145 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147 * interp.c (sync_operation): Rename from SyncOperation, make
2148 global, add SD argument.
2149 (prefetch): Rename from Prefetch, make global, add SD argument.
2150 (decode_coproc): Make global.
2152 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2154 * gencode.c (build_instruction): Generate DecodeCoproc not
2155 decode_coproc calls.
2157 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2158 (SizeFGR): Move to sim-main.h
2159 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2160 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2161 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2163 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2164 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2165 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2166 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2167 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2168 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2170 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2172 (sim-alu.h): Include.
2173 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2174 (sim_cia): Typedef to instruction_address.
2176 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2178 * Makefile.in (interp.o): Rename generated file engine.c to
2183 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2187 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189 * gencode.c (build_instruction): For "FPSQRT", output correct
2190 number of arguments to Recip.
2192 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2194 * Makefile.in (interp.o): Depends on sim-main.h
2196 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2198 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2199 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2200 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2201 STATE, DSSTATE): Define
2202 (GPR, FGRIDX, ..): Define.
2204 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2205 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2206 (GPR, FGRIDX, ...): Delete macros.
2208 * interp.c: Update names to match defines from sim-main.h
2210 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2212 * interp.c (sim_monitor): Add SD argument.
2213 (sim_warning): Delete. Replace calls with calls to
2215 (sim_error): Delete. Replace calls with sim_io_error.
2216 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2217 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2218 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2220 (mips_size): Rename from sim_size. Add SD argument.
2222 * interp.c (simulator): Delete global variable.
2223 (callback): Delete global variable.
2224 (mips_option_handler, sim_open, sim_write, sim_read,
2225 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2226 sim_size,sim_monitor): Use sim_io_* not callback->*.
2227 (sim_open): ZALLOC simulator struct.
2228 (PROFILE): Do not define.
2230 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2233 support.h with corresponding code.
2235 * sim-main.h (word64, uword64), support.h: Move definition to
2237 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2240 * Makefile.in: Update dependencies
2241 * interp.c: Do not include.
2243 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2245 * interp.c (address_translation, load_memory, store_memory,
2246 cache_op): Rename to from AddressTranslation et.al., make global,
2249 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2252 * interp.c (SignalException): Rename to signal_exception, make
2255 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2257 * sim-main.h (SignalException, SignalExceptionInterrupt,
2258 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2259 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2260 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2263 * interp.c, support.h: Use.
2265 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2267 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2268 to value_fpr / store_fpr. Add SD argument.
2269 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2270 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2272 * sim-main.h (ValueFPR, StoreFPR): Define.
2274 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2276 * interp.c (sim_engine_run): Check consistency between configure
2277 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2280 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2281 (mips_fpu): Configure WITH_FLOATING_POINT.
2282 (mips_endian): Configure WITH_TARGET_ENDIAN.
2283 * configure: Update.
2285 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2287 * configure: Regenerated to track ../common/aclocal.m4 changes.
2289 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2291 * configure: Regenerated.
2293 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2295 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2297 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2299 * gencode.c (print_igen_insn_models): Assume certain architectures
2300 include all mips* instructions.
2301 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2304 * Makefile.in (tmp.igen): Add target. Generate igen input from
2307 * gencode.c (FEATURE_IGEN): Define.
2308 (main): Add --igen option. Generate output in igen format.
2309 (process_instructions): Format output according to igen option.
2310 (print_igen_insn_format): New function.
2311 (print_igen_insn_models): New function.
2312 (process_instructions): Only issue warnings and ignore
2313 instructions when no FEATURE_IGEN.
2315 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2317 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2320 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2322 * configure: Regenerated to track ../common/aclocal.m4 changes.
2324 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2327 SIM_RESERVED_BITS): Delete, moved to common.
2328 (SIM_EXTRA_CFLAGS): Update.
2330 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332 * configure.in: Configure non-strict memory alignment.
2333 * configure: Regenerated to track ../common/aclocal.m4 changes.
2335 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337 * configure: Regenerated to track ../common/aclocal.m4 changes.
2339 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2341 * gencode.c (SDBBP,DERET): Added (3900) insns.
2342 (RFE): Turn on for 3900.
2343 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2344 (dsstate): Made global.
2345 (SUBTARGET_R3900): Added.
2346 (CANCELDELAYSLOT): New.
2347 (SignalException): Ignore SystemCall rather than ignore and
2348 terminate. Add DebugBreakPoint handling.
2349 (decode_coproc): New insns RFE, DERET; and new registers Debug
2350 and DEPC protected by SUBTARGET_R3900.
2351 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2353 * Makefile.in,configure.in: Add mips subtarget option.
2354 * configure: Update.
2356 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2358 * gencode.c: Add r3900 (tx39).
2361 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2363 * gencode.c (build_instruction): Don't need to subtract 4 for
2366 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2368 * interp.c: Correct some HASFPU problems.
2370 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2372 * configure: Regenerated to track ../common/aclocal.m4 changes.
2374 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2376 * interp.c (mips_options): Fix samples option short form, should
2379 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2381 * interp.c (sim_info): Enable info code. Was just returning.
2383 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2385 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2388 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2390 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2392 (build_instruction): Ditto for LL.
2394 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2396 * configure: Regenerated to track ../common/aclocal.m4 changes.
2398 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400 * configure: Regenerated to track ../common/aclocal.m4 changes.
2403 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2405 * interp.c (sim_open): Add call to sim_analyze_program, update
2408 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2410 * interp.c (sim_kill): Delete.
2411 (sim_create_inferior): Add ABFD argument. Set PC from same.
2412 (sim_load): Move code initializing trap handlers from here.
2413 (sim_open): To here.
2414 (sim_load): Delete, use sim-hload.c.
2416 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2418 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2420 * configure: Regenerated to track ../common/aclocal.m4 changes.
2423 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2425 * interp.c (sim_open): Add ABFD argument.
2426 (sim_load): Move call to sim_config from here.
2427 (sim_open): To here. Check return status.
2429 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2431 * gencode.c (build_instruction): Two arg MADD should
2432 not assign result to $0.
2434 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2436 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2437 * sim/mips/configure.in: Regenerate.
2439 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2441 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2442 signed8, unsigned8 et.al. types.
2444 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2445 hosts when selecting subreg.
2447 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2449 * interp.c (sim_engine_run): Reset the ZERO register to zero
2450 regardless of FEATURE_WARN_ZERO.
2451 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2453 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2455 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2456 (SignalException): For BreakPoints ignore any mode bits and just
2458 (SignalException): Always set the CAUSE register.
2460 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2462 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2463 exception has been taken.
2465 * interp.c: Implement the ERET and mt/f sr instructions.
2467 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2469 * interp.c (SignalException): Don't bother restarting an
2472 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2474 * interp.c (SignalException): Really take an interrupt.
2475 (interrupt_event): Only deliver interrupts when enabled.
2477 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2479 * interp.c (sim_info): Only print info when verbose.
2480 (sim_info) Use sim_io_printf for output.
2482 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2484 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2487 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489 * interp.c (sim_do_command): Check for common commands if a
2490 simulator specific command fails.
2492 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2494 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2495 and simBE when DEBUG is defined.
2497 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2499 * interp.c (interrupt_event): New function. Pass exception event
2500 onto exception handler.
2502 * configure.in: Check for stdlib.h.
2503 * configure: Regenerate.
2505 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2506 variable declaration.
2507 (build_instruction): Initialize memval1.
2508 (build_instruction): Add UNUSED attribute to byte, bigend,
2510 (build_operands): Ditto.
2512 * interp.c: Fix GCC warnings.
2513 (sim_get_quit_code): Delete.
2515 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2516 * Makefile.in: Ditto.
2517 * configure: Re-generate.
2519 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2521 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2523 * interp.c (mips_option_handler): New function parse argumes using
2525 (myname): Replace with STATE_MY_NAME.
2526 (sim_open): Delete check for host endianness - performed by
2528 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2529 (sim_open): Move much of the initialization from here.
2530 (sim_load): To here. After the image has been loaded and
2532 (sim_open): Move ColdReset from here.
2533 (sim_create_inferior): To here.
2534 (sim_open): Make FP check less dependant on host endianness.
2536 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2538 * interp.c (sim_set_callbacks): Delete.
2540 * interp.c (membank, membank_base, membank_size): Replace with
2541 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2542 (sim_open): Remove call to callback->init. gdb/run do this.
2546 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2548 * interp.c (big_endian_p): Delete, replaced by
2549 current_target_byte_order.
2551 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2553 * interp.c (host_read_long, host_read_word, host_swap_word,
2554 host_swap_long): Delete. Using common sim-endian.
2555 (sim_fetch_register, sim_store_register): Use H2T.
2556 (pipeline_ticks): Delete. Handled by sim-events.
2558 (sim_engine_run): Update.
2560 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2564 (SignalException): To here. Signal using sim_engine_halt.
2565 (sim_stop_reason): Delete, moved to common.
2567 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2569 * interp.c (sim_open): Add callback argument.
2570 (sim_set_callbacks): Delete SIM_DESC argument.
2573 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2575 * Makefile.in (SIM_OBJS): Add common modules.
2577 * interp.c (sim_set_callbacks): Also set SD callback.
2578 (set_endianness, xfer_*, swap_*): Delete.
2579 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2580 Change to functions using sim-endian macros.
2581 (control_c, sim_stop): Delete, use common version.
2582 (simulate): Convert into.
2583 (sim_engine_run): This function.
2584 (sim_resume): Delete.
2586 * interp.c (simulation): New variable - the simulator object.
2587 (sim_kind): Delete global - merged into simulation.
2588 (sim_load): Cleanup. Move PC assignment from here.
2589 (sim_create_inferior): To here.
2591 * sim-main.h: New file.
2592 * interp.c (sim-main.h): Include.
2594 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2596 * configure: Regenerated to track ../common/aclocal.m4 changes.
2598 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2600 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2602 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2604 * gencode.c (build_instruction): DIV instructions: check
2605 for division by zero and integer overflow before using
2606 host's division operation.
2608 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2610 * Makefile.in (SIM_OBJS): Add sim-load.o.
2611 * interp.c: #include bfd.h.
2612 (target_byte_order): Delete.
2613 (sim_kind, myname, big_endian_p): New static locals.
2614 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2615 after argument parsing. Recognize -E arg, set endianness accordingly.
2616 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2617 load file into simulator. Set PC from bfd.
2618 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2619 (set_endianness): Use big_endian_p instead of target_byte_order.
2621 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2623 * interp.c (sim_size): Delete prototype - conflicts with
2624 definition in remote-sim.h. Correct definition.
2626 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2628 * configure: Regenerated to track ../common/aclocal.m4 changes.
2631 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2633 * interp.c (sim_open): New arg `kind'.
2635 * configure: Regenerated to track ../common/aclocal.m4 changes.
2637 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2639 * configure: Regenerated to track ../common/aclocal.m4 changes.
2641 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2643 * interp.c (sim_open): Set optind to 0 before calling getopt.
2645 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2647 * configure: Regenerated to track ../common/aclocal.m4 changes.
2649 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2651 * interp.c : Replace uses of pr_addr with pr_uword64
2652 where the bit length is always 64 independent of SIM_ADDR.
2653 (pr_uword64) : added.
2655 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2657 * configure: Re-generate.
2659 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2661 * configure: Regenerate to track ../common/aclocal.m4 changes.
2663 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2665 * interp.c (sim_open): New SIM_DESC result. Argument is now
2667 (other sim_*): New SIM_DESC argument.
2669 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2671 * interp.c: Fix printing of addresses for non-64-bit targets.
2672 (pr_addr): Add function to print address based on size.
2674 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2676 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2678 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2680 * gencode.c (build_mips16_operands): Correct computation of base
2681 address for extended PC relative instruction.
2683 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2685 * interp.c (mips16_entry): Add support for floating point cases.
2686 (SignalException): Pass floating point cases to mips16_entry.
2687 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2689 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2691 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2692 and then set the state to fmt_uninterpreted.
2693 (COP_SW): Temporarily set the state to fmt_word while calling
2696 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2698 * gencode.c (build_instruction): The high order may be set in the
2699 comparison flags at any ISA level, not just ISA 4.
2701 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2703 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2704 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2705 * configure.in: sinclude ../common/aclocal.m4.
2706 * configure: Regenerated.
2708 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2710 * configure: Rebuild after change to aclocal.m4.
2712 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2714 * configure configure.in Makefile.in: Update to new configure
2715 scheme which is more compatible with WinGDB builds.
2716 * configure.in: Improve comment on how to run autoconf.
2717 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2718 * Makefile.in: Use autoconf substitution to install common
2721 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2723 * gencode.c (build_instruction): Use BigEndianCPU instead of
2726 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2728 * interp.c (sim_monitor): Make output to stdout visible in
2729 wingdb's I/O log window.
2731 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2733 * support.h: Undo previous change to SIGTRAP
2736 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2738 * interp.c (store_word, load_word): New static functions.
2739 (mips16_entry): New static function.
2740 (SignalException): Look for mips16 entry and exit instructions.
2741 (simulate): Use the correct index when setting fpr_state after
2742 doing a pending move.
2744 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2746 * interp.c: Fix byte-swapping code throughout to work on
2747 both little- and big-endian hosts.
2749 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2751 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2752 with gdb/config/i386/xm-windows.h.
2754 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2756 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2757 that messes up arithmetic shifts.
2759 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2761 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2762 SIGTRAP and SIGQUIT for _WIN32.
2764 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2766 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2767 force a 64 bit multiplication.
2768 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2769 destination register is 0, since that is the default mips16 nop
2772 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2774 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2775 (build_endian_shift): Don't check proc64.
2776 (build_instruction): Always set memval to uword64. Cast op2 to
2777 uword64 when shifting it left in memory instructions. Always use
2778 the same code for stores--don't special case proc64.
2780 * gencode.c (build_mips16_operands): Fix base PC value for PC
2782 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2784 * interp.c (simJALDELAYSLOT): Define.
2785 (JALDELAYSLOT): Define.
2786 (INDELAYSLOT, INJALDELAYSLOT): Define.
2787 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2789 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2791 * interp.c (sim_open): add flush_cache as a PMON routine
2792 (sim_monitor): handle flush_cache by ignoring it
2794 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2796 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2798 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2799 (BigEndianMem): Rename to ByteSwapMem and change sense.
2800 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2801 BigEndianMem references to !ByteSwapMem.
2802 (set_endianness): New function, with prototype.
2803 (sim_open): Call set_endianness.
2804 (sim_info): Use simBE instead of BigEndianMem.
2805 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2806 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2807 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2808 ifdefs, keeping the prototype declaration.
2809 (swap_word): Rewrite correctly.
2810 (ColdReset): Delete references to CONFIG. Delete endianness related
2811 code; moved to set_endianness.
2813 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2815 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2816 * interp.c (CHECKHILO): Define away.
2817 (simSIGINT): New macro.
2818 (membank_size): Increase from 1MB to 2MB.
2819 (control_c): New function.
2820 (sim_resume): Rename parameter signal to signal_number. Add local
2821 variable prev. Call signal before and after simulate.
2822 (sim_stop_reason): Add simSIGINT support.
2823 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2825 (sim_warning): Delete call to SignalException. Do call printf_filtered
2827 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2828 a call to sim_warning.
2830 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2832 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2833 16 bit instructions.
2835 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2837 Add support for mips16 (16 bit MIPS implementation):
2838 * gencode.c (inst_type): Add mips16 instruction encoding types.
2839 (GETDATASIZEINSN): Define.
2840 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2841 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2843 (MIPS16_DECODE): New table, for mips16 instructions.
2844 (bitmap_val): New static function.
2845 (struct mips16_op): Define.
2846 (mips16_op_table): New table, for mips16 operands.
2847 (build_mips16_operands): New static function.
2848 (process_instructions): If PC is odd, decode a mips16
2849 instruction. Break out instruction handling into new
2850 build_instruction function.
2851 (build_instruction): New static function, broken out of
2852 process_instructions. Check modifiers rather than flags for SHIFT
2853 bit count and m[ft]{hi,lo} direction.
2854 (usage): Pass program name to fprintf.
2855 (main): Remove unused variable this_option_optind. Change
2856 ``*loptarg++'' to ``loptarg++''.
2857 (my_strtoul): Parenthesize && within ||.
2858 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2859 (simulate): If PC is odd, fetch a 16 bit instruction, and
2860 increment PC by 2 rather than 4.
2861 * configure.in: Add case for mips16*-*-*.
2862 * configure: Rebuild.
2864 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2866 * interp.c: Allow -t to enable tracing in standalone simulator.
2867 Fix garbage output in trace file and error messages.
2869 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2871 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2872 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2873 * configure.in: Simplify using macros in ../common/aclocal.m4.
2874 * configure: Regenerated.
2875 * tconfig.in: New file.
2877 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2879 * interp.c: Fix bugs in 64-bit port.
2880 Use ansi function declarations for msvc compiler.
2881 Initialize and test file pointer in trace code.
2882 Prevent duplicate definition of LAST_EMED_REGNUM.
2884 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2886 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2888 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2890 * interp.c (SignalException): Check for explicit terminating
2892 * gencode.c: Pass instruction value through SignalException()
2893 calls for Trap, Breakpoint and Syscall.
2895 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2897 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2898 only used on those hosts that provide it.
2899 * configure.in: Add sqrt() to list of functions to be checked for.
2900 * config.in: Re-generated.
2901 * configure: Re-generated.
2903 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2905 * gencode.c (process_instructions): Call build_endian_shift when
2906 expanding STORE RIGHT, to fix swr.
2907 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2908 clear the high bits.
2909 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2910 Fix float to int conversions to produce signed values.
2912 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2914 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2915 (process_instructions): Correct handling of nor instruction.
2916 Correct shift count for 32 bit shift instructions. Correct sign
2917 extension for arithmetic shifts to not shift the number of bits in
2918 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2919 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2921 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2922 It's OK to have a mult follow a mult. What's not OK is to have a
2923 mult follow an mfhi.
2924 (Convert): Comment out incorrect rounding code.
2926 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2928 * interp.c (sim_monitor): Improved monitor printf
2929 simulation. Tidied up simulator warnings, and added "--log" option
2930 for directing warning message output.
2931 * gencode.c: Use sim_warning() rather than WARNING macro.
2933 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2935 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2936 getopt1.o, rather than on gencode.c. Link objects together.
2937 Don't link against -liberty.
2938 (gencode.o, getopt.o, getopt1.o): New targets.
2939 * gencode.c: Include <ctype.h> and "ansidecl.h".
2940 (AND): Undefine after including "ansidecl.h".
2941 (ULONG_MAX): Define if not defined.
2942 (OP_*): Don't define macros; now defined in opcode/mips.h.
2943 (main): Call my_strtoul rather than strtoul.
2944 (my_strtoul): New static function.
2946 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2948 * gencode.c (process_instructions): Generate word64 and uword64
2949 instead of `long long' and `unsigned long long' data types.
2950 * interp.c: #include sysdep.h to get signals, and define default
2952 * (Convert): Work around for Visual-C++ compiler bug with type
2954 * support.h: Make things compile under Visual-C++ by using
2955 __int64 instead of `long long'. Change many refs to long long
2956 into word64/uword64 typedefs.
2958 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2960 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2961 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2963 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2964 (AC_PROG_INSTALL): Added.
2965 (AC_PROG_CC): Moved to before configure.host call.
2966 * configure: Rebuilt.
2968 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2970 * configure.in: Define @SIMCONF@ depending on mips target.
2971 * configure: Rebuild.
2972 * Makefile.in (run): Add @SIMCONF@ to control simulator
2974 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2975 * interp.c: Remove some debugging, provide more detailed error
2976 messages, update memory accesses to use LOADDRMASK.
2978 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2980 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2981 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2983 * configure: Rebuild.
2984 * config.in: New file, generated by autoheader.
2985 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2986 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2987 HAVE_ANINT and HAVE_AINT, as appropriate.
2988 * Makefile.in (run): Use @LIBS@ rather than -lm.
2989 (interp.o): Depend upon config.h.
2990 (Makefile): Just rebuild Makefile.
2991 (clean): Remove stamp-h.
2992 (mostlyclean): Make the same as clean, not as distclean.
2993 (config.h, stamp-h): New targets.
2995 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2997 * interp.c (ColdReset): Fix boolean test. Make all simulator
3000 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3002 * interp.c (xfer_direct_word, xfer_direct_long,
3003 swap_direct_word, swap_direct_long, xfer_big_word,
3004 xfer_big_long, xfer_little_word, xfer_little_long,
3005 swap_word,swap_long): Added.
3006 * interp.c (ColdReset): Provide function indirection to
3007 host<->simulated_target transfer routines.
3008 * interp.c (sim_store_register, sim_fetch_register): Updated to
3009 make use of indirected transfer routines.
3011 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3013 * gencode.c (process_instructions): Ensure FP ABS instruction
3015 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3016 system call support.
3018 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3020 * interp.c (sim_do_command): Complain if callback structure not
3023 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3025 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3026 support for Sun hosts.
3027 * Makefile.in (gencode): Ensure the host compiler and libraries
3028 used for cross-hosted build.
3030 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3032 * interp.c, gencode.c: Some more (TODO) tidying.
3034 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3036 * gencode.c, interp.c: Replaced explicit long long references with
3037 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3038 * support.h (SET64LO, SET64HI): Macros added.
3040 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3042 * configure: Regenerate with autoconf 2.7.
3044 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3046 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3047 * support.h: Remove superfluous "1" from #if.
3048 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3050 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3052 * interp.c (StoreFPR): Control UndefinedResult() call on
3053 WARN_RESULT manifest.
3055 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3057 * gencode.c: Tidied instruction decoding, and added FP instruction
3060 * interp.c: Added dineroIII, and BSD profiling support. Also
3061 run-time FP handling.
3063 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3065 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3066 gencode.c, interp.c, support.h: created.