2 Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
4 * sim-main.c (tlb_try_match): Include physical address in
5 scratchpad non-mapping warning.
9 Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
11 * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
12 as per customer patch.
15 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
17 * interp.c: #include "itable.h" if WITH_IGEN.
18 (get_insn_name): New function.
19 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
20 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
23 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
25 * sim-main.c (tlb_try_match): Specially match virtual
26 pages mapped to scratchpad RAM, an unimplemented feature.
30 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
32 * r5900.igen (prot3w): Correct rotation sequence; patch
36 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
38 * configure: Rebuilt to inhale new common/aclocal.m4.
41 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
43 * r5900.igen (plzcw): Make `i' signed.
45 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
47 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
48 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
49 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
50 * interp.c (signal_exception, sky version): Handle INT 2.
52 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
54 * sim-main.h: track COP0 registers
55 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
57 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
59 * r5900.igen (mtsab): Correct typo in input register.
61 * sim-main.h (TMP_*): New macros for accessing local 128-bit
62 temporary for multimedia instructions.
63 * r5900.igen (*): Convert most instructions to use new TMP
64 macros to store output result during computation.
68 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
70 * dv-tx3904sio.c: Include sim-assert.h.
72 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
74 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
75 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
76 Reorganize target-specific sim-hardware checks.
78 * interp.c (sim_open): For tx39 target boards, set
79 OPERATING_ENVIRONMENT, add tx3904sio devices.
80 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
81 ROM executables. Install dv-sockser into sim-modules list.
83 * dv-tx3904irc.c: Compiler warning clean-up.
84 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
85 frequent hw-trace messages.
89 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
91 * interp.c (signal_exception): Set IP3 bit in CAUSE on
95 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
97 * vr.igen (MulAcc): Identify as a vr4100 specific function.
99 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
101 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
104 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
105 * mips.igen: Define vr4100 model. Include vr.igen.
106 start-sanitize-cygnus
107 * vr5400.igen: Move instructions to vr.igen
108 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
110 start-sanitize-vr4320
111 * vr4320.igen: Move instructions to vr.igen.
112 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
116 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
118 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
119 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
120 confusing message if not enough --load-next options appear.
122 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
123 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
124 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
125 (resume_handler): Same.
126 (suspend_handler): Same.
128 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
130 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
131 to trigger multi-phase load.
133 * sim-main.c: Include sim-assert.h for ASSERT macro.
134 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
137 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
140 * interp.c (sim_open): Initialize TLB.
141 * interp.c (signal_exceptions): New 5900 handling.
142 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
143 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
144 (address_translation): Use the TLB.
145 * sim-main.h (r4000_tlb_entry_t): New type.
146 (TLB_*): New constants.
147 (COP0_*): New register names.
149 Sky character I/O device.
150 * sky-psio.c: New file.
151 * sky-psio.h: New file.
152 * Makefile.in: Add sky-psio.o.
156 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
158 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
161 (r59fp_store): Update calls.
162 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
165 start-sanitize-branchbug4011
166 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
168 * interp.c (OPTION_BRANCH_BUG_4011): Add.
169 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
170 (mips_options): Define the option.
171 * mips.igen (check_4011_branch_bug): New.
172 (mark_4011_branch_bug): New.
173 (all branch insn): Call mark_branch_bug, and check_branch_bug.
174 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
175 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
176 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
177 check_branch_bug, mark_branch_bug): Define.
179 end-sanitize-branchbug4011
180 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
182 * mips.igen (check_mf_hilo): Correct check.
185 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
187 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
188 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
189 purpose registers, add 8 COP0 break-point registers, add 64 COP0
190 performance registers.
192 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
193 MFP* instructions. Just transfer value to/from corresponding
196 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
197 status is always true.
198 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
199 (EI, DI): Set/clear Status-EIE bit.
203 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
205 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
209 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
212 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
214 * sky-gdb.c: Include "sim-assert.h".
217 * sim-main.h (interrupt_event): Add prototype.
219 start-sanitize-tx3904
220 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
221 register_ptr, register_value.
222 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
225 * sim-main.h (tracefh): Make extern.
227 start-sanitize-tx3904
228 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
230 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
231 Reduce unnecessarily high timer event frequency.
232 * dv-tx3904cpu.c: Ditto for interrupt event.
236 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
238 * interp.c (decode_coproc): Removed COP2 branches.
239 * r5900.igen: Moved COP2 branch instructions here.
240 * mips.igen: Restricted COPz == COP2 bit pattern to
241 exclude COP2 branches.
244 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
246 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
248 (interrupt_event): Made non-static.
249 start-sanitize-tx3904
251 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
252 interchange of configuration values for external vs. internal
256 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
258 * mips.igen (BREAK): Moved code to here for
259 simulator-reserved break instructions.
260 * gencode.c (build_instruction): Ditto.
261 * interp.c (signal_exception): Code moved from here. Non-
262 reserved instructions now use exception vector, rather
264 * sim-main.h: Moved magic constants to here.
266 start-sanitize-tx3904
267 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
269 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
270 register upon non-zero interrupt event level, clear upon zero
272 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
273 by passing zero event value.
274 (*_io_{read,write}_buffer): Endianness fixes.
275 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
276 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
278 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
279 serial I/O and timer module at base address 0xFFFF0000.
282 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
284 * mips.igen (SWC1) : Correct the handling of ReverseEndian
287 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
289 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
293 start-sanitize-tx3904
294 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
296 * dv-tx3904tmr.c: New file - implements tx3904 timer.
297 * dv-tx3904{irc,cpu}.c: Mild reformatting.
298 * configure.in: Include tx3904tmr in hw_device list.
299 * configure: Rebuilt.
300 * interp.c (sim_open): Instantiate three timer instances.
301 Fix address typo of tx3904irc instance.
305 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
307 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
308 Select corresponding check_mt_hilo function.
309 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
312 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
316 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
318 * interp.c (signal_exception): SystemCall exception now uses
319 the exception vector.
321 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
323 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
327 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
329 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
333 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
335 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
337 start-sanitize-tx3904
338 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
340 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
342 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
343 sim-main.h. Declare a struct hw_descriptor instead of struct
344 hw_device_descriptor.
347 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
349 * mips.igen (do_store_left, do_load_left): Compute nr of left and
350 right bits and then re-align left hand bytes to correct byte
351 lanes. Fix incorrect computation in do_store_left when loading
352 bytes from second word.
354 start-sanitize-tx3904
355 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
357 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
358 * interp.c (sim_open): Only create a device tree when HW is
361 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
362 * interp.c (signal_exception): Ditto.
365 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
367 * gencode.c: Mark BEGEZALL as LIKELY.
369 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
371 * sim-main.h (ALU32_END): Sign extend 32 bit results.
372 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
375 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
377 * interp.c (sim_fetch_register): Convert internal r5900 regs to
381 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
383 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
384 modules. Recognize TX39 target with "mips*tx39" pattern.
385 * configure: Rebuilt.
386 * sim-main.h (*): Added many macros defining bits in
387 TX39 control registers.
388 (SignalInterrupt): Send actual PC instead of NULL.
389 (SignalNMIReset): New exception type.
390 * interp.c (board): New variable for future use to identify
391 a particular board being simulated.
392 (mips_option_handler,mips_options): Added "--board" option.
393 (interrupt_event): Send actual PC.
394 (sim_open): Make memory layout conditional on board setting.
395 (signal_exception): Initial implementation of hardware interrupt
396 handling. Accept another break instruction variant for simulator
398 (decode_coproc): Implement RFE instruction for TX39.
399 (mips.igen): Decode RFE instruction as such.
400 start-sanitize-tx3904
401 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
402 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
403 bbegin to implement memory map.
404 * dv-tx3904cpu.c: New file.
405 * dv-tx3904irc.c: New file.
408 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
410 * mips.igen (check_mt_hilo): Create a separate r3900 version.
413 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
415 * r5900.igen: Replace the calls and the definition of the
416 function check_op_hilo_hi1lo1 with the pair
417 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
420 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
422 * tx.igen (madd,maddu): Replace calls to check_op_hilo
423 with calls to check_div_hilo.
425 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
427 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
428 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
429 Add special r3900 version of do_mult_hilo.
430 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
431 with calls to check_mult_hilo.
432 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
433 with calls to check_div_hilo.
435 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
437 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
438 Document a replacement.
440 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
442 * interp.c (sim_monitor): Make mon_printf work.
444 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
446 * sim-main.h (INSN_NAME): New arg `cpu'.
449 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
451 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
456 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
458 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
459 * r5900.igen (r59fp_overflow): Use.
461 * r5900.igen (r59fp_op3): Rename to
462 (r59fp_mula): This, delete opm argument.
463 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
464 (r59fp_mula): Overflowing product propogates through to result.
465 (r59fp_mula): ACC to the MAX propogates to result.
466 (r59fp_mula): Underflow during multiply only sets SU.
469 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
471 * configure: Regenerated to track ../common/aclocal.m4 changes.
473 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
475 * configure: Regenerated to track ../common/aclocal.m4 changes.
478 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
480 * acconfig.h: New file.
481 * configure.in: Reverted change of Apr 24; use sinclude again.
483 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
485 * configure: Regenerated to track ../common/aclocal.m4 changes.
488 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
490 * configure.in: Don't call sinclude.
492 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
494 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
496 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
498 * mips.igen (ERET): Implement.
500 * interp.c (decode_coproc): Return sign-extended EPC.
502 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
504 * interp.c (signal_exception): Do not ignore Trap.
505 (signal_exception): On TRAP, restart at exception address.
506 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
507 (signal_exception): Update.
508 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
509 so that TRAP instructions are caught.
511 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
513 * sim-main.h (struct hilo_access, struct hilo_history): Define,
514 contains HI/LO access history.
515 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
516 (HIACCESS, LOACCESS): Delete, replace with
517 (HIHISTORY, LOHISTORY): New macros.
518 (start-sanitize-r5900):
519 (struct sim_5900_cpu): Make hi1access, lo1access of type
521 (HI1ACCESS, LO1ACCESS): Delete, replace with
522 (HI1HISTORY, LO1HISTORY): New macros.
523 (end-sanitize-r5900):
524 (CHECKHILO): Delete all, moved to mips.igen
526 * gencode.c (build_instruction): Do not generate checks for
527 correct HI/LO register usage.
529 * interp.c (old_engine_run): Delete checks for correct HI/LO
532 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
533 check_mf_cycles): New functions.
534 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
535 do_divu, domultx, do_mult, do_multu): Use.
537 * tx.igen ("madd", "maddu"): Use.
538 (start-sanitize-r5900):
540 r5900.igen: Update all HI/LO checks.
541 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
542 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
543 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
544 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
545 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
547 (end-sanitize-r5900):
550 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
552 * interp.c (decode_coproc): Correct CMFC2/QMTC2
555 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
556 instead of a single 128-bit access.
560 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
562 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
563 * interp.c (cop_[ls]q): Fixes corresponding to above.
567 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
569 * interp.c (decode_coproc): Adapt COP2 micro interlock to
570 clarified specs. Reset "M" bit; exit also on "E" bit.
574 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
576 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
577 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
579 * r5900.igen (r59fp_unpack): New function.
580 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
581 RSQRT.S, SQRT.S): Use.
582 (r59fp_zero): New function.
583 (r59fp_overflow): Generate r5900 specific overflow value.
584 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
586 (CVT.S.W, CVT.W.S): Exchange implementations.
588 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
592 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
594 * configure.in (tx19, sim_use_gen): Switch to igen.
595 * configure: Re-build.
599 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
601 * interp.c (decode_coproc): Make COP2 branch code compile after
602 igen signature changes.
605 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
607 * mips.igen (DSRAV): Use function do_dsrav.
608 (SRAV): Use new function do_srav.
610 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
611 (B): Sign extend 11 bit immediate.
612 (EXT-B*): Shift 16 bit immediate left by 1.
613 (ADDIU*): Don't sign extend immediate value.
615 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
617 * m16run.c (sim_engine_run): Restore CIA after handling an event.
620 * mips.igen (mtc0): Valid tx19 instruction.
623 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
626 * mips.igen (delayslot32, nullify_next_insn): New functions.
627 (m16.igen): Always include.
628 (do_*): Add more tracing.
630 * m16.igen (delayslot16): Add NIA argument, could be called by a
631 32 bit MIPS16 instruction.
633 * interp.c (ifetch16): Move function from here.
634 * sim-main.c (ifetch16): To here.
636 * sim-main.c (ifetch16, ifetch32): Update to match current
637 implementations of LH, LW.
638 (signal_exception): Don't print out incorrect hex value of illegal
641 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
643 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
646 * m16.igen: Implement MIPS16 instructions.
648 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
649 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
650 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
651 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
652 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
653 bodies of corresponding code from 32 bit insn to these. Also used
654 by MIPS16 versions of functions.
656 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
657 (IMEM16): Drop NR argument from macro.
660 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
662 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
663 of VU lower instruction.
667 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
669 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
672 * sim-main.h: Removed attempt at allowing 128-bit access.
676 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
678 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
680 * interp.c (decode_coproc): Refer to VU CIA as a "special"
681 register, not as a "misc" register. Aha. Add activity
682 assertions after VCALLMS* instructions.
686 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
688 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
689 to upper code of generated VU instruction.
693 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
695 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
697 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
700 * r5900.igen (SQC2): Thinko.
704 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
706 * interp.c (*): Adapt code to merged VU device & state structs.
707 (decode_coproc): Execute COP2 each macroinstruction without
708 pipelining, by stepping VU to completion state. Adapted to
709 read_vu_*_reg style of register access.
711 * mips.igen ([SL]QC2): Removed these COP2 instructions.
713 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
715 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
718 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
720 * Makefile.in (SIM_OBJS): Add sim-main.o.
722 * sim-main.h (address_translation, load_memory, store_memory,
723 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
725 (pr_addr, pr_uword64): Declare.
726 (sim-main.c): Include when H_REVEALS_MODULE_P.
728 * interp.c (address_translation, load_memory, store_memory,
729 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
731 * sim-main.c: To here. Fix compilation problems.
733 * configure.in: Enable inlining.
734 * configure: Re-config.
736 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
738 * configure: Regenerated to track ../common/aclocal.m4 changes.
740 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
742 * mips.igen: Include tx.igen.
743 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
744 * tx.igen: New file, contains MADD and MADDU.
746 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
747 the hardwired constant `7'.
748 (store_memory): Ditto.
749 (LOADDRMASK): Move definition to sim-main.h.
751 mips.igen (MTC0): Enable for r3900.
754 mips.igen (do_load_byte): Delete.
755 (do_load, do_store, do_load_left, do_load_write, do_store_left,
756 do_store_right): New functions.
757 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
759 configure.in: Let the tx39 use igen again.
762 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
764 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
765 not an address sized quantity. Return zero for cache sizes.
767 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
769 * mips.igen (r3900): r3900 does not support 64 bit integer
773 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
775 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
779 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
781 * interp.c (decode_coproc): Continuing COP2 work.
782 (cop_[ls]q): Make sky-target-only.
784 * sim-main.h (COP_[LS]Q): Make sky-target-only.
786 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
788 * configure.in (mipstx39*-*-*): Use gencode simulator rather
790 * configure : Rebuild.
793 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
795 * interp.c (decode_coproc): Added a missing TARGET_SKY check
796 around COP2 implementation skeleton.
800 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
802 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
804 * interp.c (sim_{load,store}_register): Use new vu[01]_device
805 static to access VU registers.
806 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
807 decoding. Work in progress.
809 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
810 overlapping/redundant bit pattern.
811 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
814 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
817 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
818 access to coprocessor registers.
820 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
822 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
824 * configure: Regenerated to track ../common/aclocal.m4 changes.
826 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
828 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
830 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
832 * configure: Regenerated to track ../common/aclocal.m4 changes.
833 * config.in: Regenerated to track ../common/aclocal.m4 changes.
835 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
837 * configure: Regenerated to track ../common/aclocal.m4 changes.
839 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
841 * interp.c (Max, Min): Comment out functions. Not yet used.
843 start-sanitize-vr4320
844 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
846 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
849 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
851 * configure: Regenerated to track ../common/aclocal.m4 changes.
853 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
855 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
856 configurable settings for stand-alone simulator.
859 * configure.in: Added --with-sim-gpu2 option to specify path of
860 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
861 links/compiles stand-alone simulator with this library.
863 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
865 * configure.in: Added X11 search, just in case.
867 * configure: Regenerated.
869 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
871 * interp.c (sim_write, sim_read, load_memory, store_memory):
872 Replace sim_core_*_map with read_map, write_map, exec_map resp.
874 start-sanitize-vr4320
875 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
877 * vr4320.igen (clz,dclz) : Added.
878 (dmac): Replaced 99, with LO.
881 start-sanitize-cygnus
882 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
884 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
887 start-sanitize-vr4320
888 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
890 * vr4320.igen: New file.
891 * Makefile.in (vr4320.igen) : Added.
892 * configure.in (mips64vr4320-*-*): Added.
893 * configure : Rebuilt.
894 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
895 Add the vr4320 model entry and mark the vr4320 insn as necessary.
898 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
900 * sim-main.h (GETFCC): Return an unsigned value.
903 * r5900.igen: Use an unsigned array index variable `i'.
904 (QFSRV): Ditto for variable bytes.
907 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
909 * mips.igen (DIV): Fix check for -1 / MIN_INT.
910 (DADD): Result destination is RD not RT.
913 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
914 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
918 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * sim-main.h (HIACCESS, LOACCESS): Always define.
922 * mdmx.igen (Maxi, Mini): Rename Max, Min.
924 * interp.c (sim_info): Delete.
926 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
928 * interp.c (DECLARE_OPTION_HANDLER): Use it.
929 (mips_option_handler): New argument `cpu'.
930 (sim_open): Update call to sim_add_option_table.
932 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
934 * mips.igen (CxC1): Add tracing.
937 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
939 * r5900.igen (StoreFP): Delete.
940 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
942 (rsqrt.s, sqrt.s): Implement.
943 (r59cond): New function.
944 (C.COND.S): Call r59cond in assembler line.
945 (cvt.w.s, cvt.s.w): Implement.
947 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
950 * sim-main.h: Define an enum of r5900 FCSR bit fields.
954 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
956 * r5900.igen: Add tracing to all p* instructions.
958 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
960 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
961 to get gdb talking to re-aranged sim_cpu register structure.
964 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
966 * sim-main.h (Max, Min): Declare.
968 * interp.c (Max, Min): New functions.
970 * mips.igen (BC1): Add tracing.
972 start-sanitize-cygnus
973 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
975 * mdmx.igen: Tag all functions as requiring either with mdmx or
980 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
982 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
984 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
986 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
988 * r5900.igen: Rewrite.
990 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
992 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
993 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
996 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
998 * interp.c Added memory map for stack in vr4100
1000 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1002 * interp.c (load_memory): Add missing "break"'s.
1004 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006 * interp.c (sim_store_register, sim_fetch_register): Pass in
1007 length parameter. Return -1.
1009 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1011 * interp.c: Added hardware init hook, fixed warnings.
1013 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1017 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019 * interp.c (ifetch16): New function.
1021 * sim-main.h (IMEM32): Rename IMEM.
1022 (IMEM16_IMMED): Define.
1024 (DELAY_SLOT): Update.
1026 * m16run.c (sim_engine_run): New file.
1028 * m16.igen: All instructions except LB.
1029 (LB): Call do_load_byte.
1030 * mips.igen (do_load_byte): New function.
1031 (LB): Call do_load_byte.
1033 * mips.igen: Move spec for insn bit size and high bit from here.
1034 * Makefile.in (tmp-igen, tmp-m16): To here.
1036 * m16.dc: New file, decode mips16 instructions.
1038 * Makefile.in (SIM_NO_ALL): Define.
1039 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1042 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1046 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1048 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1049 point unit to 32 bit registers.
1050 * configure: Re-generate.
1052 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054 * configure.in (sim_use_gen): Make IGEN the default simulator
1055 generator for generic 32 and 64 bit mips targets.
1056 * configure: Re-generate.
1058 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1060 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1063 * interp.c (sim_fetch_register, sim_store_register): Read/write
1064 FGR from correct location.
1065 (sim_open): Set size of FGR's according to
1066 WITH_TARGET_FLOATING_POINT_BITSIZE.
1068 * sim-main.h (FGR): Store floating point registers in a separate
1071 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073 * configure: Regenerated to track ../common/aclocal.m4 changes.
1075 start-sanitize-cygnus
1076 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1079 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1083 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1085 * interp.c (pending_tick): New function. Deliver pending writes.
1087 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1088 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1089 it can handle mixed sized quantites and single bits.
1091 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1093 * interp.c (oengine.h): Do not include when building with IGEN.
1094 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1095 (sim_info): Ditto for PROCESSOR_64BIT.
1096 (sim_monitor): Replace ut_reg with unsigned_word.
1097 (*): Ditto for t_reg.
1098 (LOADDRMASK): Define.
1099 (sim_open): Remove defunct check that host FP is IEEE compliant,
1100 using software to emulate floating point.
1101 (value_fpr, ...): Always compile, was conditional on HASFPU.
1103 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1108 * interp.c (SD, CPU): Define.
1109 (mips_option_handler): Set flags in each CPU.
1110 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1111 (sim_close): Do not clear STATE, deleted anyway.
1112 (sim_write, sim_read): Assume CPU zero's vm should be used for
1114 (sim_create_inferior): Set the PC for all processors.
1115 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1117 (mips16_entry): Pass correct nr of args to store_word, load_word.
1118 (ColdReset): Cold reset all cpu's.
1119 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1120 (sim_monitor, load_memory, store_memory, signal_exception): Use
1121 `CPU' instead of STATE_CPU.
1124 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1127 * sim-main.h (signal_exception): Add sim_cpu arg.
1128 (SignalException*): Pass both SD and CPU to signal_exception.
1129 * interp.c (signal_exception): Update.
1131 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1133 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1134 address_translation): Ditto
1135 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1137 start-sanitize-cygnus
1138 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1140 (ByteAlign): Use StoreFPR, pass args in correct order.
1143 start-sanitize-r5900
1144 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1146 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1149 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1151 * configure: Regenerated to track ../common/aclocal.m4 changes.
1153 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155 start-sanitize-r5900
1156 * configure.in (sim_igen_filter): For r5900, use igen.
1157 * configure: Re-generate.
1160 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1162 * mips.igen (model): Map processor names onto BFD name.
1164 * sim-main.h (CPU_CIA): Delete.
1165 (SET_CIA, GET_CIA): Define
1167 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1169 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1172 * configure.in (default_endian): Configure a big-endian simulator
1174 * configure: Re-generate.
1176 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1178 * configure: Regenerated to track ../common/aclocal.m4 changes.
1180 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1182 * interp.c (sim_monitor): Handle Densan monitor outbyte
1183 and inbyte functions.
1185 1997-12-29 Felix Lee <flee@cygnus.com>
1187 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1189 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1191 * Makefile.in (tmp-igen): Arrange for $zero to always be
1192 reset to zero after every instruction.
1194 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1196 * configure: Regenerated to track ../common/aclocal.m4 changes.
1199 start-sanitize-cygnus
1200 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1202 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1205 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1207 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1208 vr5400 with the vr5000 as the default.
1211 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1213 * mips.igen (MSUB): Fix to work like MADD.
1214 * gencode.c (MSUB): Similarly.
1216 start-sanitize-cygnus
1217 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1219 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1223 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1225 * configure: Regenerated to track ../common/aclocal.m4 changes.
1227 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1229 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1231 start-sanitize-cygnus
1232 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1233 (value_cc, store_cc): Implement.
1235 * sim-main.h: Add 8*3*8 bit accumulator.
1237 * vr5400.igen: Move mdmx instructins from here
1238 * mdmx.igen: To here - new file. Add/fix missing instructions.
1239 * mips.igen: Include mdmx.igen.
1240 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1243 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245 * sim-main.h (sim-fpu.h): Include.
1247 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1248 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1249 using host independant sim_fpu module.
1251 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253 * interp.c (signal_exception): Report internal errors with SIGABRT
1256 * sim-main.h (C0_CONFIG): New register.
1257 (signal.h): No longer include.
1259 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1261 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1263 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1265 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267 * mips.igen: Tag vr5000 instructions.
1268 (ANDI): Was missing mipsIV model, fix assembler syntax.
1269 (do_c_cond_fmt): New function.
1270 (C.cond.fmt): Handle mips I-III which do not support CC field
1272 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1273 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1275 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1276 vr5000 which saves LO in a GPR separatly.
1278 * configure.in (enable-sim-igen): For vr5000, select vr5000
1279 specific instructions.
1280 * configure: Re-generate.
1282 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1286 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1287 fmt_uninterpreted_64 bit cases to switch. Convert to
1290 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1292 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1293 as specified in IV3.2 spec.
1294 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1296 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1298 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1299 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1300 (start-sanitize-r5900):
1301 (LWXC1, SWXC1): Delete from r5900 instruction set.
1302 (end-sanitize-r5900):
1303 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1304 PENDING_FILL versions of instructions. Simplify.
1306 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1308 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1310 (MTHI, MFHI): Disable code checking HI-LO.
1312 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1314 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1316 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1318 * gencode.c (build_mips16_operands): Replace IPC with cia.
1320 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1321 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1323 (UndefinedResult): Replace function with macro/function
1325 (sim_engine_run): Don't save PC in IPC.
1327 * sim-main.h (IPC): Delete.
1329 start-sanitize-cygnus
1330 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1331 (do_select): Rename function select.
1334 * interp.c (signal_exception, store_word, load_word,
1335 address_translation, load_memory, store_memory, cache_op,
1336 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1337 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1338 current instruction address - cia - argument.
1339 (sim_read, sim_write): Call address_translation directly.
1340 (sim_engine_run): Rename variable vaddr to cia.
1341 (signal_exception): Pass cia to sim_monitor
1343 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1344 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1345 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1347 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1348 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1351 * interp.c (signal_exception): Pass restart address to
1354 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1355 idecode.o): Add dependency.
1357 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1359 (DELAY_SLOT): Update NIA not PC with branch address.
1360 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1362 * mips.igen: Use CIA not PC in branch calculations.
1363 (illegal): Call SignalException.
1364 (BEQ, ADDIU): Fix assembler.
1366 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1368 * m16.igen (JALX): Was missing.
1370 * configure.in (enable-sim-igen): New configuration option.
1371 * configure: Re-generate.
1373 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1375 * interp.c (load_memory, store_memory): Delete parameter RAW.
1376 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1377 bypassing {load,store}_memory.
1379 * sim-main.h (ByteSwapMem): Delete definition.
1381 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1383 * interp.c (sim_do_command, sim_commands): Delete mips specific
1384 commands. Handled by module sim-options.
1386 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1387 (WITH_MODULO_MEMORY): Define.
1389 * interp.c (sim_info): Delete code printing memory size.
1391 * interp.c (mips_size): Nee sim_size, delete function.
1393 (monitor, monitor_base, monitor_size): Delete global variables.
1394 (sim_open, sim_close): Delete code creating monitor and other
1395 memory regions. Use sim-memopts module, via sim_do_commandf, to
1396 manage memory regions.
1397 (load_memory, store_memory): Use sim-core for memory model.
1399 * interp.c (address_translation): Delete all memory map code
1400 except line forcing 32 bit addresses.
1402 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1404 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1407 * interp.c (logfh, logfile): Delete globals.
1408 (sim_open, sim_close): Delete code opening & closing log file.
1409 (mips_option_handler): Delete -l and -n options.
1410 (OPTION mips_options): Ditto.
1412 * interp.c (OPTION mips_options): Rename option trace to dinero.
1413 (mips_option_handler): Update.
1415 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1417 * interp.c (fetch_str): New function.
1418 (sim_monitor): Rewrite using sim_read & sim_write.
1419 (sim_open): Check magic number.
1420 (sim_open): Write monitor vectors into memory using sim_write.
1421 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1422 (sim_read, sim_write): Simplify - transfer data one byte at a
1424 (load_memory, store_memory): Clarify meaning of parameter RAW.
1426 * sim-main.h (isHOST): Defete definition.
1427 (isTARGET): Mark as depreciated.
1428 (address_translation): Delete parameter HOST.
1430 * interp.c (address_translation): Delete parameter HOST.
1433 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1435 * gencode.c: Add tx49 configury and insns.
1436 * configure.in: Add tx49 configury.
1437 * configure: Update.
1440 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1445 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1447 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1449 * mips.igen: Add model filter field to records.
1451 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1453 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1455 interp.c (sim_engine_run): Do not compile function sim_engine_run
1456 when WITH_IGEN == 1.
1458 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1459 target architecture.
1461 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1462 igen. Replace with configuration variables sim_igen_flags /
1465 start-sanitize-r5900
1466 * r5900.igen: New file. Copy r5900 insns here.
1468 start-sanitize-cygnus
1469 * vr5400.igen: New file.
1471 * m16.igen: New file. Copy mips16 insns here.
1472 * mips.igen: From here.
1474 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1476 start-sanitize-cygnus
1477 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1479 * configure.in: Add mips64vr5400 target.
1480 * configure: Re-generate.
1483 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1485 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1487 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1489 * gencode.c (build_instruction): Follow sim_write's lead in using
1490 BigEndianMem instead of !ByteSwapMem.
1492 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494 * configure.in (sim_gen): Dependent on target, select type of
1495 generator. Always select old style generator.
1497 configure: Re-generate.
1499 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1501 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1502 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1503 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1504 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1505 SIM_@sim_gen@_*, set by autoconf.
1507 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1511 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1512 CURRENT_FLOATING_POINT instead.
1514 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1515 (address_translation): Raise exception InstructionFetch when
1516 translation fails and isINSTRUCTION.
1518 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1519 sim_engine_run): Change type of of vaddr and paddr to
1521 (address_translation, prefetch, load_memory, store_memory,
1522 cache_op): Change type of vAddr and pAddr to address_word.
1524 * gencode.c (build_instruction): Change type of vaddr and paddr to
1527 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1529 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1530 macro to obtain result of ALU op.
1532 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534 * interp.c (sim_info): Call profile_print.
1536 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1538 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1540 * sim-main.h (WITH_PROFILE): Do not define, defined in
1541 common/sim-config.h. Use sim-profile module.
1542 (simPROFILE): Delete defintion.
1544 * interp.c (PROFILE): Delete definition.
1545 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1546 (sim_close): Delete code writing profile histogram.
1547 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1549 (sim_engine_run): Delete code profiling the PC.
1551 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1553 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1555 * interp.c (sim_monitor): Make register pointers of type
1558 * sim-main.h: Make registers of type unsigned_word not
1561 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563 start-sanitize-r5900
1564 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1565 ...): Move to sim-main.h
1568 * interp.c (sync_operation): Rename from SyncOperation, make
1569 global, add SD argument.
1570 (prefetch): Rename from Prefetch, make global, add SD argument.
1571 (decode_coproc): Make global.
1573 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1575 * gencode.c (build_instruction): Generate DecodeCoproc not
1576 decode_coproc calls.
1578 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1579 (SizeFGR): Move to sim-main.h
1580 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1581 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1582 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1584 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1585 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1586 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1587 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1588 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1589 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1591 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1593 (sim-alu.h): Include.
1594 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1595 (sim_cia): Typedef to instruction_address.
1597 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1599 * Makefile.in (interp.o): Rename generated file engine.c to
1604 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1606 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1608 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610 * gencode.c (build_instruction): For "FPSQRT", output correct
1611 number of arguments to Recip.
1613 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1615 * Makefile.in (interp.o): Depends on sim-main.h
1617 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1619 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1620 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1621 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1622 STATE, DSSTATE): Define
1623 (GPR, FGRIDX, ..): Define.
1625 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1626 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1627 (GPR, FGRIDX, ...): Delete macros.
1629 * interp.c: Update names to match defines from sim-main.h
1631 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633 * interp.c (sim_monitor): Add SD argument.
1634 (sim_warning): Delete. Replace calls with calls to
1636 (sim_error): Delete. Replace calls with sim_io_error.
1637 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1638 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1639 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1641 (mips_size): Rename from sim_size. Add SD argument.
1643 * interp.c (simulator): Delete global variable.
1644 (callback): Delete global variable.
1645 (mips_option_handler, sim_open, sim_write, sim_read,
1646 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1647 sim_size,sim_monitor): Use sim_io_* not callback->*.
1648 (sim_open): ZALLOC simulator struct.
1649 (PROFILE): Do not define.
1651 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1654 support.h with corresponding code.
1656 * sim-main.h (word64, uword64), support.h: Move definition to
1658 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1661 * Makefile.in: Update dependencies
1662 * interp.c: Do not include.
1664 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1666 * interp.c (address_translation, load_memory, store_memory,
1667 cache_op): Rename to from AddressTranslation et.al., make global,
1670 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1673 * interp.c (SignalException): Rename to signal_exception, make
1676 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1678 * sim-main.h (SignalException, SignalExceptionInterrupt,
1679 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1680 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1681 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1684 * interp.c, support.h: Use.
1686 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1689 to value_fpr / store_fpr. Add SD argument.
1690 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1691 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1693 * sim-main.h (ValueFPR, StoreFPR): Define.
1695 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1697 * interp.c (sim_engine_run): Check consistency between configure
1698 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1701 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1702 (mips_fpu): Configure WITH_FLOATING_POINT.
1703 (mips_endian): Configure WITH_TARGET_ENDIAN.
1704 * configure: Update.
1706 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1708 * configure: Regenerated to track ../common/aclocal.m4 changes.
1710 start-sanitize-r5900
1711 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713 * interp.c (MAX_REG): Allow up-to 128 registers.
1714 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1715 (REGISTER_SA): Ditto.
1716 (sim_open): Initialize register_widths for r5900 specific
1718 (sim_fetch_register, sim_store_register): Check for request of
1719 r5900 specific SA register. Check for request for hi 64 bits of
1720 r5900 specific registers.
1723 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1725 * configure: Regenerated.
1727 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1729 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1731 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1733 * gencode.c (print_igen_insn_models): Assume certain architectures
1734 include all mips* instructions.
1735 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1738 * Makefile.in (tmp.igen): Add target. Generate igen input from
1741 * gencode.c (FEATURE_IGEN): Define.
1742 (main): Add --igen option. Generate output in igen format.
1743 (process_instructions): Format output according to igen option.
1744 (print_igen_insn_format): New function.
1745 (print_igen_insn_models): New function.
1746 (process_instructions): Only issue warnings and ignore
1747 instructions when no FEATURE_IGEN.
1749 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1754 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1761 SIM_RESERVED_BITS): Delete, moved to common.
1762 (SIM_EXTRA_CFLAGS): Update.
1764 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766 * configure.in: Configure non-strict memory alignment.
1767 * configure: Regenerated to track ../common/aclocal.m4 changes.
1769 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1771 * configure: Regenerated to track ../common/aclocal.m4 changes.
1773 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1775 * gencode.c (SDBBP,DERET): Added (3900) insns.
1776 (RFE): Turn on for 3900.
1777 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1778 (dsstate): Made global.
1779 (SUBTARGET_R3900): Added.
1780 (CANCELDELAYSLOT): New.
1781 (SignalException): Ignore SystemCall rather than ignore and
1782 terminate. Add DebugBreakPoint handling.
1783 (decode_coproc): New insns RFE, DERET; and new registers Debug
1784 and DEPC protected by SUBTARGET_R3900.
1785 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1787 * Makefile.in,configure.in: Add mips subtarget option.
1788 * configure: Update.
1790 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1792 * gencode.c: Add r3900 (tx39).
1795 * gencode.c: Fix some configuration problems by improving
1796 the relationship between tx19 and tx39.
1799 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1801 * gencode.c (build_instruction): Don't need to subtract 4 for
1804 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1806 * interp.c: Correct some HASFPU problems.
1808 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810 * configure: Regenerated to track ../common/aclocal.m4 changes.
1812 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814 * interp.c (mips_options): Fix samples option short form, should
1817 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819 * interp.c (sim_info): Enable info code. Was just returning.
1821 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1823 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1826 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1830 (build_instruction): Ditto for LL.
1833 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1835 * mips/configure.in, mips/gencode: Add tx19/r1900.
1838 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1840 * configure: Regenerated to track ../common/aclocal.m4 changes.
1842 start-sanitize-r5900
1843 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1846 for overflow due to ABS of MININT, set result to MAXINT.
1847 (build_instruction): For "psrlvw", signextend bit 31.
1850 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1852 * configure: Regenerated to track ../common/aclocal.m4 changes.
1855 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857 * interp.c (sim_open): Add call to sim_analyze_program, update
1860 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1862 * interp.c (sim_kill): Delete.
1863 (sim_create_inferior): Add ABFD argument. Set PC from same.
1864 (sim_load): Move code initializing trap handlers from here.
1865 (sim_open): To here.
1866 (sim_load): Delete, use sim-hload.c.
1868 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1870 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1872 * configure: Regenerated to track ../common/aclocal.m4 changes.
1875 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1877 * interp.c (sim_open): Add ABFD argument.
1878 (sim_load): Move call to sim_config from here.
1879 (sim_open): To here. Check return status.
1881 start-sanitize-r5900
1882 * gencode.c (build_instruction): Do not define x8000000000000000,
1883 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1886 start-sanitize-r5900
1887 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1890 "pdivuw" check for overflow due to signed divide by -1.
1893 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1895 * gencode.c (build_instruction): Two arg MADD should
1896 not assign result to $0.
1898 start-sanitize-r5900
1899 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1901 * gencode.c (build_instruction): For "ppac5" use unsigned
1902 arrithmetic so that the sign bit doesn't smear when right shifted.
1903 (build_instruction): For "pdiv" perform sign extension when
1904 storing results in HI and LO.
1905 (build_instructions): For "pdiv" and "pdivbw" check for
1907 (build_instruction): For "pmfhl.slw" update hi part of dest
1908 register as well as low part.
1909 (build_instruction): For "pmfhl" portably handle long long values.
1910 (build_instruction): For "pmfhl.sh" correctly negative values.
1911 Store half words 2 and three in the correct place.
1912 (build_instruction): For "psllvw", sign extend value after shift.
1915 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1917 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1918 * sim/mips/configure.in: Regenerate.
1920 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1922 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1923 signed8, unsigned8 et.al. types.
1925 start-sanitize-r5900
1926 * gencode.c (build_instruction): For PMULTU* do not sign extend
1927 registers. Make generated code easier to debug.
1930 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1931 hosts when selecting subreg.
1933 start-sanitize-r5900
1934 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1936 * gencode.c (type_for_data_len): For 32bit operations concerned
1937 with overflow, perform op using 64bits.
1938 (build_instruction): For PADD, always compute operation using type
1939 returned by type_for_data_len.
1940 (build_instruction): For PSUBU, when overflow, saturate to zero as
1944 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1946 start-sanitize-r5900
1947 * gencode.c (build_instruction): Handle "pext5" according to
1948 version 1.95 of the r5900 ISA.
1950 * gencode.c (build_instruction): Handle "ppac5" according to
1951 version 1.95 of the r5900 ISA.
1954 * interp.c (sim_engine_run): Reset the ZERO register to zero
1955 regardless of FEATURE_WARN_ZERO.
1956 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1958 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1960 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1961 (SignalException): For BreakPoints ignore any mode bits and just
1963 (SignalException): Always set the CAUSE register.
1965 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1967 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1968 exception has been taken.
1970 * interp.c: Implement the ERET and mt/f sr instructions.
1972 start-sanitize-r5900
1973 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * gencode.c (build_instruction): For paddu, extract unsigned
1978 * gencode.c (build_instruction): Saturate padds instead of padd
1982 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984 * interp.c (SignalException): Don't bother restarting an
1987 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989 * interp.c (SignalException): Really take an interrupt.
1990 (interrupt_event): Only deliver interrupts when enabled.
1992 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994 * interp.c (sim_info): Only print info when verbose.
1995 (sim_info) Use sim_io_printf for output.
1997 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1999 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2002 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004 * interp.c (sim_do_command): Check for common commands if a
2005 simulator specific command fails.
2007 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2009 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2010 and simBE when DEBUG is defined.
2012 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014 * interp.c (interrupt_event): New function. Pass exception event
2015 onto exception handler.
2017 * configure.in: Check for stdlib.h.
2018 * configure: Regenerate.
2020 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2021 variable declaration.
2022 (build_instruction): Initialize memval1.
2023 (build_instruction): Add UNUSED attribute to byte, bigend,
2025 (build_operands): Ditto.
2027 * interp.c: Fix GCC warnings.
2028 (sim_get_quit_code): Delete.
2030 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2031 * Makefile.in: Ditto.
2032 * configure: Re-generate.
2034 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2036 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2038 * interp.c (mips_option_handler): New function parse argumes using
2040 (myname): Replace with STATE_MY_NAME.
2041 (sim_open): Delete check for host endianness - performed by
2043 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2044 (sim_open): Move much of the initialization from here.
2045 (sim_load): To here. After the image has been loaded and
2047 (sim_open): Move ColdReset from here.
2048 (sim_create_inferior): To here.
2049 (sim_open): Make FP check less dependant on host endianness.
2051 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2053 * interp.c (sim_set_callbacks): Delete.
2055 * interp.c (membank, membank_base, membank_size): Replace with
2056 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2057 (sim_open): Remove call to callback->init. gdb/run do this.
2061 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2063 * interp.c (big_endian_p): Delete, replaced by
2064 current_target_byte_order.
2066 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2068 * interp.c (host_read_long, host_read_word, host_swap_word,
2069 host_swap_long): Delete. Using common sim-endian.
2070 (sim_fetch_register, sim_store_register): Use H2T.
2071 (pipeline_ticks): Delete. Handled by sim-events.
2073 (sim_engine_run): Update.
2075 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2077 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2079 (SignalException): To here. Signal using sim_engine_halt.
2080 (sim_stop_reason): Delete, moved to common.
2082 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2084 * interp.c (sim_open): Add callback argument.
2085 (sim_set_callbacks): Delete SIM_DESC argument.
2088 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2090 * Makefile.in (SIM_OBJS): Add common modules.
2092 * interp.c (sim_set_callbacks): Also set SD callback.
2093 (set_endianness, xfer_*, swap_*): Delete.
2094 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2095 Change to functions using sim-endian macros.
2096 (control_c, sim_stop): Delete, use common version.
2097 (simulate): Convert into.
2098 (sim_engine_run): This function.
2099 (sim_resume): Delete.
2101 * interp.c (simulation): New variable - the simulator object.
2102 (sim_kind): Delete global - merged into simulation.
2103 (sim_load): Cleanup. Move PC assignment from here.
2104 (sim_create_inferior): To here.
2106 * sim-main.h: New file.
2107 * interp.c (sim-main.h): Include.
2109 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2111 * configure: Regenerated to track ../common/aclocal.m4 changes.
2113 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2115 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2117 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2119 * gencode.c (build_instruction): DIV instructions: check
2120 for division by zero and integer overflow before using
2121 host's division operation.
2123 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2125 * Makefile.in (SIM_OBJS): Add sim-load.o.
2126 * interp.c: #include bfd.h.
2127 (target_byte_order): Delete.
2128 (sim_kind, myname, big_endian_p): New static locals.
2129 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2130 after argument parsing. Recognize -E arg, set endianness accordingly.
2131 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2132 load file into simulator. Set PC from bfd.
2133 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2134 (set_endianness): Use big_endian_p instead of target_byte_order.
2136 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2138 * interp.c (sim_size): Delete prototype - conflicts with
2139 definition in remote-sim.h. Correct definition.
2141 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2143 * configure: Regenerated to track ../common/aclocal.m4 changes.
2146 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2148 * interp.c (sim_open): New arg `kind'.
2150 * configure: Regenerated to track ../common/aclocal.m4 changes.
2152 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2154 * configure: Regenerated to track ../common/aclocal.m4 changes.
2156 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2158 * interp.c (sim_open): Set optind to 0 before calling getopt.
2160 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2162 * configure: Regenerated to track ../common/aclocal.m4 changes.
2164 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2166 * interp.c : Replace uses of pr_addr with pr_uword64
2167 where the bit length is always 64 independent of SIM_ADDR.
2168 (pr_uword64) : added.
2170 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2172 * configure: Re-generate.
2174 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2176 * configure: Regenerate to track ../common/aclocal.m4 changes.
2178 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2180 * interp.c (sim_open): New SIM_DESC result. Argument is now
2182 (other sim_*): New SIM_DESC argument.
2184 start-sanitize-r5900
2185 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2187 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2188 Change values to avoid overloading DOUBLEWORD which is tested
2190 * gencode.c: reinstate "offending code".
2193 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2195 * interp.c: Fix printing of addresses for non-64-bit targets.
2196 (pr_addr): Add function to print address based on size.
2197 start-sanitize-r5900
2198 * gencode.c: #ifdef out offending code until a permanent fix
2199 can be added. Code is causing build errors for non-5900 mips targets.
2202 start-sanitize-r5900
2203 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2205 * gencode.c (process_instructions): Correct test for ISA dependent
2206 architecture bits in isa field of MIPS_DECODE.
2209 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2211 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2213 start-sanitize-r5900
2214 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2216 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2220 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2222 * gencode.c (build_mips16_operands): Correct computation of base
2223 address for extended PC relative instruction.
2225 start-sanitize-r5900
2226 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2228 * Makefile.in, configure, configure.in, gencode.c,
2229 interp.c, support.h: add r5900.
2232 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2234 * interp.c (mips16_entry): Add support for floating point cases.
2235 (SignalException): Pass floating point cases to mips16_entry.
2236 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2238 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2240 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2241 and then set the state to fmt_uninterpreted.
2242 (COP_SW): Temporarily set the state to fmt_word while calling
2245 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2247 * gencode.c (build_instruction): The high order may be set in the
2248 comparison flags at any ISA level, not just ISA 4.
2250 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2252 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2253 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2254 * configure.in: sinclude ../common/aclocal.m4.
2255 * configure: Regenerated.
2257 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2259 * configure: Rebuild after change to aclocal.m4.
2261 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2263 * configure configure.in Makefile.in: Update to new configure
2264 scheme which is more compatible with WinGDB builds.
2265 * configure.in: Improve comment on how to run autoconf.
2266 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2267 * Makefile.in: Use autoconf substitution to install common
2270 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2272 * gencode.c (build_instruction): Use BigEndianCPU instead of
2275 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2277 * interp.c (sim_monitor): Make output to stdout visible in
2278 wingdb's I/O log window.
2280 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2282 * support.h: Undo previous change to SIGTRAP
2285 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2287 * interp.c (store_word, load_word): New static functions.
2288 (mips16_entry): New static function.
2289 (SignalException): Look for mips16 entry and exit instructions.
2290 (simulate): Use the correct index when setting fpr_state after
2291 doing a pending move.
2293 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2295 * interp.c: Fix byte-swapping code throughout to work on
2296 both little- and big-endian hosts.
2298 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2300 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2301 with gdb/config/i386/xm-windows.h.
2303 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2305 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2306 that messes up arithmetic shifts.
2308 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2310 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2311 SIGTRAP and SIGQUIT for _WIN32.
2313 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2315 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2316 force a 64 bit multiplication.
2317 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2318 destination register is 0, since that is the default mips16 nop
2321 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2323 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2324 (build_endian_shift): Don't check proc64.
2325 (build_instruction): Always set memval to uword64. Cast op2 to
2326 uword64 when shifting it left in memory instructions. Always use
2327 the same code for stores--don't special case proc64.
2329 * gencode.c (build_mips16_operands): Fix base PC value for PC
2331 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2333 * interp.c (simJALDELAYSLOT): Define.
2334 (JALDELAYSLOT): Define.
2335 (INDELAYSLOT, INJALDELAYSLOT): Define.
2336 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2338 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2340 * interp.c (sim_open): add flush_cache as a PMON routine
2341 (sim_monitor): handle flush_cache by ignoring it
2343 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2345 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2347 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2348 (BigEndianMem): Rename to ByteSwapMem and change sense.
2349 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2350 BigEndianMem references to !ByteSwapMem.
2351 (set_endianness): New function, with prototype.
2352 (sim_open): Call set_endianness.
2353 (sim_info): Use simBE instead of BigEndianMem.
2354 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2355 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2356 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2357 ifdefs, keeping the prototype declaration.
2358 (swap_word): Rewrite correctly.
2359 (ColdReset): Delete references to CONFIG. Delete endianness related
2360 code; moved to set_endianness.
2362 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2364 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2365 * interp.c (CHECKHILO): Define away.
2366 (simSIGINT): New macro.
2367 (membank_size): Increase from 1MB to 2MB.
2368 (control_c): New function.
2369 (sim_resume): Rename parameter signal to signal_number. Add local
2370 variable prev. Call signal before and after simulate.
2371 (sim_stop_reason): Add simSIGINT support.
2372 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2374 (sim_warning): Delete call to SignalException. Do call printf_filtered
2376 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2377 a call to sim_warning.
2379 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2381 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2382 16 bit instructions.
2384 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2386 Add support for mips16 (16 bit MIPS implementation):
2387 * gencode.c (inst_type): Add mips16 instruction encoding types.
2388 (GETDATASIZEINSN): Define.
2389 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2390 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2392 (MIPS16_DECODE): New table, for mips16 instructions.
2393 (bitmap_val): New static function.
2394 (struct mips16_op): Define.
2395 (mips16_op_table): New table, for mips16 operands.
2396 (build_mips16_operands): New static function.
2397 (process_instructions): If PC is odd, decode a mips16
2398 instruction. Break out instruction handling into new
2399 build_instruction function.
2400 (build_instruction): New static function, broken out of
2401 process_instructions. Check modifiers rather than flags for SHIFT
2402 bit count and m[ft]{hi,lo} direction.
2403 (usage): Pass program name to fprintf.
2404 (main): Remove unused variable this_option_optind. Change
2405 ``*loptarg++'' to ``loptarg++''.
2406 (my_strtoul): Parenthesize && within ||.
2407 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2408 (simulate): If PC is odd, fetch a 16 bit instruction, and
2409 increment PC by 2 rather than 4.
2410 * configure.in: Add case for mips16*-*-*.
2411 * configure: Rebuild.
2413 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2415 * interp.c: Allow -t to enable tracing in standalone simulator.
2416 Fix garbage output in trace file and error messages.
2418 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2420 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2421 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2422 * configure.in: Simplify using macros in ../common/aclocal.m4.
2423 * configure: Regenerated.
2424 * tconfig.in: New file.
2426 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2428 * interp.c: Fix bugs in 64-bit port.
2429 Use ansi function declarations for msvc compiler.
2430 Initialize and test file pointer in trace code.
2431 Prevent duplicate definition of LAST_EMED_REGNUM.
2433 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2435 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2437 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2439 * interp.c (SignalException): Check for explicit terminating
2441 * gencode.c: Pass instruction value through SignalException()
2442 calls for Trap, Breakpoint and Syscall.
2444 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2446 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2447 only used on those hosts that provide it.
2448 * configure.in: Add sqrt() to list of functions to be checked for.
2449 * config.in: Re-generated.
2450 * configure: Re-generated.
2452 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2454 * gencode.c (process_instructions): Call build_endian_shift when
2455 expanding STORE RIGHT, to fix swr.
2456 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2457 clear the high bits.
2458 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2459 Fix float to int conversions to produce signed values.
2461 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2463 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2464 (process_instructions): Correct handling of nor instruction.
2465 Correct shift count for 32 bit shift instructions. Correct sign
2466 extension for arithmetic shifts to not shift the number of bits in
2467 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2468 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2470 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2471 It's OK to have a mult follow a mult. What's not OK is to have a
2472 mult follow an mfhi.
2473 (Convert): Comment out incorrect rounding code.
2475 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2477 * interp.c (sim_monitor): Improved monitor printf
2478 simulation. Tidied up simulator warnings, and added "--log" option
2479 for directing warning message output.
2480 * gencode.c: Use sim_warning() rather than WARNING macro.
2482 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2484 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2485 getopt1.o, rather than on gencode.c. Link objects together.
2486 Don't link against -liberty.
2487 (gencode.o, getopt.o, getopt1.o): New targets.
2488 * gencode.c: Include <ctype.h> and "ansidecl.h".
2489 (AND): Undefine after including "ansidecl.h".
2490 (ULONG_MAX): Define if not defined.
2491 (OP_*): Don't define macros; now defined in opcode/mips.h.
2492 (main): Call my_strtoul rather than strtoul.
2493 (my_strtoul): New static function.
2495 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2497 * gencode.c (process_instructions): Generate word64 and uword64
2498 instead of `long long' and `unsigned long long' data types.
2499 * interp.c: #include sysdep.h to get signals, and define default
2501 * (Convert): Work around for Visual-C++ compiler bug with type
2503 * support.h: Make things compile under Visual-C++ by using
2504 __int64 instead of `long long'. Change many refs to long long
2505 into word64/uword64 typedefs.
2507 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2509 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2510 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2512 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2513 (AC_PROG_INSTALL): Added.
2514 (AC_PROG_CC): Moved to before configure.host call.
2515 * configure: Rebuilt.
2517 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2519 * configure.in: Define @SIMCONF@ depending on mips target.
2520 * configure: Rebuild.
2521 * Makefile.in (run): Add @SIMCONF@ to control simulator
2523 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2524 * interp.c: Remove some debugging, provide more detailed error
2525 messages, update memory accesses to use LOADDRMASK.
2527 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2529 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2530 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2532 * configure: Rebuild.
2533 * config.in: New file, generated by autoheader.
2534 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2535 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2536 HAVE_ANINT and HAVE_AINT, as appropriate.
2537 * Makefile.in (run): Use @LIBS@ rather than -lm.
2538 (interp.o): Depend upon config.h.
2539 (Makefile): Just rebuild Makefile.
2540 (clean): Remove stamp-h.
2541 (mostlyclean): Make the same as clean, not as distclean.
2542 (config.h, stamp-h): New targets.
2544 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2546 * interp.c (ColdReset): Fix boolean test. Make all simulator
2549 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2551 * interp.c (xfer_direct_word, xfer_direct_long,
2552 swap_direct_word, swap_direct_long, xfer_big_word,
2553 xfer_big_long, xfer_little_word, xfer_little_long,
2554 swap_word,swap_long): Added.
2555 * interp.c (ColdReset): Provide function indirection to
2556 host<->simulated_target transfer routines.
2557 * interp.c (sim_store_register, sim_fetch_register): Updated to
2558 make use of indirected transfer routines.
2560 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2562 * gencode.c (process_instructions): Ensure FP ABS instruction
2564 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2565 system call support.
2567 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2569 * interp.c (sim_do_command): Complain if callback structure not
2572 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2574 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2575 support for Sun hosts.
2576 * Makefile.in (gencode): Ensure the host compiler and libraries
2577 used for cross-hosted build.
2579 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2581 * interp.c, gencode.c: Some more (TODO) tidying.
2583 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2585 * gencode.c, interp.c: Replaced explicit long long references with
2586 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2587 * support.h (SET64LO, SET64HI): Macros added.
2589 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2591 * configure: Regenerate with autoconf 2.7.
2593 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2595 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2596 * support.h: Remove superfluous "1" from #if.
2597 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2599 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2601 * interp.c (StoreFPR): Control UndefinedResult() call on
2602 WARN_RESULT manifest.
2604 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2606 * gencode.c: Tidied instruction decoding, and added FP instruction
2609 * interp.c: Added dineroIII, and BSD profiling support. Also
2610 run-time FP handling.
2612 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2614 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2615 gencode.c, interp.c, support.h: created.