sim/mips/ChangeLog

   1 2007-05-14  Thiemo Seufer  <ths@mips.com>
   2
   3         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
   4         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
   5         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
   6         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
   7         for mips32r2.
   8
   9 2007-03-01  Thiemo Seufer  <ths@mips.com>
  10
  11         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
  12         and mips64.
  13
  14 2007-02-20  Thiemo Seufer  <ths@mips.com>
  15
  16         * dsp.igen: Update copyright notice.
  17         * dsp2.igen: Fix copyright notice.
  18
  19 2007-02-20  Thiemo Seufer  <ths@mips.com>
  20             Chao-Ying Fu  <fu@mips.com>
  21
  22         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
  23         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  24         Add dsp2 to sim_igen_machine.
  25         * configure: Regenerate.
  26         * dsp.igen (do_ph_op): Add MUL support when op = 2.
  27         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  28         (mulq_rs.ph): Use do_ph_mulq.
  29         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  30         * mips.igen: Add dsp2 model and include dsp2.igen.
  31         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  32         for *mips32r2, *mips64r2, *dsp.
  33         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  34         for *mips32r2, *mips64r2, *dsp2.
  35         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
  36
  37 2007-02-19  Thiemo Seufer  <ths@mips.com>
  38             Nigel Stephens  <nigel@mips.com>
  39
  40         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
  41         jumps with hazard barrier.
  42
  43 2007-02-19  Thiemo Seufer  <ths@mips.com>
  44             Nigel Stephens  <nigel@mips.com>
  45
  46         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
  47         after each call to sim_io_write.
  48
  49 2007-02-19  Thiemo Seufer  <ths@mips.com>
  50             Nigel Stephens  <nigel@mips.com>
  51
  52         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
  53         supported by this simulator.
  54         (decode_coproc): Recognise additional CP0 Config registers
  55         correctly.
  56
  57 2007-02-19  Thiemo Seufer  <ths@mips.com>
  58             Nigel Stephens  <nigel@mips.com>
  59             David Ung  <davidu@mips.com>
  60
  61         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
  62         uninterpreted formats. If fmt is one of the uninterpreted types
  63         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
  64         fmt_word, and fmt_uninterpreted_64 like fmt_long.
  65         (store_fpr): When writing an invalid odd register, set the
  66         matching even register to fmt_unknown, not the following register.
  67         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
  68         the the memory window at offset 0 set by --memory-size command
  69         line option.
  70         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
  71         point register.
  72         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
  73         register.
  74         (sim_monitor): When returning the memory size to the MIPS
  75         application, use the value in STATE_MEM_SIZE, not an arbitrary
  76         hardcoded value.
  77         (cop_lw): Don' mess around with FPR_STATE, just pass
  78         fmt_uninterpreted_32 to StoreFPR.
  79         (cop_sw): Similarly.
  80         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
  81         (cop_sd): Similarly.
  82         * mips.igen (not_word_value): Single version for mips32, mips64
  83         and mips16.
  84
  85 2007-02-19  Thiemo Seufer <ths@mips.com>
  86             Nigel Stephens  <nigel@mips.com>
  87
  88         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
  89         MBytes.
  90
  91 2007-02-17  Thiemo Seufer  <ths@mips.com>
  92
  93         * configure.ac (mips*-sde-elf*): Move in front of generic machine
  94         configuration.
  95         * configure: Regenerate.
  96
  97 2007-02-17  Thiemo Seufer  <ths@mips.com>
  98
  99         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 100         Add mdmx to sim_igen_machine.
 101         (mipsisa64*-*-*): Likewise. Remove dsp.
 102         (mipsisa32*-*-*): Remove dsp.
 103         * configure: Regenerate.
 104
 105 2007-02-13  Thiemo Seufer  <ths@mips.com>
 106
 107         * configure.ac: Add mips*-sde-elf* target.
 108         * configure: Regenerate.
 109
 110 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 111
 112         * acconfig.h: Remove.
 113         * config.in, configure: Regenerate.
 114
 115 2006-11-07  Thiemo Seufer  <ths@mips.com>
 116
 117         * dsp.igen (do_w_op): Fix compiler warning.
 118
 119 2006-08-29  Thiemo Seufer  <ths@mips.com>
 120             David Ung  <davidu@mips.com>
 121
 122         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 123         sim_igen_machine.
 124         * configure: Regenerate.
 125         * mips.igen (model): Add smartmips.
 126         (MADDU): Increment ACX if carry.
 127         (do_mult): Clear ACX.
 128         (ROR,RORV): Add smartmips.
 129         (include): Include smartmips.igen.
 130         * sim-main.h (ACX): Set to REGISTERS[89].
 131         * smartmips.igen: New file.
 132
 133 2006-08-29  Thiemo Seufer  <ths@mips.com>
 134             David Ung  <davidu@mips.com>
 135
 136         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 137         mips3264r2.igen. Add missing dependency rules.
 138         * m16e.igen: Support for mips16e save/restore instructions.
 139
 140 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 141
 142         * configure: Regenerated.
 143
 144 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 145
 146         * configure: Regenerated.
 147
 148 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 149
 150         * configure: Regenerated.
 151
 152 2006-05-15 Chao-ying Fu  <fu@mips.com>
 153
 154         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 155
 156 2006-04-18  Nick Clifton  <nickc@redhat.com>
 157
 158         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 159         statement.
 160
 161 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 162
 163         * configure: Regenerate.
 164
 165 2005-12-14  Chao-ying Fu  <fu@mips.com>
 166
 167         * Makefile.in (SIM_OBJS): Add dsp.o.
 168         (dsp.o): New dependency.
 169         (IGEN_INCLUDE): Add dsp.igen.
 170         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 171         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 172         * configure: Regenerate.
 173         * mips.igen: Add dsp model and include dsp.igen.
 174         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 175         because these instructions are extended in DSP ASE.
 176         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 177         adding 6 DSP accumulator registers and 1 DSP control register.
 178         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 179         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 180         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 181         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 182         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 183         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 184         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 185         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 186         DSPCR_CCOND_SMASK): New define.
 187         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 188         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 189
 190 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 191
 192         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 193
 194 2005-06-16  David Ung  <davidu@mips.com>
 195             Nigel Stephens  <nigel@mips.com>
 196
 197         * mips.igen: New mips16e model and include m16e.igen.
 198         (check_u64): Add mips16e tag.
 199         * m16e.igen: New file for MIPS16e instructions.
 200         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 201         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 202         models.
 203         * configure: Regenerate.
 204
 205 2005-05-26  David Ung  <davidu@mips.com>
 206
 207         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 208         tags to all instructions which are applicable to the new ISAs.
 209         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 210         vr.igen.
 211         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 212         instructions.
 213         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 214         to mips.igen.
 215         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 216         * configure: Regenerate.
 217
 218 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 219
 220         * configure: Regenerate.
 221
 222 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 223
 224         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 225         explicit call to AC_CONFIG_HEADER.
 226         * configure: Regenerate.
 227
 228 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 229
 230         * configure.ac: Update to use ../common/common.m4.
 231         * configure: Re-generate.
 232
 233 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 234
 235         * configure: Regenerated to track ../common/aclocal.m4 changes.
 236
 237 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 238
 239         * configure.ac: Rename configure.in, require autoconf 2.59.
 240         * configure: Re-generate.
 241
 242 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 243
 244         * configure: Regenerate for ../common/aclocal.m4 update.
 245
 246 2004-09-24  Monika Chaddha  <monika@acmet.com>
 247
 248         Committed by Andrew Cagney.
 249         * m16.igen (CMP, CMPI): Fix assembler.
 250
 251 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 252
 253         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 254         * configure: Regenerate.
 255
 256 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 257
 258         * configure.in (sim_m16_machine): Include mipsIII.
 259         * configure: Regenerate.
 260
 261 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 262
 263         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 264         from COP0_BADVADDR.
 265         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 266
 267 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 268
 269         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 270
 271 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 272
 273         * mips.igen (check_fmt): Remove.
 274         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 275         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 276         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 277         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 278         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 279         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 280         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 281         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 282         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 283         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 284
 285 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 286
 287         * sb1.igen (check_sbx): New function.
 288         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 289
 290 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 291             Richard Sandiford  <rsandifo@redhat.com>
 292
 293         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 294         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 295         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 296         separate implementations for mipsIV and mipsV.  Use new macros to
 297         determine whether the restrictions apply.
 298
 299 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 300
 301         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 302         (check_mult_hilo): Improve comments.
 303         (check_div_hilo): Likewise.  Also, fork off a new version
 304         to handle mips32/mips64 (since there are no hazards to check
 305         in MIPS32/MIPS64).
 306
 307 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 308
 309         * mips.igen (do_dmultx): Fix check for negative operands.
 310
 311 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 312
 313         * Makefile.in (SHELL): Make sure this is defined.
 314         (various): Use $(SHELL) whenever we invoke move-if-change.
 315
 316 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * cp1.c: Tweak attribution slightly.
 319         * cp1.h: Likewise.
 320         * mdmx.c: Likewise.
 321         * mdmx.igen: Likewise.
 322         * mips3d.igen: Likewise.
 323         * sb1.igen: Likewise.
 324
 325 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 326
 327         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 328         unsigned operands.
 329
 330 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 331
 332         * interp.c (sim_open): Rename _bfd to bfd.
 333         (sim_create_inferior): Ditto.
 334
 335 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 336
 337         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 338
 339 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 340
 341         * mips.igen (EI, DI): Remove.
 342
 343 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 344
 345         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 346
 347 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 348             Andrew Cagney  <ac131313@redhat.com>
 349             Gavin Romig-Koch  <gavin@redhat.com>
 350             Graydon Hoare  <graydon@redhat.com>
 351             Aldy Hernandez  <aldyh@redhat.com>
 352             Dave Brolley  <brolley@redhat.com>
 353             Chris Demetriou  <cgd@broadcom.com>
 354
 355         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 356         (sim_mach_default): New variable.
 357         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 358         Add a new simulator generator, MULTI.
 359         * configure: Regenerate.
 360         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 361         (multi-run.o): New dependency.
 362         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 363         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 364         (tmp-multi): Combine them.
 365         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 366         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 367         (distclean-extra): New rule.
 368         * sim-main.h: Include bfd.h.
 369         (MIPS_MACH): New macro.
 370         * mips.igen (vr4120, vr5400, vr5500): New models.
 371         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 372         * vr.igen: Replace with new version.
 373
 374 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 375
 376         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 377         * configure: Regenerate.
 378
 379 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 380
 381         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 382         * mips.igen: Remove all invocations of check_branch_bug and
 383         mark_branch_bug.
 384
 385 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 386
 387         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 388
 389 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 390
 391         * mips.igen (do_load_double, do_store_double): New functions.
 392         (LDC1, SDC1): Rename to...
 393         (LDC1b, SDC1b): respectively.
 394         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 395
 396 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 397
 398         * cp1.c (fp_recip2): Modify initialization expression so that
 399         GCC will recognize it as constant.
 400
 401 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 402
 403         * mdmx.c (SD_): Delete.
 404         (Unpredictable): Re-define, for now, to directly invoke
 405         unpredictable_action().
 406         (mdmx_acc_op): Fix error in .ob immediate handling.
 407
 408 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 409
 410         * interp.c (sim_firmware_command): Initialize `address'.
 411
 412 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 413
 414         * configure: Regenerated to track ../common/aclocal.m4 changes.
 415
 416 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 417             Ed Satterthwaite  <ehs@broadcom.com>
 418
 419         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 420         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 421         * mips.igen: Include mips3d.igen.
 422         (mips3d): New model name for MIPS-3D ASE instructions.
 423         (CVT.W.fmt): Don't use this instruction for word (source) format
 424         instructions.
 425         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 426         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 427         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 428         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 429         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 430         (RSquareRoot1, RSquareRoot2): New macros.
 431         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 432         (fp_rsqrt2): New functions.
 433         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 434         * configure: Regenerate.
 435
 436 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 437             Ed Satterthwaite  <ehs@broadcom.com>
 438
 439         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 440         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 441         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 442         (convert): Note that this function is not used for paired-single
 443         format conversions.
 444         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 445         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 446         (check_fmt_p): Enable paired-single support.
 447         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 448         (PUU.PS): New instructions.
 449         (CVT.S.fmt): Don't use this instruction for paired-single format
 450         destinations.
 451         * sim-main.h (FP_formats): New value 'fmt_ps.'
 452         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 453         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 454
 455 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 456
 457         * mips.igen: Fix formatting of function calls in
 458         many FP operations.
 459
 460 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 461
 462         * mips.igen (MOVN, MOVZ): Trace result.
 463         (TNEI): Print "tnei" as the opcode name in traces.
 464         (CEIL.W): Add disassembly string for traces.
 465         (RSQRT.fmt): Make location of disassembly string consistent
 466         with other instructions.
 467
 468 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 469
 470         * mips.igen (X): Delete unused function.
 471
 472 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 473
 474         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 475
 476 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 477             Ed Satterthwaite  <ehs@broadcom.com>
 478
 479         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 480         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 481         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 482         (fp_nmsub): New prototypes.
 483         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 484         (NegMultiplySub): New defines.
 485         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 486         (MADD.D, MADD.S): Replace with...
 487         (MADD.fmt): New instruction.
 488         (MSUB.D, MSUB.S): Replace with...
 489         (MSUB.fmt): New instruction.
 490         (NMADD.D, NMADD.S): Replace with...
 491         (NMADD.fmt): New instruction.
 492         (NMSUB.D, MSUB.S): Replace with...
 493         (NMSUB.fmt): New instruction.
 494
 495 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 496             Ed Satterthwaite  <ehs@broadcom.com>
 497
 498         * cp1.c: Fix more comment spelling and formatting.
 499         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 500         (denorm_mode): New function.
 501         (fpu_unary, fpu_binary): Round results after operation, collect
 502         status from rounding operations, and update the FCSR.
 503         (convert): Collect status from integer conversions and rounding
 504         operations, and update the FCSR.  Adjust NaN values that result
 505         from conversions.  Convert to use sim_io_eprintf rather than
 506         fprintf, and remove some debugging code.
 507         * cp1.h (fenr_FS): New define.
 508
 509 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 510
 511         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 512         rounding mode to sim FP rounding mode flag conversion code into...
 513         (rounding_mode): New function.
 514
 515 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 516
 517         * cp1.c: Clean up formatting of a few comments.
 518         (value_fpr): Reformat switch statement.
 519
 520 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 521             Ed Satterthwaite  <ehs@broadcom.com>
 522
 523         * cp1.h: New file.
 524         * sim-main.h: Include cp1.h.
 525         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 526         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 527         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 528         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 529         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 530         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 531         * cp1.c: Don't include sim-fpu.h; already included by
 532         sim-main.h.  Clean up formatting of some comments.
 533         (NaN, Equal, Less): Remove.
 534         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 535         (fp_cmp): New functions.
 536         * mips.igen (do_c_cond_fmt): Remove.
 537         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 538         Compare.  Add result tracing.
 539         (CxC1): Remove, replace with...
 540         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 541         (DMxC1): Remove, replace with...
 542         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 543         (MxC1): Remove, replace with...
 544         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 545
 546 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 547
 548         * sim-main.h (FGRIDX): Remove, replace all uses with...
 549         (FGR_BASE): New macro.
 550         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 551         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 552         (NR_FGR, FGR): Likewise.
 553         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 554         * mips.igen: Likewise.
 555
 556 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 557
 558         * cp1.c: Add an FSF Copyright notice to this file.
 559
 560 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 561             Ed Satterthwaite  <ehs@broadcom.com>
 562
 563         * cp1.c (Infinity): Remove.
 564         * sim-main.h (Infinity): Likewise.
 565
 566         * cp1.c (fp_unary, fp_binary): New functions.
 567         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 568         (fp_sqrt): New functions, implemented in terms of the above.
 569         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 570         (Recip, SquareRoot): Remove (replaced by functions above).
 571         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 572         (fp_recip, fp_sqrt): New prototypes.
 573         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 574         (Recip, SquareRoot): Replace prototypes with #defines which
 575         invoke the functions above.
 576
 577 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 578
 579         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 580         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 581         file, remove PARAMS from prototypes.
 582         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 583         simulator state arguments.
 584         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 585         pass simulator state arguments.
 586         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 587         (store_fpr, convert): Remove 'sd' argument.
 588         (value_fpr): Likewise.  Convert to use 'SD' instead.
 589
 590 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 591
 592         * cp1.c (Min, Max): Remove #if 0'd functions.
 593         * sim-main.h (Min, Max): Remove.
 594
 595 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 596
 597         * cp1.c: fix formatting of switch case and default labels.
 598         * interp.c: Likewise.
 599         * sim-main.c: Likewise.
 600
 601 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 602
 603         * cp1.c: Clean up comments which describe FP formats.
 604          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 605
 606 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 607             Ed Satterthwaite  <ehs@broadcom.com>
 608
 609         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 610         Broadcom SiByte SB-1 processor configurations.
 611         * configure: Regenerate.
 612         * sb1.igen: New file.
 613         * mips.igen: Include sb1.igen.
 614         (sb1): New model.
 615         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 616         * mdmx.igen: Add "sb1" model to all appropriate functions and
 617         instructions.
 618         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 619         (ob_func, ob_acc): Reference the above.
 620         (qh_acc): Adjust to keep the same size as ob_acc.
 621         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 622         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 623
 624 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 625
 626         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 627
 628 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 629             Ed Satterthwaite  <ehs@broadcom.com>
 630
 631         * mips.igen (mdmx): New (pseudo-)model.
 632         * mdmx.c, mdmx.igen: New files.
 633         * Makefile.in (SIM_OBJS): Add mdmx.o.
 634         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 635         New typedefs.
 636         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 637         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 638         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 639         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 640         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 641         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 642         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 643         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 644         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 645         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 646         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 647         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 648         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 649         (qh_fmtsel): New macros.
 650         (_sim_cpu): New member "acc".
 651         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 652         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 653
 654 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 655
 656         * interp.c: Use 'deprecated' rather than 'depreciated.'
 657         * sim-main.h: Likewise.
 658
 659 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 660
 661         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 662         which wouldn't compile anyway.
 663         * sim-main.h (unpredictable_action): New function prototype.
 664         (Unpredictable): Define to call igen function unpredictable().
 665         (NotWordValue): New macro to call igen function not_word_value().
 666         (UndefinedResult): Remove.
 667         * interp.c (undefined_result): Remove.
 668         (unpredictable_action): New function.
 669         * mips.igen (not_word_value, unpredictable): New functions.
 670         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 671         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 672         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 673         NotWordValue() to check for unpredictable inputs, then
 674         Unpredictable() to handle them.
 675
 676 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 677
 678         * mips.igen: Fix formatting of calls to Unpredictable().
 679
 680 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 681
 682         * interp.c (sim_open): Revert previous change.
 683
 684 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 685
 686         * interp.c (sim_open): Disable chunk of code that wrote code in
 687         vector table entries.
 688
 689 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 690
 691         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 692         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 693         unused definitions.
 694
 695 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 696
 697         * cp1.c: Fix many formatting issues.
 698
 699 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 700
 701         * cp1.c (fpu_format_name): New function to replace...
 702         (DOFMT): This.  Delete, and update all callers.
 703         (fpu_rounding_mode_name): New function to replace...
 704         (RMMODE): This.  Delete, and update all callers.
 705
 706 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 707
 708         * interp.c: Move FPU support routines from here to...
 709         * cp1.c: Here.  New file.
 710         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 711         (cp1.o): New target.
 712
 713 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 714
 715         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 716         * mips.igen (mips32, mips64): New models, add to all instructions
 717         and functions as appropriate.
 718         (loadstore_ea, check_u64): New variant for model mips64.
 719         (check_fmt_p): New variant for models mipsV and mips64, remove
 720         mipsV model marking fro other variant.
 721         (SLL) Rename to...
 722         (SLLa) this.
 723         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 724         for mips32 and mips64.
 725         (DCLO, DCLZ): New instructions for mips64.
 726
 727 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 728
 729         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 730         immediate or code as a hex value with the "%#lx" format.
 731         (ANDI): Likewise, and fix printed instruction name.
 732
 733 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 734
 735         * sim-main.h (UndefinedResult, Unpredictable): New macros
 736         which currently do nothing.
 737
 738 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 739
 740         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 741         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 742         (status_CU3): New definitions.
 743
 744         * sim-main.h (ExceptionCause): Add new values for MIPS32
 745         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 746         for DebugBreakPoint and NMIReset to note their status in
 747         MIPS32 and MIPS64.
 748         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 749         (SignalExceptionCacheErr): New exception macros.
 750
 751 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 752
 753         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 754         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 755         is always enabled.
 756         (SignalExceptionCoProcessorUnusable): Take as argument the
 757         unusable coprocessor number.
 758
 759 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 760
 761         * mips.igen: Fix formatting of all SignalException calls.
 762
 763 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 764
 765         * sim-main.h (SIGNEXTEND): Remove.
 766
 767 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 768
 769         * mips.igen: Remove gencode comment from top of file, fix
 770         spelling in another comment.
 771
 772 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 773
 774         * mips.igen (check_fmt, check_fmt_p): New functions to check
 775         whether specific floating point formats are usable.
 776         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 777         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 778         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 779         Use the new functions.
 780         (do_c_cond_fmt): Remove format checks...
 781         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 782
 783 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 784
 785         * mips.igen: Fix formatting of check_fpu calls.
 786
 787 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 788
 789         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 790
 791 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 792
 793         * mips.igen: Remove whitespace at end of lines.
 794
 795 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 796
 797         * mips.igen (loadstore_ea): New function to do effective
 798         address calculations.
 799         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 800         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 801         CACHE): Use loadstore_ea to do effective address computations.
 802
 803 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 804
 805         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 806         * mips.igen (LL, CxC1, MxC1): Likewise.
 807
 808 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 809
 810         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 811         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 812         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 813         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 814         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 815         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 816         Don't split opcode fields by hand, use the opcode field values
 817         provided by igen.
 818
 819 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 820
 821         * mips.igen (do_divu): Fix spacing.
 822
 823         * mips.igen (do_dsllv): Move to be right before DSLLV,
 824         to match the rest of the do_<shift> functions.
 825
 826 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 827
 828         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 829         DSRL32, do_dsrlv): Trace inputs and results.
 830
 831 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 832
 833         * mips.igen (CACHE): Provide instruction-printing string.
 834
 835         * interp.c (signal_exception): Comment tokens after #endif.
 836
 837 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 838
 839         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 840         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 841         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 842         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 843         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 844         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 845         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 846         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 847
 848 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 849
 850         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 851         instruction-printing string.
 852         (LWU): Use '64' as the filter flag.
 853
 854 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 855
 856         * mips.igen (SDXC1): Fix instruction-printing string.
 857
 858 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 859
 860         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 861         filter flags "32,f".
 862
 863 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 864
 865         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 866         as the filter flag.
 867
 868 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 869
 870         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 871         add a comma) so that it more closely match the MIPS ISA
 872         documentation opcode partitioning.
 873         (PREF): Put useful names on opcode fields, and include
 874         instruction-printing string.
 875
 876 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 877
 878         * mips.igen (check_u64): New function which in the future will
 879         check whether 64-bit instructions are usable and signal an
 880         exception if not.  Currently a no-op.
 881         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 882         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 883         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 884         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 885
 886         * mips.igen (check_fpu): New function which in the future will
 887         check whether FPU instructions are usable and signal an exception
 888         if not.  Currently a no-op.
 889         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 890         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 891         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 892         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 893         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 894         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 895         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 896         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 897
 898 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 899
 900         * mips.igen (do_load_left, do_load_right): Move to be immediately
 901         following do_load.
 902         (do_store_left, do_store_right): Move to be immediately following
 903         do_store.
 904
 905 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 906
 907         * mips.igen (mipsV): New model name.  Also, add it to
 908         all instructions and functions where it is appropriate.
 909
 910 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 911
 912         * mips.igen: For all functions and instructions, list model
 913         names that support that instruction one per line.
 914
 915 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 916
 917         * mips.igen: Add some additional comments about supported
 918         models, and about which instructions go where.
 919         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 920         order as is used in the rest of the file.
 921
 922 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 923
 924         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 925         indicating that ALU32_END or ALU64_END are there to check
 926         for overflow.
 927         (DADD): Likewise, but also remove previous comment about
 928         overflow checking.
 929
 930 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 931
 932         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 933         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 934         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 935         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 936         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 937         fields (i.e., add and move commas) so that they more closely
 938         match the MIPS ISA documentation opcode partitioning.
 939
 940 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 941
 942         * mips.igen (ADDI): Print immediate value.
 943         (BREAK): Print code.
 944         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 945         (SLL): Print "nop" specially, and don't run the code
 946         that does the shift for the "nop" case.
 947
 948 2001-11-17  Fred Fish  <fnf@redhat.com>
 949
 950         * sim-main.h (float_operation): Move enum declaration outside
 951         of _sim_cpu struct declaration.
 952
 953 2001-04-12  Jim Blandy  <jimb@redhat.com>
 954
 955         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 956         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 957         set of the FCSR.
 958         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 959         PENDING_FILL, and you can get the intended effect gracefully by
 960         calling PENDING_SCHED directly.
 961
 962 2001-02-23  Ben Elliston  <bje@redhat.com>
 963
 964         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 965         already defined elsewhere.
 966
 967 2001-02-19  Ben Elliston  <bje@redhat.com>
 968
 969         * sim-main.h (sim_monitor): Return an int.
 970         * interp.c (sim_monitor): Add return values.
 971         (signal_exception): Handle error conditions from sim_monitor.
 972
 973 2001-02-08  Ben Elliston  <bje@redhat.com>
 974
 975         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 976         (store_memory): Likewise, pass cia to sim_core_write*.
 977
 978 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 979
 980         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 981         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 982
 983 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 984
 985         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 986         * Makefile.in: Don't delete *.igen when cleaning directory.
 987
 988 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 989
 990         * m16.igen (break): Call SignalException not sim_engine_halt.
 991
 992 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 993
 994         From Jason Eckhardt:
 995         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 996
 997 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 998
 999         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1000
1001 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1002
1003         * mips.igen (do_dmultx): Fix typo.
1004
1005 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1006
1007         * configure: Regenerated to track ../common/aclocal.m4 changes.
1008
1009 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1010
1011         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1012
1013 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1014
1015         * sim-main.h (GPR_CLEAR): Define macro.
1016
1017 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1018
1019         * interp.c (decode_coproc): Output long using %lx and not %s.
1020
1021 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1022
1023         * interp.c (sim_open): Sort & extend dummy memory regions for
1024         --board=jmr3904 for eCos.
1025
1026 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1027
1028         * configure: Regenerated.
1029
1030 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1031
1032         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1033         calls, conditional on the simulator being in verbose mode.
1034
1035 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1036
1037         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1038         cache don't get ReservedInstruction traps.
1039
1040 1999-11-29  Mark Salter  <msalter@cygnus.com>
1041
1042         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1043         to clear status bits in sdisr register. This is how the hardware works.
1044
1045         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1046         being used by cygmon.
1047
1048 1999-11-11  Andrew Haley  <aph@cygnus.com>
1049
1050         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1051         instructions.
1052
1053 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1054
1055         * mips.igen (MULT): Correct previous mis-applied patch.
1056
1057 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1058
1059         * mips.igen (delayslot32): Handle sequence like
1060         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1061         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1062         (MULT): Actually pass the third register...
1063
1064 1999-09-03  Mark Salter  <msalter@cygnus.com>
1065
1066         * interp.c (sim_open): Added more memory aliases for additional
1067         hardware being touched by cygmon on jmr3904 board.
1068
1069 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1070
1071         * configure: Regenerated to track ../common/aclocal.m4 changes.
1072
1073 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1074
1075         * interp.c (sim_store_register): Handle case where client - GDB -
1076         specifies that a 4 byte register is 8 bytes in size.
1077         (sim_fetch_register): Ditto.
1078
1079 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1080
1081         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1082         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1083         (idt_monitor_base): Base address for IDT monitor traps.
1084         (pmon_monitor_base): Ditto for PMON.
1085         (lsipmon_monitor_base): Ditto for LSI PMON.
1086         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1087         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1088         (sim_firmware_command): New function.
1089         (mips_option_handler): Call it for OPTION_FIRMWARE.
1090         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1091         option was given, add no monitor by default.  Add BREAK hooks only if
1092         monitors are also there.
1093
1094 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1095
1096         * interp.c (sim_monitor): Flush output before reading input.
1097
1098 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1099
1100         * tconfig.in (SIM_HANDLES_LMA): Always define.
1101
1102 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         From Mark Salter <msalter@cygnus.com>:
1105         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1106         (sim_open): Add setup for BSP board.
1107
1108 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1111         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1112         them as unimplemented.
1113
1114 1999-05-08  Felix Lee  <flee@cygnus.com>
1115
1116         * configure: Regenerated to track ../common/aclocal.m4 changes.
1117
1118 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1119
1120         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1121
1122 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1123
1124         * configure.in: Any mips64vr5*-*-* target should have
1125         -DTARGET_ENABLE_FR=1.
1126         (default_endian): Any mips64vr*el-*-* target should default to
1127         LITTLE_ENDIAN.
1128         * configure: Re-generate.
1129
1130 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1131
1132         * mips.igen (ldl): Extend from _16_, not 32.
1133
1134 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1135
1136         * interp.c (sim_store_register): Force registers written to by GDB
1137         into an un-interpreted state.
1138
1139 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1140
1141         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1142         CPU, start periodic background I/O polls.
1143         (tx3904sio_poll): New function: periodic I/O poller.
1144
1145 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1146
1147         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1148
1149 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1150
1151         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1152         case statement.
1153
1154 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1155
1156         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1157         (load_word): Call SIM_CORE_SIGNAL hook on error.
1158         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1159         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1160         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1161         * sim-main.h (COP0_BADVADDR): Define.
1162         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1163         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1164         (_sim_cpu): Add exc_* fields to store register value snapshots.
1165         * mips.igen (*): Replace memory-related SignalException* calls
1166         with references to SIM_CORE_SIGNAL hook.
1167
1168         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1169         fix.
1170         * sim-main.c (*): Minor warning cleanups.
1171
1172 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1173
1174         * m16.igen (DADDIU5): Correct type-o.
1175
1176 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1177
1178         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1179         variables.
1180
1181 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1182
1183         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1184         to include path.
1185         (interp.o): Add dependency on itable.h
1186         (oengine.c, gencode): Delete remaining references.
1187         (BUILT_SRC_FROM_GEN): Clean up.
1188
1189 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1190
1191         * vr4run.c: New.
1192         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1193         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1194         tmp-run-hack) : New.
1195         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1196         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1197         Drop the "64" qualifier to get the HACK generator working.
1198         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1199         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1200         qualifier to get the hack generator working.
1201         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1202         (DSLL): Use do_dsll.
1203         (DSLLV): Use do_dsllv.
1204         (DSRA): Use do_dsra.
1205         (DSRL): Use do_dsrl.
1206         (DSRLV): Use do_dsrlv.
1207         (BC1): Move *vr4100 to get the HACK generator working.
1208         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1209         get the HACK generator working.
1210         (MACC) Rename to get the HACK generator working.
1211         (DMACC,MACCS,DMACCS): Add the 64.
1212
1213 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1214
1215         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1216         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1217
1218 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1219
1220     * mips/interp.c (DEBUG): Cleanups.
1221
1222 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1223
1224         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1225         (tx3904sio_tickle): fflush after a stdout character output.
1226
1227 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1228
1229         * interp.c (sim_close): Uninstall modules.
1230
1231 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1232
1233         * sim-main.h, interp.c (sim_monitor): Change to global
1234         function.
1235
1236 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * configure.in (vr4100): Only include vr4100 instructions in
1239         simulator.
1240         * configure: Re-generate.
1241         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1242
1243 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1244
1245         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1246         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1247         true alternative.
1248
1249         * configure.in (sim_default_gen, sim_use_gen): Replace with
1250         sim_gen.
1251         (--enable-sim-igen): Delete config option. Always using IGEN.
1252         * configure: Re-generate.
1253
1254         * Makefile.in (gencode): Kill, kill, kill.
1255         * gencode.c: Ditto.
1256
1257 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1258
1259         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1260         bit mips16 igen simulator.
1261         * configure: Re-generate.
1262
1263         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1264         as part of vr4100 ISA.
1265         * vr.igen: Mark all instructions as 64 bit only.
1266
1267 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1268
1269         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1270         Pacify GCC.
1271
1272 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1273
1274         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1275         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1276         * configure: Re-generate.
1277
1278         * m16.igen (BREAK): Define breakpoint instruction.
1279         (JALX32): Mark instruction as mips16 and not r3900.
1280         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1281
1282         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1283
1284 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1285
1286         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1287         insn as a debug breakpoint.
1288
1289         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1290         pending.slot_size.
1291         (PENDING_SCHED): Clean up trace statement.
1292         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1293         (PENDING_FILL): Delay write by only one cycle.
1294         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1295
1296         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1297         of pending writes.
1298         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1299         32 & 64.
1300         (pending_tick): Move incrementing of index to FOR statement.
1301         (pending_tick): Only update PENDING_OUT after a write has occured.
1302
1303         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1304         build simulator.
1305         * configure: Re-generate.
1306
1307         * interp.c (sim_engine_run OLD): Delete explicit call to
1308         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1309
1310 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1311
1312         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1313         interrupt level number to match changed SignalExceptionInterrupt
1314         macro.
1315
1316 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1317
1318         * interp.c: #include "itable.h" if WITH_IGEN.
1319         (get_insn_name): New function.
1320         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1321         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1322
1323 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1324
1325         * configure: Rebuilt to inhale new common/aclocal.m4.
1326
1327 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1328
1329         * dv-tx3904sio.c: Include sim-assert.h.
1330
1331 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1332
1333         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1334         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1335         Reorganize target-specific sim-hardware checks.
1336         * configure: rebuilt.
1337         * interp.c (sim_open): For tx39 target boards, set
1338         OPERATING_ENVIRONMENT, add tx3904sio devices.
1339         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1340         ROM executables.  Install dv-sockser into sim-modules list.
1341
1342         * dv-tx3904irc.c: Compiler warning clean-up.
1343         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1344         frequent hw-trace messages.
1345
1346 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1347
1348         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1349
1350 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1351
1352         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1353
1354         * vr.igen: New file.
1355         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1356         * mips.igen: Define vr4100 model. Include vr.igen.
1357 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1358
1359         * mips.igen (check_mf_hilo): Correct check.
1360
1361 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1362
1363         * sim-main.h (interrupt_event): Add prototype.
1364
1365         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1366         register_ptr, register_value.
1367         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1368
1369         * sim-main.h (tracefh): Make extern.
1370
1371 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1372
1373         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1374         Reduce unnecessarily high timer event frequency.
1375         * dv-tx3904cpu.c: Ditto for interrupt event.
1376
1377 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1378
1379         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1380         to allay warnings.
1381         (interrupt_event): Made non-static.
1382
1383         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1384         interchange of configuration values for external vs. internal
1385         clock dividers.
1386
1387 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1388
1389         * mips.igen (BREAK): Moved code to here for
1390         simulator-reserved break instructions.
1391         * gencode.c (build_instruction): Ditto.
1392         * interp.c (signal_exception): Code moved from here.  Non-
1393         reserved instructions now use exception vector, rather
1394         than halting sim.
1395         * sim-main.h: Moved magic constants to here.
1396
1397 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1398
1399         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1400         register upon non-zero interrupt event level, clear upon zero
1401         event value.
1402         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1403         by passing zero event value.
1404         (*_io_{read,write}_buffer): Endianness fixes.
1405         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1406         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1407
1408         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1409         serial I/O and timer module at base address 0xFFFF0000.
1410
1411 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1412
1413         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1414         and BigEndianCPU.
1415
1416 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1417
1418         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1419         parts.
1420         * configure: Update.
1421
1422 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1423
1424         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1425         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1426         * configure.in: Include tx3904tmr in hw_device list.
1427         * configure: Rebuilt.
1428         * interp.c (sim_open): Instantiate three timer instances.
1429         Fix address typo of tx3904irc instance.
1430
1431 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1432
1433         * interp.c (signal_exception): SystemCall exception now uses
1434         the exception vector.
1435
1436 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1437
1438         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1439         to allay warnings.
1440
1441 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1442
1443         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1444
1445 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1446
1447         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1448
1449         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1450         sim-main.h. Declare a struct hw_descriptor instead of struct
1451         hw_device_descriptor.
1452
1453 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1454
1455         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1456         right bits and then re-align left hand bytes to correct byte
1457         lanes.  Fix incorrect computation in do_store_left when loading
1458         bytes from second word.
1459
1460 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1461
1462         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1463         * interp.c (sim_open): Only create a device tree when HW is
1464         enabled.
1465
1466         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1467         * interp.c (signal_exception): Ditto.
1468
1469 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1470
1471         * gencode.c: Mark BEGEZALL as LIKELY.
1472
1473 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1474
1475         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1476         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1477
1478 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1479
1480         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1481         modules.  Recognize TX39 target with "mips*tx39" pattern.
1482         * configure: Rebuilt.
1483         * sim-main.h (*): Added many macros defining bits in
1484         TX39 control registers.
1485         (SignalInterrupt): Send actual PC instead of NULL.
1486         (SignalNMIReset): New exception type.
1487         * interp.c (board): New variable for future use to identify
1488         a particular board being simulated.
1489         (mips_option_handler,mips_options): Added "--board" option.
1490         (interrupt_event): Send actual PC.
1491         (sim_open): Make memory layout conditional on board setting.
1492         (signal_exception): Initial implementation of hardware interrupt
1493         handling.  Accept another break instruction variant for simulator
1494         exit.
1495         (decode_coproc): Implement RFE instruction for TX39.
1496         (mips.igen): Decode RFE instruction as such.
1497         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1498         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1499         bbegin to implement memory map.
1500         * dv-tx3904cpu.c: New file.
1501         * dv-tx3904irc.c: New file.
1502
1503 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1504
1505         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1506
1507 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1508
1509         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1510         with calls to check_div_hilo.
1511
1512 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1513
1514         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1515         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1516         Add special r3900 version of do_mult_hilo.
1517         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1518         with calls to check_mult_hilo.
1519         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1520         with calls to check_div_hilo.
1521
1522 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1523
1524         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1525         Document a replacement.
1526
1527 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1528
1529         * interp.c (sim_monitor): Make mon_printf work.
1530
1531 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1532
1533         * sim-main.h (INSN_NAME): New arg `cpu'.
1534
1535 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1536
1537         * configure: Regenerated to track ../common/aclocal.m4 changes.
1538
1539 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1540
1541         * configure: Regenerated to track ../common/aclocal.m4 changes.
1542         * config.in: Ditto.
1543
1544 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1545
1546         * acconfig.h: New file.
1547         * configure.in: Reverted change of Apr 24; use sinclude again.
1548
1549 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1550
1551         * configure: Regenerated to track ../common/aclocal.m4 changes.
1552         * config.in: Ditto.
1553
1554 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1555
1556         * configure.in: Don't call sinclude.
1557
1558 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1559
1560         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1561
1562 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1563
1564         * mips.igen (ERET): Implement.
1565
1566         * interp.c (decode_coproc): Return sign-extended EPC.
1567
1568         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1569
1570         * interp.c (signal_exception): Do not ignore Trap.
1571         (signal_exception): On TRAP, restart at exception address.
1572         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1573         (signal_exception): Update.
1574         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1575         so that TRAP instructions are caught.
1576
1577 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1578
1579         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1580         contains HI/LO access history.
1581         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1582         (HIACCESS, LOACCESS): Delete, replace with
1583         (HIHISTORY, LOHISTORY): New macros.
1584         (CHECKHILO): Delete all, moved to mips.igen
1585
1586         * gencode.c (build_instruction): Do not generate checks for
1587         correct HI/LO register usage.
1588
1589         * interp.c (old_engine_run): Delete checks for correct HI/LO
1590         register usage.
1591
1592         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1593         check_mf_cycles): New functions.
1594         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1595         do_divu, domultx, do_mult, do_multu): Use.
1596
1597         * tx.igen ("madd", "maddu"): Use.
1598
1599 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1600
1601         * mips.igen (DSRAV): Use function do_dsrav.
1602         (SRAV): Use new function do_srav.
1603
1604         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1605         (B): Sign extend 11 bit immediate.
1606         (EXT-B*): Shift 16 bit immediate left by 1.
1607         (ADDIU*): Don't sign extend immediate value.
1608
1609 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1610
1611         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1612
1613         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1614         functions.
1615
1616         * mips.igen (delayslot32, nullify_next_insn): New functions.
1617         (m16.igen): Always include.
1618         (do_*): Add more tracing.
1619
1620         * m16.igen (delayslot16): Add NIA argument, could be called by a
1621         32 bit MIPS16 instruction.
1622
1623         * interp.c (ifetch16): Move function from here.
1624         * sim-main.c (ifetch16): To here.
1625
1626         * sim-main.c (ifetch16, ifetch32): Update to match current
1627         implementations of LH, LW.
1628         (signal_exception): Don't print out incorrect hex value of illegal
1629         instruction.
1630
1631 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1632
1633         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1634         instruction.
1635
1636         * m16.igen: Implement MIPS16 instructions.
1637
1638         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1639         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1640         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1641         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1642         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1643         bodies of corresponding code from 32 bit insn to these.  Also used
1644         by MIPS16 versions of functions.
1645
1646         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1647         (IMEM16): Drop NR argument from macro.
1648
1649 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * Makefile.in (SIM_OBJS): Add sim-main.o.
1652
1653         * sim-main.h (address_translation, load_memory, store_memory,
1654         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1655         as INLINE_SIM_MAIN.
1656         (pr_addr, pr_uword64): Declare.
1657         (sim-main.c): Include when H_REVEALS_MODULE_P.
1658
1659         * interp.c (address_translation, load_memory, store_memory,
1660         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1661         from here.
1662         * sim-main.c: To here. Fix compilation problems.
1663
1664         * configure.in: Enable inlining.
1665         * configure: Re-config.
1666
1667 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1668
1669         * configure: Regenerated to track ../common/aclocal.m4 changes.
1670
1671 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1672
1673         * mips.igen: Include tx.igen.
1674         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1675         * tx.igen: New file, contains MADD and MADDU.
1676
1677         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1678         the hardwired constant `7'.
1679         (store_memory): Ditto.
1680         (LOADDRMASK): Move definition to sim-main.h.
1681
1682         mips.igen (MTC0): Enable for r3900.
1683         (ADDU): Add trace.
1684
1685         mips.igen (do_load_byte): Delete.
1686         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1687         do_store_right): New functions.
1688         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1689
1690         configure.in: Let the tx39 use igen again.
1691         configure: Update.
1692
1693 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1694
1695         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1696         not an address sized quantity.  Return zero for cache sizes.
1697
1698 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1699
1700         * mips.igen (r3900): r3900 does not support 64 bit integer
1701         operations.
1702
1703 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1704
1705         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1706         than igen one.
1707         * configure : Rebuild.
1708
1709 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1710
1711         * configure: Regenerated to track ../common/aclocal.m4 changes.
1712
1713 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1714
1715         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1716
1717 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1718
1719         * configure: Regenerated to track ../common/aclocal.m4 changes.
1720         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1721
1722 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1723
1724         * configure: Regenerated to track ../common/aclocal.m4 changes.
1725
1726 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1727
1728         * interp.c (Max, Min): Comment out functions. Not yet used.
1729
1730 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1731
1732         * configure: Regenerated to track ../common/aclocal.m4 changes.
1733
1734 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1735
1736         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1737         configurable settings for stand-alone simulator.
1738
1739         * configure.in: Added X11 search, just in case.
1740
1741         * configure: Regenerated.
1742
1743 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1744
1745         * interp.c (sim_write, sim_read, load_memory, store_memory):
1746         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1747
1748 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1749
1750         * sim-main.h (GETFCC): Return an unsigned value.
1751
1752 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1753
1754         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1755         (DADD): Result destination is RD not RT.
1756
1757 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1758
1759         * sim-main.h (HIACCESS, LOACCESS): Always define.
1760
1761         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1762
1763         * interp.c (sim_info): Delete.
1764
1765 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1766
1767         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1768         (mips_option_handler): New argument `cpu'.
1769         (sim_open): Update call to sim_add_option_table.
1770
1771 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1772
1773         * mips.igen (CxC1): Add tracing.
1774
1775 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * sim-main.h (Max, Min): Declare.
1778
1779         * interp.c (Max, Min): New functions.
1780
1781         * mips.igen (BC1): Add tracing.
1782
1783 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1784
1785         * interp.c Added memory map for stack in vr4100
1786
1787 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1788
1789         * interp.c (load_memory): Add missing "break"'s.
1790
1791 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1792
1793         * interp.c (sim_store_register, sim_fetch_register): Pass in
1794         length parameter.  Return -1.
1795
1796 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1797
1798         * interp.c: Added hardware init hook, fixed warnings.
1799
1800 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1801
1802         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1803
1804 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1805
1806         * interp.c (ifetch16): New function.
1807
1808         * sim-main.h (IMEM32): Rename IMEM.
1809         (IMEM16_IMMED): Define.
1810         (IMEM16): Define.
1811         (DELAY_SLOT): Update.
1812
1813         * m16run.c (sim_engine_run): New file.
1814
1815         * m16.igen: All instructions except LB.
1816         (LB): Call do_load_byte.
1817         * mips.igen (do_load_byte): New function.
1818         (LB): Call do_load_byte.
1819
1820         * mips.igen: Move spec for insn bit size and high bit from here.
1821         * Makefile.in (tmp-igen, tmp-m16): To here.
1822
1823         * m16.dc: New file, decode mips16 instructions.
1824
1825         * Makefile.in (SIM_NO_ALL): Define.
1826         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1827
1828 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1829
1830         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1831         point unit to 32 bit registers.
1832         * configure: Re-generate.
1833
1834 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * configure.in (sim_use_gen): Make IGEN the default simulator
1837         generator for generic 32 and 64 bit mips targets.
1838         * configure: Re-generate.
1839
1840 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1841
1842         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1843         bitsize.
1844
1845         * interp.c (sim_fetch_register, sim_store_register): Read/write
1846         FGR from correct location.
1847         (sim_open): Set size of FGR's according to
1848         WITH_TARGET_FLOATING_POINT_BITSIZE.
1849
1850         * sim-main.h (FGR): Store floating point registers in a separate
1851         array.
1852
1853 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1854
1855         * configure: Regenerated to track ../common/aclocal.m4 changes.
1856
1857 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1858
1859         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1860
1861         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1862
1863         * interp.c (pending_tick): New function.  Deliver pending writes.
1864
1865         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1866         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1867         it can handle mixed sized quantites and single bits.
1868
1869 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1870
1871         * interp.c (oengine.h): Do not include when building with IGEN.
1872         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1873         (sim_info): Ditto for PROCESSOR_64BIT.
1874         (sim_monitor): Replace ut_reg with unsigned_word.
1875         (*): Ditto for t_reg.
1876         (LOADDRMASK): Define.
1877         (sim_open): Remove defunct check that host FP is IEEE compliant,
1878         using software to emulate floating point.
1879         (value_fpr, ...): Always compile, was conditional on HASFPU.
1880
1881 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1882
1883         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1884         size.
1885
1886         * interp.c (SD, CPU): Define.
1887         (mips_option_handler): Set flags in each CPU.
1888         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1889         (sim_close): Do not clear STATE, deleted anyway.
1890         (sim_write, sim_read): Assume CPU zero's vm should be used for
1891         data transfers.
1892         (sim_create_inferior): Set the PC for all processors.
1893         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1894         argument.
1895         (mips16_entry): Pass correct nr of args to store_word, load_word.
1896         (ColdReset): Cold reset all cpu's.
1897         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1898         (sim_monitor, load_memory, store_memory, signal_exception): Use
1899         `CPU' instead of STATE_CPU.
1900
1901
1902         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1903         SD or CPU_.
1904
1905         * sim-main.h (signal_exception): Add sim_cpu arg.
1906         (SignalException*): Pass both SD and CPU to signal_exception.
1907         * interp.c (signal_exception): Update.
1908
1909         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1910         Ditto
1911         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1912         address_translation): Ditto
1913         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1914
1915 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1916
1917         * configure: Regenerated to track ../common/aclocal.m4 changes.
1918
1919 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1920
1921         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1922
1923         * mips.igen (model): Map processor names onto BFD name.
1924
1925         * sim-main.h (CPU_CIA): Delete.
1926         (SET_CIA, GET_CIA): Define
1927
1928 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1929
1930         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1931         regiser.
1932
1933         * configure.in (default_endian): Configure a big-endian simulator
1934         by default.
1935         * configure: Re-generate.
1936
1937 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1938
1939         * configure: Regenerated to track ../common/aclocal.m4 changes.
1940
1941 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1942
1943         * interp.c (sim_monitor): Handle Densan monitor outbyte
1944         and inbyte functions.
1945
1946 1997-12-29  Felix Lee  <flee@cygnus.com>
1947
1948         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1949
1950 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1951
1952         * Makefile.in (tmp-igen): Arrange for $zero to always be
1953         reset to zero after every instruction.
1954
1955 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1956
1957         * configure: Regenerated to track ../common/aclocal.m4 changes.
1958         * config.in: Ditto.
1959
1960 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1961
1962         * mips.igen (MSUB): Fix to work like MADD.
1963         * gencode.c (MSUB): Similarly.
1964
1965 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1966
1967         * configure: Regenerated to track ../common/aclocal.m4 changes.
1968
1969 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1970
1971         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1972
1973 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1974
1975         * sim-main.h (sim-fpu.h): Include.
1976
1977         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1978         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1979         using host independant sim_fpu module.
1980
1981 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1982
1983         * interp.c (signal_exception): Report internal errors with SIGABRT
1984         not SIGQUIT.
1985
1986         * sim-main.h (C0_CONFIG): New register.
1987         (signal.h): No longer include.
1988
1989         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1990
1991 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1992
1993         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1994
1995 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1996
1997         * mips.igen: Tag vr5000 instructions.
1998         (ANDI): Was missing mipsIV model, fix assembler syntax.
1999         (do_c_cond_fmt): New function.
2000         (C.cond.fmt): Handle mips I-III which do not support CC field
2001         separatly.
2002         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2003         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2004         in IV3.2 spec.
2005         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2006         vr5000 which saves LO in a GPR separatly.
2007
2008         * configure.in (enable-sim-igen): For vr5000, select vr5000
2009         specific instructions.
2010         * configure: Re-generate.
2011
2012 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2013
2014         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2015
2016         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2017         fmt_uninterpreted_64 bit cases to switch.  Convert to
2018         fmt_formatted,
2019
2020         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2021
2022         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2023         as specified in IV3.2 spec.
2024         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2025
2026 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2027
2028         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2029         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2030         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2031         PENDING_FILL versions of instructions.  Simplify.
2032         (X): New function.
2033         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2034         instructions.
2035         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2036         a signed value.
2037         (MTHI, MFHI): Disable code checking HI-LO.
2038
2039         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2040         global.
2041         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2042
2043 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2044
2045         * gencode.c (build_mips16_operands): Replace IPC with cia.
2046
2047         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2048         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2049         IPC to `cia'.
2050         (UndefinedResult): Replace function with macro/function
2051         combination.
2052         (sim_engine_run): Don't save PC in IPC.
2053
2054         * sim-main.h (IPC): Delete.
2055
2056
2057         * interp.c (signal_exception, store_word, load_word,
2058         address_translation, load_memory, store_memory, cache_op,
2059         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2060         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2061         current instruction address - cia - argument.
2062         (sim_read, sim_write): Call address_translation directly.
2063         (sim_engine_run): Rename variable vaddr to cia.
2064         (signal_exception): Pass cia to sim_monitor
2065
2066         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2067         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2068         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2069
2070         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2071         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2072         SIM_ASSERT.
2073
2074         * interp.c (signal_exception): Pass restart address to
2075         sim_engine_restart.
2076
2077         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2078         idecode.o): Add dependency.
2079
2080         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2081         Delete definitions
2082         (DELAY_SLOT): Update NIA not PC with branch address.
2083         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2084
2085         * mips.igen: Use CIA not PC in branch calculations.
2086         (illegal): Call SignalException.
2087         (BEQ, ADDIU): Fix assembler.
2088
2089 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2090
2091         * m16.igen (JALX): Was missing.
2092
2093         * configure.in (enable-sim-igen): New configuration option.
2094         * configure: Re-generate.
2095
2096         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2097
2098         * interp.c (load_memory, store_memory): Delete parameter RAW.
2099         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2100         bypassing {load,store}_memory.
2101
2102         * sim-main.h (ByteSwapMem): Delete definition.
2103
2104         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2105
2106         * interp.c (sim_do_command, sim_commands): Delete mips specific
2107         commands.  Handled by module sim-options.
2108
2109         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2110         (WITH_MODULO_MEMORY): Define.
2111
2112         * interp.c (sim_info): Delete code printing memory size.
2113
2114         * interp.c (mips_size): Nee sim_size, delete function.
2115         (power2): Delete.
2116         (monitor, monitor_base, monitor_size): Delete global variables.
2117         (sim_open, sim_close): Delete code creating monitor and other
2118         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2119         manage memory regions.
2120         (load_memory, store_memory): Use sim-core for memory model.
2121
2122         * interp.c (address_translation): Delete all memory map code
2123         except line forcing 32 bit addresses.
2124
2125 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2126
2127         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2128         trace options.
2129
2130         * interp.c (logfh, logfile): Delete globals.
2131         (sim_open, sim_close): Delete code opening & closing log file.
2132         (mips_option_handler): Delete -l and -n options.
2133         (OPTION mips_options): Ditto.
2134
2135         * interp.c (OPTION mips_options): Rename option trace to dinero.
2136         (mips_option_handler): Update.
2137
2138 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2139
2140         * interp.c (fetch_str): New function.
2141         (sim_monitor): Rewrite using sim_read & sim_write.
2142         (sim_open): Check magic number.
2143         (sim_open): Write monitor vectors into memory using sim_write.
2144         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2145         (sim_read, sim_write): Simplify - transfer data one byte at a
2146         time.
2147         (load_memory, store_memory): Clarify meaning of parameter RAW.
2148
2149         * sim-main.h (isHOST): Defete definition.
2150         (isTARGET): Mark as depreciated.
2151         (address_translation): Delete parameter HOST.
2152
2153         * interp.c (address_translation): Delete parameter HOST.
2154
2155 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2156
2157         * mips.igen:
2158
2159         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2160         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2161
2162 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2163
2164         * mips.igen: Add model filter field to records.
2165
2166 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2167
2168         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2169
2170         interp.c (sim_engine_run): Do not compile function sim_engine_run
2171         when WITH_IGEN == 1.
2172
2173         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2174         target architecture.
2175
2176         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2177         igen. Replace with configuration variables sim_igen_flags /
2178         sim_m16_flags.
2179
2180         * m16.igen: New file.  Copy mips16 insns here.
2181         * mips.igen: From here.
2182
2183 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2184
2185         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2186         to top.
2187         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2188
2189 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2190
2191         * gencode.c (build_instruction): Follow sim_write's lead in using
2192         BigEndianMem instead of !ByteSwapMem.
2193
2194 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2195
2196         * configure.in (sim_gen): Dependent on target, select type of
2197         generator.  Always select old style generator.
2198
2199         configure: Re-generate.
2200
2201         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2202         targets.
2203         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2204         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2205         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2206         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2207         SIM_@sim_gen@_*, set by autoconf.
2208
2209 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2210
2211         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2212
2213         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2214         CURRENT_FLOATING_POINT instead.
2215
2216         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2217         (address_translation): Raise exception InstructionFetch when
2218         translation fails and isINSTRUCTION.
2219
2220         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2221         sim_engine_run): Change type of of vaddr and paddr to
2222         address_word.
2223         (address_translation, prefetch, load_memory, store_memory,
2224         cache_op): Change type of vAddr and pAddr to address_word.
2225
2226         * gencode.c (build_instruction): Change type of vaddr and paddr to
2227         address_word.
2228
2229 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2230
2231         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2232         macro to obtain result of ALU op.
2233
2234 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2235
2236         * interp.c (sim_info): Call profile_print.
2237
2238 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2239
2240         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2241
2242         * sim-main.h (WITH_PROFILE): Do not define, defined in
2243         common/sim-config.h.  Use sim-profile module.
2244         (simPROFILE): Delete defintion.
2245
2246         * interp.c (PROFILE): Delete definition.
2247         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2248         (sim_close): Delete code writing profile histogram.
2249         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2250         Delete.
2251         (sim_engine_run): Delete code profiling the PC.
2252
2253 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2254
2255         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2256
2257         * interp.c (sim_monitor): Make register pointers of type
2258         unsigned_word*.
2259
2260         * sim-main.h: Make registers of type unsigned_word not
2261         signed_word.
2262
2263 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2264
2265         * interp.c (sync_operation): Rename from SyncOperation, make
2266         global, add SD argument.
2267         (prefetch): Rename from Prefetch, make global, add SD argument.
2268         (decode_coproc): Make global.
2269
2270         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2271
2272         * gencode.c (build_instruction): Generate DecodeCoproc not
2273         decode_coproc calls.
2274
2275         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2276         (SizeFGR): Move to sim-main.h
2277         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2278         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2279         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2280         sim-main.h.
2281         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2282         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2283         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2284         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2285         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2286         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2287
2288         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2289         exception.
2290         (sim-alu.h): Include.
2291         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2292         (sim_cia): Typedef to instruction_address.
2293
2294 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2295
2296         * Makefile.in (interp.o): Rename generated file engine.c to
2297         oengine.c.
2298
2299         * interp.c: Update.
2300
2301 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2302
2303         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2304
2305 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2306
2307         * gencode.c (build_instruction): For "FPSQRT", output correct
2308         number of arguments to Recip.
2309
2310 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2311
2312         * Makefile.in (interp.o): Depends on sim-main.h
2313
2314         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2315
2316         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2317         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2318         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2319         STATE, DSSTATE): Define
2320         (GPR, FGRIDX, ..): Define.
2321
2322         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2323         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2324         (GPR, FGRIDX, ...): Delete macros.
2325
2326         * interp.c: Update names to match defines from sim-main.h
2327
2328 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2329
2330         * interp.c (sim_monitor): Add SD argument.
2331         (sim_warning): Delete.  Replace calls with calls to
2332         sim_io_eprintf.
2333         (sim_error): Delete. Replace calls with sim_io_error.
2334         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2335         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2336         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2337         argument.
2338         (mips_size): Rename from sim_size. Add SD argument.
2339
2340         * interp.c (simulator): Delete global variable.
2341         (callback): Delete global variable.
2342         (mips_option_handler, sim_open, sim_write, sim_read,
2343         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2344         sim_size,sim_monitor): Use sim_io_* not callback->*.
2345         (sim_open): ZALLOC simulator struct.
2346         (PROFILE): Do not define.
2347
2348 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2349
2350         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2351         support.h with corresponding code.
2352
2353         * sim-main.h (word64, uword64), support.h: Move definition to
2354         sim-main.h.
2355         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2356
2357         * support.h: Delete
2358         * Makefile.in: Update dependencies
2359         * interp.c: Do not include.
2360
2361 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2362
2363         * interp.c (address_translation, load_memory, store_memory,
2364         cache_op): Rename to from AddressTranslation et.al., make global,
2365         add SD argument
2366
2367         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2368         CacheOp): Define.
2369
2370         * interp.c (SignalException): Rename to signal_exception, make
2371         global.
2372
2373         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2374
2375         * sim-main.h (SignalException, SignalExceptionInterrupt,
2376         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2377         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2378         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2379         Define.
2380
2381         * interp.c, support.h: Use.
2382
2383 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2384
2385         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2386         to value_fpr / store_fpr. Add SD argument.
2387         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2388         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2389
2390         * sim-main.h (ValueFPR, StoreFPR): Define.
2391
2392 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2393
2394         * interp.c (sim_engine_run): Check consistency between configure
2395         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2396         and HASFPU.
2397
2398         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2399         (mips_fpu): Configure WITH_FLOATING_POINT.
2400         (mips_endian): Configure WITH_TARGET_ENDIAN.
2401         * configure: Update.
2402
2403 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2404
2405         * configure: Regenerated to track ../common/aclocal.m4 changes.
2406
2407 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2408
2409         * configure: Regenerated.
2410
2411 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2412
2413         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2414
2415 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2416
2417         * gencode.c (print_igen_insn_models): Assume certain architectures
2418         include all mips* instructions.
2419         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2420         instruction.
2421
2422         * Makefile.in (tmp.igen): Add target. Generate igen input from
2423         gencode file.
2424
2425         * gencode.c (FEATURE_IGEN): Define.
2426         (main): Add --igen option.  Generate output in igen format.
2427         (process_instructions): Format output according to igen option.
2428         (print_igen_insn_format): New function.
2429         (print_igen_insn_models): New function.
2430         (process_instructions): Only issue warnings and ignore
2431         instructions when no FEATURE_IGEN.
2432
2433 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2434
2435         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2436         MIPS targets.
2437
2438 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2439
2440         * configure: Regenerated to track ../common/aclocal.m4 changes.
2441
2442 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2443
2444         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2445         SIM_RESERVED_BITS): Delete, moved to common.
2446         (SIM_EXTRA_CFLAGS): Update.
2447
2448 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2449
2450         * configure.in: Configure non-strict memory alignment.
2451         * configure: Regenerated to track ../common/aclocal.m4 changes.
2452
2453 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2454
2455         * configure: Regenerated to track ../common/aclocal.m4 changes.
2456
2457 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2458
2459         * gencode.c (SDBBP,DERET): Added (3900) insns.
2460         (RFE): Turn on for 3900.
2461         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2462         (dsstate): Made global.
2463         (SUBTARGET_R3900): Added.
2464         (CANCELDELAYSLOT): New.
2465         (SignalException): Ignore SystemCall rather than ignore and
2466         terminate.  Add DebugBreakPoint handling.
2467         (decode_coproc): New insns RFE, DERET; and new registers Debug
2468         and DEPC protected by SUBTARGET_R3900.
2469         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2470         bits explicitly.
2471         * Makefile.in,configure.in: Add mips subtarget option.
2472         * configure: Update.
2473
2474 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2475
2476         * gencode.c: Add r3900 (tx39).
2477
2478
2479 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2480
2481         * gencode.c (build_instruction): Don't need to subtract 4 for
2482         JALR, just 2.
2483
2484 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2485
2486         * interp.c: Correct some HASFPU problems.
2487
2488 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2489
2490         * configure: Regenerated to track ../common/aclocal.m4 changes.
2491
2492 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2493
2494         * interp.c (mips_options): Fix samples option short form, should
2495         be `x'.
2496
2497 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2498
2499         * interp.c (sim_info): Enable info code.  Was just returning.
2500
2501 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2502
2503         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2504         MFC0.
2505
2506 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2507
2508         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2509         constants.
2510         (build_instruction): Ditto for LL.
2511
2512 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2513
2514         * configure: Regenerated to track ../common/aclocal.m4 changes.
2515
2516 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2517
2518         * configure: Regenerated to track ../common/aclocal.m4 changes.
2519         * config.in: Ditto.
2520
2521 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2522
2523         * interp.c (sim_open): Add call to sim_analyze_program, update
2524         call to sim_config.
2525
2526 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2527
2528         * interp.c (sim_kill): Delete.
2529         (sim_create_inferior): Add ABFD argument. Set PC from same.
2530         (sim_load): Move code initializing trap handlers from here.
2531         (sim_open): To here.
2532         (sim_load): Delete, use sim-hload.c.
2533
2534         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2535
2536 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2537
2538         * configure: Regenerated to track ../common/aclocal.m4 changes.
2539         * config.in: Ditto.
2540
2541 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2542
2543         * interp.c (sim_open): Add ABFD argument.
2544         (sim_load): Move call to sim_config from here.
2545         (sim_open): To here.  Check return status.
2546
2547 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2548
2549         * gencode.c (build_instruction): Two arg MADD should
2550         not assign result to $0.
2551
2552 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2553
2554         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2555         * sim/mips/configure.in: Regenerate.
2556
2557 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2558
2559         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2560         signed8, unsigned8 et.al. types.
2561
2562         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2563         hosts when selecting subreg.
2564
2565 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2566
2567         * interp.c (sim_engine_run): Reset the ZERO register to zero
2568         regardless of FEATURE_WARN_ZERO.
2569         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2570
2571 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2572
2573         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2574         (SignalException): For BreakPoints ignore any mode bits and just
2575         save the PC.
2576         (SignalException): Always set the CAUSE register.
2577
2578 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2579
2580         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2581         exception has been taken.
2582
2583         * interp.c: Implement the ERET and mt/f sr instructions.
2584
2585 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2586
2587         * interp.c (SignalException): Don't bother restarting an
2588         interrupt.
2589
2590 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2591
2592         * interp.c (SignalException): Really take an interrupt.
2593         (interrupt_event): Only deliver interrupts when enabled.
2594
2595 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2596
2597         * interp.c (sim_info): Only print info when verbose.
2598         (sim_info) Use sim_io_printf for output.
2599
2600 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2601
2602         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2603         mips architectures.
2604
2605 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2606
2607         * interp.c (sim_do_command): Check for common commands if a
2608         simulator specific command fails.
2609
2610 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2611
2612         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2613         and simBE when DEBUG is defined.
2614
2615 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2616
2617         * interp.c (interrupt_event): New function.  Pass exception event
2618         onto exception handler.
2619
2620         * configure.in: Check for stdlib.h.
2621         * configure: Regenerate.
2622
2623         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2624         variable declaration.
2625         (build_instruction): Initialize memval1.
2626         (build_instruction): Add UNUSED attribute to byte, bigend,
2627         reverse.
2628         (build_operands): Ditto.
2629
2630         * interp.c: Fix GCC warnings.
2631         (sim_get_quit_code): Delete.
2632
2633         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2634         * Makefile.in: Ditto.
2635         * configure: Re-generate.
2636
2637         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2638
2639 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2640
2641         * interp.c (mips_option_handler): New function parse argumes using
2642         sim-options.
2643         (myname): Replace with STATE_MY_NAME.
2644         (sim_open): Delete check for host endianness - performed by
2645         sim_config.
2646         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2647         (sim_open): Move much of the initialization from here.
2648         (sim_load): To here.  After the image has been loaded and
2649         endianness set.
2650         (sim_open): Move ColdReset from here.
2651         (sim_create_inferior): To here.
2652         (sim_open): Make FP check less dependant on host endianness.
2653
2654         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2655         run.
2656         * interp.c (sim_set_callbacks): Delete.
2657
2658         * interp.c (membank, membank_base, membank_size): Replace with
2659         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2660         (sim_open): Remove call to callback->init. gdb/run do this.
2661
2662         * interp.c: Update
2663
2664         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2665
2666         * interp.c (big_endian_p): Delete, replaced by
2667         current_target_byte_order.
2668
2669 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2670
2671         * interp.c (host_read_long, host_read_word, host_swap_word,
2672         host_swap_long): Delete. Using common sim-endian.
2673         (sim_fetch_register, sim_store_register): Use H2T.
2674         (pipeline_ticks): Delete.  Handled by sim-events.
2675         (sim_info): Update.
2676         (sim_engine_run): Update.
2677
2678 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2679
2680         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2681         reason from here.
2682         (SignalException): To here. Signal using sim_engine_halt.
2683         (sim_stop_reason): Delete, moved to common.
2684
2685 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2686
2687         * interp.c (sim_open): Add callback argument.
2688         (sim_set_callbacks): Delete SIM_DESC argument.
2689         (sim_size): Ditto.
2690
2691 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2692
2693         * Makefile.in (SIM_OBJS): Add common modules.
2694
2695         * interp.c (sim_set_callbacks): Also set SD callback.
2696         (set_endianness, xfer_*, swap_*): Delete.
2697         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2698         Change to functions using sim-endian macros.
2699         (control_c, sim_stop): Delete, use common version.
2700         (simulate): Convert into.
2701         (sim_engine_run): This function.
2702         (sim_resume): Delete.
2703
2704         * interp.c (simulation): New variable - the simulator object.
2705         (sim_kind): Delete global - merged into simulation.
2706         (sim_load): Cleanup.  Move PC assignment from here.
2707         (sim_create_inferior): To here.
2708
2709         * sim-main.h: New file.
2710         * interp.c (sim-main.h): Include.
2711
2712 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2713
2714         * configure: Regenerated to track ../common/aclocal.m4 changes.
2715
2716 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2717
2718         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2719
2720 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2721
2722         * gencode.c (build_instruction): DIV instructions: check
2723         for division by zero and integer overflow before using
2724         host's division operation.
2725
2726 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2727
2728         * Makefile.in (SIM_OBJS): Add sim-load.o.
2729         * interp.c: #include bfd.h.
2730         (target_byte_order): Delete.
2731         (sim_kind, myname, big_endian_p): New static locals.
2732         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2733         after argument parsing.  Recognize -E arg, set endianness accordingly.
2734         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2735         load file into simulator.  Set PC from bfd.
2736         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2737         (set_endianness): Use big_endian_p instead of target_byte_order.
2738
2739 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2740
2741         * interp.c (sim_size): Delete prototype - conflicts with
2742         definition in remote-sim.h.  Correct definition.
2743
2744 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2745
2746         * configure: Regenerated to track ../common/aclocal.m4 changes.
2747         * config.in: Ditto.
2748
2749 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2750
2751         * interp.c (sim_open): New arg `kind'.
2752
2753         * configure: Regenerated to track ../common/aclocal.m4 changes.
2754
2755 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2756
2757         * configure: Regenerated to track ../common/aclocal.m4 changes.
2758
2759 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2760
2761         * interp.c (sim_open): Set optind to 0 before calling getopt.
2762
2763 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2764
2765         * configure: Regenerated to track ../common/aclocal.m4 changes.
2766
2767 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2768
2769         * interp.c : Replace uses of pr_addr with pr_uword64
2770         where the bit length is always 64 independent of SIM_ADDR.
2771         (pr_uword64) : added.
2772
2773 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2774
2775         * configure: Re-generate.
2776
2777 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2778
2779         * configure: Regenerate to track ../common/aclocal.m4 changes.
2780
2781 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2782
2783         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2784         in argv form.
2785         (other sim_*): New SIM_DESC argument.
2786
2787 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2788
2789         * interp.c: Fix printing of addresses for non-64-bit targets.
2790         (pr_addr): Add function to print address based on size.
2791
2792 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2793
2794         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2795
2796 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2797
2798         * gencode.c (build_mips16_operands): Correct computation of base
2799         address for extended PC relative instruction.
2800
2801 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2802
2803         * interp.c (mips16_entry): Add support for floating point cases.
2804         (SignalException): Pass floating point cases to mips16_entry.
2805         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2806         registers.
2807         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2808         or fmt_word.
2809         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2810         and then set the state to fmt_uninterpreted.
2811         (COP_SW): Temporarily set the state to fmt_word while calling
2812         ValueFPR.
2813
2814 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2815
2816         * gencode.c (build_instruction): The high order may be set in the
2817         comparison flags at any ISA level, not just ISA 4.
2818
2819 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2820
2821         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2822         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2823         * configure.in: sinclude ../common/aclocal.m4.
2824         * configure: Regenerated.
2825
2826 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2827
2828         * configure: Rebuild after change to aclocal.m4.
2829
2830 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2831
2832         * configure configure.in Makefile.in:  Update to new configure
2833         scheme which is more compatible with WinGDB builds.
2834         * configure.in:  Improve comment on how to run autoconf.
2835         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2836         * Makefile.in:  Use autoconf substitution to install common
2837         makefile fragment.
2838
2839 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2840
2841         * gencode.c (build_instruction): Use BigEndianCPU instead of
2842         ByteSwapMem.
2843
2844 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2845
2846         * interp.c (sim_monitor): Make output to stdout visible in
2847         wingdb's I/O log window.
2848
2849 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2850
2851         * support.h: Undo previous change to SIGTRAP
2852         and SIGQUIT values.
2853
2854 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2855
2856         * interp.c (store_word, load_word): New static functions.
2857         (mips16_entry): New static function.
2858         (SignalException): Look for mips16 entry and exit instructions.
2859         (simulate): Use the correct index when setting fpr_state after
2860         doing a pending move.
2861
2862 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2863
2864         * interp.c: Fix byte-swapping code throughout to work on
2865         both little- and big-endian hosts.
2866
2867 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2868
2869         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2870         with gdb/config/i386/xm-windows.h.
2871
2872 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2873
2874         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2875         that messes up arithmetic shifts.
2876
2877 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2878
2879         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2880         SIGTRAP and SIGQUIT for _WIN32.
2881
2882 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2883
2884         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2885         force a 64 bit multiplication.
2886         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2887         destination register is 0, since that is the default mips16 nop
2888         instruction.
2889
2890 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2891
2892         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2893         (build_endian_shift): Don't check proc64.
2894         (build_instruction): Always set memval to uword64.  Cast op2 to
2895         uword64 when shifting it left in memory instructions.  Always use
2896         the same code for stores--don't special case proc64.
2897
2898         * gencode.c (build_mips16_operands): Fix base PC value for PC
2899         relative operands.
2900         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2901         jal instruction.
2902         * interp.c (simJALDELAYSLOT): Define.
2903         (JALDELAYSLOT): Define.
2904         (INDELAYSLOT, INJALDELAYSLOT): Define.
2905         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2906
2907 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2908
2909         * interp.c (sim_open): add flush_cache as a PMON routine
2910         (sim_monitor): handle flush_cache by ignoring it
2911
2912 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2913
2914         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2915         BigEndianMem.
2916         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2917         (BigEndianMem): Rename to ByteSwapMem and change sense.
2918         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2919         BigEndianMem references to !ByteSwapMem.
2920         (set_endianness): New function, with prototype.
2921         (sim_open): Call set_endianness.
2922         (sim_info): Use simBE instead of BigEndianMem.
2923         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2924         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2925         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2926         ifdefs, keeping the prototype declaration.
2927         (swap_word): Rewrite correctly.
2928         (ColdReset): Delete references to CONFIG.  Delete endianness related
2929         code; moved to set_endianness.
2930
2931 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2932
2933         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2934         * interp.c (CHECKHILO): Define away.
2935         (simSIGINT): New macro.
2936         (membank_size): Increase from 1MB to 2MB.
2937         (control_c): New function.
2938         (sim_resume): Rename parameter signal to signal_number.  Add local
2939         variable prev.  Call signal before and after simulate.
2940         (sim_stop_reason): Add simSIGINT support.
2941         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2942         functions always.
2943         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2944         if logfh is NULL.
2945         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2946         a call to sim_warning.
2947
2948 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2949
2950         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2951         16 bit instructions.
2952
2953 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2954
2955         Add support for mips16 (16 bit MIPS implementation):
2956         * gencode.c (inst_type): Add mips16 instruction encoding types.
2957         (GETDATASIZEINSN): Define.
2958         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2959         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2960         mtlo.
2961         (MIPS16_DECODE): New table, for mips16 instructions.
2962         (bitmap_val): New static function.
2963         (struct mips16_op): Define.
2964         (mips16_op_table): New table, for mips16 operands.
2965         (build_mips16_operands): New static function.
2966         (process_instructions): If PC is odd, decode a mips16
2967         instruction.  Break out instruction handling into new
2968         build_instruction function.
2969         (build_instruction): New static function, broken out of
2970         process_instructions.  Check modifiers rather than flags for SHIFT
2971         bit count and m[ft]{hi,lo} direction.
2972         (usage): Pass program name to fprintf.
2973         (main): Remove unused variable this_option_optind.  Change
2974         ``*loptarg++'' to ``loptarg++''.
2975         (my_strtoul): Parenthesize && within ||.
2976         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2977         (simulate): If PC is odd, fetch a 16 bit instruction, and
2978         increment PC by 2 rather than 4.
2979         * configure.in: Add case for mips16*-*-*.
2980         * configure: Rebuild.
2981
2982 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2983
2984         * interp.c: Allow -t to enable tracing in standalone simulator.
2985         Fix garbage output in trace file and error messages.
2986
2987 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2988
2989         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2990         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2991         * configure.in: Simplify using macros in ../common/aclocal.m4.
2992         * configure: Regenerated.
2993         * tconfig.in: New file.
2994
2995 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2996
2997         * interp.c: Fix bugs in 64-bit port.
2998         Use ansi function declarations for msvc compiler.
2999         Initialize and test file pointer in trace code.
3000         Prevent duplicate definition of LAST_EMED_REGNUM.
3001
3002 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3003
3004         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3005
3006 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3007
3008         * interp.c (SignalException): Check for explicit terminating
3009         breakpoint value.
3010         * gencode.c: Pass instruction value through SignalException()
3011         calls for Trap, Breakpoint and Syscall.
3012
3013 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3014
3015         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3016         only used on those hosts that provide it.
3017         * configure.in: Add sqrt() to list of functions to be checked for.
3018         * config.in: Re-generated.
3019         * configure: Re-generated.
3020
3021 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3022
3023         * gencode.c (process_instructions): Call build_endian_shift when
3024         expanding STORE RIGHT, to fix swr.
3025         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3026         clear the high bits.
3027         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3028         Fix float to int conversions to produce signed values.
3029
3030 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3031
3032         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3033         (process_instructions): Correct handling of nor instruction.
3034         Correct shift count for 32 bit shift instructions. Correct sign
3035         extension for arithmetic shifts to not shift the number of bits in
3036         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3037         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3038         Fix madd.
3039         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3040         It's OK to have a mult follow a mult.  What's not OK is to have a
3041         mult follow an mfhi.
3042         (Convert): Comment out incorrect rounding code.
3043
3044 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3045
3046         * interp.c (sim_monitor): Improved monitor printf
3047         simulation. Tidied up simulator warnings, and added "--log" option
3048         for directing warning message output.
3049         * gencode.c: Use sim_warning() rather than WARNING macro.
3050
3051 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3052
3053         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3054         getopt1.o, rather than on gencode.c.  Link objects together.
3055         Don't link against -liberty.
3056         (gencode.o, getopt.o, getopt1.o): New targets.
3057         * gencode.c: Include <ctype.h> and "ansidecl.h".
3058         (AND): Undefine after including "ansidecl.h".
3059         (ULONG_MAX): Define if not defined.
3060         (OP_*): Don't define macros; now defined in opcode/mips.h.
3061         (main): Call my_strtoul rather than strtoul.
3062         (my_strtoul): New static function.
3063
3064 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3065
3066         * gencode.c (process_instructions):  Generate word64 and uword64
3067         instead of `long long' and `unsigned long long' data types.
3068         * interp.c:  #include sysdep.h to get signals, and define default
3069         for SIGBUS.
3070         * (Convert):  Work around for Visual-C++ compiler bug with type
3071         conversion.
3072         * support.h:  Make things compile under Visual-C++ by using
3073         __int64 instead of `long long'.  Change many refs to long long
3074         into word64/uword64 typedefs.
3075
3076 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3077
3078         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3079         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3080         (docdir): Removed.
3081         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3082         (AC_PROG_INSTALL): Added.
3083         (AC_PROG_CC): Moved to before configure.host call.
3084         * configure: Rebuilt.
3085
3086 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3087
3088         * configure.in: Define @SIMCONF@ depending on mips target.
3089         * configure: Rebuild.
3090         * Makefile.in (run): Add @SIMCONF@ to control simulator
3091         construction.
3092         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3093         * interp.c: Remove some debugging, provide more detailed error
3094         messages, update memory accesses to use LOADDRMASK.
3095
3096 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3097
3098         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3099         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3100         stamp-h.
3101         * configure: Rebuild.
3102         * config.in: New file, generated by autoheader.
3103         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3104         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3105         HAVE_ANINT and HAVE_AINT, as appropriate.
3106         * Makefile.in (run): Use @LIBS@ rather than -lm.
3107         (interp.o): Depend upon config.h.
3108         (Makefile): Just rebuild Makefile.
3109         (clean): Remove stamp-h.
3110         (mostlyclean): Make the same as clean, not as distclean.
3111         (config.h, stamp-h): New targets.
3112
3113 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3114
3115         * interp.c (ColdReset): Fix boolean test. Make all simulator
3116         globals static.
3117
3118 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3119
3120         * interp.c (xfer_direct_word, xfer_direct_long,
3121         swap_direct_word, swap_direct_long, xfer_big_word,
3122         xfer_big_long, xfer_little_word, xfer_little_long,
3123         swap_word,swap_long): Added.
3124         * interp.c (ColdReset): Provide function indirection to
3125         host<->simulated_target transfer routines.
3126         * interp.c (sim_store_register, sim_fetch_register): Updated to
3127         make use of indirected transfer routines.
3128
3129 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3130
3131         * gencode.c (process_instructions): Ensure FP ABS instruction
3132         recognised.
3133         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3134         system call support.
3135
3136 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3137
3138         * interp.c (sim_do_command): Complain if callback structure not
3139         initialised.
3140
3141 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3142
3143         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3144         support for Sun hosts.
3145         * Makefile.in (gencode): Ensure the host compiler and libraries
3146         used for cross-hosted build.
3147
3148 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3149
3150         * interp.c, gencode.c: Some more (TODO) tidying.
3151
3152 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3153
3154         * gencode.c, interp.c: Replaced explicit long long references with
3155         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3156         * support.h (SET64LO, SET64HI): Macros added.
3157
3158 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3159
3160         * configure: Regenerate with autoconf 2.7.
3161
3162 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3163
3164         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3165         * support.h: Remove superfluous "1" from #if.
3166         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3167
3168 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3169
3170         * interp.c (StoreFPR): Control UndefinedResult() call on
3171         WARN_RESULT manifest.
3172
3173 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3174
3175         * gencode.c: Tidied instruction decoding, and added FP instruction
3176         support.
3177
3178         * interp.c: Added dineroIII, and BSD profiling support. Also
3179         run-time FP handling.
3180
3181 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3182
3183         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3184         gencode.c, interp.c, support.h: created.