2 Wed Nov 11 16:53:57 1998 Andrew Cagney <cagney@b1.cygnus.com>
4 * r5900.igen (RSQRT): Set both I/SI and D/SD when div-0.
6 Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
8 * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
10 Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
12 * r5900.igen (DIV): Do not clear clear SO/SU when already set.
14 * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
15 negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR
18 * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
20 (r59fp_store): Clarify "bad value" abort messages.
24 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
26 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
27 interrupt level number to match changed SignalExceptionInterrupt
32 Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
34 * sim-main.c (tlb_try_match): Include physical address in
35 scratchpad non-mapping warning.
39 Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
41 * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
42 as per customer patch.
45 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
47 * interp.c: #include "itable.h" if WITH_IGEN.
48 (get_insn_name): New function.
49 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
50 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
53 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
55 * sim-main.c (tlb_try_match): Specially match virtual
56 pages mapped to scratchpad RAM, an unimplemented feature.
60 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
62 * r5900.igen (prot3w): Correct rotation sequence; patch
66 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
68 * configure: Rebuilt to inhale new common/aclocal.m4.
71 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
73 * r5900.igen (plzcw): Make `i' signed.
75 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
77 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
78 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
79 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
80 * interp.c (signal_exception, sky version): Handle INT 2.
82 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
84 * sim-main.h: track COP0 registers
85 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
87 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
89 * r5900.igen (mtsab): Correct typo in input register.
91 * sim-main.h (TMP_*): New macros for accessing local 128-bit
92 temporary for multimedia instructions.
93 * r5900.igen (*): Convert most instructions to use new TMP
94 macros to store output result during computation.
98 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
100 * dv-tx3904sio.c: Include sim-assert.h.
102 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
104 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
105 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
106 Reorganize target-specific sim-hardware checks.
107 * configure: rebuilt.
108 * interp.c (sim_open): For tx39 target boards, set
109 OPERATING_ENVIRONMENT, add tx3904sio devices.
110 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
111 ROM executables. Install dv-sockser into sim-modules list.
113 * dv-tx3904irc.c: Compiler warning clean-up.
114 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
115 frequent hw-trace messages.
119 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
121 * interp.c (signal_exception): Set IP3 bit in CAUSE on
125 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
127 * vr.igen (MulAcc): Identify as a vr4100 specific function.
129 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
131 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
134 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
135 * mips.igen: Define vr4100 model. Include vr.igen.
136 start-sanitize-cygnus
137 * vr5400.igen: Move instructions to vr.igen
138 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
140 start-sanitize-vr4320
141 * vr4320.igen: Move instructions to vr.igen.
142 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
146 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
148 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
149 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
150 confusing message if not enough --load-next options appear.
152 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
153 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
154 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
155 (resume_handler): Same.
156 (suspend_handler): Same.
158 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
160 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
161 to trigger multi-phase load.
163 * sim-main.c: Include sim-assert.h for ASSERT macro.
164 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
167 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
170 * interp.c (sim_open): Initialize TLB.
171 * interp.c (signal_exceptions): New 5900 handling.
172 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
173 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
174 (address_translation): Use the TLB.
175 * sim-main.h (r4000_tlb_entry_t): New type.
176 (TLB_*): New constants.
177 (COP0_*): New register names.
179 Sky character I/O device.
180 * sky-psio.c: New file.
181 * sky-psio.h: New file.
182 * Makefile.in: Add sky-psio.o.
186 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
188 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
191 (r59fp_store): Update calls.
192 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
195 start-sanitize-branchbug4011
196 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
198 * interp.c (OPTION_BRANCH_BUG_4011): Add.
199 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
200 (mips_options): Define the option.
201 * mips.igen (check_4011_branch_bug): New.
202 (mark_4011_branch_bug): New.
203 (all branch insn): Call mark_branch_bug, and check_branch_bug.
204 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
205 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
206 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
207 check_branch_bug, mark_branch_bug): Define.
209 end-sanitize-branchbug4011
210 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
212 * mips.igen (check_mf_hilo): Correct check.
215 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
217 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
218 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
219 purpose registers, add 8 COP0 break-point registers, add 64 COP0
220 performance registers.
222 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
223 MFP* instructions. Just transfer value to/from corresponding
226 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
227 status is always true.
228 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
229 (EI, DI): Set/clear Status-EIE bit.
233 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
235 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
239 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
242 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
244 * sky-gdb.c: Include "sim-assert.h".
247 * sim-main.h (interrupt_event): Add prototype.
249 start-sanitize-tx3904
250 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
251 register_ptr, register_value.
252 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
255 * sim-main.h (tracefh): Make extern.
257 start-sanitize-tx3904
258 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
260 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
261 Reduce unnecessarily high timer event frequency.
262 * dv-tx3904cpu.c: Ditto for interrupt event.
266 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
268 * interp.c (decode_coproc): Removed COP2 branches.
269 * r5900.igen: Moved COP2 branch instructions here.
270 * mips.igen: Restricted COPz == COP2 bit pattern to
271 exclude COP2 branches.
274 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
276 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
278 (interrupt_event): Made non-static.
279 start-sanitize-tx3904
281 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
282 interchange of configuration values for external vs. internal
286 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
288 * mips.igen (BREAK): Moved code to here for
289 simulator-reserved break instructions.
290 * gencode.c (build_instruction): Ditto.
291 * interp.c (signal_exception): Code moved from here. Non-
292 reserved instructions now use exception vector, rather
294 * sim-main.h: Moved magic constants to here.
296 start-sanitize-tx3904
297 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
299 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
300 register upon non-zero interrupt event level, clear upon zero
302 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
303 by passing zero event value.
304 (*_io_{read,write}_buffer): Endianness fixes.
305 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
306 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
308 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
309 serial I/O and timer module at base address 0xFFFF0000.
312 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
314 * mips.igen (SWC1) : Correct the handling of ReverseEndian
317 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
319 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
323 start-sanitize-tx3904
324 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
326 * dv-tx3904tmr.c: New file - implements tx3904 timer.
327 * dv-tx3904{irc,cpu}.c: Mild reformatting.
328 * configure.in: Include tx3904tmr in hw_device list.
329 * configure: Rebuilt.
330 * interp.c (sim_open): Instantiate three timer instances.
331 Fix address typo of tx3904irc instance.
335 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
337 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
338 Select corresponding check_mt_hilo function.
339 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
342 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
346 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
348 * interp.c (signal_exception): SystemCall exception now uses
349 the exception vector.
351 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
353 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
357 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
359 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
363 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
365 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
367 start-sanitize-tx3904
368 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
370 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
372 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
373 sim-main.h. Declare a struct hw_descriptor instead of struct
374 hw_device_descriptor.
377 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
379 * mips.igen (do_store_left, do_load_left): Compute nr of left and
380 right bits and then re-align left hand bytes to correct byte
381 lanes. Fix incorrect computation in do_store_left when loading
382 bytes from second word.
384 start-sanitize-tx3904
385 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
387 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
388 * interp.c (sim_open): Only create a device tree when HW is
391 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
392 * interp.c (signal_exception): Ditto.
395 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
397 * gencode.c: Mark BEGEZALL as LIKELY.
399 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
401 * sim-main.h (ALU32_END): Sign extend 32 bit results.
402 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
405 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
407 * interp.c (sim_fetch_register): Convert internal r5900 regs to
411 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
413 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
414 modules. Recognize TX39 target with "mips*tx39" pattern.
415 * configure: Rebuilt.
416 * sim-main.h (*): Added many macros defining bits in
417 TX39 control registers.
418 (SignalInterrupt): Send actual PC instead of NULL.
419 (SignalNMIReset): New exception type.
420 * interp.c (board): New variable for future use to identify
421 a particular board being simulated.
422 (mips_option_handler,mips_options): Added "--board" option.
423 (interrupt_event): Send actual PC.
424 (sim_open): Make memory layout conditional on board setting.
425 (signal_exception): Initial implementation of hardware interrupt
426 handling. Accept another break instruction variant for simulator
428 (decode_coproc): Implement RFE instruction for TX39.
429 (mips.igen): Decode RFE instruction as such.
430 start-sanitize-tx3904
431 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
432 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
433 bbegin to implement memory map.
434 * dv-tx3904cpu.c: New file.
435 * dv-tx3904irc.c: New file.
438 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
440 * mips.igen (check_mt_hilo): Create a separate r3900 version.
443 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
445 * r5900.igen: Replace the calls and the definition of the
446 function check_op_hilo_hi1lo1 with the pair
447 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
450 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
452 * tx.igen (madd,maddu): Replace calls to check_op_hilo
453 with calls to check_div_hilo.
455 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
457 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
458 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
459 Add special r3900 version of do_mult_hilo.
460 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
461 with calls to check_mult_hilo.
462 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
463 with calls to check_div_hilo.
465 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
467 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
468 Document a replacement.
470 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
472 * interp.c (sim_monitor): Make mon_printf work.
474 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
476 * sim-main.h (INSN_NAME): New arg `cpu'.
479 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
481 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
486 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
488 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
489 * r5900.igen (r59fp_overflow): Use.
491 * r5900.igen (r59fp_op3): Rename to
492 (r59fp_mula): This, delete opm argument.
493 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
494 (r59fp_mula): Overflowing product propogates through to result.
495 (r59fp_mula): ACC to the MAX propogates to result.
496 (r59fp_mula): Underflow during multiply only sets SU.
499 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
501 * configure: Regenerated to track ../common/aclocal.m4 changes.
503 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
505 * configure: Regenerated to track ../common/aclocal.m4 changes.
508 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
510 * acconfig.h: New file.
511 * configure.in: Reverted change of Apr 24; use sinclude again.
513 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
515 * configure: Regenerated to track ../common/aclocal.m4 changes.
518 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
520 * configure.in: Don't call sinclude.
522 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
524 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
526 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
528 * mips.igen (ERET): Implement.
530 * interp.c (decode_coproc): Return sign-extended EPC.
532 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
534 * interp.c (signal_exception): Do not ignore Trap.
535 (signal_exception): On TRAP, restart at exception address.
536 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
537 (signal_exception): Update.
538 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
539 so that TRAP instructions are caught.
541 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
543 * sim-main.h (struct hilo_access, struct hilo_history): Define,
544 contains HI/LO access history.
545 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
546 (HIACCESS, LOACCESS): Delete, replace with
547 (HIHISTORY, LOHISTORY): New macros.
548 (start-sanitize-r5900):
549 (struct sim_5900_cpu): Make hi1access, lo1access of type
551 (HI1ACCESS, LO1ACCESS): Delete, replace with
552 (HI1HISTORY, LO1HISTORY): New macros.
553 (end-sanitize-r5900):
554 (CHECKHILO): Delete all, moved to mips.igen
556 * gencode.c (build_instruction): Do not generate checks for
557 correct HI/LO register usage.
559 * interp.c (old_engine_run): Delete checks for correct HI/LO
562 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
563 check_mf_cycles): New functions.
564 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
565 do_divu, domultx, do_mult, do_multu): Use.
567 * tx.igen ("madd", "maddu"): Use.
568 (start-sanitize-r5900):
570 r5900.igen: Update all HI/LO checks.
571 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
572 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
573 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
574 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
575 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
577 (end-sanitize-r5900):
580 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
582 * interp.c (decode_coproc): Correct CMFC2/QMTC2
585 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
586 instead of a single 128-bit access.
590 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
592 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
593 * interp.c (cop_[ls]q): Fixes corresponding to above.
597 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
599 * interp.c (decode_coproc): Adapt COP2 micro interlock to
600 clarified specs. Reset "M" bit; exit also on "E" bit.
604 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
606 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
607 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
609 * r5900.igen (r59fp_unpack): New function.
610 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
611 RSQRT.S, SQRT.S): Use.
612 (r59fp_zero): New function.
613 (r59fp_overflow): Generate r5900 specific overflow value.
614 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
616 (CVT.S.W, CVT.W.S): Exchange implementations.
618 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
622 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
624 * configure.in (tx19, sim_use_gen): Switch to igen.
625 * configure: Re-build.
629 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
631 * interp.c (decode_coproc): Make COP2 branch code compile after
632 igen signature changes.
635 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
637 * mips.igen (DSRAV): Use function do_dsrav.
638 (SRAV): Use new function do_srav.
640 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
641 (B): Sign extend 11 bit immediate.
642 (EXT-B*): Shift 16 bit immediate left by 1.
643 (ADDIU*): Don't sign extend immediate value.
645 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
647 * m16run.c (sim_engine_run): Restore CIA after handling an event.
650 * mips.igen (mtc0): Valid tx19 instruction.
653 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
656 * mips.igen (delayslot32, nullify_next_insn): New functions.
657 (m16.igen): Always include.
658 (do_*): Add more tracing.
660 * m16.igen (delayslot16): Add NIA argument, could be called by a
661 32 bit MIPS16 instruction.
663 * interp.c (ifetch16): Move function from here.
664 * sim-main.c (ifetch16): To here.
666 * sim-main.c (ifetch16, ifetch32): Update to match current
667 implementations of LH, LW.
668 (signal_exception): Don't print out incorrect hex value of illegal
671 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
673 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
676 * m16.igen: Implement MIPS16 instructions.
678 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
679 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
680 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
681 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
682 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
683 bodies of corresponding code from 32 bit insn to these. Also used
684 by MIPS16 versions of functions.
686 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
687 (IMEM16): Drop NR argument from macro.
690 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
692 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
693 of VU lower instruction.
697 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
699 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
702 * sim-main.h: Removed attempt at allowing 128-bit access.
706 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
708 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
710 * interp.c (decode_coproc): Refer to VU CIA as a "special"
711 register, not as a "misc" register. Aha. Add activity
712 assertions after VCALLMS* instructions.
716 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
718 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
719 to upper code of generated VU instruction.
723 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
725 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
727 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
730 * r5900.igen (SQC2): Thinko.
734 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
736 * interp.c (*): Adapt code to merged VU device & state structs.
737 (decode_coproc): Execute COP2 each macroinstruction without
738 pipelining, by stepping VU to completion state. Adapted to
739 read_vu_*_reg style of register access.
741 * mips.igen ([SL]QC2): Removed these COP2 instructions.
743 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
745 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
748 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
750 * Makefile.in (SIM_OBJS): Add sim-main.o.
752 * sim-main.h (address_translation, load_memory, store_memory,
753 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
755 (pr_addr, pr_uword64): Declare.
756 (sim-main.c): Include when H_REVEALS_MODULE_P.
758 * interp.c (address_translation, load_memory, store_memory,
759 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
761 * sim-main.c: To here. Fix compilation problems.
763 * configure.in: Enable inlining.
764 * configure: Re-config.
766 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
768 * configure: Regenerated to track ../common/aclocal.m4 changes.
770 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
772 * mips.igen: Include tx.igen.
773 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
774 * tx.igen: New file, contains MADD and MADDU.
776 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
777 the hardwired constant `7'.
778 (store_memory): Ditto.
779 (LOADDRMASK): Move definition to sim-main.h.
781 mips.igen (MTC0): Enable for r3900.
784 mips.igen (do_load_byte): Delete.
785 (do_load, do_store, do_load_left, do_load_write, do_store_left,
786 do_store_right): New functions.
787 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
789 configure.in: Let the tx39 use igen again.
792 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
794 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
795 not an address sized quantity. Return zero for cache sizes.
797 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
799 * mips.igen (r3900): r3900 does not support 64 bit integer
803 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
805 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
809 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
811 * interp.c (decode_coproc): Continuing COP2 work.
812 (cop_[ls]q): Make sky-target-only.
814 * sim-main.h (COP_[LS]Q): Make sky-target-only.
816 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
818 * configure.in (mipstx39*-*-*): Use gencode simulator rather
820 * configure : Rebuild.
823 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
825 * interp.c (decode_coproc): Added a missing TARGET_SKY check
826 around COP2 implementation skeleton.
830 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
832 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
834 * interp.c (sim_{load,store}_register): Use new vu[01]_device
835 static to access VU registers.
836 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
837 decoding. Work in progress.
839 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
840 overlapping/redundant bit pattern.
841 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
844 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
847 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
848 access to coprocessor registers.
850 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
852 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
854 * configure: Regenerated to track ../common/aclocal.m4 changes.
856 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
858 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
860 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
863 * config.in: Regenerated to track ../common/aclocal.m4 changes.
865 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
867 * configure: Regenerated to track ../common/aclocal.m4 changes.
869 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
871 * interp.c (Max, Min): Comment out functions. Not yet used.
873 start-sanitize-vr4320
874 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
876 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
879 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
881 * configure: Regenerated to track ../common/aclocal.m4 changes.
883 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
885 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
886 configurable settings for stand-alone simulator.
889 * configure.in: Added --with-sim-gpu2 option to specify path of
890 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
891 links/compiles stand-alone simulator with this library.
893 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
895 * configure.in: Added X11 search, just in case.
897 * configure: Regenerated.
899 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
901 * interp.c (sim_write, sim_read, load_memory, store_memory):
902 Replace sim_core_*_map with read_map, write_map, exec_map resp.
904 start-sanitize-vr4320
905 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
907 * vr4320.igen (clz,dclz) : Added.
908 (dmac): Replaced 99, with LO.
911 start-sanitize-cygnus
912 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
914 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
917 start-sanitize-vr4320
918 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
920 * vr4320.igen: New file.
921 * Makefile.in (vr4320.igen) : Added.
922 * configure.in (mips64vr4320-*-*): Added.
923 * configure : Rebuilt.
924 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
925 Add the vr4320 model entry and mark the vr4320 insn as necessary.
928 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
930 * sim-main.h (GETFCC): Return an unsigned value.
933 * r5900.igen: Use an unsigned array index variable `i'.
934 (QFSRV): Ditto for variable bytes.
937 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
939 * mips.igen (DIV): Fix check for -1 / MIN_INT.
940 (DADD): Result destination is RD not RT.
943 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
944 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
948 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
950 * sim-main.h (HIACCESS, LOACCESS): Always define.
952 * mdmx.igen (Maxi, Mini): Rename Max, Min.
954 * interp.c (sim_info): Delete.
956 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
958 * interp.c (DECLARE_OPTION_HANDLER): Use it.
959 (mips_option_handler): New argument `cpu'.
960 (sim_open): Update call to sim_add_option_table.
962 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
964 * mips.igen (CxC1): Add tracing.
967 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
969 * r5900.igen (StoreFP): Delete.
970 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
972 (rsqrt.s, sqrt.s): Implement.
973 (r59cond): New function.
974 (C.COND.S): Call r59cond in assembler line.
975 (cvt.w.s, cvt.s.w): Implement.
977 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
980 * sim-main.h: Define an enum of r5900 FCSR bit fields.
984 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
986 * r5900.igen: Add tracing to all p* instructions.
988 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
990 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
991 to get gdb talking to re-aranged sim_cpu register structure.
994 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
996 * sim-main.h (Max, Min): Declare.
998 * interp.c (Max, Min): New functions.
1000 * mips.igen (BC1): Add tracing.
1002 start-sanitize-cygnus
1003 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005 * mdmx.igen: Tag all functions as requiring either with mdmx or
1009 start-sanitize-r5900
1010 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1014 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1016 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1018 * r5900.igen: Rewrite.
1020 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1022 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1023 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1026 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1028 * interp.c Added memory map for stack in vr4100
1030 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1032 * interp.c (load_memory): Add missing "break"'s.
1034 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1036 * interp.c (sim_store_register, sim_fetch_register): Pass in
1037 length parameter. Return -1.
1039 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1041 * interp.c: Added hardware init hook, fixed warnings.
1043 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1047 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049 * interp.c (ifetch16): New function.
1051 * sim-main.h (IMEM32): Rename IMEM.
1052 (IMEM16_IMMED): Define.
1054 (DELAY_SLOT): Update.
1056 * m16run.c (sim_engine_run): New file.
1058 * m16.igen: All instructions except LB.
1059 (LB): Call do_load_byte.
1060 * mips.igen (do_load_byte): New function.
1061 (LB): Call do_load_byte.
1063 * mips.igen: Move spec for insn bit size and high bit from here.
1064 * Makefile.in (tmp-igen, tmp-m16): To here.
1066 * m16.dc: New file, decode mips16 instructions.
1068 * Makefile.in (SIM_NO_ALL): Define.
1069 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1072 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1076 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1078 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1079 point unit to 32 bit registers.
1080 * configure: Re-generate.
1082 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1084 * configure.in (sim_use_gen): Make IGEN the default simulator
1085 generator for generic 32 and 64 bit mips targets.
1086 * configure: Re-generate.
1088 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1090 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1093 * interp.c (sim_fetch_register, sim_store_register): Read/write
1094 FGR from correct location.
1095 (sim_open): Set size of FGR's according to
1096 WITH_TARGET_FLOATING_POINT_BITSIZE.
1098 * sim-main.h (FGR): Store floating point registers in a separate
1101 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1103 * configure: Regenerated to track ../common/aclocal.m4 changes.
1105 start-sanitize-cygnus
1106 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1109 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1111 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1113 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1115 * interp.c (pending_tick): New function. Deliver pending writes.
1117 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1118 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1119 it can handle mixed sized quantites and single bits.
1121 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123 * interp.c (oengine.h): Do not include when building with IGEN.
1124 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1125 (sim_info): Ditto for PROCESSOR_64BIT.
1126 (sim_monitor): Replace ut_reg with unsigned_word.
1127 (*): Ditto for t_reg.
1128 (LOADDRMASK): Define.
1129 (sim_open): Remove defunct check that host FP is IEEE compliant,
1130 using software to emulate floating point.
1131 (value_fpr, ...): Always compile, was conditional on HASFPU.
1133 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1135 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1138 * interp.c (SD, CPU): Define.
1139 (mips_option_handler): Set flags in each CPU.
1140 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1141 (sim_close): Do not clear STATE, deleted anyway.
1142 (sim_write, sim_read): Assume CPU zero's vm should be used for
1144 (sim_create_inferior): Set the PC for all processors.
1145 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1147 (mips16_entry): Pass correct nr of args to store_word, load_word.
1148 (ColdReset): Cold reset all cpu's.
1149 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1150 (sim_monitor, load_memory, store_memory, signal_exception): Use
1151 `CPU' instead of STATE_CPU.
1154 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1157 * sim-main.h (signal_exception): Add sim_cpu arg.
1158 (SignalException*): Pass both SD and CPU to signal_exception.
1159 * interp.c (signal_exception): Update.
1161 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1163 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1164 address_translation): Ditto
1165 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1167 start-sanitize-cygnus
1168 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1170 (ByteAlign): Use StoreFPR, pass args in correct order.
1173 start-sanitize-r5900
1174 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1179 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1181 * configure: Regenerated to track ../common/aclocal.m4 changes.
1183 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185 start-sanitize-r5900
1186 * configure.in (sim_igen_filter): For r5900, use igen.
1187 * configure: Re-generate.
1190 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1192 * mips.igen (model): Map processor names onto BFD name.
1194 * sim-main.h (CPU_CIA): Delete.
1195 (SET_CIA, GET_CIA): Define
1197 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1199 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1202 * configure.in (default_endian): Configure a big-endian simulator
1204 * configure: Re-generate.
1206 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1208 * configure: Regenerated to track ../common/aclocal.m4 changes.
1210 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1212 * interp.c (sim_monitor): Handle Densan monitor outbyte
1213 and inbyte functions.
1215 1997-12-29 Felix Lee <flee@cygnus.com>
1217 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1219 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1221 * Makefile.in (tmp-igen): Arrange for $zero to always be
1222 reset to zero after every instruction.
1224 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1226 * configure: Regenerated to track ../common/aclocal.m4 changes.
1229 start-sanitize-cygnus
1230 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1232 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1235 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1237 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1238 vr5400 with the vr5000 as the default.
1241 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1243 * mips.igen (MSUB): Fix to work like MADD.
1244 * gencode.c (MSUB): Similarly.
1246 start-sanitize-cygnus
1247 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1249 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1253 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1255 * configure: Regenerated to track ../common/aclocal.m4 changes.
1257 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1259 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1261 start-sanitize-cygnus
1262 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1263 (value_cc, store_cc): Implement.
1265 * sim-main.h: Add 8*3*8 bit accumulator.
1267 * vr5400.igen: Move mdmx instructins from here
1268 * mdmx.igen: To here - new file. Add/fix missing instructions.
1269 * mips.igen: Include mdmx.igen.
1270 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1273 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1275 * sim-main.h (sim-fpu.h): Include.
1277 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1278 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1279 using host independant sim_fpu module.
1281 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1283 * interp.c (signal_exception): Report internal errors with SIGABRT
1286 * sim-main.h (C0_CONFIG): New register.
1287 (signal.h): No longer include.
1289 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1291 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1293 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1295 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * mips.igen: Tag vr5000 instructions.
1298 (ANDI): Was missing mipsIV model, fix assembler syntax.
1299 (do_c_cond_fmt): New function.
1300 (C.cond.fmt): Handle mips I-III which do not support CC field
1302 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1303 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1305 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1306 vr5000 which saves LO in a GPR separatly.
1308 * configure.in (enable-sim-igen): For vr5000, select vr5000
1309 specific instructions.
1310 * configure: Re-generate.
1312 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1314 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1316 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1317 fmt_uninterpreted_64 bit cases to switch. Convert to
1320 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1322 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1323 as specified in IV3.2 spec.
1324 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1326 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1328 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1329 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1330 (start-sanitize-r5900):
1331 (LWXC1, SWXC1): Delete from r5900 instruction set.
1332 (end-sanitize-r5900):
1333 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1334 PENDING_FILL versions of instructions. Simplify.
1336 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1338 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1340 (MTHI, MFHI): Disable code checking HI-LO.
1342 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1344 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1346 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1348 * gencode.c (build_mips16_operands): Replace IPC with cia.
1350 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1351 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1353 (UndefinedResult): Replace function with macro/function
1355 (sim_engine_run): Don't save PC in IPC.
1357 * sim-main.h (IPC): Delete.
1359 start-sanitize-cygnus
1360 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1361 (do_select): Rename function select.
1364 * interp.c (signal_exception, store_word, load_word,
1365 address_translation, load_memory, store_memory, cache_op,
1366 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1367 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1368 current instruction address - cia - argument.
1369 (sim_read, sim_write): Call address_translation directly.
1370 (sim_engine_run): Rename variable vaddr to cia.
1371 (signal_exception): Pass cia to sim_monitor
1373 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1374 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1375 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1377 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1378 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1381 * interp.c (signal_exception): Pass restart address to
1384 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1385 idecode.o): Add dependency.
1387 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1389 (DELAY_SLOT): Update NIA not PC with branch address.
1390 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1392 * mips.igen: Use CIA not PC in branch calculations.
1393 (illegal): Call SignalException.
1394 (BEQ, ADDIU): Fix assembler.
1396 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1398 * m16.igen (JALX): Was missing.
1400 * configure.in (enable-sim-igen): New configuration option.
1401 * configure: Re-generate.
1403 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1405 * interp.c (load_memory, store_memory): Delete parameter RAW.
1406 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1407 bypassing {load,store}_memory.
1409 * sim-main.h (ByteSwapMem): Delete definition.
1411 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1413 * interp.c (sim_do_command, sim_commands): Delete mips specific
1414 commands. Handled by module sim-options.
1416 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1417 (WITH_MODULO_MEMORY): Define.
1419 * interp.c (sim_info): Delete code printing memory size.
1421 * interp.c (mips_size): Nee sim_size, delete function.
1423 (monitor, monitor_base, monitor_size): Delete global variables.
1424 (sim_open, sim_close): Delete code creating monitor and other
1425 memory regions. Use sim-memopts module, via sim_do_commandf, to
1426 manage memory regions.
1427 (load_memory, store_memory): Use sim-core for memory model.
1429 * interp.c (address_translation): Delete all memory map code
1430 except line forcing 32 bit addresses.
1432 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1434 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1437 * interp.c (logfh, logfile): Delete globals.
1438 (sim_open, sim_close): Delete code opening & closing log file.
1439 (mips_option_handler): Delete -l and -n options.
1440 (OPTION mips_options): Ditto.
1442 * interp.c (OPTION mips_options): Rename option trace to dinero.
1443 (mips_option_handler): Update.
1445 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1447 * interp.c (fetch_str): New function.
1448 (sim_monitor): Rewrite using sim_read & sim_write.
1449 (sim_open): Check magic number.
1450 (sim_open): Write monitor vectors into memory using sim_write.
1451 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1452 (sim_read, sim_write): Simplify - transfer data one byte at a
1454 (load_memory, store_memory): Clarify meaning of parameter RAW.
1456 * sim-main.h (isHOST): Defete definition.
1457 (isTARGET): Mark as depreciated.
1458 (address_translation): Delete parameter HOST.
1460 * interp.c (address_translation): Delete parameter HOST.
1463 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1465 * gencode.c: Add tx49 configury and insns.
1466 * configure.in: Add tx49 configury.
1467 * configure: Update.
1470 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1474 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1475 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1477 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479 * mips.igen: Add model filter field to records.
1481 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1483 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1485 interp.c (sim_engine_run): Do not compile function sim_engine_run
1486 when WITH_IGEN == 1.
1488 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1489 target architecture.
1491 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1492 igen. Replace with configuration variables sim_igen_flags /
1495 start-sanitize-r5900
1496 * r5900.igen: New file. Copy r5900 insns here.
1498 start-sanitize-cygnus
1499 * vr5400.igen: New file.
1501 * m16.igen: New file. Copy mips16 insns here.
1502 * mips.igen: From here.
1504 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506 start-sanitize-cygnus
1507 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1509 * configure.in: Add mips64vr5400 target.
1510 * configure: Re-generate.
1513 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1515 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1517 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1519 * gencode.c (build_instruction): Follow sim_write's lead in using
1520 BigEndianMem instead of !ByteSwapMem.
1522 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1524 * configure.in (sim_gen): Dependent on target, select type of
1525 generator. Always select old style generator.
1527 configure: Re-generate.
1529 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1531 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1532 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1533 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1534 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1535 SIM_@sim_gen@_*, set by autoconf.
1537 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1539 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1541 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1542 CURRENT_FLOATING_POINT instead.
1544 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1545 (address_translation): Raise exception InstructionFetch when
1546 translation fails and isINSTRUCTION.
1548 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1549 sim_engine_run): Change type of of vaddr and paddr to
1551 (address_translation, prefetch, load_memory, store_memory,
1552 cache_op): Change type of vAddr and pAddr to address_word.
1554 * gencode.c (build_instruction): Change type of vaddr and paddr to
1557 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1560 macro to obtain result of ALU op.
1562 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * interp.c (sim_info): Call profile_print.
1566 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1568 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1570 * sim-main.h (WITH_PROFILE): Do not define, defined in
1571 common/sim-config.h. Use sim-profile module.
1572 (simPROFILE): Delete defintion.
1574 * interp.c (PROFILE): Delete definition.
1575 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1576 (sim_close): Delete code writing profile histogram.
1577 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1579 (sim_engine_run): Delete code profiling the PC.
1581 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1583 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1585 * interp.c (sim_monitor): Make register pointers of type
1588 * sim-main.h: Make registers of type unsigned_word not
1591 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1593 start-sanitize-r5900
1594 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1595 ...): Move to sim-main.h
1598 * interp.c (sync_operation): Rename from SyncOperation, make
1599 global, add SD argument.
1600 (prefetch): Rename from Prefetch, make global, add SD argument.
1601 (decode_coproc): Make global.
1603 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1605 * gencode.c (build_instruction): Generate DecodeCoproc not
1606 decode_coproc calls.
1608 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1609 (SizeFGR): Move to sim-main.h
1610 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1611 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1612 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1614 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1615 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1616 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1617 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1618 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1619 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1621 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1623 (sim-alu.h): Include.
1624 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1625 (sim_cia): Typedef to instruction_address.
1627 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1629 * Makefile.in (interp.o): Rename generated file engine.c to
1634 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1638 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640 * gencode.c (build_instruction): For "FPSQRT", output correct
1641 number of arguments to Recip.
1643 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1645 * Makefile.in (interp.o): Depends on sim-main.h
1647 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1649 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1650 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1651 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1652 STATE, DSSTATE): Define
1653 (GPR, FGRIDX, ..): Define.
1655 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1656 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1657 (GPR, FGRIDX, ...): Delete macros.
1659 * interp.c: Update names to match defines from sim-main.h
1661 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * interp.c (sim_monitor): Add SD argument.
1664 (sim_warning): Delete. Replace calls with calls to
1666 (sim_error): Delete. Replace calls with sim_io_error.
1667 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1668 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1669 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1671 (mips_size): Rename from sim_size. Add SD argument.
1673 * interp.c (simulator): Delete global variable.
1674 (callback): Delete global variable.
1675 (mips_option_handler, sim_open, sim_write, sim_read,
1676 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1677 sim_size,sim_monitor): Use sim_io_* not callback->*.
1678 (sim_open): ZALLOC simulator struct.
1679 (PROFILE): Do not define.
1681 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1683 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1684 support.h with corresponding code.
1686 * sim-main.h (word64, uword64), support.h: Move definition to
1688 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1691 * Makefile.in: Update dependencies
1692 * interp.c: Do not include.
1694 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696 * interp.c (address_translation, load_memory, store_memory,
1697 cache_op): Rename to from AddressTranslation et.al., make global,
1700 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1703 * interp.c (SignalException): Rename to signal_exception, make
1706 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1708 * sim-main.h (SignalException, SignalExceptionInterrupt,
1709 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1710 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1711 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1714 * interp.c, support.h: Use.
1716 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1718 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1719 to value_fpr / store_fpr. Add SD argument.
1720 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1721 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1723 * sim-main.h (ValueFPR, StoreFPR): Define.
1725 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * interp.c (sim_engine_run): Check consistency between configure
1728 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1731 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1732 (mips_fpu): Configure WITH_FLOATING_POINT.
1733 (mips_endian): Configure WITH_TARGET_ENDIAN.
1734 * configure: Update.
1736 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1738 * configure: Regenerated to track ../common/aclocal.m4 changes.
1740 start-sanitize-r5900
1741 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743 * interp.c (MAX_REG): Allow up-to 128 registers.
1744 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1745 (REGISTER_SA): Ditto.
1746 (sim_open): Initialize register_widths for r5900 specific
1748 (sim_fetch_register, sim_store_register): Check for request of
1749 r5900 specific SA register. Check for request for hi 64 bits of
1750 r5900 specific registers.
1753 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1755 * configure: Regenerated.
1757 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1759 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1761 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1763 * gencode.c (print_igen_insn_models): Assume certain architectures
1764 include all mips* instructions.
1765 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1768 * Makefile.in (tmp.igen): Add target. Generate igen input from
1771 * gencode.c (FEATURE_IGEN): Define.
1772 (main): Add --igen option. Generate output in igen format.
1773 (process_instructions): Format output according to igen option.
1774 (print_igen_insn_format): New function.
1775 (print_igen_insn_models): New function.
1776 (process_instructions): Only issue warnings and ignore
1777 instructions when no FEATURE_IGEN.
1779 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1784 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786 * configure: Regenerated to track ../common/aclocal.m4 changes.
1788 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1790 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1791 SIM_RESERVED_BITS): Delete, moved to common.
1792 (SIM_EXTRA_CFLAGS): Update.
1794 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796 * configure.in: Configure non-strict memory alignment.
1797 * configure: Regenerated to track ../common/aclocal.m4 changes.
1799 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1801 * configure: Regenerated to track ../common/aclocal.m4 changes.
1803 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1805 * gencode.c (SDBBP,DERET): Added (3900) insns.
1806 (RFE): Turn on for 3900.
1807 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1808 (dsstate): Made global.
1809 (SUBTARGET_R3900): Added.
1810 (CANCELDELAYSLOT): New.
1811 (SignalException): Ignore SystemCall rather than ignore and
1812 terminate. Add DebugBreakPoint handling.
1813 (decode_coproc): New insns RFE, DERET; and new registers Debug
1814 and DEPC protected by SUBTARGET_R3900.
1815 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1817 * Makefile.in,configure.in: Add mips subtarget option.
1818 * configure: Update.
1820 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1822 * gencode.c: Add r3900 (tx39).
1825 * gencode.c: Fix some configuration problems by improving
1826 the relationship between tx19 and tx39.
1829 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1831 * gencode.c (build_instruction): Don't need to subtract 4 for
1834 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1836 * interp.c: Correct some HASFPU problems.
1838 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * configure: Regenerated to track ../common/aclocal.m4 changes.
1842 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1844 * interp.c (mips_options): Fix samples option short form, should
1847 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849 * interp.c (sim_info): Enable info code. Was just returning.
1851 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1853 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1856 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1860 (build_instruction): Ditto for LL.
1863 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1865 * mips/configure.in, mips/gencode: Add tx19/r1900.
1868 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1870 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872 start-sanitize-r5900
1873 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1876 for overflow due to ABS of MININT, set result to MAXINT.
1877 (build_instruction): For "psrlvw", signextend bit 31.
1880 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1882 * configure: Regenerated to track ../common/aclocal.m4 changes.
1885 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1887 * interp.c (sim_open): Add call to sim_analyze_program, update
1890 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1892 * interp.c (sim_kill): Delete.
1893 (sim_create_inferior): Add ABFD argument. Set PC from same.
1894 (sim_load): Move code initializing trap handlers from here.
1895 (sim_open): To here.
1896 (sim_load): Delete, use sim-hload.c.
1898 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1900 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * configure: Regenerated to track ../common/aclocal.m4 changes.
1905 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907 * interp.c (sim_open): Add ABFD argument.
1908 (sim_load): Move call to sim_config from here.
1909 (sim_open): To here. Check return status.
1911 start-sanitize-r5900
1912 * gencode.c (build_instruction): Do not define x8000000000000000,
1913 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1916 start-sanitize-r5900
1917 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1919 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1920 "pdivuw" check for overflow due to signed divide by -1.
1923 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1925 * gencode.c (build_instruction): Two arg MADD should
1926 not assign result to $0.
1928 start-sanitize-r5900
1929 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1931 * gencode.c (build_instruction): For "ppac5" use unsigned
1932 arrithmetic so that the sign bit doesn't smear when right shifted.
1933 (build_instruction): For "pdiv" perform sign extension when
1934 storing results in HI and LO.
1935 (build_instructions): For "pdiv" and "pdivbw" check for
1937 (build_instruction): For "pmfhl.slw" update hi part of dest
1938 register as well as low part.
1939 (build_instruction): For "pmfhl" portably handle long long values.
1940 (build_instruction): For "pmfhl.sh" correctly negative values.
1941 Store half words 2 and three in the correct place.
1942 (build_instruction): For "psllvw", sign extend value after shift.
1945 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1947 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1948 * sim/mips/configure.in: Regenerate.
1950 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1952 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1953 signed8, unsigned8 et.al. types.
1955 start-sanitize-r5900
1956 * gencode.c (build_instruction): For PMULTU* do not sign extend
1957 registers. Make generated code easier to debug.
1960 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1961 hosts when selecting subreg.
1963 start-sanitize-r5900
1964 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1966 * gencode.c (type_for_data_len): For 32bit operations concerned
1967 with overflow, perform op using 64bits.
1968 (build_instruction): For PADD, always compute operation using type
1969 returned by type_for_data_len.
1970 (build_instruction): For PSUBU, when overflow, saturate to zero as
1974 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1976 start-sanitize-r5900
1977 * gencode.c (build_instruction): Handle "pext5" according to
1978 version 1.95 of the r5900 ISA.
1980 * gencode.c (build_instruction): Handle "ppac5" according to
1981 version 1.95 of the r5900 ISA.
1984 * interp.c (sim_engine_run): Reset the ZERO register to zero
1985 regardless of FEATURE_WARN_ZERO.
1986 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1988 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1990 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1991 (SignalException): For BreakPoints ignore any mode bits and just
1993 (SignalException): Always set the CAUSE register.
1995 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1997 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1998 exception has been taken.
2000 * interp.c: Implement the ERET and mt/f sr instructions.
2002 start-sanitize-r5900
2003 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005 * gencode.c (build_instruction): For paddu, extract unsigned
2008 * gencode.c (build_instruction): Saturate padds instead of padd
2012 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014 * interp.c (SignalException): Don't bother restarting an
2017 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2019 * interp.c (SignalException): Really take an interrupt.
2020 (interrupt_event): Only deliver interrupts when enabled.
2022 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024 * interp.c (sim_info): Only print info when verbose.
2025 (sim_info) Use sim_io_printf for output.
2027 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2032 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2034 * interp.c (sim_do_command): Check for common commands if a
2035 simulator specific command fails.
2037 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2039 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2040 and simBE when DEBUG is defined.
2042 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2044 * interp.c (interrupt_event): New function. Pass exception event
2045 onto exception handler.
2047 * configure.in: Check for stdlib.h.
2048 * configure: Regenerate.
2050 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2051 variable declaration.
2052 (build_instruction): Initialize memval1.
2053 (build_instruction): Add UNUSED attribute to byte, bigend,
2055 (build_operands): Ditto.
2057 * interp.c: Fix GCC warnings.
2058 (sim_get_quit_code): Delete.
2060 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2061 * Makefile.in: Ditto.
2062 * configure: Re-generate.
2064 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2066 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2068 * interp.c (mips_option_handler): New function parse argumes using
2070 (myname): Replace with STATE_MY_NAME.
2071 (sim_open): Delete check for host endianness - performed by
2073 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2074 (sim_open): Move much of the initialization from here.
2075 (sim_load): To here. After the image has been loaded and
2077 (sim_open): Move ColdReset from here.
2078 (sim_create_inferior): To here.
2079 (sim_open): Make FP check less dependant on host endianness.
2081 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2083 * interp.c (sim_set_callbacks): Delete.
2085 * interp.c (membank, membank_base, membank_size): Replace with
2086 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2087 (sim_open): Remove call to callback->init. gdb/run do this.
2091 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2093 * interp.c (big_endian_p): Delete, replaced by
2094 current_target_byte_order.
2096 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098 * interp.c (host_read_long, host_read_word, host_swap_word,
2099 host_swap_long): Delete. Using common sim-endian.
2100 (sim_fetch_register, sim_store_register): Use H2T.
2101 (pipeline_ticks): Delete. Handled by sim-events.
2103 (sim_engine_run): Update.
2105 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2109 (SignalException): To here. Signal using sim_engine_halt.
2110 (sim_stop_reason): Delete, moved to common.
2112 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2114 * interp.c (sim_open): Add callback argument.
2115 (sim_set_callbacks): Delete SIM_DESC argument.
2118 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120 * Makefile.in (SIM_OBJS): Add common modules.
2122 * interp.c (sim_set_callbacks): Also set SD callback.
2123 (set_endianness, xfer_*, swap_*): Delete.
2124 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2125 Change to functions using sim-endian macros.
2126 (control_c, sim_stop): Delete, use common version.
2127 (simulate): Convert into.
2128 (sim_engine_run): This function.
2129 (sim_resume): Delete.
2131 * interp.c (simulation): New variable - the simulator object.
2132 (sim_kind): Delete global - merged into simulation.
2133 (sim_load): Cleanup. Move PC assignment from here.
2134 (sim_create_inferior): To here.
2136 * sim-main.h: New file.
2137 * interp.c (sim-main.h): Include.
2139 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2141 * configure: Regenerated to track ../common/aclocal.m4 changes.
2143 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2145 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2147 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2149 * gencode.c (build_instruction): DIV instructions: check
2150 for division by zero and integer overflow before using
2151 host's division operation.
2153 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2155 * Makefile.in (SIM_OBJS): Add sim-load.o.
2156 * interp.c: #include bfd.h.
2157 (target_byte_order): Delete.
2158 (sim_kind, myname, big_endian_p): New static locals.
2159 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2160 after argument parsing. Recognize -E arg, set endianness accordingly.
2161 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2162 load file into simulator. Set PC from bfd.
2163 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2164 (set_endianness): Use big_endian_p instead of target_byte_order.
2166 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168 * interp.c (sim_size): Delete prototype - conflicts with
2169 definition in remote-sim.h. Correct definition.
2171 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2173 * configure: Regenerated to track ../common/aclocal.m4 changes.
2176 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2178 * interp.c (sim_open): New arg `kind'.
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2184 * configure: Regenerated to track ../common/aclocal.m4 changes.
2186 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2188 * interp.c (sim_open): Set optind to 0 before calling getopt.
2190 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2192 * configure: Regenerated to track ../common/aclocal.m4 changes.
2194 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2196 * interp.c : Replace uses of pr_addr with pr_uword64
2197 where the bit length is always 64 independent of SIM_ADDR.
2198 (pr_uword64) : added.
2200 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2202 * configure: Re-generate.
2204 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2206 * configure: Regenerate to track ../common/aclocal.m4 changes.
2208 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2210 * interp.c (sim_open): New SIM_DESC result. Argument is now
2212 (other sim_*): New SIM_DESC argument.
2214 start-sanitize-r5900
2215 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2217 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2218 Change values to avoid overloading DOUBLEWORD which is tested
2220 * gencode.c: reinstate "offending code".
2223 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2225 * interp.c: Fix printing of addresses for non-64-bit targets.
2226 (pr_addr): Add function to print address based on size.
2227 start-sanitize-r5900
2228 * gencode.c: #ifdef out offending code until a permanent fix
2229 can be added. Code is causing build errors for non-5900 mips targets.
2232 start-sanitize-r5900
2233 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2235 * gencode.c (process_instructions): Correct test for ISA dependent
2236 architecture bits in isa field of MIPS_DECODE.
2239 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2241 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2243 start-sanitize-r5900
2244 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2246 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2250 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2252 * gencode.c (build_mips16_operands): Correct computation of base
2253 address for extended PC relative instruction.
2255 start-sanitize-r5900
2256 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2258 * Makefile.in, configure, configure.in, gencode.c,
2259 interp.c, support.h: add r5900.
2262 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2264 * interp.c (mips16_entry): Add support for floating point cases.
2265 (SignalException): Pass floating point cases to mips16_entry.
2266 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2268 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2270 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2271 and then set the state to fmt_uninterpreted.
2272 (COP_SW): Temporarily set the state to fmt_word while calling
2275 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2277 * gencode.c (build_instruction): The high order may be set in the
2278 comparison flags at any ISA level, not just ISA 4.
2280 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2282 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2283 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2284 * configure.in: sinclude ../common/aclocal.m4.
2285 * configure: Regenerated.
2287 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2289 * configure: Rebuild after change to aclocal.m4.
2291 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2293 * configure configure.in Makefile.in: Update to new configure
2294 scheme which is more compatible with WinGDB builds.
2295 * configure.in: Improve comment on how to run autoconf.
2296 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2297 * Makefile.in: Use autoconf substitution to install common
2300 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2302 * gencode.c (build_instruction): Use BigEndianCPU instead of
2305 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2307 * interp.c (sim_monitor): Make output to stdout visible in
2308 wingdb's I/O log window.
2310 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2312 * support.h: Undo previous change to SIGTRAP
2315 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2317 * interp.c (store_word, load_word): New static functions.
2318 (mips16_entry): New static function.
2319 (SignalException): Look for mips16 entry and exit instructions.
2320 (simulate): Use the correct index when setting fpr_state after
2321 doing a pending move.
2323 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2325 * interp.c: Fix byte-swapping code throughout to work on
2326 both little- and big-endian hosts.
2328 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2330 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2331 with gdb/config/i386/xm-windows.h.
2333 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2335 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2336 that messes up arithmetic shifts.
2338 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2340 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2341 SIGTRAP and SIGQUIT for _WIN32.
2343 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2345 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2346 force a 64 bit multiplication.
2347 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2348 destination register is 0, since that is the default mips16 nop
2351 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2353 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2354 (build_endian_shift): Don't check proc64.
2355 (build_instruction): Always set memval to uword64. Cast op2 to
2356 uword64 when shifting it left in memory instructions. Always use
2357 the same code for stores--don't special case proc64.
2359 * gencode.c (build_mips16_operands): Fix base PC value for PC
2361 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2363 * interp.c (simJALDELAYSLOT): Define.
2364 (JALDELAYSLOT): Define.
2365 (INDELAYSLOT, INJALDELAYSLOT): Define.
2366 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2368 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2370 * interp.c (sim_open): add flush_cache as a PMON routine
2371 (sim_monitor): handle flush_cache by ignoring it
2373 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2375 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2377 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2378 (BigEndianMem): Rename to ByteSwapMem and change sense.
2379 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2380 BigEndianMem references to !ByteSwapMem.
2381 (set_endianness): New function, with prototype.
2382 (sim_open): Call set_endianness.
2383 (sim_info): Use simBE instead of BigEndianMem.
2384 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2385 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2386 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2387 ifdefs, keeping the prototype declaration.
2388 (swap_word): Rewrite correctly.
2389 (ColdReset): Delete references to CONFIG. Delete endianness related
2390 code; moved to set_endianness.
2392 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2394 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2395 * interp.c (CHECKHILO): Define away.
2396 (simSIGINT): New macro.
2397 (membank_size): Increase from 1MB to 2MB.
2398 (control_c): New function.
2399 (sim_resume): Rename parameter signal to signal_number. Add local
2400 variable prev. Call signal before and after simulate.
2401 (sim_stop_reason): Add simSIGINT support.
2402 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2404 (sim_warning): Delete call to SignalException. Do call printf_filtered
2406 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2407 a call to sim_warning.
2409 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2411 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2412 16 bit instructions.
2414 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2416 Add support for mips16 (16 bit MIPS implementation):
2417 * gencode.c (inst_type): Add mips16 instruction encoding types.
2418 (GETDATASIZEINSN): Define.
2419 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2420 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2422 (MIPS16_DECODE): New table, for mips16 instructions.
2423 (bitmap_val): New static function.
2424 (struct mips16_op): Define.
2425 (mips16_op_table): New table, for mips16 operands.
2426 (build_mips16_operands): New static function.
2427 (process_instructions): If PC is odd, decode a mips16
2428 instruction. Break out instruction handling into new
2429 build_instruction function.
2430 (build_instruction): New static function, broken out of
2431 process_instructions. Check modifiers rather than flags for SHIFT
2432 bit count and m[ft]{hi,lo} direction.
2433 (usage): Pass program name to fprintf.
2434 (main): Remove unused variable this_option_optind. Change
2435 ``*loptarg++'' to ``loptarg++''.
2436 (my_strtoul): Parenthesize && within ||.
2437 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2438 (simulate): If PC is odd, fetch a 16 bit instruction, and
2439 increment PC by 2 rather than 4.
2440 * configure.in: Add case for mips16*-*-*.
2441 * configure: Rebuild.
2443 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2445 * interp.c: Allow -t to enable tracing in standalone simulator.
2446 Fix garbage output in trace file and error messages.
2448 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2450 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2451 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2452 * configure.in: Simplify using macros in ../common/aclocal.m4.
2453 * configure: Regenerated.
2454 * tconfig.in: New file.
2456 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2458 * interp.c: Fix bugs in 64-bit port.
2459 Use ansi function declarations for msvc compiler.
2460 Initialize and test file pointer in trace code.
2461 Prevent duplicate definition of LAST_EMED_REGNUM.
2463 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2465 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2467 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2469 * interp.c (SignalException): Check for explicit terminating
2471 * gencode.c: Pass instruction value through SignalException()
2472 calls for Trap, Breakpoint and Syscall.
2474 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2476 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2477 only used on those hosts that provide it.
2478 * configure.in: Add sqrt() to list of functions to be checked for.
2479 * config.in: Re-generated.
2480 * configure: Re-generated.
2482 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2484 * gencode.c (process_instructions): Call build_endian_shift when
2485 expanding STORE RIGHT, to fix swr.
2486 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2487 clear the high bits.
2488 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2489 Fix float to int conversions to produce signed values.
2491 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2493 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2494 (process_instructions): Correct handling of nor instruction.
2495 Correct shift count for 32 bit shift instructions. Correct sign
2496 extension for arithmetic shifts to not shift the number of bits in
2497 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2498 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2500 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2501 It's OK to have a mult follow a mult. What's not OK is to have a
2502 mult follow an mfhi.
2503 (Convert): Comment out incorrect rounding code.
2505 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2507 * interp.c (sim_monitor): Improved monitor printf
2508 simulation. Tidied up simulator warnings, and added "--log" option
2509 for directing warning message output.
2510 * gencode.c: Use sim_warning() rather than WARNING macro.
2512 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2514 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2515 getopt1.o, rather than on gencode.c. Link objects together.
2516 Don't link against -liberty.
2517 (gencode.o, getopt.o, getopt1.o): New targets.
2518 * gencode.c: Include <ctype.h> and "ansidecl.h".
2519 (AND): Undefine after including "ansidecl.h".
2520 (ULONG_MAX): Define if not defined.
2521 (OP_*): Don't define macros; now defined in opcode/mips.h.
2522 (main): Call my_strtoul rather than strtoul.
2523 (my_strtoul): New static function.
2525 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2527 * gencode.c (process_instructions): Generate word64 and uword64
2528 instead of `long long' and `unsigned long long' data types.
2529 * interp.c: #include sysdep.h to get signals, and define default
2531 * (Convert): Work around for Visual-C++ compiler bug with type
2533 * support.h: Make things compile under Visual-C++ by using
2534 __int64 instead of `long long'. Change many refs to long long
2535 into word64/uword64 typedefs.
2537 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2539 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2540 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2542 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2543 (AC_PROG_INSTALL): Added.
2544 (AC_PROG_CC): Moved to before configure.host call.
2545 * configure: Rebuilt.
2547 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2549 * configure.in: Define @SIMCONF@ depending on mips target.
2550 * configure: Rebuild.
2551 * Makefile.in (run): Add @SIMCONF@ to control simulator
2553 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2554 * interp.c: Remove some debugging, provide more detailed error
2555 messages, update memory accesses to use LOADDRMASK.
2557 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2559 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2560 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2562 * configure: Rebuild.
2563 * config.in: New file, generated by autoheader.
2564 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2565 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2566 HAVE_ANINT and HAVE_AINT, as appropriate.
2567 * Makefile.in (run): Use @LIBS@ rather than -lm.
2568 (interp.o): Depend upon config.h.
2569 (Makefile): Just rebuild Makefile.
2570 (clean): Remove stamp-h.
2571 (mostlyclean): Make the same as clean, not as distclean.
2572 (config.h, stamp-h): New targets.
2574 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2576 * interp.c (ColdReset): Fix boolean test. Make all simulator
2579 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2581 * interp.c (xfer_direct_word, xfer_direct_long,
2582 swap_direct_word, swap_direct_long, xfer_big_word,
2583 xfer_big_long, xfer_little_word, xfer_little_long,
2584 swap_word,swap_long): Added.
2585 * interp.c (ColdReset): Provide function indirection to
2586 host<->simulated_target transfer routines.
2587 * interp.c (sim_store_register, sim_fetch_register): Updated to
2588 make use of indirected transfer routines.
2590 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2592 * gencode.c (process_instructions): Ensure FP ABS instruction
2594 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2595 system call support.
2597 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2599 * interp.c (sim_do_command): Complain if callback structure not
2602 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2604 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2605 support for Sun hosts.
2606 * Makefile.in (gencode): Ensure the host compiler and libraries
2607 used for cross-hosted build.
2609 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2611 * interp.c, gencode.c: Some more (TODO) tidying.
2613 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2615 * gencode.c, interp.c: Replaced explicit long long references with
2616 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2617 * support.h (SET64LO, SET64HI): Macros added.
2619 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2621 * configure: Regenerate with autoconf 2.7.
2623 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2625 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2626 * support.h: Remove superfluous "1" from #if.
2627 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2629 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2631 * interp.c (StoreFPR): Control UndefinedResult() call on
2632 WARN_RESULT manifest.
2634 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2636 * gencode.c: Tidied instruction decoding, and added FP instruction
2639 * interp.c: Added dineroIII, and BSD profiling support. Also
2640 run-time FP handling.
2642 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2644 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2645 gencode.c, interp.c, support.h: created.