1 2002-02-24 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen: Fix formatting of calls to Unpredictable().
5 2002-04-20 Andrew Cagney <ac131313@redhat.com>
7 * interp.c (sim_open): Revert previous change.
9 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
11 * interp.c (sim_open): Disable chunk of code that wrote code in
14 2002-03-19 Chris Demetriou <cgd@broadcom.com>
16 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
17 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
20 2002-03-19 Chris Demetriou <cgd@broadcom.com>
22 * cp1.c: Fix many formatting issues.
24 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
26 * cp1.c (fpu_format_name): New function to replace...
27 (DOFMT): This. Delete, and update all callers.
28 (fpu_rounding_mode_name): New function to replace...
29 (RMMODE): This. Delete, and update all callers.
31 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
33 * interp.c: Move FPU support routines from here to...
34 * cp1.c: Here. New file.
35 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
38 2002-03-12 Chris Demetriou <cgd@broadcom.com>
40 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
41 * mips.igen (mips32, mips64): New models, add to all instructions
42 and functions as appropriate.
43 (loadstore_ea, check_u64): New variant for model mips64.
44 (check_fmt_p): New variant for models mipsV and mips64, remove
45 mipsV model marking fro other variant.
48 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
49 for mips32 and mips64.
50 (DCLO, DCLZ): New instructions for mips64.
52 2002-03-07 Chris Demetriou <cgd@broadcom.com>
54 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
55 immediate or code as a hex value with the "%#lx" format.
56 (ANDI): Likewise, and fix printed instruction name.
58 2002-03-05 Chris Demetriou <cgd@broadcom.com>
60 * sim-main.h (UndefinedResult, Unpredictable): New macros
61 which currently do nothing.
63 2002-03-05 Chris Demetriou <cgd@broadcom.com>
65 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
66 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
67 (status_CU3): New definitions.
69 * sim-main.h (ExceptionCause): Add new values for MIPS32
70 and MIPS64: MDMX, MCheck, CacheErr. Update comments
71 for DebugBreakPoint and NMIReset to note their status in
73 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
74 (SignalExceptionCacheErr): New exception macros.
76 2002-03-05 Chris Demetriou <cgd@broadcom.com>
78 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
79 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
81 (SignalExceptionCoProcessorUnusable): Take as argument the
82 unusable coprocessor number.
84 2002-03-05 Chris Demetriou <cgd@broadcom.com>
86 * mips.igen: Fix formatting of all SignalException calls.
88 2002-03-05 Chris Demetriou <cgd@broadcom.com>
90 * sim-main.h (SIGNEXTEND): Remove.
92 2002-03-04 Chris Demetriou <cgd@broadcom.com>
94 * mips.igen: Remove gencode comment from top of file, fix
95 spelling in another comment.
97 2002-03-04 Chris Demetriou <cgd@broadcom.com>
99 * mips.igen (check_fmt, check_fmt_p): New functions to check
100 whether specific floating point formats are usable.
101 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
102 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
103 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
104 Use the new functions.
105 (do_c_cond_fmt): Remove format checks...
106 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
108 2002-03-03 Chris Demetriou <cgd@broadcom.com>
110 * mips.igen: Fix formatting of check_fpu calls.
112 2002-03-03 Chris Demetriou <cgd@broadcom.com>
114 * mips.igen (FLOOR.L.fmt): Store correct destination register.
116 2002-03-03 Chris Demetriou <cgd@broadcom.com>
118 * mips.igen: Remove whitespace at end of lines.
120 2002-03-02 Chris Demetriou <cgd@broadcom.com>
122 * mips.igen (loadstore_ea): New function to do effective
123 address calculations.
124 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
125 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
126 CACHE): Use loadstore_ea to do effective address computations.
128 2002-03-02 Chris Demetriou <cgd@broadcom.com>
130 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
131 * mips.igen (LL, CxC1, MxC1): Likewise.
133 2002-03-02 Chris Demetriou <cgd@broadcom.com>
135 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
136 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
137 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
138 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
139 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
140 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
141 Don't split opcode fields by hand, use the opcode field values
144 2002-03-01 Chris Demetriou <cgd@broadcom.com>
146 * mips.igen (do_divu): Fix spacing.
148 * mips.igen (do_dsllv): Move to be right before DSLLV,
149 to match the rest of the do_<shift> functions.
151 2002-03-01 Chris Demetriou <cgd@broadcom.com>
153 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
154 DSRL32, do_dsrlv): Trace inputs and results.
156 2002-03-01 Chris Demetriou <cgd@broadcom.com>
158 * mips.igen (CACHE): Provide instruction-printing string.
160 * interp.c (signal_exception): Comment tokens after #endif.
162 2002-02-28 Chris Demetriou <cgd@broadcom.com>
164 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
165 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
166 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
167 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
168 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
169 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
170 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
171 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
173 2002-02-28 Chris Demetriou <cgd@broadcom.com>
175 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
176 instruction-printing string.
177 (LWU): Use '64' as the filter flag.
179 2002-02-28 Chris Demetriou <cgd@broadcom.com>
181 * mips.igen (SDXC1): Fix instruction-printing string.
183 2002-02-28 Chris Demetriou <cgd@broadcom.com>
185 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
188 2002-02-27 Chris Demetriou <cgd@broadcom.com>
190 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
193 2002-02-27 Chris Demetriou <cgd@broadcom.com>
195 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
196 add a comma) so that it more closely match the MIPS ISA
197 documentation opcode partitioning.
198 (PREF): Put useful names on opcode fields, and include
199 instruction-printing string.
201 2002-02-27 Chris Demetriou <cgd@broadcom.com>
203 * mips.igen (check_u64): New function which in the future will
204 check whether 64-bit instructions are usable and signal an
205 exception if not. Currently a no-op.
206 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
207 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
208 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
209 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
211 * mips.igen (check_fpu): New function which in the future will
212 check whether FPU instructions are usable and signal an exception
213 if not. Currently a no-op.
214 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
215 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
216 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
217 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
218 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
219 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
220 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
221 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
223 2002-02-27 Chris Demetriou <cgd@broadcom.com>
225 * mips.igen (do_load_left, do_load_right): Move to be immediately
227 (do_store_left, do_store_right): Move to be immediately following
230 2002-02-27 Chris Demetriou <cgd@broadcom.com>
232 * mips.igen (mipsV): New model name. Also, add it to
233 all instructions and functions where it is appropriate.
235 2002-02-18 Chris Demetriou <cgd@broadcom.com>
237 * mips.igen: For all functions and instructions, list model
238 names that support that instruction one per line.
240 2002-02-11 Chris Demetriou <cgd@broadcom.com>
242 * mips.igen: Add some additional comments about supported
243 models, and about which instructions go where.
244 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
245 order as is used in the rest of the file.
247 2002-02-11 Chris Demetriou <cgd@broadcom.com>
249 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
250 indicating that ALU32_END or ALU64_END are there to check
252 (DADD): Likewise, but also remove previous comment about
255 2002-02-10 Chris Demetriou <cgd@broadcom.com>
257 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
258 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
259 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
260 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
261 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
262 fields (i.e., add and move commas) so that they more closely
263 match the MIPS ISA documentation opcode partitioning.
265 2002-02-10 Chris Demetriou <cgd@broadcom.com>
267 * mips.igen (ADDI): Print immediate value.
269 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
270 (SLL): Print "nop" specially, and don't run the code
271 that does the shift for the "nop" case.
273 2001-11-17 Fred Fish <fnf@redhat.com>
275 * sim-main.h (float_operation): Move enum declaration outside
276 of _sim_cpu struct declaration.
278 2001-04-12 Jim Blandy <jimb@redhat.com>
280 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
281 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
283 * sim-main.h (COCIDX): Remove definition; this isn't supported by
284 PENDING_FILL, and you can get the intended effect gracefully by
285 calling PENDING_SCHED directly.
287 2001-02-23 Ben Elliston <bje@redhat.com>
289 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
290 already defined elsewhere.
292 2001-02-19 Ben Elliston <bje@redhat.com>
294 * sim-main.h (sim_monitor): Return an int.
295 * interp.c (sim_monitor): Add return values.
296 (signal_exception): Handle error conditions from sim_monitor.
298 2001-02-08 Ben Elliston <bje@redhat.com>
300 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
301 (store_memory): Likewise, pass cia to sim_core_write*.
303 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
305 On advice from Chris G. Demetriou <cgd@sibyte.com>:
306 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
308 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
310 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
311 * Makefile.in: Don't delete *.igen when cleaning directory.
313 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
315 * m16.igen (break): Call SignalException not sim_engine_halt.
317 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
320 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
322 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
324 * mips.igen (MxC1, DMxC1): Fix printf formatting.
326 2000-05-24 Michael Hayes <mhayes@cygnus.com>
328 * mips.igen (do_dmultx): Fix typo.
330 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
332 * configure: Regenerated to track ../common/aclocal.m4 changes.
334 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
336 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
338 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
340 * sim-main.h (GPR_CLEAR): Define macro.
342 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
344 * interp.c (decode_coproc): Output long using %lx and not %s.
346 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
348 * interp.c (sim_open): Sort & extend dummy memory regions for
349 --board=jmr3904 for eCos.
351 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
353 * configure: Regenerated.
355 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
357 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
358 calls, conditional on the simulator being in verbose mode.
360 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
362 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
363 cache don't get ReservedInstruction traps.
365 1999-11-29 Mark Salter <msalter@cygnus.com>
367 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
368 to clear status bits in sdisr register. This is how the hardware works.
370 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
371 being used by cygmon.
373 1999-11-11 Andrew Haley <aph@cygnus.com>
375 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
378 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
380 * mips.igen (MULT): Correct previous mis-applied patch.
382 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
384 * mips.igen (delayslot32): Handle sequence like
385 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
386 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
387 (MULT): Actually pass the third register...
389 1999-09-03 Mark Salter <msalter@cygnus.com>
391 * interp.c (sim_open): Added more memory aliases for additional
392 hardware being touched by cygmon on jmr3904 board.
394 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
396 * configure: Regenerated to track ../common/aclocal.m4 changes.
398 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
400 * interp.c (sim_store_register): Handle case where client - GDB -
401 specifies that a 4 byte register is 8 bytes in size.
402 (sim_fetch_register): Ditto.
404 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
406 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
407 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
408 (idt_monitor_base): Base address for IDT monitor traps.
409 (pmon_monitor_base): Ditto for PMON.
410 (lsipmon_monitor_base): Ditto for LSI PMON.
411 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
412 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
413 (sim_firmware_command): New function.
414 (mips_option_handler): Call it for OPTION_FIRMWARE.
415 (sim_open): Allocate memory for idt_monitor region. If "--board"
416 option was given, add no monitor by default. Add BREAK hooks only if
417 monitors are also there.
419 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
421 * interp.c (sim_monitor): Flush output before reading input.
423 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
425 * tconfig.in (SIM_HANDLES_LMA): Always define.
427 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
429 From Mark Salter <msalter@cygnus.com>:
430 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
431 (sim_open): Add setup for BSP board.
433 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
435 * mips.igen (MULT, MULTU): Add syntax for two operand version.
436 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
437 them as unimplemented.
439 1999-05-08 Felix Lee <flee@cygnus.com>
441 * configure: Regenerated to track ../common/aclocal.m4 changes.
443 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
445 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
447 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
449 * configure.in: Any mips64vr5*-*-* target should have
450 -DTARGET_ENABLE_FR=1.
451 (default_endian): Any mips64vr*el-*-* target should default to
453 * configure: Re-generate.
455 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
457 * mips.igen (ldl): Extend from _16_, not 32.
459 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
461 * interp.c (sim_store_register): Force registers written to by GDB
462 into an un-interpreted state.
464 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
466 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
467 CPU, start periodic background I/O polls.
468 (tx3904sio_poll): New function: periodic I/O poller.
470 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
472 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
474 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
476 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
479 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
481 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
482 (load_word): Call SIM_CORE_SIGNAL hook on error.
483 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
484 starting. For exception dispatching, pass PC instead of NULL_CIA.
485 (decode_coproc): Use COP0_BADVADDR to store faulting address.
486 * sim-main.h (COP0_BADVADDR): Define.
487 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
488 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
489 (_sim_cpu): Add exc_* fields to store register value snapshots.
490 * mips.igen (*): Replace memory-related SignalException* calls
491 with references to SIM_CORE_SIGNAL hook.
493 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
495 * sim-main.c (*): Minor warning cleanups.
497 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
499 * m16.igen (DADDIU5): Correct type-o.
501 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
503 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
506 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
508 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
510 (interp.o): Add dependency on itable.h
511 (oengine.c, gencode): Delete remaining references.
512 (BUILT_SRC_FROM_GEN): Clean up.
514 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
517 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
518 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
520 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
521 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
522 Drop the "64" qualifier to get the HACK generator working.
523 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
524 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
525 qualifier to get the hack generator working.
526 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
528 (DSLLV): Use do_dsllv.
531 (DSRLV): Use do_dsrlv.
532 (BC1): Move *vr4100 to get the HACK generator working.
533 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
534 get the HACK generator working.
535 (MACC) Rename to get the HACK generator working.
536 (DMACC,MACCS,DMACCS): Add the 64.
538 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
540 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
541 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
543 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
545 * mips/interp.c (DEBUG): Cleanups.
547 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
549 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
550 (tx3904sio_tickle): fflush after a stdout character output.
552 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
554 * interp.c (sim_close): Uninstall modules.
556 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
558 * sim-main.h, interp.c (sim_monitor): Change to global
561 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
563 * configure.in (vr4100): Only include vr4100 instructions in
565 * configure: Re-generate.
566 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
568 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
570 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
571 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
574 * configure.in (sim_default_gen, sim_use_gen): Replace with
576 (--enable-sim-igen): Delete config option. Always using IGEN.
577 * configure: Re-generate.
579 * Makefile.in (gencode): Kill, kill, kill.
582 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
584 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
585 bit mips16 igen simulator.
586 * configure: Re-generate.
588 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
589 as part of vr4100 ISA.
590 * vr.igen: Mark all instructions as 64 bit only.
592 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
594 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
597 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
599 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
600 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
601 * configure: Re-generate.
603 * m16.igen (BREAK): Define breakpoint instruction.
604 (JALX32): Mark instruction as mips16 and not r3900.
605 * mips.igen (C.cond.fmt): Fix typo in instruction format.
607 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
609 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
611 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
612 insn as a debug breakpoint.
614 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
616 (PENDING_SCHED): Clean up trace statement.
617 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
618 (PENDING_FILL): Delay write by only one cycle.
619 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
621 * sim-main.c (pending_tick): Clean up trace statements. Add trace
623 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
625 (pending_tick): Move incrementing of index to FOR statement.
626 (pending_tick): Only update PENDING_OUT after a write has occured.
628 * configure.in: Add explicit mips-lsi-* target. Use gencode to
630 * configure: Re-generate.
632 * interp.c (sim_engine_run OLD): Delete explicit call to
633 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
635 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
637 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
638 interrupt level number to match changed SignalExceptionInterrupt
641 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
643 * interp.c: #include "itable.h" if WITH_IGEN.
644 (get_insn_name): New function.
645 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
646 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
648 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
650 * configure: Rebuilt to inhale new common/aclocal.m4.
652 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
654 * dv-tx3904sio.c: Include sim-assert.h.
656 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
658 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
659 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
660 Reorganize target-specific sim-hardware checks.
661 * configure: rebuilt.
662 * interp.c (sim_open): For tx39 target boards, set
663 OPERATING_ENVIRONMENT, add tx3904sio devices.
664 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
665 ROM executables. Install dv-sockser into sim-modules list.
667 * dv-tx3904irc.c: Compiler warning clean-up.
668 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
669 frequent hw-trace messages.
671 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
673 * vr.igen (MulAcc): Identify as a vr4100 specific function.
675 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
677 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
680 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
681 * mips.igen: Define vr4100 model. Include vr.igen.
682 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
684 * mips.igen (check_mf_hilo): Correct check.
686 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
688 * sim-main.h (interrupt_event): Add prototype.
690 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
691 register_ptr, register_value.
692 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
694 * sim-main.h (tracefh): Make extern.
696 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
698 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
699 Reduce unnecessarily high timer event frequency.
700 * dv-tx3904cpu.c: Ditto for interrupt event.
702 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
704 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
706 (interrupt_event): Made non-static.
708 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
709 interchange of configuration values for external vs. internal
712 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
714 * mips.igen (BREAK): Moved code to here for
715 simulator-reserved break instructions.
716 * gencode.c (build_instruction): Ditto.
717 * interp.c (signal_exception): Code moved from here. Non-
718 reserved instructions now use exception vector, rather
720 * sim-main.h: Moved magic constants to here.
722 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
724 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
725 register upon non-zero interrupt event level, clear upon zero
727 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
728 by passing zero event value.
729 (*_io_{read,write}_buffer): Endianness fixes.
730 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
731 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
733 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
734 serial I/O and timer module at base address 0xFFFF0000.
736 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
738 * mips.igen (SWC1) : Correct the handling of ReverseEndian
741 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
743 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
747 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
749 * dv-tx3904tmr.c: New file - implements tx3904 timer.
750 * dv-tx3904{irc,cpu}.c: Mild reformatting.
751 * configure.in: Include tx3904tmr in hw_device list.
752 * configure: Rebuilt.
753 * interp.c (sim_open): Instantiate three timer instances.
754 Fix address typo of tx3904irc instance.
756 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
758 * interp.c (signal_exception): SystemCall exception now uses
759 the exception vector.
761 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
763 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
766 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
768 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
770 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
772 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
774 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
775 sim-main.h. Declare a struct hw_descriptor instead of struct
776 hw_device_descriptor.
778 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
780 * mips.igen (do_store_left, do_load_left): Compute nr of left and
781 right bits and then re-align left hand bytes to correct byte
782 lanes. Fix incorrect computation in do_store_left when loading
783 bytes from second word.
785 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
788 * interp.c (sim_open): Only create a device tree when HW is
791 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
792 * interp.c (signal_exception): Ditto.
794 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
796 * gencode.c: Mark BEGEZALL as LIKELY.
798 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
800 * sim-main.h (ALU32_END): Sign extend 32 bit results.
801 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
803 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
805 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
806 modules. Recognize TX39 target with "mips*tx39" pattern.
807 * configure: Rebuilt.
808 * sim-main.h (*): Added many macros defining bits in
809 TX39 control registers.
810 (SignalInterrupt): Send actual PC instead of NULL.
811 (SignalNMIReset): New exception type.
812 * interp.c (board): New variable for future use to identify
813 a particular board being simulated.
814 (mips_option_handler,mips_options): Added "--board" option.
815 (interrupt_event): Send actual PC.
816 (sim_open): Make memory layout conditional on board setting.
817 (signal_exception): Initial implementation of hardware interrupt
818 handling. Accept another break instruction variant for simulator
820 (decode_coproc): Implement RFE instruction for TX39.
821 (mips.igen): Decode RFE instruction as such.
822 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
823 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
824 bbegin to implement memory map.
825 * dv-tx3904cpu.c: New file.
826 * dv-tx3904irc.c: New file.
828 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
830 * mips.igen (check_mt_hilo): Create a separate r3900 version.
832 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
834 * tx.igen (madd,maddu): Replace calls to check_op_hilo
835 with calls to check_div_hilo.
837 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
839 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
840 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
841 Add special r3900 version of do_mult_hilo.
842 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
843 with calls to check_mult_hilo.
844 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
845 with calls to check_div_hilo.
847 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
849 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
850 Document a replacement.
852 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
854 * interp.c (sim_monitor): Make mon_printf work.
856 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
858 * sim-main.h (INSN_NAME): New arg `cpu'.
860 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
864 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
866 * configure: Regenerated to track ../common/aclocal.m4 changes.
869 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
871 * acconfig.h: New file.
872 * configure.in: Reverted change of Apr 24; use sinclude again.
874 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
876 * configure: Regenerated to track ../common/aclocal.m4 changes.
879 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
881 * configure.in: Don't call sinclude.
883 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
885 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
887 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
889 * mips.igen (ERET): Implement.
891 * interp.c (decode_coproc): Return sign-extended EPC.
893 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
895 * interp.c (signal_exception): Do not ignore Trap.
896 (signal_exception): On TRAP, restart at exception address.
897 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
898 (signal_exception): Update.
899 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
900 so that TRAP instructions are caught.
902 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
904 * sim-main.h (struct hilo_access, struct hilo_history): Define,
905 contains HI/LO access history.
906 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
907 (HIACCESS, LOACCESS): Delete, replace with
908 (HIHISTORY, LOHISTORY): New macros.
909 (CHECKHILO): Delete all, moved to mips.igen
911 * gencode.c (build_instruction): Do not generate checks for
912 correct HI/LO register usage.
914 * interp.c (old_engine_run): Delete checks for correct HI/LO
917 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
918 check_mf_cycles): New functions.
919 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
920 do_divu, domultx, do_mult, do_multu): Use.
922 * tx.igen ("madd", "maddu"): Use.
924 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
926 * mips.igen (DSRAV): Use function do_dsrav.
927 (SRAV): Use new function do_srav.
929 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
930 (B): Sign extend 11 bit immediate.
931 (EXT-B*): Shift 16 bit immediate left by 1.
932 (ADDIU*): Don't sign extend immediate value.
934 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
936 * m16run.c (sim_engine_run): Restore CIA after handling an event.
938 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
941 * mips.igen (delayslot32, nullify_next_insn): New functions.
942 (m16.igen): Always include.
943 (do_*): Add more tracing.
945 * m16.igen (delayslot16): Add NIA argument, could be called by a
946 32 bit MIPS16 instruction.
948 * interp.c (ifetch16): Move function from here.
949 * sim-main.c (ifetch16): To here.
951 * sim-main.c (ifetch16, ifetch32): Update to match current
952 implementations of LH, LW.
953 (signal_exception): Don't print out incorrect hex value of illegal
956 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
958 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
961 * m16.igen: Implement MIPS16 instructions.
963 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
964 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
965 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
966 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
967 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
968 bodies of corresponding code from 32 bit insn to these. Also used
969 by MIPS16 versions of functions.
971 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
972 (IMEM16): Drop NR argument from macro.
974 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
976 * Makefile.in (SIM_OBJS): Add sim-main.o.
978 * sim-main.h (address_translation, load_memory, store_memory,
979 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
981 (pr_addr, pr_uword64): Declare.
982 (sim-main.c): Include when H_REVEALS_MODULE_P.
984 * interp.c (address_translation, load_memory, store_memory,
985 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
987 * sim-main.c: To here. Fix compilation problems.
989 * configure.in: Enable inlining.
990 * configure: Re-config.
992 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
994 * configure: Regenerated to track ../common/aclocal.m4 changes.
996 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
998 * mips.igen: Include tx.igen.
999 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1000 * tx.igen: New file, contains MADD and MADDU.
1002 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1003 the hardwired constant `7'.
1004 (store_memory): Ditto.
1005 (LOADDRMASK): Move definition to sim-main.h.
1007 mips.igen (MTC0): Enable for r3900.
1010 mips.igen (do_load_byte): Delete.
1011 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1012 do_store_right): New functions.
1013 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1015 configure.in: Let the tx39 use igen again.
1018 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1021 not an address sized quantity. Return zero for cache sizes.
1023 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1025 * mips.igen (r3900): r3900 does not support 64 bit integer
1028 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1030 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1032 * configure : Rebuild.
1034 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1036 * configure: Regenerated to track ../common/aclocal.m4 changes.
1038 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1040 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1042 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1044 * configure: Regenerated to track ../common/aclocal.m4 changes.
1045 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1047 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049 * configure: Regenerated to track ../common/aclocal.m4 changes.
1051 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1053 * interp.c (Max, Min): Comment out functions. Not yet used.
1055 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1057 * configure: Regenerated to track ../common/aclocal.m4 changes.
1059 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1061 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1062 configurable settings for stand-alone simulator.
1064 * configure.in: Added X11 search, just in case.
1066 * configure: Regenerated.
1068 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070 * interp.c (sim_write, sim_read, load_memory, store_memory):
1071 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1073 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1075 * sim-main.h (GETFCC): Return an unsigned value.
1077 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1079 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1080 (DADD): Result destination is RD not RT.
1082 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1084 * sim-main.h (HIACCESS, LOACCESS): Always define.
1086 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1088 * interp.c (sim_info): Delete.
1090 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1092 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1093 (mips_option_handler): New argument `cpu'.
1094 (sim_open): Update call to sim_add_option_table.
1096 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1098 * mips.igen (CxC1): Add tracing.
1100 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1102 * sim-main.h (Max, Min): Declare.
1104 * interp.c (Max, Min): New functions.
1106 * mips.igen (BC1): Add tracing.
1108 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1110 * interp.c Added memory map for stack in vr4100
1112 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1114 * interp.c (load_memory): Add missing "break"'s.
1116 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1118 * interp.c (sim_store_register, sim_fetch_register): Pass in
1119 length parameter. Return -1.
1121 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1123 * interp.c: Added hardware init hook, fixed warnings.
1125 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1129 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131 * interp.c (ifetch16): New function.
1133 * sim-main.h (IMEM32): Rename IMEM.
1134 (IMEM16_IMMED): Define.
1136 (DELAY_SLOT): Update.
1138 * m16run.c (sim_engine_run): New file.
1140 * m16.igen: All instructions except LB.
1141 (LB): Call do_load_byte.
1142 * mips.igen (do_load_byte): New function.
1143 (LB): Call do_load_byte.
1145 * mips.igen: Move spec for insn bit size and high bit from here.
1146 * Makefile.in (tmp-igen, tmp-m16): To here.
1148 * m16.dc: New file, decode mips16 instructions.
1150 * Makefile.in (SIM_NO_ALL): Define.
1151 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1153 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1156 point unit to 32 bit registers.
1157 * configure: Re-generate.
1159 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1161 * configure.in (sim_use_gen): Make IGEN the default simulator
1162 generator for generic 32 and 64 bit mips targets.
1163 * configure: Re-generate.
1165 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1167 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1170 * interp.c (sim_fetch_register, sim_store_register): Read/write
1171 FGR from correct location.
1172 (sim_open): Set size of FGR's according to
1173 WITH_TARGET_FLOATING_POINT_BITSIZE.
1175 * sim-main.h (FGR): Store floating point registers in a separate
1178 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1180 * configure: Regenerated to track ../common/aclocal.m4 changes.
1182 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1186 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1188 * interp.c (pending_tick): New function. Deliver pending writes.
1190 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1191 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1192 it can handle mixed sized quantites and single bits.
1194 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1196 * interp.c (oengine.h): Do not include when building with IGEN.
1197 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1198 (sim_info): Ditto for PROCESSOR_64BIT.
1199 (sim_monitor): Replace ut_reg with unsigned_word.
1200 (*): Ditto for t_reg.
1201 (LOADDRMASK): Define.
1202 (sim_open): Remove defunct check that host FP is IEEE compliant,
1203 using software to emulate floating point.
1204 (value_fpr, ...): Always compile, was conditional on HASFPU.
1206 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1211 * interp.c (SD, CPU): Define.
1212 (mips_option_handler): Set flags in each CPU.
1213 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1214 (sim_close): Do not clear STATE, deleted anyway.
1215 (sim_write, sim_read): Assume CPU zero's vm should be used for
1217 (sim_create_inferior): Set the PC for all processors.
1218 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1220 (mips16_entry): Pass correct nr of args to store_word, load_word.
1221 (ColdReset): Cold reset all cpu's.
1222 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1223 (sim_monitor, load_memory, store_memory, signal_exception): Use
1224 `CPU' instead of STATE_CPU.
1227 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1230 * sim-main.h (signal_exception): Add sim_cpu arg.
1231 (SignalException*): Pass both SD and CPU to signal_exception.
1232 * interp.c (signal_exception): Update.
1234 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1236 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1237 address_translation): Ditto
1238 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1240 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1242 * configure: Regenerated to track ../common/aclocal.m4 changes.
1244 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1246 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1248 * mips.igen (model): Map processor names onto BFD name.
1250 * sim-main.h (CPU_CIA): Delete.
1251 (SET_CIA, GET_CIA): Define
1253 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1255 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1258 * configure.in (default_endian): Configure a big-endian simulator
1260 * configure: Re-generate.
1262 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1264 * configure: Regenerated to track ../common/aclocal.m4 changes.
1266 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1268 * interp.c (sim_monitor): Handle Densan monitor outbyte
1269 and inbyte functions.
1271 1997-12-29 Felix Lee <flee@cygnus.com>
1273 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1275 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1277 * Makefile.in (tmp-igen): Arrange for $zero to always be
1278 reset to zero after every instruction.
1280 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1282 * configure: Regenerated to track ../common/aclocal.m4 changes.
1285 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1287 * mips.igen (MSUB): Fix to work like MADD.
1288 * gencode.c (MSUB): Similarly.
1290 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1292 * configure: Regenerated to track ../common/aclocal.m4 changes.
1294 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1296 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1298 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1300 * sim-main.h (sim-fpu.h): Include.
1302 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1303 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1304 using host independant sim_fpu module.
1306 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1308 * interp.c (signal_exception): Report internal errors with SIGABRT
1311 * sim-main.h (C0_CONFIG): New register.
1312 (signal.h): No longer include.
1314 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1316 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1318 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1320 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 * mips.igen: Tag vr5000 instructions.
1323 (ANDI): Was missing mipsIV model, fix assembler syntax.
1324 (do_c_cond_fmt): New function.
1325 (C.cond.fmt): Handle mips I-III which do not support CC field
1327 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1328 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1330 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1331 vr5000 which saves LO in a GPR separatly.
1333 * configure.in (enable-sim-igen): For vr5000, select vr5000
1334 specific instructions.
1335 * configure: Re-generate.
1337 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1339 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1341 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1342 fmt_uninterpreted_64 bit cases to switch. Convert to
1345 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1347 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1348 as specified in IV3.2 spec.
1349 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1351 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1353 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1354 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1355 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1356 PENDING_FILL versions of instructions. Simplify.
1358 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1360 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1362 (MTHI, MFHI): Disable code checking HI-LO.
1364 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1366 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1368 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1370 * gencode.c (build_mips16_operands): Replace IPC with cia.
1372 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1373 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1375 (UndefinedResult): Replace function with macro/function
1377 (sim_engine_run): Don't save PC in IPC.
1379 * sim-main.h (IPC): Delete.
1382 * interp.c (signal_exception, store_word, load_word,
1383 address_translation, load_memory, store_memory, cache_op,
1384 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1385 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1386 current instruction address - cia - argument.
1387 (sim_read, sim_write): Call address_translation directly.
1388 (sim_engine_run): Rename variable vaddr to cia.
1389 (signal_exception): Pass cia to sim_monitor
1391 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1392 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1393 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1395 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1396 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1399 * interp.c (signal_exception): Pass restart address to
1402 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1403 idecode.o): Add dependency.
1405 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1407 (DELAY_SLOT): Update NIA not PC with branch address.
1408 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1410 * mips.igen: Use CIA not PC in branch calculations.
1411 (illegal): Call SignalException.
1412 (BEQ, ADDIU): Fix assembler.
1414 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1416 * m16.igen (JALX): Was missing.
1418 * configure.in (enable-sim-igen): New configuration option.
1419 * configure: Re-generate.
1421 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1423 * interp.c (load_memory, store_memory): Delete parameter RAW.
1424 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1425 bypassing {load,store}_memory.
1427 * sim-main.h (ByteSwapMem): Delete definition.
1429 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1431 * interp.c (sim_do_command, sim_commands): Delete mips specific
1432 commands. Handled by module sim-options.
1434 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1435 (WITH_MODULO_MEMORY): Define.
1437 * interp.c (sim_info): Delete code printing memory size.
1439 * interp.c (mips_size): Nee sim_size, delete function.
1441 (monitor, monitor_base, monitor_size): Delete global variables.
1442 (sim_open, sim_close): Delete code creating monitor and other
1443 memory regions. Use sim-memopts module, via sim_do_commandf, to
1444 manage memory regions.
1445 (load_memory, store_memory): Use sim-core for memory model.
1447 * interp.c (address_translation): Delete all memory map code
1448 except line forcing 32 bit addresses.
1450 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1452 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1455 * interp.c (logfh, logfile): Delete globals.
1456 (sim_open, sim_close): Delete code opening & closing log file.
1457 (mips_option_handler): Delete -l and -n options.
1458 (OPTION mips_options): Ditto.
1460 * interp.c (OPTION mips_options): Rename option trace to dinero.
1461 (mips_option_handler): Update.
1463 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1465 * interp.c (fetch_str): New function.
1466 (sim_monitor): Rewrite using sim_read & sim_write.
1467 (sim_open): Check magic number.
1468 (sim_open): Write monitor vectors into memory using sim_write.
1469 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1470 (sim_read, sim_write): Simplify - transfer data one byte at a
1472 (load_memory, store_memory): Clarify meaning of parameter RAW.
1474 * sim-main.h (isHOST): Defete definition.
1475 (isTARGET): Mark as depreciated.
1476 (address_translation): Delete parameter HOST.
1478 * interp.c (address_translation): Delete parameter HOST.
1480 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1484 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1485 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1487 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489 * mips.igen: Add model filter field to records.
1491 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1493 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1495 interp.c (sim_engine_run): Do not compile function sim_engine_run
1496 when WITH_IGEN == 1.
1498 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1499 target architecture.
1501 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1502 igen. Replace with configuration variables sim_igen_flags /
1505 * m16.igen: New file. Copy mips16 insns here.
1506 * mips.igen: From here.
1508 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1512 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1514 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1516 * gencode.c (build_instruction): Follow sim_write's lead in using
1517 BigEndianMem instead of !ByteSwapMem.
1519 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1521 * configure.in (sim_gen): Dependent on target, select type of
1522 generator. Always select old style generator.
1524 configure: Re-generate.
1526 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1528 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1529 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1530 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1531 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1532 SIM_@sim_gen@_*, set by autoconf.
1534 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1538 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1539 CURRENT_FLOATING_POINT instead.
1541 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1542 (address_translation): Raise exception InstructionFetch when
1543 translation fails and isINSTRUCTION.
1545 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1546 sim_engine_run): Change type of of vaddr and paddr to
1548 (address_translation, prefetch, load_memory, store_memory,
1549 cache_op): Change type of vAddr and pAddr to address_word.
1551 * gencode.c (build_instruction): Change type of vaddr and paddr to
1554 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1557 macro to obtain result of ALU op.
1559 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1561 * interp.c (sim_info): Call profile_print.
1563 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1565 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1567 * sim-main.h (WITH_PROFILE): Do not define, defined in
1568 common/sim-config.h. Use sim-profile module.
1569 (simPROFILE): Delete defintion.
1571 * interp.c (PROFILE): Delete definition.
1572 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1573 (sim_close): Delete code writing profile histogram.
1574 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1576 (sim_engine_run): Delete code profiling the PC.
1578 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1582 * interp.c (sim_monitor): Make register pointers of type
1585 * sim-main.h: Make registers of type unsigned_word not
1588 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1590 * interp.c (sync_operation): Rename from SyncOperation, make
1591 global, add SD argument.
1592 (prefetch): Rename from Prefetch, make global, add SD argument.
1593 (decode_coproc): Make global.
1595 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1597 * gencode.c (build_instruction): Generate DecodeCoproc not
1598 decode_coproc calls.
1600 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1601 (SizeFGR): Move to sim-main.h
1602 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1603 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1604 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1606 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1607 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1608 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1609 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1610 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1611 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1613 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1615 (sim-alu.h): Include.
1616 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1617 (sim_cia): Typedef to instruction_address.
1619 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621 * Makefile.in (interp.o): Rename generated file engine.c to
1626 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1630 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * gencode.c (build_instruction): For "FPSQRT", output correct
1633 number of arguments to Recip.
1635 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637 * Makefile.in (interp.o): Depends on sim-main.h
1639 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1641 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1642 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1643 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1644 STATE, DSSTATE): Define
1645 (GPR, FGRIDX, ..): Define.
1647 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1648 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1649 (GPR, FGRIDX, ...): Delete macros.
1651 * interp.c: Update names to match defines from sim-main.h
1653 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1655 * interp.c (sim_monitor): Add SD argument.
1656 (sim_warning): Delete. Replace calls with calls to
1658 (sim_error): Delete. Replace calls with sim_io_error.
1659 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1660 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1661 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1663 (mips_size): Rename from sim_size. Add SD argument.
1665 * interp.c (simulator): Delete global variable.
1666 (callback): Delete global variable.
1667 (mips_option_handler, sim_open, sim_write, sim_read,
1668 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1669 sim_size,sim_monitor): Use sim_io_* not callback->*.
1670 (sim_open): ZALLOC simulator struct.
1671 (PROFILE): Do not define.
1673 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1676 support.h with corresponding code.
1678 * sim-main.h (word64, uword64), support.h: Move definition to
1680 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1683 * Makefile.in: Update dependencies
1684 * interp.c: Do not include.
1686 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688 * interp.c (address_translation, load_memory, store_memory,
1689 cache_op): Rename to from AddressTranslation et.al., make global,
1692 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1695 * interp.c (SignalException): Rename to signal_exception, make
1698 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1700 * sim-main.h (SignalException, SignalExceptionInterrupt,
1701 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1702 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1703 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1706 * interp.c, support.h: Use.
1708 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1710 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1711 to value_fpr / store_fpr. Add SD argument.
1712 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1713 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1715 * sim-main.h (ValueFPR, StoreFPR): Define.
1717 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719 * interp.c (sim_engine_run): Check consistency between configure
1720 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1723 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1724 (mips_fpu): Configure WITH_FLOATING_POINT.
1725 (mips_endian): Configure WITH_TARGET_ENDIAN.
1726 * configure: Update.
1728 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1730 * configure: Regenerated to track ../common/aclocal.m4 changes.
1732 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1734 * configure: Regenerated.
1736 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1738 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1740 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * gencode.c (print_igen_insn_models): Assume certain architectures
1743 include all mips* instructions.
1744 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1747 * Makefile.in (tmp.igen): Add target. Generate igen input from
1750 * gencode.c (FEATURE_IGEN): Define.
1751 (main): Add --igen option. Generate output in igen format.
1752 (process_instructions): Format output according to igen option.
1753 (print_igen_insn_format): New function.
1754 (print_igen_insn_models): New function.
1755 (process_instructions): Only issue warnings and ignore
1756 instructions when no FEATURE_IGEN.
1758 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1763 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1765 * configure: Regenerated to track ../common/aclocal.m4 changes.
1767 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1769 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1770 SIM_RESERVED_BITS): Delete, moved to common.
1771 (SIM_EXTRA_CFLAGS): Update.
1773 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775 * configure.in: Configure non-strict memory alignment.
1776 * configure: Regenerated to track ../common/aclocal.m4 changes.
1778 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1780 * configure: Regenerated to track ../common/aclocal.m4 changes.
1782 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1784 * gencode.c (SDBBP,DERET): Added (3900) insns.
1785 (RFE): Turn on for 3900.
1786 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1787 (dsstate): Made global.
1788 (SUBTARGET_R3900): Added.
1789 (CANCELDELAYSLOT): New.
1790 (SignalException): Ignore SystemCall rather than ignore and
1791 terminate. Add DebugBreakPoint handling.
1792 (decode_coproc): New insns RFE, DERET; and new registers Debug
1793 and DEPC protected by SUBTARGET_R3900.
1794 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1796 * Makefile.in,configure.in: Add mips subtarget option.
1797 * configure: Update.
1799 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1801 * gencode.c: Add r3900 (tx39).
1804 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1806 * gencode.c (build_instruction): Don't need to subtract 4 for
1809 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1811 * interp.c: Correct some HASFPU problems.
1813 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819 * interp.c (mips_options): Fix samples option short form, should
1822 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1824 * interp.c (sim_info): Enable info code. Was just returning.
1826 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1831 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1833 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1835 (build_instruction): Ditto for LL.
1837 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1839 * configure: Regenerated to track ../common/aclocal.m4 changes.
1841 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843 * configure: Regenerated to track ../common/aclocal.m4 changes.
1846 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848 * interp.c (sim_open): Add call to sim_analyze_program, update
1851 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1853 * interp.c (sim_kill): Delete.
1854 (sim_create_inferior): Add ABFD argument. Set PC from same.
1855 (sim_load): Move code initializing trap handlers from here.
1856 (sim_open): To here.
1857 (sim_load): Delete, use sim-hload.c.
1859 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1861 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863 * configure: Regenerated to track ../common/aclocal.m4 changes.
1866 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1868 * interp.c (sim_open): Add ABFD argument.
1869 (sim_load): Move call to sim_config from here.
1870 (sim_open): To here. Check return status.
1872 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1874 * gencode.c (build_instruction): Two arg MADD should
1875 not assign result to $0.
1877 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1879 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1880 * sim/mips/configure.in: Regenerate.
1882 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1884 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1885 signed8, unsigned8 et.al. types.
1887 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1888 hosts when selecting subreg.
1890 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1892 * interp.c (sim_engine_run): Reset the ZERO register to zero
1893 regardless of FEATURE_WARN_ZERO.
1894 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1896 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1899 (SignalException): For BreakPoints ignore any mode bits and just
1901 (SignalException): Always set the CAUSE register.
1903 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1905 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1906 exception has been taken.
1908 * interp.c: Implement the ERET and mt/f sr instructions.
1910 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1912 * interp.c (SignalException): Don't bother restarting an
1915 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1917 * interp.c (SignalException): Really take an interrupt.
1918 (interrupt_event): Only deliver interrupts when enabled.
1920 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922 * interp.c (sim_info): Only print info when verbose.
1923 (sim_info) Use sim_io_printf for output.
1925 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1930 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1932 * interp.c (sim_do_command): Check for common commands if a
1933 simulator specific command fails.
1935 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1937 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1938 and simBE when DEBUG is defined.
1940 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1942 * interp.c (interrupt_event): New function. Pass exception event
1943 onto exception handler.
1945 * configure.in: Check for stdlib.h.
1946 * configure: Regenerate.
1948 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1949 variable declaration.
1950 (build_instruction): Initialize memval1.
1951 (build_instruction): Add UNUSED attribute to byte, bigend,
1953 (build_operands): Ditto.
1955 * interp.c: Fix GCC warnings.
1956 (sim_get_quit_code): Delete.
1958 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1959 * Makefile.in: Ditto.
1960 * configure: Re-generate.
1962 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1964 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1966 * interp.c (mips_option_handler): New function parse argumes using
1968 (myname): Replace with STATE_MY_NAME.
1969 (sim_open): Delete check for host endianness - performed by
1971 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1972 (sim_open): Move much of the initialization from here.
1973 (sim_load): To here. After the image has been loaded and
1975 (sim_open): Move ColdReset from here.
1976 (sim_create_inferior): To here.
1977 (sim_open): Make FP check less dependant on host endianness.
1979 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1981 * interp.c (sim_set_callbacks): Delete.
1983 * interp.c (membank, membank_base, membank_size): Replace with
1984 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1985 (sim_open): Remove call to callback->init. gdb/run do this.
1989 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1991 * interp.c (big_endian_p): Delete, replaced by
1992 current_target_byte_order.
1994 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996 * interp.c (host_read_long, host_read_word, host_swap_word,
1997 host_swap_long): Delete. Using common sim-endian.
1998 (sim_fetch_register, sim_store_register): Use H2T.
1999 (pipeline_ticks): Delete. Handled by sim-events.
2001 (sim_engine_run): Update.
2003 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2007 (SignalException): To here. Signal using sim_engine_halt.
2008 (sim_stop_reason): Delete, moved to common.
2010 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2012 * interp.c (sim_open): Add callback argument.
2013 (sim_set_callbacks): Delete SIM_DESC argument.
2016 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018 * Makefile.in (SIM_OBJS): Add common modules.
2020 * interp.c (sim_set_callbacks): Also set SD callback.
2021 (set_endianness, xfer_*, swap_*): Delete.
2022 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2023 Change to functions using sim-endian macros.
2024 (control_c, sim_stop): Delete, use common version.
2025 (simulate): Convert into.
2026 (sim_engine_run): This function.
2027 (sim_resume): Delete.
2029 * interp.c (simulation): New variable - the simulator object.
2030 (sim_kind): Delete global - merged into simulation.
2031 (sim_load): Cleanup. Move PC assignment from here.
2032 (sim_create_inferior): To here.
2034 * sim-main.h: New file.
2035 * interp.c (sim-main.h): Include.
2037 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2039 * configure: Regenerated to track ../common/aclocal.m4 changes.
2041 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2043 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2045 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2047 * gencode.c (build_instruction): DIV instructions: check
2048 for division by zero and integer overflow before using
2049 host's division operation.
2051 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2053 * Makefile.in (SIM_OBJS): Add sim-load.o.
2054 * interp.c: #include bfd.h.
2055 (target_byte_order): Delete.
2056 (sim_kind, myname, big_endian_p): New static locals.
2057 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2058 after argument parsing. Recognize -E arg, set endianness accordingly.
2059 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2060 load file into simulator. Set PC from bfd.
2061 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2062 (set_endianness): Use big_endian_p instead of target_byte_order.
2064 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066 * interp.c (sim_size): Delete prototype - conflicts with
2067 definition in remote-sim.h. Correct definition.
2069 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2071 * configure: Regenerated to track ../common/aclocal.m4 changes.
2074 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2076 * interp.c (sim_open): New arg `kind'.
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2080 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2082 * configure: Regenerated to track ../common/aclocal.m4 changes.
2084 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2086 * interp.c (sim_open): Set optind to 0 before calling getopt.
2088 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2090 * configure: Regenerated to track ../common/aclocal.m4 changes.
2092 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2094 * interp.c : Replace uses of pr_addr with pr_uword64
2095 where the bit length is always 64 independent of SIM_ADDR.
2096 (pr_uword64) : added.
2098 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2100 * configure: Re-generate.
2102 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2104 * configure: Regenerate to track ../common/aclocal.m4 changes.
2106 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2108 * interp.c (sim_open): New SIM_DESC result. Argument is now
2110 (other sim_*): New SIM_DESC argument.
2112 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2114 * interp.c: Fix printing of addresses for non-64-bit targets.
2115 (pr_addr): Add function to print address based on size.
2117 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2119 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2121 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2123 * gencode.c (build_mips16_operands): Correct computation of base
2124 address for extended PC relative instruction.
2126 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2128 * interp.c (mips16_entry): Add support for floating point cases.
2129 (SignalException): Pass floating point cases to mips16_entry.
2130 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2132 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2134 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2135 and then set the state to fmt_uninterpreted.
2136 (COP_SW): Temporarily set the state to fmt_word while calling
2139 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2141 * gencode.c (build_instruction): The high order may be set in the
2142 comparison flags at any ISA level, not just ISA 4.
2144 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2146 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2147 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2148 * configure.in: sinclude ../common/aclocal.m4.
2149 * configure: Regenerated.
2151 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2153 * configure: Rebuild after change to aclocal.m4.
2155 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2157 * configure configure.in Makefile.in: Update to new configure
2158 scheme which is more compatible with WinGDB builds.
2159 * configure.in: Improve comment on how to run autoconf.
2160 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2161 * Makefile.in: Use autoconf substitution to install common
2164 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2166 * gencode.c (build_instruction): Use BigEndianCPU instead of
2169 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2171 * interp.c (sim_monitor): Make output to stdout visible in
2172 wingdb's I/O log window.
2174 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2176 * support.h: Undo previous change to SIGTRAP
2179 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2181 * interp.c (store_word, load_word): New static functions.
2182 (mips16_entry): New static function.
2183 (SignalException): Look for mips16 entry and exit instructions.
2184 (simulate): Use the correct index when setting fpr_state after
2185 doing a pending move.
2187 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2189 * interp.c: Fix byte-swapping code throughout to work on
2190 both little- and big-endian hosts.
2192 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2194 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2195 with gdb/config/i386/xm-windows.h.
2197 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2199 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2200 that messes up arithmetic shifts.
2202 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2204 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2205 SIGTRAP and SIGQUIT for _WIN32.
2207 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2209 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2210 force a 64 bit multiplication.
2211 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2212 destination register is 0, since that is the default mips16 nop
2215 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2217 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2218 (build_endian_shift): Don't check proc64.
2219 (build_instruction): Always set memval to uword64. Cast op2 to
2220 uword64 when shifting it left in memory instructions. Always use
2221 the same code for stores--don't special case proc64.
2223 * gencode.c (build_mips16_operands): Fix base PC value for PC
2225 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2227 * interp.c (simJALDELAYSLOT): Define.
2228 (JALDELAYSLOT): Define.
2229 (INDELAYSLOT, INJALDELAYSLOT): Define.
2230 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2232 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2234 * interp.c (sim_open): add flush_cache as a PMON routine
2235 (sim_monitor): handle flush_cache by ignoring it
2237 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2239 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2241 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2242 (BigEndianMem): Rename to ByteSwapMem and change sense.
2243 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2244 BigEndianMem references to !ByteSwapMem.
2245 (set_endianness): New function, with prototype.
2246 (sim_open): Call set_endianness.
2247 (sim_info): Use simBE instead of BigEndianMem.
2248 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2249 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2250 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2251 ifdefs, keeping the prototype declaration.
2252 (swap_word): Rewrite correctly.
2253 (ColdReset): Delete references to CONFIG. Delete endianness related
2254 code; moved to set_endianness.
2256 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2258 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2259 * interp.c (CHECKHILO): Define away.
2260 (simSIGINT): New macro.
2261 (membank_size): Increase from 1MB to 2MB.
2262 (control_c): New function.
2263 (sim_resume): Rename parameter signal to signal_number. Add local
2264 variable prev. Call signal before and after simulate.
2265 (sim_stop_reason): Add simSIGINT support.
2266 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2268 (sim_warning): Delete call to SignalException. Do call printf_filtered
2270 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2271 a call to sim_warning.
2273 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2275 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2276 16 bit instructions.
2278 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2280 Add support for mips16 (16 bit MIPS implementation):
2281 * gencode.c (inst_type): Add mips16 instruction encoding types.
2282 (GETDATASIZEINSN): Define.
2283 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2284 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2286 (MIPS16_DECODE): New table, for mips16 instructions.
2287 (bitmap_val): New static function.
2288 (struct mips16_op): Define.
2289 (mips16_op_table): New table, for mips16 operands.
2290 (build_mips16_operands): New static function.
2291 (process_instructions): If PC is odd, decode a mips16
2292 instruction. Break out instruction handling into new
2293 build_instruction function.
2294 (build_instruction): New static function, broken out of
2295 process_instructions. Check modifiers rather than flags for SHIFT
2296 bit count and m[ft]{hi,lo} direction.
2297 (usage): Pass program name to fprintf.
2298 (main): Remove unused variable this_option_optind. Change
2299 ``*loptarg++'' to ``loptarg++''.
2300 (my_strtoul): Parenthesize && within ||.
2301 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2302 (simulate): If PC is odd, fetch a 16 bit instruction, and
2303 increment PC by 2 rather than 4.
2304 * configure.in: Add case for mips16*-*-*.
2305 * configure: Rebuild.
2307 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2309 * interp.c: Allow -t to enable tracing in standalone simulator.
2310 Fix garbage output in trace file and error messages.
2312 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2314 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2315 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2316 * configure.in: Simplify using macros in ../common/aclocal.m4.
2317 * configure: Regenerated.
2318 * tconfig.in: New file.
2320 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2322 * interp.c: Fix bugs in 64-bit port.
2323 Use ansi function declarations for msvc compiler.
2324 Initialize and test file pointer in trace code.
2325 Prevent duplicate definition of LAST_EMED_REGNUM.
2327 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2329 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2331 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2333 * interp.c (SignalException): Check for explicit terminating
2335 * gencode.c: Pass instruction value through SignalException()
2336 calls for Trap, Breakpoint and Syscall.
2338 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2340 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2341 only used on those hosts that provide it.
2342 * configure.in: Add sqrt() to list of functions to be checked for.
2343 * config.in: Re-generated.
2344 * configure: Re-generated.
2346 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2348 * gencode.c (process_instructions): Call build_endian_shift when
2349 expanding STORE RIGHT, to fix swr.
2350 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2351 clear the high bits.
2352 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2353 Fix float to int conversions to produce signed values.
2355 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2357 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2358 (process_instructions): Correct handling of nor instruction.
2359 Correct shift count for 32 bit shift instructions. Correct sign
2360 extension for arithmetic shifts to not shift the number of bits in
2361 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2362 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2364 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2365 It's OK to have a mult follow a mult. What's not OK is to have a
2366 mult follow an mfhi.
2367 (Convert): Comment out incorrect rounding code.
2369 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2371 * interp.c (sim_monitor): Improved monitor printf
2372 simulation. Tidied up simulator warnings, and added "--log" option
2373 for directing warning message output.
2374 * gencode.c: Use sim_warning() rather than WARNING macro.
2376 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2378 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2379 getopt1.o, rather than on gencode.c. Link objects together.
2380 Don't link against -liberty.
2381 (gencode.o, getopt.o, getopt1.o): New targets.
2382 * gencode.c: Include <ctype.h> and "ansidecl.h".
2383 (AND): Undefine after including "ansidecl.h".
2384 (ULONG_MAX): Define if not defined.
2385 (OP_*): Don't define macros; now defined in opcode/mips.h.
2386 (main): Call my_strtoul rather than strtoul.
2387 (my_strtoul): New static function.
2389 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2391 * gencode.c (process_instructions): Generate word64 and uword64
2392 instead of `long long' and `unsigned long long' data types.
2393 * interp.c: #include sysdep.h to get signals, and define default
2395 * (Convert): Work around for Visual-C++ compiler bug with type
2397 * support.h: Make things compile under Visual-C++ by using
2398 __int64 instead of `long long'. Change many refs to long long
2399 into word64/uword64 typedefs.
2401 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2403 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2404 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2406 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2407 (AC_PROG_INSTALL): Added.
2408 (AC_PROG_CC): Moved to before configure.host call.
2409 * configure: Rebuilt.
2411 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2413 * configure.in: Define @SIMCONF@ depending on mips target.
2414 * configure: Rebuild.
2415 * Makefile.in (run): Add @SIMCONF@ to control simulator
2417 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2418 * interp.c: Remove some debugging, provide more detailed error
2419 messages, update memory accesses to use LOADDRMASK.
2421 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2423 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2424 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2426 * configure: Rebuild.
2427 * config.in: New file, generated by autoheader.
2428 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2429 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2430 HAVE_ANINT and HAVE_AINT, as appropriate.
2431 * Makefile.in (run): Use @LIBS@ rather than -lm.
2432 (interp.o): Depend upon config.h.
2433 (Makefile): Just rebuild Makefile.
2434 (clean): Remove stamp-h.
2435 (mostlyclean): Make the same as clean, not as distclean.
2436 (config.h, stamp-h): New targets.
2438 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2440 * interp.c (ColdReset): Fix boolean test. Make all simulator
2443 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2445 * interp.c (xfer_direct_word, xfer_direct_long,
2446 swap_direct_word, swap_direct_long, xfer_big_word,
2447 xfer_big_long, xfer_little_word, xfer_little_long,
2448 swap_word,swap_long): Added.
2449 * interp.c (ColdReset): Provide function indirection to
2450 host<->simulated_target transfer routines.
2451 * interp.c (sim_store_register, sim_fetch_register): Updated to
2452 make use of indirected transfer routines.
2454 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2456 * gencode.c (process_instructions): Ensure FP ABS instruction
2458 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2459 system call support.
2461 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2463 * interp.c (sim_do_command): Complain if callback structure not
2466 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2468 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2469 support for Sun hosts.
2470 * Makefile.in (gencode): Ensure the host compiler and libraries
2471 used for cross-hosted build.
2473 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2475 * interp.c, gencode.c: Some more (TODO) tidying.
2477 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2479 * gencode.c, interp.c: Replaced explicit long long references with
2480 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2481 * support.h (SET64LO, SET64HI): Macros added.
2483 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2485 * configure: Regenerate with autoconf 2.7.
2487 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2489 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2490 * support.h: Remove superfluous "1" from #if.
2491 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2493 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2495 * interp.c (StoreFPR): Control UndefinedResult() call on
2496 WARN_RESULT manifest.
2498 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2500 * gencode.c: Tidied instruction decoding, and added FP instruction
2503 * interp.c: Added dineroIII, and BSD profiling support. Also
2504 run-time FP handling.
2506 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2508 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2509 gencode.c, interp.c, support.h: created.