2 Thu Nov 5 10:29:42 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
4 * r5900.igen (r59fp_opdiv): Correct erroneous FGR[FD] reference.
6 Thu Nov 5 19:40:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
8 * r5900.igen (DIV): Do not clear clear SO/SU when already set.
10 * r5900.igen (RSQRT.S): Do not compute 1/srqt(abs(T)) when T
11 negative, compute S/sqrt(abs(T)) instead. Correctly set FCSR
14 * r5900.igen (RSQRT.S): Handle overflow/underflow better. Check
16 (r59fp_store): Clarify "bad value" abort messages.
20 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
22 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
23 interrupt level number to match changed SignalExceptionInterrupt
28 Thu Oct 29 12:47:46 1998 Frank Ch. Eigler <fche@cygnus.com>
30 * sim-main.c (tlb_try_match): Include physical address in
31 scratchpad non-mapping warning.
35 Thu Oct 29 11:06:30 EST 1998 Frank Ch. Eigler <fche@cygnus.com>
37 * r5900.igen: Fix PSRLVW, MULTU1, PADSBH instructions,
38 as per customer patch.
41 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
43 * interp.c: #include "itable.h" if WITH_IGEN.
44 (get_insn_name): New function.
45 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
46 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
49 Tue Sep 22 10:35:37 1998 Frank Ch. Eigler <fche@cygnus.com>
51 * sim-main.c (tlb_try_match): Specially match virtual
52 pages mapped to scratchpad RAM, an unimplemented feature.
56 Fri Sep 18 11:31:16 1998 Frank Ch. Eigler <fche@cygnus.com>
58 * r5900.igen (prot3w): Correct rotation sequence; patch
62 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
64 * configure: Rebuilt to inhale new common/aclocal.m4.
67 Thu Sep 10 11:50:54 1998 Doug Evans <devans@canuck.cygnus.com>
69 * r5900.igen (plzcw): Make `i' signed.
71 Wed Sep 9 15:02:10 1998 Doug Evans <devans@canuck.cygnus.com>
73 * sim-main.h (COP0_COUNT,COP0_COMPARE,status_IM7): New macros.
74 * sky-engine.c (cpu_issue): Increment COP0_COUNT and signal an
75 interrupt if == COP0_COMPARE and interrupt masks/enables allow it.
76 * interp.c (signal_exception, sky version): Handle INT 2.
78 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
80 * sim-main.h: track COP0 registers
81 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
83 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
85 * r5900.igen (mtsab): Correct typo in input register.
87 * sim-main.h (TMP_*): New macros for accessing local 128-bit
88 temporary for multimedia instructions.
89 * r5900.igen (*): Convert most instructions to use new TMP
90 macros to store output result during computation.
94 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
96 * dv-tx3904sio.c: Include sim-assert.h.
98 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
100 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
101 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
102 Reorganize target-specific sim-hardware checks.
103 * configure: rebuilt.
104 * interp.c (sim_open): For tx39 target boards, set
105 OPERATING_ENVIRONMENT, add tx3904sio devices.
106 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
107 ROM executables. Install dv-sockser into sim-modules list.
109 * dv-tx3904irc.c: Compiler warning clean-up.
110 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
111 frequent hw-trace messages.
115 Tue Aug 11 13:52:16 1998 Frank Ch. Eigler <fche@cygnus.com>
117 * interp.c (signal_exception): Set IP3 bit in CAUSE on
121 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
123 * vr.igen (MulAcc): Identify as a vr4100 specific function.
125 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
127 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
130 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
131 * mips.igen: Define vr4100 model. Include vr.igen.
132 start-sanitize-cygnus
133 * vr5400.igen: Move instructions to vr.igen
134 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
136 start-sanitize-vr4320
137 * vr4320.igen: Move instructions to vr.igen.
138 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
142 Fri Jul 24 16:01:03 1998 Ian Carmichael <iancarm@cygnus.com>
144 * interp.c (MONITOR_SIZE): Make 1MB monitor for SKY.
145 * mips.igen (BREAK): Fix 0xffff2 monitor call. Slightly less
146 confusing message if not enough --load-next options appear.
148 * sky-pke.h (VUx_MEMx_SRCADDR_START): Move to 0x19800000 range.
149 * sim-main.c (GDB_COMM_AREA): Move to 0x19810000.
150 * sky-gdb.c (init_fifo_bp_cache): Use VIO_BASE when reading GDB area.
151 (resume_handler): Same.
152 (suspend_handler): Same.
154 Wed Jul 22 13:04:13 1998 Frank Ch. Eigler <fche@cygnus.com>
156 * mips.igen (break): Implement LOAD_INSTRUCTION ("break 0xffff1")
157 to trigger multi-phase load.
159 * sim-main.c: Include sim-assert.h for ASSERT macro.
160 * sim-main.h (PRINTF_INSTRUCTION): Correct bit pattern for
163 Tue Jul 21 18:37:36 1998 Ian Carmichael <iancarm@cygnus.com>
166 * interp.c (sim_open): Initialize TLB.
167 * interp.c (signal_exceptions): New 5900 handling.
168 * r5900.igen (TLBWR, TLBWI, TLBR, TLBP): Make these work.
169 * sim-main.c (tlb_try_match, tlb_lookup): New functions.
170 (address_translation): Use the TLB.
171 * sim-main.h (r4000_tlb_entry_t): New type.
172 (TLB_*): New constants.
173 (COP0_*): New register names.
175 Sky character I/O device.
176 * sky-psio.c: New file.
177 * sky-psio.h: New file.
178 * Makefile.in: Add sky-psio.o.
182 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
184 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
187 (r59fp_store): Update calls.
188 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
191 start-sanitize-branchbug4011
192 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
194 * interp.c (OPTION_BRANCH_BUG_4011): Add.
195 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
196 (mips_options): Define the option.
197 * mips.igen (check_4011_branch_bug): New.
198 (mark_4011_branch_bug): New.
199 (all branch insn): Call mark_branch_bug, and check_branch_bug.
200 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
201 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
202 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
203 check_branch_bug, mark_branch_bug): Define.
205 end-sanitize-branchbug4011
206 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
208 * mips.igen (check_mf_hilo): Correct check.
211 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
213 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
214 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
215 purpose registers, add 8 COP0 break-point registers, add 64 COP0
216 performance registers.
218 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
219 MFP* instructions. Just transfer value to/from corresponding
222 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
223 status is always true.
224 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
225 (EI, DI): Set/clear Status-EIE bit.
229 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
231 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
235 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
238 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
240 * sky-gdb.c: Include "sim-assert.h".
243 * sim-main.h (interrupt_event): Add prototype.
245 start-sanitize-tx3904
246 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
247 register_ptr, register_value.
248 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
251 * sim-main.h (tracefh): Make extern.
253 start-sanitize-tx3904
254 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
256 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
257 Reduce unnecessarily high timer event frequency.
258 * dv-tx3904cpu.c: Ditto for interrupt event.
262 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
264 * interp.c (decode_coproc): Removed COP2 branches.
265 * r5900.igen: Moved COP2 branch instructions here.
266 * mips.igen: Restricted COPz == COP2 bit pattern to
267 exclude COP2 branches.
270 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
272 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
274 (interrupt_event): Made non-static.
275 start-sanitize-tx3904
277 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
278 interchange of configuration values for external vs. internal
282 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
284 * mips.igen (BREAK): Moved code to here for
285 simulator-reserved break instructions.
286 * gencode.c (build_instruction): Ditto.
287 * interp.c (signal_exception): Code moved from here. Non-
288 reserved instructions now use exception vector, rather
290 * sim-main.h: Moved magic constants to here.
292 start-sanitize-tx3904
293 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
295 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
296 register upon non-zero interrupt event level, clear upon zero
298 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
299 by passing zero event value.
300 (*_io_{read,write}_buffer): Endianness fixes.
301 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
302 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
304 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
305 serial I/O and timer module at base address 0xFFFF0000.
308 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
310 * mips.igen (SWC1) : Correct the handling of ReverseEndian
313 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
315 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
319 start-sanitize-tx3904
320 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
322 * dv-tx3904tmr.c: New file - implements tx3904 timer.
323 * dv-tx3904{irc,cpu}.c: Mild reformatting.
324 * configure.in: Include tx3904tmr in hw_device list.
325 * configure: Rebuilt.
326 * interp.c (sim_open): Instantiate three timer instances.
327 Fix address typo of tx3904irc instance.
331 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
333 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
334 Select corresponding check_mt_hilo function.
335 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
338 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
342 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
344 * interp.c (signal_exception): SystemCall exception now uses
345 the exception vector.
347 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
349 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
353 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
355 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
359 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
361 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
363 start-sanitize-tx3904
364 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
366 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
368 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
369 sim-main.h. Declare a struct hw_descriptor instead of struct
370 hw_device_descriptor.
373 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
375 * mips.igen (do_store_left, do_load_left): Compute nr of left and
376 right bits and then re-align left hand bytes to correct byte
377 lanes. Fix incorrect computation in do_store_left when loading
378 bytes from second word.
380 start-sanitize-tx3904
381 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
383 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
384 * interp.c (sim_open): Only create a device tree when HW is
387 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
388 * interp.c (signal_exception): Ditto.
391 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
393 * gencode.c: Mark BEGEZALL as LIKELY.
395 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
397 * sim-main.h (ALU32_END): Sign extend 32 bit results.
398 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
401 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
403 * interp.c (sim_fetch_register): Convert internal r5900 regs to
407 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
409 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
410 modules. Recognize TX39 target with "mips*tx39" pattern.
411 * configure: Rebuilt.
412 * sim-main.h (*): Added many macros defining bits in
413 TX39 control registers.
414 (SignalInterrupt): Send actual PC instead of NULL.
415 (SignalNMIReset): New exception type.
416 * interp.c (board): New variable for future use to identify
417 a particular board being simulated.
418 (mips_option_handler,mips_options): Added "--board" option.
419 (interrupt_event): Send actual PC.
420 (sim_open): Make memory layout conditional on board setting.
421 (signal_exception): Initial implementation of hardware interrupt
422 handling. Accept another break instruction variant for simulator
424 (decode_coproc): Implement RFE instruction for TX39.
425 (mips.igen): Decode RFE instruction as such.
426 start-sanitize-tx3904
427 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
428 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
429 bbegin to implement memory map.
430 * dv-tx3904cpu.c: New file.
431 * dv-tx3904irc.c: New file.
434 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
436 * mips.igen (check_mt_hilo): Create a separate r3900 version.
439 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
441 * r5900.igen: Replace the calls and the definition of the
442 function check_op_hilo_hi1lo1 with the pair
443 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
446 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
448 * tx.igen (madd,maddu): Replace calls to check_op_hilo
449 with calls to check_div_hilo.
451 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
453 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
454 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
455 Add special r3900 version of do_mult_hilo.
456 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
457 with calls to check_mult_hilo.
458 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
459 with calls to check_div_hilo.
461 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
463 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
464 Document a replacement.
466 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
468 * interp.c (sim_monitor): Make mon_printf work.
470 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
472 * sim-main.h (INSN_NAME): New arg `cpu'.
475 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
482 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
484 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
485 * r5900.igen (r59fp_overflow): Use.
487 * r5900.igen (r59fp_op3): Rename to
488 (r59fp_mula): This, delete opm argument.
489 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
490 (r59fp_mula): Overflowing product propogates through to result.
491 (r59fp_mula): ACC to the MAX propogates to result.
492 (r59fp_mula): Underflow during multiply only sets SU.
495 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
497 * configure: Regenerated to track ../common/aclocal.m4 changes.
499 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
501 * configure: Regenerated to track ../common/aclocal.m4 changes.
504 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
506 * acconfig.h: New file.
507 * configure.in: Reverted change of Apr 24; use sinclude again.
509 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
511 * configure: Regenerated to track ../common/aclocal.m4 changes.
514 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
516 * configure.in: Don't call sinclude.
518 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
520 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
522 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
524 * mips.igen (ERET): Implement.
526 * interp.c (decode_coproc): Return sign-extended EPC.
528 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
530 * interp.c (signal_exception): Do not ignore Trap.
531 (signal_exception): On TRAP, restart at exception address.
532 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
533 (signal_exception): Update.
534 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
535 so that TRAP instructions are caught.
537 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
539 * sim-main.h (struct hilo_access, struct hilo_history): Define,
540 contains HI/LO access history.
541 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
542 (HIACCESS, LOACCESS): Delete, replace with
543 (HIHISTORY, LOHISTORY): New macros.
544 (start-sanitize-r5900):
545 (struct sim_5900_cpu): Make hi1access, lo1access of type
547 (HI1ACCESS, LO1ACCESS): Delete, replace with
548 (HI1HISTORY, LO1HISTORY): New macros.
549 (end-sanitize-r5900):
550 (CHECKHILO): Delete all, moved to mips.igen
552 * gencode.c (build_instruction): Do not generate checks for
553 correct HI/LO register usage.
555 * interp.c (old_engine_run): Delete checks for correct HI/LO
558 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
559 check_mf_cycles): New functions.
560 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
561 do_divu, domultx, do_mult, do_multu): Use.
563 * tx.igen ("madd", "maddu"): Use.
564 (start-sanitize-r5900):
566 r5900.igen: Update all HI/LO checks.
567 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
568 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
569 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
570 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
571 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
573 (end-sanitize-r5900):
576 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
578 * interp.c (decode_coproc): Correct CMFC2/QMTC2
581 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
582 instead of a single 128-bit access.
586 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
588 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
589 * interp.c (cop_[ls]q): Fixes corresponding to above.
593 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
595 * interp.c (decode_coproc): Adapt COP2 micro interlock to
596 clarified specs. Reset "M" bit; exit also on "E" bit.
600 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
602 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
603 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
605 * r5900.igen (r59fp_unpack): New function.
606 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
607 RSQRT.S, SQRT.S): Use.
608 (r59fp_zero): New function.
609 (r59fp_overflow): Generate r5900 specific overflow value.
610 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
612 (CVT.S.W, CVT.W.S): Exchange implementations.
614 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
618 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
620 * configure.in (tx19, sim_use_gen): Switch to igen.
621 * configure: Re-build.
625 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
627 * interp.c (decode_coproc): Make COP2 branch code compile after
628 igen signature changes.
631 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
633 * mips.igen (DSRAV): Use function do_dsrav.
634 (SRAV): Use new function do_srav.
636 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
637 (B): Sign extend 11 bit immediate.
638 (EXT-B*): Shift 16 bit immediate left by 1.
639 (ADDIU*): Don't sign extend immediate value.
641 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
643 * m16run.c (sim_engine_run): Restore CIA after handling an event.
646 * mips.igen (mtc0): Valid tx19 instruction.
649 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
652 * mips.igen (delayslot32, nullify_next_insn): New functions.
653 (m16.igen): Always include.
654 (do_*): Add more tracing.
656 * m16.igen (delayslot16): Add NIA argument, could be called by a
657 32 bit MIPS16 instruction.
659 * interp.c (ifetch16): Move function from here.
660 * sim-main.c (ifetch16): To here.
662 * sim-main.c (ifetch16, ifetch32): Update to match current
663 implementations of LH, LW.
664 (signal_exception): Don't print out incorrect hex value of illegal
667 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
669 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
672 * m16.igen: Implement MIPS16 instructions.
674 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
675 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
676 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
677 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
678 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
679 bodies of corresponding code from 32 bit insn to these. Also used
680 by MIPS16 versions of functions.
682 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
683 (IMEM16): Drop NR argument from macro.
686 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
688 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
689 of VU lower instruction.
693 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
695 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
698 * sim-main.h: Removed attempt at allowing 128-bit access.
702 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
704 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
706 * interp.c (decode_coproc): Refer to VU CIA as a "special"
707 register, not as a "misc" register. Aha. Add activity
708 assertions after VCALLMS* instructions.
712 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
714 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
715 to upper code of generated VU instruction.
719 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
721 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
723 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
726 * r5900.igen (SQC2): Thinko.
730 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
732 * interp.c (*): Adapt code to merged VU device & state structs.
733 (decode_coproc): Execute COP2 each macroinstruction without
734 pipelining, by stepping VU to completion state. Adapted to
735 read_vu_*_reg style of register access.
737 * mips.igen ([SL]QC2): Removed these COP2 instructions.
739 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
741 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
744 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
746 * Makefile.in (SIM_OBJS): Add sim-main.o.
748 * sim-main.h (address_translation, load_memory, store_memory,
749 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
751 (pr_addr, pr_uword64): Declare.
752 (sim-main.c): Include when H_REVEALS_MODULE_P.
754 * interp.c (address_translation, load_memory, store_memory,
755 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
757 * sim-main.c: To here. Fix compilation problems.
759 * configure.in: Enable inlining.
760 * configure: Re-config.
762 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
764 * configure: Regenerated to track ../common/aclocal.m4 changes.
766 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
768 * mips.igen: Include tx.igen.
769 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
770 * tx.igen: New file, contains MADD and MADDU.
772 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
773 the hardwired constant `7'.
774 (store_memory): Ditto.
775 (LOADDRMASK): Move definition to sim-main.h.
777 mips.igen (MTC0): Enable for r3900.
780 mips.igen (do_load_byte): Delete.
781 (do_load, do_store, do_load_left, do_load_write, do_store_left,
782 do_store_right): New functions.
783 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
785 configure.in: Let the tx39 use igen again.
788 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
790 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
791 not an address sized quantity. Return zero for cache sizes.
793 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
795 * mips.igen (r3900): r3900 does not support 64 bit integer
799 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
801 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
805 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
807 * interp.c (decode_coproc): Continuing COP2 work.
808 (cop_[ls]q): Make sky-target-only.
810 * sim-main.h (COP_[LS]Q): Make sky-target-only.
812 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
814 * configure.in (mipstx39*-*-*): Use gencode simulator rather
816 * configure : Rebuild.
819 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
821 * interp.c (decode_coproc): Added a missing TARGET_SKY check
822 around COP2 implementation skeleton.
826 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
828 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
830 * interp.c (sim_{load,store}_register): Use new vu[01]_device
831 static to access VU registers.
832 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
833 decoding. Work in progress.
835 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
836 overlapping/redundant bit pattern.
837 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
840 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
843 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
844 access to coprocessor registers.
846 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
848 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
850 * configure: Regenerated to track ../common/aclocal.m4 changes.
852 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
854 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
856 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
858 * configure: Regenerated to track ../common/aclocal.m4 changes.
859 * config.in: Regenerated to track ../common/aclocal.m4 changes.
861 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
863 * configure: Regenerated to track ../common/aclocal.m4 changes.
865 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
867 * interp.c (Max, Min): Comment out functions. Not yet used.
869 start-sanitize-vr4320
870 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
872 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
875 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
877 * configure: Regenerated to track ../common/aclocal.m4 changes.
879 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
881 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
882 configurable settings for stand-alone simulator.
885 * configure.in: Added --with-sim-gpu2 option to specify path of
886 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
887 links/compiles stand-alone simulator with this library.
889 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
891 * configure.in: Added X11 search, just in case.
893 * configure: Regenerated.
895 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
897 * interp.c (sim_write, sim_read, load_memory, store_memory):
898 Replace sim_core_*_map with read_map, write_map, exec_map resp.
900 start-sanitize-vr4320
901 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
903 * vr4320.igen (clz,dclz) : Added.
904 (dmac): Replaced 99, with LO.
907 start-sanitize-cygnus
908 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
910 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
913 start-sanitize-vr4320
914 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
916 * vr4320.igen: New file.
917 * Makefile.in (vr4320.igen) : Added.
918 * configure.in (mips64vr4320-*-*): Added.
919 * configure : Rebuilt.
920 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
921 Add the vr4320 model entry and mark the vr4320 insn as necessary.
924 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
926 * sim-main.h (GETFCC): Return an unsigned value.
929 * r5900.igen: Use an unsigned array index variable `i'.
930 (QFSRV): Ditto for variable bytes.
933 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
935 * mips.igen (DIV): Fix check for -1 / MIN_INT.
936 (DADD): Result destination is RD not RT.
939 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
940 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
944 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
946 * sim-main.h (HIACCESS, LOACCESS): Always define.
948 * mdmx.igen (Maxi, Mini): Rename Max, Min.
950 * interp.c (sim_info): Delete.
952 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
954 * interp.c (DECLARE_OPTION_HANDLER): Use it.
955 (mips_option_handler): New argument `cpu'.
956 (sim_open): Update call to sim_add_option_table.
958 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
960 * mips.igen (CxC1): Add tracing.
963 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
965 * r5900.igen (StoreFP): Delete.
966 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
968 (rsqrt.s, sqrt.s): Implement.
969 (r59cond): New function.
970 (C.COND.S): Call r59cond in assembler line.
971 (cvt.w.s, cvt.s.w): Implement.
973 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
976 * sim-main.h: Define an enum of r5900 FCSR bit fields.
980 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
982 * r5900.igen: Add tracing to all p* instructions.
984 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
986 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
987 to get gdb talking to re-aranged sim_cpu register structure.
990 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
992 * sim-main.h (Max, Min): Declare.
994 * interp.c (Max, Min): New functions.
996 * mips.igen (BC1): Add tracing.
998 start-sanitize-cygnus
999 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
1001 * mdmx.igen: Tag all functions as requiring either with mdmx or
1005 start-sanitize-r5900
1006 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
1010 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
1012 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
1014 * r5900.igen: Rewrite.
1016 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
1018 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
1019 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
1022 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1024 * interp.c Added memory map for stack in vr4100
1026 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1028 * interp.c (load_memory): Add missing "break"'s.
1030 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032 * interp.c (sim_store_register, sim_fetch_register): Pass in
1033 length parameter. Return -1.
1035 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1037 * interp.c: Added hardware init hook, fixed warnings.
1039 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1043 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045 * interp.c (ifetch16): New function.
1047 * sim-main.h (IMEM32): Rename IMEM.
1048 (IMEM16_IMMED): Define.
1050 (DELAY_SLOT): Update.
1052 * m16run.c (sim_engine_run): New file.
1054 * m16.igen: All instructions except LB.
1055 (LB): Call do_load_byte.
1056 * mips.igen (do_load_byte): New function.
1057 (LB): Call do_load_byte.
1059 * mips.igen: Move spec for insn bit size and high bit from here.
1060 * Makefile.in (tmp-igen, tmp-m16): To here.
1062 * m16.dc: New file, decode mips16 instructions.
1064 * Makefile.in (SIM_NO_ALL): Define.
1065 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1068 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
1072 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1075 point unit to 32 bit registers.
1076 * configure: Re-generate.
1078 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1080 * configure.in (sim_use_gen): Make IGEN the default simulator
1081 generator for generic 32 and 64 bit mips targets.
1082 * configure: Re-generate.
1084 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1086 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1089 * interp.c (sim_fetch_register, sim_store_register): Read/write
1090 FGR from correct location.
1091 (sim_open): Set size of FGR's according to
1092 WITH_TARGET_FLOATING_POINT_BITSIZE.
1094 * sim-main.h (FGR): Store floating point registers in a separate
1097 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1099 * configure: Regenerated to track ../common/aclocal.m4 changes.
1101 start-sanitize-cygnus
1102 * mdmx.igen: Mark all instructions as 64bit/fp specific.
1105 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1107 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1109 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1111 * interp.c (pending_tick): New function. Deliver pending writes.
1113 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1114 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1115 it can handle mixed sized quantites and single bits.
1117 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1119 * interp.c (oengine.h): Do not include when building with IGEN.
1120 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1121 (sim_info): Ditto for PROCESSOR_64BIT.
1122 (sim_monitor): Replace ut_reg with unsigned_word.
1123 (*): Ditto for t_reg.
1124 (LOADDRMASK): Define.
1125 (sim_open): Remove defunct check that host FP is IEEE compliant,
1126 using software to emulate floating point.
1127 (value_fpr, ...): Always compile, was conditional on HASFPU.
1129 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1134 * interp.c (SD, CPU): Define.
1135 (mips_option_handler): Set flags in each CPU.
1136 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1137 (sim_close): Do not clear STATE, deleted anyway.
1138 (sim_write, sim_read): Assume CPU zero's vm should be used for
1140 (sim_create_inferior): Set the PC for all processors.
1141 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1143 (mips16_entry): Pass correct nr of args to store_word, load_word.
1144 (ColdReset): Cold reset all cpu's.
1145 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1146 (sim_monitor, load_memory, store_memory, signal_exception): Use
1147 `CPU' instead of STATE_CPU.
1150 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1153 * sim-main.h (signal_exception): Add sim_cpu arg.
1154 (SignalException*): Pass both SD and CPU to signal_exception.
1155 * interp.c (signal_exception): Update.
1157 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1159 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1160 address_translation): Ditto
1161 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1163 start-sanitize-cygnus
1164 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1166 (ByteAlign): Use StoreFPR, pass args in correct order.
1169 start-sanitize-r5900
1170 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1175 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1177 * configure: Regenerated to track ../common/aclocal.m4 changes.
1179 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1181 start-sanitize-r5900
1182 * configure.in (sim_igen_filter): For r5900, use igen.
1183 * configure: Re-generate.
1186 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1188 * mips.igen (model): Map processor names onto BFD name.
1190 * sim-main.h (CPU_CIA): Delete.
1191 (SET_CIA, GET_CIA): Define
1193 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1195 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1198 * configure.in (default_endian): Configure a big-endian simulator
1200 * configure: Re-generate.
1202 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1204 * configure: Regenerated to track ../common/aclocal.m4 changes.
1206 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1208 * interp.c (sim_monitor): Handle Densan monitor outbyte
1209 and inbyte functions.
1211 1997-12-29 Felix Lee <flee@cygnus.com>
1213 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1215 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1217 * Makefile.in (tmp-igen): Arrange for $zero to always be
1218 reset to zero after every instruction.
1220 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1222 * configure: Regenerated to track ../common/aclocal.m4 changes.
1225 start-sanitize-cygnus
1226 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1228 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1231 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1233 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1234 vr5400 with the vr5000 as the default.
1237 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1239 * mips.igen (MSUB): Fix to work like MADD.
1240 * gencode.c (MSUB): Similarly.
1242 start-sanitize-cygnus
1243 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1245 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1249 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1251 * configure: Regenerated to track ../common/aclocal.m4 changes.
1253 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1255 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1257 start-sanitize-cygnus
1258 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1259 (value_cc, store_cc): Implement.
1261 * sim-main.h: Add 8*3*8 bit accumulator.
1263 * vr5400.igen: Move mdmx instructins from here
1264 * mdmx.igen: To here - new file. Add/fix missing instructions.
1265 * mips.igen: Include mdmx.igen.
1266 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1269 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271 * sim-main.h (sim-fpu.h): Include.
1273 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1274 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1275 using host independant sim_fpu module.
1277 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1279 * interp.c (signal_exception): Report internal errors with SIGABRT
1282 * sim-main.h (C0_CONFIG): New register.
1283 (signal.h): No longer include.
1285 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1287 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1289 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1291 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1293 * mips.igen: Tag vr5000 instructions.
1294 (ANDI): Was missing mipsIV model, fix assembler syntax.
1295 (do_c_cond_fmt): New function.
1296 (C.cond.fmt): Handle mips I-III which do not support CC field
1298 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1299 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1301 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1302 vr5000 which saves LO in a GPR separatly.
1304 * configure.in (enable-sim-igen): For vr5000, select vr5000
1305 specific instructions.
1306 * configure: Re-generate.
1308 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1312 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1313 fmt_uninterpreted_64 bit cases to switch. Convert to
1316 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1318 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1319 as specified in IV3.2 spec.
1320 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1322 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1324 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1325 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1326 (start-sanitize-r5900):
1327 (LWXC1, SWXC1): Delete from r5900 instruction set.
1328 (end-sanitize-r5900):
1329 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1330 PENDING_FILL versions of instructions. Simplify.
1332 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1334 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1336 (MTHI, MFHI): Disable code checking HI-LO.
1338 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1340 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1342 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1344 * gencode.c (build_mips16_operands): Replace IPC with cia.
1346 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1347 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1349 (UndefinedResult): Replace function with macro/function
1351 (sim_engine_run): Don't save PC in IPC.
1353 * sim-main.h (IPC): Delete.
1355 start-sanitize-cygnus
1356 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1357 (do_select): Rename function select.
1360 * interp.c (signal_exception, store_word, load_word,
1361 address_translation, load_memory, store_memory, cache_op,
1362 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1363 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1364 current instruction address - cia - argument.
1365 (sim_read, sim_write): Call address_translation directly.
1366 (sim_engine_run): Rename variable vaddr to cia.
1367 (signal_exception): Pass cia to sim_monitor
1369 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1370 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1371 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1373 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1374 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1377 * interp.c (signal_exception): Pass restart address to
1380 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1381 idecode.o): Add dependency.
1383 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1385 (DELAY_SLOT): Update NIA not PC with branch address.
1386 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1388 * mips.igen: Use CIA not PC in branch calculations.
1389 (illegal): Call SignalException.
1390 (BEQ, ADDIU): Fix assembler.
1392 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1394 * m16.igen (JALX): Was missing.
1396 * configure.in (enable-sim-igen): New configuration option.
1397 * configure: Re-generate.
1399 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1401 * interp.c (load_memory, store_memory): Delete parameter RAW.
1402 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1403 bypassing {load,store}_memory.
1405 * sim-main.h (ByteSwapMem): Delete definition.
1407 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1409 * interp.c (sim_do_command, sim_commands): Delete mips specific
1410 commands. Handled by module sim-options.
1412 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1413 (WITH_MODULO_MEMORY): Define.
1415 * interp.c (sim_info): Delete code printing memory size.
1417 * interp.c (mips_size): Nee sim_size, delete function.
1419 (monitor, monitor_base, monitor_size): Delete global variables.
1420 (sim_open, sim_close): Delete code creating monitor and other
1421 memory regions. Use sim-memopts module, via sim_do_commandf, to
1422 manage memory regions.
1423 (load_memory, store_memory): Use sim-core for memory model.
1425 * interp.c (address_translation): Delete all memory map code
1426 except line forcing 32 bit addresses.
1428 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1430 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1433 * interp.c (logfh, logfile): Delete globals.
1434 (sim_open, sim_close): Delete code opening & closing log file.
1435 (mips_option_handler): Delete -l and -n options.
1436 (OPTION mips_options): Ditto.
1438 * interp.c (OPTION mips_options): Rename option trace to dinero.
1439 (mips_option_handler): Update.
1441 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1443 * interp.c (fetch_str): New function.
1444 (sim_monitor): Rewrite using sim_read & sim_write.
1445 (sim_open): Check magic number.
1446 (sim_open): Write monitor vectors into memory using sim_write.
1447 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1448 (sim_read, sim_write): Simplify - transfer data one byte at a
1450 (load_memory, store_memory): Clarify meaning of parameter RAW.
1452 * sim-main.h (isHOST): Defete definition.
1453 (isTARGET): Mark as depreciated.
1454 (address_translation): Delete parameter HOST.
1456 * interp.c (address_translation): Delete parameter HOST.
1459 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1461 * gencode.c: Add tx49 configury and insns.
1462 * configure.in: Add tx49 configury.
1463 * configure: Update.
1466 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1470 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1471 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1473 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475 * mips.igen: Add model filter field to records.
1477 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1481 interp.c (sim_engine_run): Do not compile function sim_engine_run
1482 when WITH_IGEN == 1.
1484 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1485 target architecture.
1487 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1488 igen. Replace with configuration variables sim_igen_flags /
1491 start-sanitize-r5900
1492 * r5900.igen: New file. Copy r5900 insns here.
1494 start-sanitize-cygnus
1495 * vr5400.igen: New file.
1497 * m16.igen: New file. Copy mips16 insns here.
1498 * mips.igen: From here.
1500 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502 start-sanitize-cygnus
1503 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1505 * configure.in: Add mips64vr5400 target.
1506 * configure: Re-generate.
1509 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1511 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1513 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1515 * gencode.c (build_instruction): Follow sim_write's lead in using
1516 BigEndianMem instead of !ByteSwapMem.
1518 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520 * configure.in (sim_gen): Dependent on target, select type of
1521 generator. Always select old style generator.
1523 configure: Re-generate.
1525 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1527 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1528 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1529 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1530 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1531 SIM_@sim_gen@_*, set by autoconf.
1533 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1537 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1538 CURRENT_FLOATING_POINT instead.
1540 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1541 (address_translation): Raise exception InstructionFetch when
1542 translation fails and isINSTRUCTION.
1544 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1545 sim_engine_run): Change type of of vaddr and paddr to
1547 (address_translation, prefetch, load_memory, store_memory,
1548 cache_op): Change type of vAddr and pAddr to address_word.
1550 * gencode.c (build_instruction): Change type of vaddr and paddr to
1553 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1556 macro to obtain result of ALU op.
1558 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560 * interp.c (sim_info): Call profile_print.
1562 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1566 * sim-main.h (WITH_PROFILE): Do not define, defined in
1567 common/sim-config.h. Use sim-profile module.
1568 (simPROFILE): Delete defintion.
1570 * interp.c (PROFILE): Delete definition.
1571 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1572 (sim_close): Delete code writing profile histogram.
1573 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1575 (sim_engine_run): Delete code profiling the PC.
1577 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1579 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1581 * interp.c (sim_monitor): Make register pointers of type
1584 * sim-main.h: Make registers of type unsigned_word not
1587 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1589 start-sanitize-r5900
1590 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1591 ...): Move to sim-main.h
1594 * interp.c (sync_operation): Rename from SyncOperation, make
1595 global, add SD argument.
1596 (prefetch): Rename from Prefetch, make global, add SD argument.
1597 (decode_coproc): Make global.
1599 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1601 * gencode.c (build_instruction): Generate DecodeCoproc not
1602 decode_coproc calls.
1604 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1605 (SizeFGR): Move to sim-main.h
1606 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1607 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1608 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1610 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1611 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1612 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1613 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1614 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1615 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1617 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1619 (sim-alu.h): Include.
1620 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1621 (sim_cia): Typedef to instruction_address.
1623 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625 * Makefile.in (interp.o): Rename generated file engine.c to
1630 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1634 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * gencode.c (build_instruction): For "FPSQRT", output correct
1637 number of arguments to Recip.
1639 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1641 * Makefile.in (interp.o): Depends on sim-main.h
1643 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1645 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1646 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1647 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1648 STATE, DSSTATE): Define
1649 (GPR, FGRIDX, ..): Define.
1651 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1652 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1653 (GPR, FGRIDX, ...): Delete macros.
1655 * interp.c: Update names to match defines from sim-main.h
1657 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659 * interp.c (sim_monitor): Add SD argument.
1660 (sim_warning): Delete. Replace calls with calls to
1662 (sim_error): Delete. Replace calls with sim_io_error.
1663 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1664 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1665 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1667 (mips_size): Rename from sim_size. Add SD argument.
1669 * interp.c (simulator): Delete global variable.
1670 (callback): Delete global variable.
1671 (mips_option_handler, sim_open, sim_write, sim_read,
1672 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1673 sim_size,sim_monitor): Use sim_io_* not callback->*.
1674 (sim_open): ZALLOC simulator struct.
1675 (PROFILE): Do not define.
1677 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1679 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1680 support.h with corresponding code.
1682 * sim-main.h (word64, uword64), support.h: Move definition to
1684 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1687 * Makefile.in: Update dependencies
1688 * interp.c: Do not include.
1690 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1692 * interp.c (address_translation, load_memory, store_memory,
1693 cache_op): Rename to from AddressTranslation et.al., make global,
1696 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1699 * interp.c (SignalException): Rename to signal_exception, make
1702 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1704 * sim-main.h (SignalException, SignalExceptionInterrupt,
1705 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1706 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1707 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1710 * interp.c, support.h: Use.
1712 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1714 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1715 to value_fpr / store_fpr. Add SD argument.
1716 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1717 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1719 * sim-main.h (ValueFPR, StoreFPR): Define.
1721 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1723 * interp.c (sim_engine_run): Check consistency between configure
1724 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1727 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1728 (mips_fpu): Configure WITH_FLOATING_POINT.
1729 (mips_endian): Configure WITH_TARGET_ENDIAN.
1730 * configure: Update.
1732 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1734 * configure: Regenerated to track ../common/aclocal.m4 changes.
1736 start-sanitize-r5900
1737 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1739 * interp.c (MAX_REG): Allow up-to 128 registers.
1740 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1741 (REGISTER_SA): Ditto.
1742 (sim_open): Initialize register_widths for r5900 specific
1744 (sim_fetch_register, sim_store_register): Check for request of
1745 r5900 specific SA register. Check for request for hi 64 bits of
1746 r5900 specific registers.
1749 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1751 * configure: Regenerated.
1753 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1755 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1757 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1759 * gencode.c (print_igen_insn_models): Assume certain architectures
1760 include all mips* instructions.
1761 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1764 * Makefile.in (tmp.igen): Add target. Generate igen input from
1767 * gencode.c (FEATURE_IGEN): Define.
1768 (main): Add --igen option. Generate output in igen format.
1769 (process_instructions): Format output according to igen option.
1770 (print_igen_insn_format): New function.
1771 (print_igen_insn_models): New function.
1772 (process_instructions): Only issue warnings and ignore
1773 instructions when no FEATURE_IGEN.
1775 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1780 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1782 * configure: Regenerated to track ../common/aclocal.m4 changes.
1784 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1787 SIM_RESERVED_BITS): Delete, moved to common.
1788 (SIM_EXTRA_CFLAGS): Update.
1790 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792 * configure.in: Configure non-strict memory alignment.
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1795 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797 * configure: Regenerated to track ../common/aclocal.m4 changes.
1799 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1801 * gencode.c (SDBBP,DERET): Added (3900) insns.
1802 (RFE): Turn on for 3900.
1803 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1804 (dsstate): Made global.
1805 (SUBTARGET_R3900): Added.
1806 (CANCELDELAYSLOT): New.
1807 (SignalException): Ignore SystemCall rather than ignore and
1808 terminate. Add DebugBreakPoint handling.
1809 (decode_coproc): New insns RFE, DERET; and new registers Debug
1810 and DEPC protected by SUBTARGET_R3900.
1811 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1813 * Makefile.in,configure.in: Add mips subtarget option.
1814 * configure: Update.
1816 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1818 * gencode.c: Add r3900 (tx39).
1821 * gencode.c: Fix some configuration problems by improving
1822 the relationship between tx19 and tx39.
1825 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1827 * gencode.c (build_instruction): Don't need to subtract 4 for
1830 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1832 * interp.c: Correct some HASFPU problems.
1834 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1840 * interp.c (mips_options): Fix samples option short form, should
1843 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845 * interp.c (sim_info): Enable info code. Was just returning.
1847 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1852 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1856 (build_instruction): Ditto for LL.
1859 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1861 * mips/configure.in, mips/gencode: Add tx19/r1900.
1864 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1866 * configure: Regenerated to track ../common/aclocal.m4 changes.
1868 start-sanitize-r5900
1869 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1871 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1872 for overflow due to ABS of MININT, set result to MAXINT.
1873 (build_instruction): For "psrlvw", signextend bit 31.
1876 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1878 * configure: Regenerated to track ../common/aclocal.m4 changes.
1881 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1883 * interp.c (sim_open): Add call to sim_analyze_program, update
1886 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888 * interp.c (sim_kill): Delete.
1889 (sim_create_inferior): Add ABFD argument. Set PC from same.
1890 (sim_load): Move code initializing trap handlers from here.
1891 (sim_open): To here.
1892 (sim_load): Delete, use sim-hload.c.
1894 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1896 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898 * configure: Regenerated to track ../common/aclocal.m4 changes.
1901 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903 * interp.c (sim_open): Add ABFD argument.
1904 (sim_load): Move call to sim_config from here.
1905 (sim_open): To here. Check return status.
1907 start-sanitize-r5900
1908 * gencode.c (build_instruction): Do not define x8000000000000000,
1909 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1912 start-sanitize-r5900
1913 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1916 "pdivuw" check for overflow due to signed divide by -1.
1919 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1921 * gencode.c (build_instruction): Two arg MADD should
1922 not assign result to $0.
1924 start-sanitize-r5900
1925 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1927 * gencode.c (build_instruction): For "ppac5" use unsigned
1928 arrithmetic so that the sign bit doesn't smear when right shifted.
1929 (build_instruction): For "pdiv" perform sign extension when
1930 storing results in HI and LO.
1931 (build_instructions): For "pdiv" and "pdivbw" check for
1933 (build_instruction): For "pmfhl.slw" update hi part of dest
1934 register as well as low part.
1935 (build_instruction): For "pmfhl" portably handle long long values.
1936 (build_instruction): For "pmfhl.sh" correctly negative values.
1937 Store half words 2 and three in the correct place.
1938 (build_instruction): For "psllvw", sign extend value after shift.
1941 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1943 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1944 * sim/mips/configure.in: Regenerate.
1946 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1948 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1949 signed8, unsigned8 et.al. types.
1951 start-sanitize-r5900
1952 * gencode.c (build_instruction): For PMULTU* do not sign extend
1953 registers. Make generated code easier to debug.
1956 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1957 hosts when selecting subreg.
1959 start-sanitize-r5900
1960 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1962 * gencode.c (type_for_data_len): For 32bit operations concerned
1963 with overflow, perform op using 64bits.
1964 (build_instruction): For PADD, always compute operation using type
1965 returned by type_for_data_len.
1966 (build_instruction): For PSUBU, when overflow, saturate to zero as
1970 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1972 start-sanitize-r5900
1973 * gencode.c (build_instruction): Handle "pext5" according to
1974 version 1.95 of the r5900 ISA.
1976 * gencode.c (build_instruction): Handle "ppac5" according to
1977 version 1.95 of the r5900 ISA.
1980 * interp.c (sim_engine_run): Reset the ZERO register to zero
1981 regardless of FEATURE_WARN_ZERO.
1982 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1984 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1986 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1987 (SignalException): For BreakPoints ignore any mode bits and just
1989 (SignalException): Always set the CAUSE register.
1991 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1993 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1994 exception has been taken.
1996 * interp.c: Implement the ERET and mt/f sr instructions.
1998 start-sanitize-r5900
1999 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
2001 * gencode.c (build_instruction): For paddu, extract unsigned
2004 * gencode.c (build_instruction): Saturate padds instead of padd
2008 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2010 * interp.c (SignalException): Don't bother restarting an
2013 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2015 * interp.c (SignalException): Really take an interrupt.
2016 (interrupt_event): Only deliver interrupts when enabled.
2018 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020 * interp.c (sim_info): Only print info when verbose.
2021 (sim_info) Use sim_io_printf for output.
2023 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2025 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2028 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2030 * interp.c (sim_do_command): Check for common commands if a
2031 simulator specific command fails.
2033 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2035 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2036 and simBE when DEBUG is defined.
2038 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2040 * interp.c (interrupt_event): New function. Pass exception event
2041 onto exception handler.
2043 * configure.in: Check for stdlib.h.
2044 * configure: Regenerate.
2046 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2047 variable declaration.
2048 (build_instruction): Initialize memval1.
2049 (build_instruction): Add UNUSED attribute to byte, bigend,
2051 (build_operands): Ditto.
2053 * interp.c: Fix GCC warnings.
2054 (sim_get_quit_code): Delete.
2056 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2057 * Makefile.in: Ditto.
2058 * configure: Re-generate.
2060 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2062 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2064 * interp.c (mips_option_handler): New function parse argumes using
2066 (myname): Replace with STATE_MY_NAME.
2067 (sim_open): Delete check for host endianness - performed by
2069 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2070 (sim_open): Move much of the initialization from here.
2071 (sim_load): To here. After the image has been loaded and
2073 (sim_open): Move ColdReset from here.
2074 (sim_create_inferior): To here.
2075 (sim_open): Make FP check less dependant on host endianness.
2077 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2079 * interp.c (sim_set_callbacks): Delete.
2081 * interp.c (membank, membank_base, membank_size): Replace with
2082 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2083 (sim_open): Remove call to callback->init. gdb/run do this.
2087 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2089 * interp.c (big_endian_p): Delete, replaced by
2090 current_target_byte_order.
2092 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2094 * interp.c (host_read_long, host_read_word, host_swap_word,
2095 host_swap_long): Delete. Using common sim-endian.
2096 (sim_fetch_register, sim_store_register): Use H2T.
2097 (pipeline_ticks): Delete. Handled by sim-events.
2099 (sim_engine_run): Update.
2101 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2103 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2105 (SignalException): To here. Signal using sim_engine_halt.
2106 (sim_stop_reason): Delete, moved to common.
2108 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2110 * interp.c (sim_open): Add callback argument.
2111 (sim_set_callbacks): Delete SIM_DESC argument.
2114 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * Makefile.in (SIM_OBJS): Add common modules.
2118 * interp.c (sim_set_callbacks): Also set SD callback.
2119 (set_endianness, xfer_*, swap_*): Delete.
2120 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2121 Change to functions using sim-endian macros.
2122 (control_c, sim_stop): Delete, use common version.
2123 (simulate): Convert into.
2124 (sim_engine_run): This function.
2125 (sim_resume): Delete.
2127 * interp.c (simulation): New variable - the simulator object.
2128 (sim_kind): Delete global - merged into simulation.
2129 (sim_load): Cleanup. Move PC assignment from here.
2130 (sim_create_inferior): To here.
2132 * sim-main.h: New file.
2133 * interp.c (sim-main.h): Include.
2135 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2137 * configure: Regenerated to track ../common/aclocal.m4 changes.
2139 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2141 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2143 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2145 * gencode.c (build_instruction): DIV instructions: check
2146 for division by zero and integer overflow before using
2147 host's division operation.
2149 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2151 * Makefile.in (SIM_OBJS): Add sim-load.o.
2152 * interp.c: #include bfd.h.
2153 (target_byte_order): Delete.
2154 (sim_kind, myname, big_endian_p): New static locals.
2155 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2156 after argument parsing. Recognize -E arg, set endianness accordingly.
2157 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2158 load file into simulator. Set PC from bfd.
2159 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2160 (set_endianness): Use big_endian_p instead of target_byte_order.
2162 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164 * interp.c (sim_size): Delete prototype - conflicts with
2165 definition in remote-sim.h. Correct definition.
2167 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2169 * configure: Regenerated to track ../common/aclocal.m4 changes.
2172 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2174 * interp.c (sim_open): New arg `kind'.
2176 * configure: Regenerated to track ../common/aclocal.m4 changes.
2178 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2184 * interp.c (sim_open): Set optind to 0 before calling getopt.
2186 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2188 * configure: Regenerated to track ../common/aclocal.m4 changes.
2190 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2192 * interp.c : Replace uses of pr_addr with pr_uword64
2193 where the bit length is always 64 independent of SIM_ADDR.
2194 (pr_uword64) : added.
2196 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2198 * configure: Re-generate.
2200 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2202 * configure: Regenerate to track ../common/aclocal.m4 changes.
2204 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2206 * interp.c (sim_open): New SIM_DESC result. Argument is now
2208 (other sim_*): New SIM_DESC argument.
2210 start-sanitize-r5900
2211 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2213 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2214 Change values to avoid overloading DOUBLEWORD which is tested
2216 * gencode.c: reinstate "offending code".
2219 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2221 * interp.c: Fix printing of addresses for non-64-bit targets.
2222 (pr_addr): Add function to print address based on size.
2223 start-sanitize-r5900
2224 * gencode.c: #ifdef out offending code until a permanent fix
2225 can be added. Code is causing build errors for non-5900 mips targets.
2228 start-sanitize-r5900
2229 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2231 * gencode.c (process_instructions): Correct test for ISA dependent
2232 architecture bits in isa field of MIPS_DECODE.
2235 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2237 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2239 start-sanitize-r5900
2240 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2242 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2246 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2248 * gencode.c (build_mips16_operands): Correct computation of base
2249 address for extended PC relative instruction.
2251 start-sanitize-r5900
2252 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2254 * Makefile.in, configure, configure.in, gencode.c,
2255 interp.c, support.h: add r5900.
2258 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2260 * interp.c (mips16_entry): Add support for floating point cases.
2261 (SignalException): Pass floating point cases to mips16_entry.
2262 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2264 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2266 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2267 and then set the state to fmt_uninterpreted.
2268 (COP_SW): Temporarily set the state to fmt_word while calling
2271 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2273 * gencode.c (build_instruction): The high order may be set in the
2274 comparison flags at any ISA level, not just ISA 4.
2276 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2278 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2279 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2280 * configure.in: sinclude ../common/aclocal.m4.
2281 * configure: Regenerated.
2283 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2285 * configure: Rebuild after change to aclocal.m4.
2287 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2289 * configure configure.in Makefile.in: Update to new configure
2290 scheme which is more compatible with WinGDB builds.
2291 * configure.in: Improve comment on how to run autoconf.
2292 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2293 * Makefile.in: Use autoconf substitution to install common
2296 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2298 * gencode.c (build_instruction): Use BigEndianCPU instead of
2301 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2303 * interp.c (sim_monitor): Make output to stdout visible in
2304 wingdb's I/O log window.
2306 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2308 * support.h: Undo previous change to SIGTRAP
2311 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2313 * interp.c (store_word, load_word): New static functions.
2314 (mips16_entry): New static function.
2315 (SignalException): Look for mips16 entry and exit instructions.
2316 (simulate): Use the correct index when setting fpr_state after
2317 doing a pending move.
2319 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2321 * interp.c: Fix byte-swapping code throughout to work on
2322 both little- and big-endian hosts.
2324 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2326 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2327 with gdb/config/i386/xm-windows.h.
2329 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2331 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2332 that messes up arithmetic shifts.
2334 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2336 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2337 SIGTRAP and SIGQUIT for _WIN32.
2339 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2341 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2342 force a 64 bit multiplication.
2343 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2344 destination register is 0, since that is the default mips16 nop
2347 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2349 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2350 (build_endian_shift): Don't check proc64.
2351 (build_instruction): Always set memval to uword64. Cast op2 to
2352 uword64 when shifting it left in memory instructions. Always use
2353 the same code for stores--don't special case proc64.
2355 * gencode.c (build_mips16_operands): Fix base PC value for PC
2357 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2359 * interp.c (simJALDELAYSLOT): Define.
2360 (JALDELAYSLOT): Define.
2361 (INDELAYSLOT, INJALDELAYSLOT): Define.
2362 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2364 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2366 * interp.c (sim_open): add flush_cache as a PMON routine
2367 (sim_monitor): handle flush_cache by ignoring it
2369 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2371 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2373 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2374 (BigEndianMem): Rename to ByteSwapMem and change sense.
2375 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2376 BigEndianMem references to !ByteSwapMem.
2377 (set_endianness): New function, with prototype.
2378 (sim_open): Call set_endianness.
2379 (sim_info): Use simBE instead of BigEndianMem.
2380 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2381 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2382 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2383 ifdefs, keeping the prototype declaration.
2384 (swap_word): Rewrite correctly.
2385 (ColdReset): Delete references to CONFIG. Delete endianness related
2386 code; moved to set_endianness.
2388 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2390 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2391 * interp.c (CHECKHILO): Define away.
2392 (simSIGINT): New macro.
2393 (membank_size): Increase from 1MB to 2MB.
2394 (control_c): New function.
2395 (sim_resume): Rename parameter signal to signal_number. Add local
2396 variable prev. Call signal before and after simulate.
2397 (sim_stop_reason): Add simSIGINT support.
2398 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2400 (sim_warning): Delete call to SignalException. Do call printf_filtered
2402 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2403 a call to sim_warning.
2405 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2407 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2408 16 bit instructions.
2410 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2412 Add support for mips16 (16 bit MIPS implementation):
2413 * gencode.c (inst_type): Add mips16 instruction encoding types.
2414 (GETDATASIZEINSN): Define.
2415 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2416 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2418 (MIPS16_DECODE): New table, for mips16 instructions.
2419 (bitmap_val): New static function.
2420 (struct mips16_op): Define.
2421 (mips16_op_table): New table, for mips16 operands.
2422 (build_mips16_operands): New static function.
2423 (process_instructions): If PC is odd, decode a mips16
2424 instruction. Break out instruction handling into new
2425 build_instruction function.
2426 (build_instruction): New static function, broken out of
2427 process_instructions. Check modifiers rather than flags for SHIFT
2428 bit count and m[ft]{hi,lo} direction.
2429 (usage): Pass program name to fprintf.
2430 (main): Remove unused variable this_option_optind. Change
2431 ``*loptarg++'' to ``loptarg++''.
2432 (my_strtoul): Parenthesize && within ||.
2433 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2434 (simulate): If PC is odd, fetch a 16 bit instruction, and
2435 increment PC by 2 rather than 4.
2436 * configure.in: Add case for mips16*-*-*.
2437 * configure: Rebuild.
2439 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2441 * interp.c: Allow -t to enable tracing in standalone simulator.
2442 Fix garbage output in trace file and error messages.
2444 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2446 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2447 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2448 * configure.in: Simplify using macros in ../common/aclocal.m4.
2449 * configure: Regenerated.
2450 * tconfig.in: New file.
2452 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2454 * interp.c: Fix bugs in 64-bit port.
2455 Use ansi function declarations for msvc compiler.
2456 Initialize and test file pointer in trace code.
2457 Prevent duplicate definition of LAST_EMED_REGNUM.
2459 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2461 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2463 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2465 * interp.c (SignalException): Check for explicit terminating
2467 * gencode.c: Pass instruction value through SignalException()
2468 calls for Trap, Breakpoint and Syscall.
2470 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2472 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2473 only used on those hosts that provide it.
2474 * configure.in: Add sqrt() to list of functions to be checked for.
2475 * config.in: Re-generated.
2476 * configure: Re-generated.
2478 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2480 * gencode.c (process_instructions): Call build_endian_shift when
2481 expanding STORE RIGHT, to fix swr.
2482 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2483 clear the high bits.
2484 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2485 Fix float to int conversions to produce signed values.
2487 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2489 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2490 (process_instructions): Correct handling of nor instruction.
2491 Correct shift count for 32 bit shift instructions. Correct sign
2492 extension for arithmetic shifts to not shift the number of bits in
2493 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2494 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2496 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2497 It's OK to have a mult follow a mult. What's not OK is to have a
2498 mult follow an mfhi.
2499 (Convert): Comment out incorrect rounding code.
2501 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2503 * interp.c (sim_monitor): Improved monitor printf
2504 simulation. Tidied up simulator warnings, and added "--log" option
2505 for directing warning message output.
2506 * gencode.c: Use sim_warning() rather than WARNING macro.
2508 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2510 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2511 getopt1.o, rather than on gencode.c. Link objects together.
2512 Don't link against -liberty.
2513 (gencode.o, getopt.o, getopt1.o): New targets.
2514 * gencode.c: Include <ctype.h> and "ansidecl.h".
2515 (AND): Undefine after including "ansidecl.h".
2516 (ULONG_MAX): Define if not defined.
2517 (OP_*): Don't define macros; now defined in opcode/mips.h.
2518 (main): Call my_strtoul rather than strtoul.
2519 (my_strtoul): New static function.
2521 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2523 * gencode.c (process_instructions): Generate word64 and uword64
2524 instead of `long long' and `unsigned long long' data types.
2525 * interp.c: #include sysdep.h to get signals, and define default
2527 * (Convert): Work around for Visual-C++ compiler bug with type
2529 * support.h: Make things compile under Visual-C++ by using
2530 __int64 instead of `long long'. Change many refs to long long
2531 into word64/uword64 typedefs.
2533 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2535 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2536 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2538 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2539 (AC_PROG_INSTALL): Added.
2540 (AC_PROG_CC): Moved to before configure.host call.
2541 * configure: Rebuilt.
2543 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2545 * configure.in: Define @SIMCONF@ depending on mips target.
2546 * configure: Rebuild.
2547 * Makefile.in (run): Add @SIMCONF@ to control simulator
2549 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2550 * interp.c: Remove some debugging, provide more detailed error
2551 messages, update memory accesses to use LOADDRMASK.
2553 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2555 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2556 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2558 * configure: Rebuild.
2559 * config.in: New file, generated by autoheader.
2560 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2561 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2562 HAVE_ANINT and HAVE_AINT, as appropriate.
2563 * Makefile.in (run): Use @LIBS@ rather than -lm.
2564 (interp.o): Depend upon config.h.
2565 (Makefile): Just rebuild Makefile.
2566 (clean): Remove stamp-h.
2567 (mostlyclean): Make the same as clean, not as distclean.
2568 (config.h, stamp-h): New targets.
2570 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2572 * interp.c (ColdReset): Fix boolean test. Make all simulator
2575 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2577 * interp.c (xfer_direct_word, xfer_direct_long,
2578 swap_direct_word, swap_direct_long, xfer_big_word,
2579 xfer_big_long, xfer_little_word, xfer_little_long,
2580 swap_word,swap_long): Added.
2581 * interp.c (ColdReset): Provide function indirection to
2582 host<->simulated_target transfer routines.
2583 * interp.c (sim_store_register, sim_fetch_register): Updated to
2584 make use of indirected transfer routines.
2586 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2588 * gencode.c (process_instructions): Ensure FP ABS instruction
2590 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2591 system call support.
2593 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2595 * interp.c (sim_do_command): Complain if callback structure not
2598 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2600 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2601 support for Sun hosts.
2602 * Makefile.in (gencode): Ensure the host compiler and libraries
2603 used for cross-hosted build.
2605 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2607 * interp.c, gencode.c: Some more (TODO) tidying.
2609 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2611 * gencode.c, interp.c: Replaced explicit long long references with
2612 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2613 * support.h (SET64LO, SET64HI): Macros added.
2615 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2617 * configure: Regenerate with autoconf 2.7.
2619 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2621 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2622 * support.h: Remove superfluous "1" from #if.
2623 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2625 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2627 * interp.c (StoreFPR): Control UndefinedResult() call on
2628 WARN_RESULT manifest.
2630 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2632 * gencode.c: Tidied instruction decoding, and added FP instruction
2635 * interp.c: Added dineroIII, and BSD profiling support. Also
2636 run-time FP handling.
2638 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2640 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2641 gencode.c, interp.c, support.h: created.