1 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
3 * sim-main.h (ALU32_END): Sign extend 32 bit results.
4 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
7 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
9 * interp.c (sim_fetch_register): Convert internal r5900 regs to
13 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
15 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
16 modules. Recognize TX39 target with "mips*tx39" pattern.
18 * sim-main.h (*): Added many macros defining bits in
19 TX39 control registers.
20 (SignalInterrupt): Send actual PC instead of NULL.
21 (SignalNMIReset): New exception type.
22 * interp.c (board): New variable for future use to identify
23 a particular board being simulated.
24 (mips_option_handler,mips_options): Added "--board" option.
25 (interrupt_event): Send actual PC.
26 (sim_open): Make memory layout conditional on board setting.
27 (signal_exception): Initial implementation of hardware interrupt
28 handling. Accept another break instruction variant for simulator
30 (decode_coproc): Implement RFE instruction for TX39.
31 (mips.igen): Decode RFE instruction as such.
33 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
34 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
35 bbegin to implement memory map.
36 * dv-tx3904cpu.c: New file.
37 * dv-tx3904irc.c: New file.
40 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
42 * mips.igen (check_mt_hilo): Create a separate r3900 version.
44 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
46 * r5900.igen: Replace the calls and the definition of the
47 function check_op_hilo_hi1lo1 with the pair
48 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
51 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
53 * tx.igen (madd,maddu): Replace calls to check_op_hilo
54 with calls to check_div_hilo.
57 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
59 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
60 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
61 Add special r3900 version of do_mult_hilo.
62 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
63 with calls to check_mult_hilo.
64 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
65 with calls to check_div_hilo.
67 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
69 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
70 Document a replacement.
72 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
74 * interp.c (sim_monitor): Make mon_printf work.
76 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
78 * sim-main.h (INSN_NAME): New arg `cpu'.
81 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
83 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
88 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
90 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
91 * r5900.igen (r59fp_overflow): Use.
93 * r5900.igen (r59fp_op3): Rename to
94 (r59fp_mula): This, delete opm argument.
95 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
96 (r59fp_mula): Overflowing product propogates through to result.
97 (r59fp_mula): ACC to the MAX propogates to result.
98 (r59fp_mula): Underflow during multiply only sets SU.
101 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
103 * configure: Regenerated to track ../common/aclocal.m4 changes.
105 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
107 * configure: Regenerated to track ../common/aclocal.m4 changes.
110 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
112 * acconfig.h: New file.
113 * configure.in: Reverted change of Apr 24; use sinclude again.
115 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
117 * configure: Regenerated to track ../common/aclocal.m4 changes.
120 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
122 * configure.in: Don't call sinclude.
124 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
126 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
128 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
130 * mips.igen (ERET): Implement.
132 * interp.c (decode_coproc): Return sign-extended EPC.
134 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
136 * interp.c (signal_exception): Do not ignore Trap.
137 (signal_exception): On TRAP, restart at exception address.
138 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
139 (signal_exception): Update.
140 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
141 so that TRAP instructions are caught.
143 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
145 * sim-main.h (struct hilo_access, struct hilo_history): Define,
146 contains HI/LO access history.
147 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
148 (HIACCESS, LOACCESS): Delete, replace with
149 (HIHISTORY, LOHISTORY): New macros.
150 (start-sanitize-r5900):
151 (struct sim_5900_cpu): Make hi1access, lo1access of type
153 (HI1ACCESS, LO1ACCESS): Delete, replace with
154 (HI1HISTORY, LO1HISTORY): New macros.
155 (end-sanitize-r5900):
156 (CHECKHILO): Delete all, moved to mips.igen
158 * gencode.c (build_instruction): Do not generate checks for
159 correct HI/LO register usage.
161 * interp.c (old_engine_run): Delete checks for correct HI/LO
164 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
165 check_mf_cycles): New functions.
166 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
167 do_divu, domultx, do_mult, do_multu): Use.
169 * tx.igen ("madd", "maddu"): Use.
170 (start-sanitize-r5900):
172 r5900.igen: Update all HI/LO checks.
173 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
174 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
175 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
176 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
177 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
179 (end-sanitize-r5900):
182 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
184 * interp.c (decode_coproc): Correct CMFC2/QMTC2
187 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
188 instead of a single 128-bit access.
192 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
194 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
195 * interp.c (cop_[ls]q): Fixes corresponding to above.
199 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
201 * interp.c (decode_coproc): Adapt COP2 micro interlock to
202 clarified specs. Reset "M" bit; exit also on "E" bit.
206 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
208 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
209 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
211 * r5900.igen (r59fp_unpack): New function.
212 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
213 RSQRT.S, SQRT.S): Use.
214 (r59fp_zero): New function.
215 (r59fp_overflow): Generate r5900 specific overflow value.
216 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
218 (CVT.S.W, CVT.W.S): Exchange implementations.
220 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
224 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
226 * configure.in (tx19, sim_use_gen): Switch to igen.
227 * configure: Re-build.
231 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
233 * interp.c (decode_coproc): Make COP2 branch code compile after
234 igen signature changes.
237 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
239 * mips.igen (DSRAV): Use function do_dsrav.
240 (SRAV): Use new function do_srav.
242 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
243 (B): Sign extend 11 bit immediate.
244 (EXT-B*): Shift 16 bit immediate left by 1.
245 (ADDIU*): Don't sign extend immediate value.
247 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
249 * m16run.c (sim_engine_run): Restore CIA after handling an event.
252 * mips.igen (mtc0): Valid tx19 instruction.
255 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
258 * mips.igen (delayslot32, nullify_next_insn): New functions.
259 (m16.igen): Always include.
260 (do_*): Add more tracing.
262 * m16.igen (delayslot16): Add NIA argument, could be called by a
263 32 bit MIPS16 instruction.
265 * interp.c (ifetch16): Move function from here.
266 * sim-main.c (ifetch16): To here.
268 * sim-main.c (ifetch16, ifetch32): Update to match current
269 implementations of LH, LW.
270 (signal_exception): Don't print out incorrect hex value of illegal
273 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
275 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
278 * m16.igen: Implement MIPS16 instructions.
280 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
281 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
282 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
283 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
284 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
285 bodies of corresponding code from 32 bit insn to these. Also used
286 by MIPS16 versions of functions.
288 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
289 (IMEM16): Drop NR argument from macro.
292 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
294 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
295 of VU lower instruction.
299 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
301 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
304 * sim-main.h: Removed attempt at allowing 128-bit access.
308 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
310 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
312 * interp.c (decode_coproc): Refer to VU CIA as a "special"
313 register, not as a "misc" register. Aha. Add activity
314 assertions after VCALLMS* instructions.
318 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
320 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
321 to upper code of generated VU instruction.
325 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
327 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
329 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
332 * r5900.igen (SQC2): Thinko.
336 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
338 * interp.c (*): Adapt code to merged VU device & state structs.
339 (decode_coproc): Execute COP2 each macroinstruction without
340 pipelining, by stepping VU to completion state. Adapted to
341 read_vu_*_reg style of register access.
343 * mips.igen ([SL]QC2): Removed these COP2 instructions.
345 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
347 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
350 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
352 * Makefile.in (SIM_OBJS): Add sim-main.o.
354 * sim-main.h (address_translation, load_memory, store_memory,
355 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
357 (pr_addr, pr_uword64): Declare.
358 (sim-main.c): Include when H_REVEALS_MODULE_P.
360 * interp.c (address_translation, load_memory, store_memory,
361 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
363 * sim-main.c: To here. Fix compilation problems.
365 * configure.in: Enable inlining.
366 * configure: Re-config.
368 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
370 * configure: Regenerated to track ../common/aclocal.m4 changes.
372 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
374 * mips.igen: Include tx.igen.
375 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
376 * tx.igen: New file, contains MADD and MADDU.
378 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
379 the hardwired constant `7'.
380 (store_memory): Ditto.
381 (LOADDRMASK): Move definition to sim-main.h.
383 mips.igen (MTC0): Enable for r3900.
386 mips.igen (do_load_byte): Delete.
387 (do_load, do_store, do_load_left, do_load_write, do_store_left,
388 do_store_right): New functions.
389 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
391 configure.in: Let the tx39 use igen again.
394 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
396 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
397 not an address sized quantity. Return zero for cache sizes.
399 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
401 * mips.igen (r3900): r3900 does not support 64 bit integer
405 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
407 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
411 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
413 * interp.c (decode_coproc): Continuing COP2 work.
414 (cop_[ls]q): Make sky-target-only.
416 * sim-main.h (COP_[LS]Q): Make sky-target-only.
418 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
420 * configure.in (mipstx39*-*-*): Use gencode simulator rather
422 * configure : Rebuild.
425 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
427 * interp.c (decode_coproc): Added a missing TARGET_SKY check
428 around COP2 implementation skeleton.
432 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
434 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
436 * interp.c (sim_{load,store}_register): Use new vu[01]_device
437 static to access VU registers.
438 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
439 decoding. Work in progress.
441 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
442 overlapping/redundant bit pattern.
443 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
446 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
449 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
450 access to coprocessor registers.
452 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
454 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
456 * configure: Regenerated to track ../common/aclocal.m4 changes.
458 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
460 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
462 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
464 * configure: Regenerated to track ../common/aclocal.m4 changes.
465 * config.in: Regenerated to track ../common/aclocal.m4 changes.
467 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
469 * configure: Regenerated to track ../common/aclocal.m4 changes.
471 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
473 * interp.c (Max, Min): Comment out functions. Not yet used.
475 start-sanitize-vr4320
476 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
478 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
481 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
483 * configure: Regenerated to track ../common/aclocal.m4 changes.
485 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
487 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
488 configurable settings for stand-alone simulator.
491 * configure.in: Added --with-sim-gpu2 option to specify path of
492 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
493 links/compiles stand-alone simulator with this library.
495 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
497 * configure.in: Added X11 search, just in case.
499 * configure: Regenerated.
501 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
503 * interp.c (sim_write, sim_read, load_memory, store_memory):
504 Replace sim_core_*_map with read_map, write_map, exec_map resp.
506 start-sanitize-vr4320
507 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
509 * vr4320.igen (clz,dclz) : Added.
510 (dmac): Replaced 99, with LO.
513 start-sanitize-vr5400
514 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
516 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
519 start-sanitize-vr4320
520 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
522 * vr4320.igen: New file.
523 * Makefile.in (vr4320.igen) : Added.
524 * configure.in (mips64vr4320-*-*): Added.
525 * configure : Rebuilt.
526 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
527 Add the vr4320 model entry and mark the vr4320 insn as necessary.
530 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
532 * sim-main.h (GETFCC): Return an unsigned value.
535 * r5900.igen: Use an unsigned array index variable `i'.
536 (QFSRV): Ditto for variable bytes.
539 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
541 * mips.igen (DIV): Fix check for -1 / MIN_INT.
542 (DADD): Result destination is RD not RT.
545 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
546 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
550 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
552 * sim-main.h (HIACCESS, LOACCESS): Always define.
554 * mdmx.igen (Maxi, Mini): Rename Max, Min.
556 * interp.c (sim_info): Delete.
558 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
560 * interp.c (DECLARE_OPTION_HANDLER): Use it.
561 (mips_option_handler): New argument `cpu'.
562 (sim_open): Update call to sim_add_option_table.
564 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
566 * mips.igen (CxC1): Add tracing.
569 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
571 * r5900.igen (StoreFP): Delete.
572 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
574 (rsqrt.s, sqrt.s): Implement.
575 (r59cond): New function.
576 (C.COND.S): Call r59cond in assembler line.
577 (cvt.w.s, cvt.s.w): Implement.
579 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
582 * sim-main.h: Define an enum of r5900 FCSR bit fields.
586 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
588 * r5900.igen: Add tracing to all p* instructions.
590 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
592 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
593 to get gdb talking to re-aranged sim_cpu register structure.
596 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
598 * sim-main.h (Max, Min): Declare.
600 * interp.c (Max, Min): New functions.
602 * mips.igen (BC1): Add tracing.
604 start-sanitize-vr5400
605 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
607 * mdmx.igen: Tag all functions as requiring either with mdmx or
612 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
614 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
616 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
618 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
620 * r5900.igen: Rewrite.
622 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
624 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
625 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
628 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
630 * interp.c Added memory map for stack in vr4100
632 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
634 * interp.c (load_memory): Add missing "break"'s.
636 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
638 * interp.c (sim_store_register, sim_fetch_register): Pass in
639 length parameter. Return -1.
641 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
643 * interp.c: Added hardware init hook, fixed warnings.
645 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
647 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
649 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
651 * interp.c (ifetch16): New function.
653 * sim-main.h (IMEM32): Rename IMEM.
654 (IMEM16_IMMED): Define.
656 (DELAY_SLOT): Update.
658 * m16run.c (sim_engine_run): New file.
660 * m16.igen: All instructions except LB.
661 (LB): Call do_load_byte.
662 * mips.igen (do_load_byte): New function.
663 (LB): Call do_load_byte.
665 * mips.igen: Move spec for insn bit size and high bit from here.
666 * Makefile.in (tmp-igen, tmp-m16): To here.
668 * m16.dc: New file, decode mips16 instructions.
670 * Makefile.in (SIM_NO_ALL): Define.
671 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
674 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
678 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
680 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
681 point unit to 32 bit registers.
682 * configure: Re-generate.
684 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
686 * configure.in (sim_use_gen): Make IGEN the default simulator
687 generator for generic 32 and 64 bit mips targets.
688 * configure: Re-generate.
690 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
692 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
695 * interp.c (sim_fetch_register, sim_store_register): Read/write
696 FGR from correct location.
697 (sim_open): Set size of FGR's according to
698 WITH_TARGET_FLOATING_POINT_BITSIZE.
700 * sim-main.h (FGR): Store floating point registers in a separate
703 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
705 * configure: Regenerated to track ../common/aclocal.m4 changes.
707 start-sanitize-vr5400
708 * mdmx.igen: Mark all instructions as 64bit/fp specific.
711 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
713 * interp.c (ColdReset): Call PENDING_INVALIDATE.
715 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
717 * interp.c (pending_tick): New function. Deliver pending writes.
719 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
720 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
721 it can handle mixed sized quantites and single bits.
723 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
725 * interp.c (oengine.h): Do not include when building with IGEN.
726 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
727 (sim_info): Ditto for PROCESSOR_64BIT.
728 (sim_monitor): Replace ut_reg with unsigned_word.
729 (*): Ditto for t_reg.
730 (LOADDRMASK): Define.
731 (sim_open): Remove defunct check that host FP is IEEE compliant,
732 using software to emulate floating point.
733 (value_fpr, ...): Always compile, was conditional on HASFPU.
735 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
737 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
740 * interp.c (SD, CPU): Define.
741 (mips_option_handler): Set flags in each CPU.
742 (interrupt_event): Assume CPU 0 is the one being iterrupted.
743 (sim_close): Do not clear STATE, deleted anyway.
744 (sim_write, sim_read): Assume CPU zero's vm should be used for
746 (sim_create_inferior): Set the PC for all processors.
747 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
749 (mips16_entry): Pass correct nr of args to store_word, load_word.
750 (ColdReset): Cold reset all cpu's.
751 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
752 (sim_monitor, load_memory, store_memory, signal_exception): Use
753 `CPU' instead of STATE_CPU.
756 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
759 * sim-main.h (signal_exception): Add sim_cpu arg.
760 (SignalException*): Pass both SD and CPU to signal_exception.
761 * interp.c (signal_exception): Update.
763 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
765 (sync_operation, prefetch, cache_op, store_memory, load_memory,
766 address_translation): Ditto
767 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
769 start-sanitize-vr5400
770 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
772 (ByteAlign): Use StoreFPR, pass args in correct order.
776 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
778 * configure.in (sim_igen_filter): For r5900, configure as SMP.
781 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
783 * configure: Regenerated to track ../common/aclocal.m4 changes.
785 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
788 * configure.in (sim_igen_filter): For r5900, use igen.
789 * configure: Re-generate.
792 * interp.c (sim_engine_run): Add `nr_cpus' argument.
794 * mips.igen (model): Map processor names onto BFD name.
796 * sim-main.h (CPU_CIA): Delete.
797 (SET_CIA, GET_CIA): Define
799 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
801 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
804 * configure.in (default_endian): Configure a big-endian simulator
806 * configure: Re-generate.
808 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
812 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
814 * interp.c (sim_monitor): Handle Densan monitor outbyte
815 and inbyte functions.
817 1997-12-29 Felix Lee <flee@cygnus.com>
819 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
821 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
823 * Makefile.in (tmp-igen): Arrange for $zero to always be
824 reset to zero after every instruction.
826 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
828 * configure: Regenerated to track ../common/aclocal.m4 changes.
831 start-sanitize-vr5400
832 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
834 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
838 start-sanitize-vr5400
839 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
841 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
842 vr5400 with the vr5000 as the default.
845 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
847 * mips.igen (MSUB): Fix to work like MADD.
848 * gencode.c (MSUB): Similarly.
850 start-sanitize-vr5400
851 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
853 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
857 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
859 * configure: Regenerated to track ../common/aclocal.m4 changes.
861 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
863 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
865 start-sanitize-vr5400
866 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
867 (value_cc, store_cc): Implement.
869 * sim-main.h: Add 8*3*8 bit accumulator.
871 * vr5400.igen: Move mdmx instructins from here
872 * mdmx.igen: To here - new file. Add/fix missing instructions.
873 * mips.igen: Include mdmx.igen.
874 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
877 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
879 * sim-main.h (sim-fpu.h): Include.
881 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
882 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
883 using host independant sim_fpu module.
885 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
887 * interp.c (signal_exception): Report internal errors with SIGABRT
890 * sim-main.h (C0_CONFIG): New register.
891 (signal.h): No longer include.
893 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
895 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
897 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
899 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
901 * mips.igen: Tag vr5000 instructions.
902 (ANDI): Was missing mipsIV model, fix assembler syntax.
903 (do_c_cond_fmt): New function.
904 (C.cond.fmt): Handle mips I-III which do not support CC field
906 (bc1): Handle mips IV which do not have a delaed FCC separatly.
907 (SDR): Mask paddr when BigEndianMem, not the converse as specified
909 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
910 vr5000 which saves LO in a GPR separatly.
912 * configure.in (enable-sim-igen): For vr5000, select vr5000
913 specific instructions.
914 * configure: Re-generate.
916 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
918 * Makefile.in (SIM_OBJS): Add sim-fpu module.
920 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
921 fmt_uninterpreted_64 bit cases to switch. Convert to
924 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
926 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
927 as specified in IV3.2 spec.
928 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
930 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
932 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
933 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
934 (start-sanitize-r5900):
935 (LWXC1, SWXC1): Delete from r5900 instruction set.
936 (end-sanitize-r5900):
937 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
938 PENDING_FILL versions of instructions. Simplify.
940 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
942 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
944 (MTHI, MFHI): Disable code checking HI-LO.
946 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
948 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
950 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
952 * gencode.c (build_mips16_operands): Replace IPC with cia.
954 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
955 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
957 (UndefinedResult): Replace function with macro/function
959 (sim_engine_run): Don't save PC in IPC.
961 * sim-main.h (IPC): Delete.
963 start-sanitize-vr5400
964 * vr5400.igen (vr): Add missing cia argument to value_fpr.
965 (do_select): Rename function select.
968 * interp.c (signal_exception, store_word, load_word,
969 address_translation, load_memory, store_memory, cache_op,
970 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
971 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
972 current instruction address - cia - argument.
973 (sim_read, sim_write): Call address_translation directly.
974 (sim_engine_run): Rename variable vaddr to cia.
975 (signal_exception): Pass cia to sim_monitor
977 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
978 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
979 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
981 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
982 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
985 * interp.c (signal_exception): Pass restart address to
988 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
989 idecode.o): Add dependency.
991 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
993 (DELAY_SLOT): Update NIA not PC with branch address.
994 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
996 * mips.igen: Use CIA not PC in branch calculations.
997 (illegal): Call SignalException.
998 (BEQ, ADDIU): Fix assembler.
1000 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1002 * m16.igen (JALX): Was missing.
1004 * configure.in (enable-sim-igen): New configuration option.
1005 * configure: Re-generate.
1007 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1009 * interp.c (load_memory, store_memory): Delete parameter RAW.
1010 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1011 bypassing {load,store}_memory.
1013 * sim-main.h (ByteSwapMem): Delete definition.
1015 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1017 * interp.c (sim_do_command, sim_commands): Delete mips specific
1018 commands. Handled by module sim-options.
1020 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1021 (WITH_MODULO_MEMORY): Define.
1023 * interp.c (sim_info): Delete code printing memory size.
1025 * interp.c (mips_size): Nee sim_size, delete function.
1027 (monitor, monitor_base, monitor_size): Delete global variables.
1028 (sim_open, sim_close): Delete code creating monitor and other
1029 memory regions. Use sim-memopts module, via sim_do_commandf, to
1030 manage memory regions.
1031 (load_memory, store_memory): Use sim-core for memory model.
1033 * interp.c (address_translation): Delete all memory map code
1034 except line forcing 32 bit addresses.
1036 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1038 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1041 * interp.c (logfh, logfile): Delete globals.
1042 (sim_open, sim_close): Delete code opening & closing log file.
1043 (mips_option_handler): Delete -l and -n options.
1044 (OPTION mips_options): Ditto.
1046 * interp.c (OPTION mips_options): Rename option trace to dinero.
1047 (mips_option_handler): Update.
1049 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1051 * interp.c (fetch_str): New function.
1052 (sim_monitor): Rewrite using sim_read & sim_write.
1053 (sim_open): Check magic number.
1054 (sim_open): Write monitor vectors into memory using sim_write.
1055 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1056 (sim_read, sim_write): Simplify - transfer data one byte at a
1058 (load_memory, store_memory): Clarify meaning of parameter RAW.
1060 * sim-main.h (isHOST): Defete definition.
1061 (isTARGET): Mark as depreciated.
1062 (address_translation): Delete parameter HOST.
1064 * interp.c (address_translation): Delete parameter HOST.
1067 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1069 * gencode.c: Add tx49 configury and insns.
1070 * configure.in: Add tx49 configury.
1071 * configure: Update.
1074 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1078 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1079 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1081 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1083 * mips.igen: Add model filter field to records.
1085 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1087 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1089 interp.c (sim_engine_run): Do not compile function sim_engine_run
1090 when WITH_IGEN == 1.
1092 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1093 target architecture.
1095 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1096 igen. Replace with configuration variables sim_igen_flags /
1099 start-sanitize-r5900
1100 * r5900.igen: New file. Copy r5900 insns here.
1102 start-sanitize-vr5400
1103 * vr5400.igen: New file.
1105 * m16.igen: New file. Copy mips16 insns here.
1106 * mips.igen: From here.
1108 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1110 start-sanitize-vr5400
1111 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1113 * configure.in: Add mips64vr5400 target.
1114 * configure: Re-generate.
1117 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1119 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1121 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1123 * gencode.c (build_instruction): Follow sim_write's lead in using
1124 BigEndianMem instead of !ByteSwapMem.
1126 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1128 * configure.in (sim_gen): Dependent on target, select type of
1129 generator. Always select old style generator.
1131 configure: Re-generate.
1133 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1135 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1136 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1137 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1138 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1139 SIM_@sim_gen@_*, set by autoconf.
1141 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1143 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1145 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1146 CURRENT_FLOATING_POINT instead.
1148 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1149 (address_translation): Raise exception InstructionFetch when
1150 translation fails and isINSTRUCTION.
1152 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1153 sim_engine_run): Change type of of vaddr and paddr to
1155 (address_translation, prefetch, load_memory, store_memory,
1156 cache_op): Change type of vAddr and pAddr to address_word.
1158 * gencode.c (build_instruction): Change type of vaddr and paddr to
1161 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1164 macro to obtain result of ALU op.
1166 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1168 * interp.c (sim_info): Call profile_print.
1170 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1172 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1174 * sim-main.h (WITH_PROFILE): Do not define, defined in
1175 common/sim-config.h. Use sim-profile module.
1176 (simPROFILE): Delete defintion.
1178 * interp.c (PROFILE): Delete definition.
1179 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1180 (sim_close): Delete code writing profile histogram.
1181 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1183 (sim_engine_run): Delete code profiling the PC.
1185 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1187 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1189 * interp.c (sim_monitor): Make register pointers of type
1192 * sim-main.h: Make registers of type unsigned_word not
1195 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1197 start-sanitize-r5900
1198 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1199 ...): Move to sim-main.h
1202 * interp.c (sync_operation): Rename from SyncOperation, make
1203 global, add SD argument.
1204 (prefetch): Rename from Prefetch, make global, add SD argument.
1205 (decode_coproc): Make global.
1207 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1209 * gencode.c (build_instruction): Generate DecodeCoproc not
1210 decode_coproc calls.
1212 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1213 (SizeFGR): Move to sim-main.h
1214 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1215 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1216 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1218 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1219 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1220 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1221 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1222 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1223 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1225 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1227 (sim-alu.h): Include.
1228 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1229 (sim_cia): Typedef to instruction_address.
1231 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1233 * Makefile.in (interp.o): Rename generated file engine.c to
1238 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1240 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1242 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1244 * gencode.c (build_instruction): For "FPSQRT", output correct
1245 number of arguments to Recip.
1247 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1249 * Makefile.in (interp.o): Depends on sim-main.h
1251 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1253 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1254 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1255 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1256 STATE, DSSTATE): Define
1257 (GPR, FGRIDX, ..): Define.
1259 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1260 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1261 (GPR, FGRIDX, ...): Delete macros.
1263 * interp.c: Update names to match defines from sim-main.h
1265 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1267 * interp.c (sim_monitor): Add SD argument.
1268 (sim_warning): Delete. Replace calls with calls to
1270 (sim_error): Delete. Replace calls with sim_io_error.
1271 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1272 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1273 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1275 (mips_size): Rename from sim_size. Add SD argument.
1277 * interp.c (simulator): Delete global variable.
1278 (callback): Delete global variable.
1279 (mips_option_handler, sim_open, sim_write, sim_read,
1280 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1281 sim_size,sim_monitor): Use sim_io_* not callback->*.
1282 (sim_open): ZALLOC simulator struct.
1283 (PROFILE): Do not define.
1285 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1287 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1288 support.h with corresponding code.
1290 * sim-main.h (word64, uword64), support.h: Move definition to
1292 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1295 * Makefile.in: Update dependencies
1296 * interp.c: Do not include.
1298 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1300 * interp.c (address_translation, load_memory, store_memory,
1301 cache_op): Rename to from AddressTranslation et.al., make global,
1304 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1307 * interp.c (SignalException): Rename to signal_exception, make
1310 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1312 * sim-main.h (SignalException, SignalExceptionInterrupt,
1313 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1314 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1315 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1318 * interp.c, support.h: Use.
1320 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1323 to value_fpr / store_fpr. Add SD argument.
1324 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1325 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1327 * sim-main.h (ValueFPR, StoreFPR): Define.
1329 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1331 * interp.c (sim_engine_run): Check consistency between configure
1332 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1335 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1336 (mips_fpu): Configure WITH_FLOATING_POINT.
1337 (mips_endian): Configure WITH_TARGET_ENDIAN.
1338 * configure: Update.
1340 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1342 * configure: Regenerated to track ../common/aclocal.m4 changes.
1344 start-sanitize-r5900
1345 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1347 * interp.c (MAX_REG): Allow up-to 128 registers.
1348 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1349 (REGISTER_SA): Ditto.
1350 (sim_open): Initialize register_widths for r5900 specific
1352 (sim_fetch_register, sim_store_register): Check for request of
1353 r5900 specific SA register. Check for request for hi 64 bits of
1354 r5900 specific registers.
1357 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1359 * configure: Regenerated.
1361 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1363 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1365 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1367 * gencode.c (print_igen_insn_models): Assume certain architectures
1368 include all mips* instructions.
1369 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1372 * Makefile.in (tmp.igen): Add target. Generate igen input from
1375 * gencode.c (FEATURE_IGEN): Define.
1376 (main): Add --igen option. Generate output in igen format.
1377 (process_instructions): Format output according to igen option.
1378 (print_igen_insn_format): New function.
1379 (print_igen_insn_models): New function.
1380 (process_instructions): Only issue warnings and ignore
1381 instructions when no FEATURE_IGEN.
1383 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1385 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1388 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390 * configure: Regenerated to track ../common/aclocal.m4 changes.
1392 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1394 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1395 SIM_RESERVED_BITS): Delete, moved to common.
1396 (SIM_EXTRA_CFLAGS): Update.
1398 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1400 * configure.in: Configure non-strict memory alignment.
1401 * configure: Regenerated to track ../common/aclocal.m4 changes.
1403 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1405 * configure: Regenerated to track ../common/aclocal.m4 changes.
1407 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1409 * gencode.c (SDBBP,DERET): Added (3900) insns.
1410 (RFE): Turn on for 3900.
1411 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1412 (dsstate): Made global.
1413 (SUBTARGET_R3900): Added.
1414 (CANCELDELAYSLOT): New.
1415 (SignalException): Ignore SystemCall rather than ignore and
1416 terminate. Add DebugBreakPoint handling.
1417 (decode_coproc): New insns RFE, DERET; and new registers Debug
1418 and DEPC protected by SUBTARGET_R3900.
1419 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1421 * Makefile.in,configure.in: Add mips subtarget option.
1422 * configure: Update.
1424 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1426 * gencode.c: Add r3900 (tx39).
1429 * gencode.c: Fix some configuration problems by improving
1430 the relationship between tx19 and tx39.
1433 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1435 * gencode.c (build_instruction): Don't need to subtract 4 for
1438 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1440 * interp.c: Correct some HASFPU problems.
1442 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1444 * configure: Regenerated to track ../common/aclocal.m4 changes.
1446 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448 * interp.c (mips_options): Fix samples option short form, should
1451 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1453 * interp.c (sim_info): Enable info code. Was just returning.
1455 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1457 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1460 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1464 (build_instruction): Ditto for LL.
1467 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1469 * mips/configure.in, mips/gencode: Add tx19/r1900.
1472 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1474 * configure: Regenerated to track ../common/aclocal.m4 changes.
1476 start-sanitize-r5900
1477 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1479 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1480 for overflow due to ABS of MININT, set result to MAXINT.
1481 (build_instruction): For "psrlvw", signextend bit 31.
1484 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1486 * configure: Regenerated to track ../common/aclocal.m4 changes.
1489 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1491 * interp.c (sim_open): Add call to sim_analyze_program, update
1494 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1496 * interp.c (sim_kill): Delete.
1497 (sim_create_inferior): Add ABFD argument. Set PC from same.
1498 (sim_load): Move code initializing trap handlers from here.
1499 (sim_open): To here.
1500 (sim_load): Delete, use sim-hload.c.
1502 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1504 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1506 * configure: Regenerated to track ../common/aclocal.m4 changes.
1509 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1511 * interp.c (sim_open): Add ABFD argument.
1512 (sim_load): Move call to sim_config from here.
1513 (sim_open): To here. Check return status.
1515 start-sanitize-r5900
1516 * gencode.c (build_instruction): Do not define x8000000000000000,
1517 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1520 start-sanitize-r5900
1521 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1523 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1524 "pdivuw" check for overflow due to signed divide by -1.
1527 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1529 * gencode.c (build_instruction): Two arg MADD should
1530 not assign result to $0.
1532 start-sanitize-r5900
1533 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1535 * gencode.c (build_instruction): For "ppac5" use unsigned
1536 arrithmetic so that the sign bit doesn't smear when right shifted.
1537 (build_instruction): For "pdiv" perform sign extension when
1538 storing results in HI and LO.
1539 (build_instructions): For "pdiv" and "pdivbw" check for
1541 (build_instruction): For "pmfhl.slw" update hi part of dest
1542 register as well as low part.
1543 (build_instruction): For "pmfhl" portably handle long long values.
1544 (build_instruction): For "pmfhl.sh" correctly negative values.
1545 Store half words 2 and three in the correct place.
1546 (build_instruction): For "psllvw", sign extend value after shift.
1549 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1551 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1552 * sim/mips/configure.in: Regenerate.
1554 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1556 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1557 signed8, unsigned8 et.al. types.
1559 start-sanitize-r5900
1560 * gencode.c (build_instruction): For PMULTU* do not sign extend
1561 registers. Make generated code easier to debug.
1564 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1565 hosts when selecting subreg.
1567 start-sanitize-r5900
1568 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1570 * gencode.c (type_for_data_len): For 32bit operations concerned
1571 with overflow, perform op using 64bits.
1572 (build_instruction): For PADD, always compute operation using type
1573 returned by type_for_data_len.
1574 (build_instruction): For PSUBU, when overflow, saturate to zero as
1578 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1580 start-sanitize-r5900
1581 * gencode.c (build_instruction): Handle "pext5" according to
1582 version 1.95 of the r5900 ISA.
1584 * gencode.c (build_instruction): Handle "ppac5" according to
1585 version 1.95 of the r5900 ISA.
1588 * interp.c (sim_engine_run): Reset the ZERO register to zero
1589 regardless of FEATURE_WARN_ZERO.
1590 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1592 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1594 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1595 (SignalException): For BreakPoints ignore any mode bits and just
1597 (SignalException): Always set the CAUSE register.
1599 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1602 exception has been taken.
1604 * interp.c: Implement the ERET and mt/f sr instructions.
1606 start-sanitize-r5900
1607 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1609 * gencode.c (build_instruction): For paddu, extract unsigned
1612 * gencode.c (build_instruction): Saturate padds instead of padd
1616 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618 * interp.c (SignalException): Don't bother restarting an
1621 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1623 * interp.c (SignalException): Really take an interrupt.
1624 (interrupt_event): Only deliver interrupts when enabled.
1626 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * interp.c (sim_info): Only print info when verbose.
1629 (sim_info) Use sim_io_printf for output.
1631 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1636 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1638 * interp.c (sim_do_command): Check for common commands if a
1639 simulator specific command fails.
1641 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1643 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1644 and simBE when DEBUG is defined.
1646 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1648 * interp.c (interrupt_event): New function. Pass exception event
1649 onto exception handler.
1651 * configure.in: Check for stdlib.h.
1652 * configure: Regenerate.
1654 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1655 variable declaration.
1656 (build_instruction): Initialize memval1.
1657 (build_instruction): Add UNUSED attribute to byte, bigend,
1659 (build_operands): Ditto.
1661 * interp.c: Fix GCC warnings.
1662 (sim_get_quit_code): Delete.
1664 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1665 * Makefile.in: Ditto.
1666 * configure: Re-generate.
1668 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1670 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1672 * interp.c (mips_option_handler): New function parse argumes using
1674 (myname): Replace with STATE_MY_NAME.
1675 (sim_open): Delete check for host endianness - performed by
1677 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1678 (sim_open): Move much of the initialization from here.
1679 (sim_load): To here. After the image has been loaded and
1681 (sim_open): Move ColdReset from here.
1682 (sim_create_inferior): To here.
1683 (sim_open): Make FP check less dependant on host endianness.
1685 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1687 * interp.c (sim_set_callbacks): Delete.
1689 * interp.c (membank, membank_base, membank_size): Replace with
1690 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1691 (sim_open): Remove call to callback->init. gdb/run do this.
1695 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1697 * interp.c (big_endian_p): Delete, replaced by
1698 current_target_byte_order.
1700 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702 * interp.c (host_read_long, host_read_word, host_swap_word,
1703 host_swap_long): Delete. Using common sim-endian.
1704 (sim_fetch_register, sim_store_register): Use H2T.
1705 (pipeline_ticks): Delete. Handled by sim-events.
1707 (sim_engine_run): Update.
1709 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1713 (SignalException): To here. Signal using sim_engine_halt.
1714 (sim_stop_reason): Delete, moved to common.
1716 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1718 * interp.c (sim_open): Add callback argument.
1719 (sim_set_callbacks): Delete SIM_DESC argument.
1722 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1724 * Makefile.in (SIM_OBJS): Add common modules.
1726 * interp.c (sim_set_callbacks): Also set SD callback.
1727 (set_endianness, xfer_*, swap_*): Delete.
1728 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1729 Change to functions using sim-endian macros.
1730 (control_c, sim_stop): Delete, use common version.
1731 (simulate): Convert into.
1732 (sim_engine_run): This function.
1733 (sim_resume): Delete.
1735 * interp.c (simulation): New variable - the simulator object.
1736 (sim_kind): Delete global - merged into simulation.
1737 (sim_load): Cleanup. Move PC assignment from here.
1738 (sim_create_inferior): To here.
1740 * sim-main.h: New file.
1741 * interp.c (sim-main.h): Include.
1743 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1745 * configure: Regenerated to track ../common/aclocal.m4 changes.
1747 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1749 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1751 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1753 * gencode.c (build_instruction): DIV instructions: check
1754 for division by zero and integer overflow before using
1755 host's division operation.
1757 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1759 * Makefile.in (SIM_OBJS): Add sim-load.o.
1760 * interp.c: #include bfd.h.
1761 (target_byte_order): Delete.
1762 (sim_kind, myname, big_endian_p): New static locals.
1763 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1764 after argument parsing. Recognize -E arg, set endianness accordingly.
1765 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1766 load file into simulator. Set PC from bfd.
1767 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1768 (set_endianness): Use big_endian_p instead of target_byte_order.
1770 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772 * interp.c (sim_size): Delete prototype - conflicts with
1773 definition in remote-sim.h. Correct definition.
1775 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1777 * configure: Regenerated to track ../common/aclocal.m4 changes.
1780 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1782 * interp.c (sim_open): New arg `kind'.
1784 * configure: Regenerated to track ../common/aclocal.m4 changes.
1786 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1788 * configure: Regenerated to track ../common/aclocal.m4 changes.
1790 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1792 * interp.c (sim_open): Set optind to 0 before calling getopt.
1794 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1796 * configure: Regenerated to track ../common/aclocal.m4 changes.
1798 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1800 * interp.c : Replace uses of pr_addr with pr_uword64
1801 where the bit length is always 64 independent of SIM_ADDR.
1802 (pr_uword64) : added.
1804 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1806 * configure: Re-generate.
1808 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1810 * configure: Regenerate to track ../common/aclocal.m4 changes.
1812 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1814 * interp.c (sim_open): New SIM_DESC result. Argument is now
1816 (other sim_*): New SIM_DESC argument.
1818 start-sanitize-r5900
1819 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1821 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1822 Change values to avoid overloading DOUBLEWORD which is tested
1824 * gencode.c: reinstate "offending code".
1827 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1829 * interp.c: Fix printing of addresses for non-64-bit targets.
1830 (pr_addr): Add function to print address based on size.
1831 start-sanitize-r5900
1832 * gencode.c: #ifdef out offending code until a permanent fix
1833 can be added. Code is causing build errors for non-5900 mips targets.
1836 start-sanitize-r5900
1837 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1839 * gencode.c (process_instructions): Correct test for ISA dependent
1840 architecture bits in isa field of MIPS_DECODE.
1843 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1845 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1847 start-sanitize-r5900
1848 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1850 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1854 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1856 * gencode.c (build_mips16_operands): Correct computation of base
1857 address for extended PC relative instruction.
1859 start-sanitize-r5900
1860 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1862 * Makefile.in, configure, configure.in, gencode.c,
1863 interp.c, support.h: add r5900.
1866 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1868 * interp.c (mips16_entry): Add support for floating point cases.
1869 (SignalException): Pass floating point cases to mips16_entry.
1870 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1872 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1874 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1875 and then set the state to fmt_uninterpreted.
1876 (COP_SW): Temporarily set the state to fmt_word while calling
1879 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1881 * gencode.c (build_instruction): The high order may be set in the
1882 comparison flags at any ISA level, not just ISA 4.
1884 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1886 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1887 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1888 * configure.in: sinclude ../common/aclocal.m4.
1889 * configure: Regenerated.
1891 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1893 * configure: Rebuild after change to aclocal.m4.
1895 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1897 * configure configure.in Makefile.in: Update to new configure
1898 scheme which is more compatible with WinGDB builds.
1899 * configure.in: Improve comment on how to run autoconf.
1900 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1901 * Makefile.in: Use autoconf substitution to install common
1904 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1906 * gencode.c (build_instruction): Use BigEndianCPU instead of
1909 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1911 * interp.c (sim_monitor): Make output to stdout visible in
1912 wingdb's I/O log window.
1914 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1916 * support.h: Undo previous change to SIGTRAP
1919 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1921 * interp.c (store_word, load_word): New static functions.
1922 (mips16_entry): New static function.
1923 (SignalException): Look for mips16 entry and exit instructions.
1924 (simulate): Use the correct index when setting fpr_state after
1925 doing a pending move.
1927 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1929 * interp.c: Fix byte-swapping code throughout to work on
1930 both little- and big-endian hosts.
1932 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1934 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1935 with gdb/config/i386/xm-windows.h.
1937 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1939 * gencode.c (build_instruction): Work around MSVC++ code gen bug
1940 that messes up arithmetic shifts.
1942 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
1944 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
1945 SIGTRAP and SIGQUIT for _WIN32.
1947 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
1949 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1950 force a 64 bit multiplication.
1951 (build_instruction) [OR]: In mips16 mode, don't do anything if the
1952 destination register is 0, since that is the default mips16 nop
1955 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
1957 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1958 (build_endian_shift): Don't check proc64.
1959 (build_instruction): Always set memval to uword64. Cast op2 to
1960 uword64 when shifting it left in memory instructions. Always use
1961 the same code for stores--don't special case proc64.
1963 * gencode.c (build_mips16_operands): Fix base PC value for PC
1965 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1967 * interp.c (simJALDELAYSLOT): Define.
1968 (JALDELAYSLOT): Define.
1969 (INDELAYSLOT, INJALDELAYSLOT): Define.
1970 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1972 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
1974 * interp.c (sim_open): add flush_cache as a PMON routine
1975 (sim_monitor): handle flush_cache by ignoring it
1977 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
1979 * gencode.c (build_instruction): Use !ByteSwapMem instead of
1981 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1982 (BigEndianMem): Rename to ByteSwapMem and change sense.
1983 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1984 BigEndianMem references to !ByteSwapMem.
1985 (set_endianness): New function, with prototype.
1986 (sim_open): Call set_endianness.
1987 (sim_info): Use simBE instead of BigEndianMem.
1988 (xfer_direct_word, xfer_direct_long, swap_direct_word,
1989 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1990 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1991 ifdefs, keeping the prototype declaration.
1992 (swap_word): Rewrite correctly.
1993 (ColdReset): Delete references to CONFIG. Delete endianness related
1994 code; moved to set_endianness.
1996 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
1998 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1999 * interp.c (CHECKHILO): Define away.
2000 (simSIGINT): New macro.
2001 (membank_size): Increase from 1MB to 2MB.
2002 (control_c): New function.
2003 (sim_resume): Rename parameter signal to signal_number. Add local
2004 variable prev. Call signal before and after simulate.
2005 (sim_stop_reason): Add simSIGINT support.
2006 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2008 (sim_warning): Delete call to SignalException. Do call printf_filtered
2010 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2011 a call to sim_warning.
2013 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2015 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2016 16 bit instructions.
2018 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2020 Add support for mips16 (16 bit MIPS implementation):
2021 * gencode.c (inst_type): Add mips16 instruction encoding types.
2022 (GETDATASIZEINSN): Define.
2023 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2024 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2026 (MIPS16_DECODE): New table, for mips16 instructions.
2027 (bitmap_val): New static function.
2028 (struct mips16_op): Define.
2029 (mips16_op_table): New table, for mips16 operands.
2030 (build_mips16_operands): New static function.
2031 (process_instructions): If PC is odd, decode a mips16
2032 instruction. Break out instruction handling into new
2033 build_instruction function.
2034 (build_instruction): New static function, broken out of
2035 process_instructions. Check modifiers rather than flags for SHIFT
2036 bit count and m[ft]{hi,lo} direction.
2037 (usage): Pass program name to fprintf.
2038 (main): Remove unused variable this_option_optind. Change
2039 ``*loptarg++'' to ``loptarg++''.
2040 (my_strtoul): Parenthesize && within ||.
2041 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2042 (simulate): If PC is odd, fetch a 16 bit instruction, and
2043 increment PC by 2 rather than 4.
2044 * configure.in: Add case for mips16*-*-*.
2045 * configure: Rebuild.
2047 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2049 * interp.c: Allow -t to enable tracing in standalone simulator.
2050 Fix garbage output in trace file and error messages.
2052 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2054 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2055 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2056 * configure.in: Simplify using macros in ../common/aclocal.m4.
2057 * configure: Regenerated.
2058 * tconfig.in: New file.
2060 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2062 * interp.c: Fix bugs in 64-bit port.
2063 Use ansi function declarations for msvc compiler.
2064 Initialize and test file pointer in trace code.
2065 Prevent duplicate definition of LAST_EMED_REGNUM.
2067 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2069 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2071 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2073 * interp.c (SignalException): Check for explicit terminating
2075 * gencode.c: Pass instruction value through SignalException()
2076 calls for Trap, Breakpoint and Syscall.
2078 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2080 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2081 only used on those hosts that provide it.
2082 * configure.in: Add sqrt() to list of functions to be checked for.
2083 * config.in: Re-generated.
2084 * configure: Re-generated.
2086 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2088 * gencode.c (process_instructions): Call build_endian_shift when
2089 expanding STORE RIGHT, to fix swr.
2090 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2091 clear the high bits.
2092 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2093 Fix float to int conversions to produce signed values.
2095 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2097 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2098 (process_instructions): Correct handling of nor instruction.
2099 Correct shift count for 32 bit shift instructions. Correct sign
2100 extension for arithmetic shifts to not shift the number of bits in
2101 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2102 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2104 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2105 It's OK to have a mult follow a mult. What's not OK is to have a
2106 mult follow an mfhi.
2107 (Convert): Comment out incorrect rounding code.
2109 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2111 * interp.c (sim_monitor): Improved monitor printf
2112 simulation. Tidied up simulator warnings, and added "--log" option
2113 for directing warning message output.
2114 * gencode.c: Use sim_warning() rather than WARNING macro.
2116 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2118 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2119 getopt1.o, rather than on gencode.c. Link objects together.
2120 Don't link against -liberty.
2121 (gencode.o, getopt.o, getopt1.o): New targets.
2122 * gencode.c: Include <ctype.h> and "ansidecl.h".
2123 (AND): Undefine after including "ansidecl.h".
2124 (ULONG_MAX): Define if not defined.
2125 (OP_*): Don't define macros; now defined in opcode/mips.h.
2126 (main): Call my_strtoul rather than strtoul.
2127 (my_strtoul): New static function.
2129 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2131 * gencode.c (process_instructions): Generate word64 and uword64
2132 instead of `long long' and `unsigned long long' data types.
2133 * interp.c: #include sysdep.h to get signals, and define default
2135 * (Convert): Work around for Visual-C++ compiler bug with type
2137 * support.h: Make things compile under Visual-C++ by using
2138 __int64 instead of `long long'. Change many refs to long long
2139 into word64/uword64 typedefs.
2141 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2143 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2144 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2146 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2147 (AC_PROG_INSTALL): Added.
2148 (AC_PROG_CC): Moved to before configure.host call.
2149 * configure: Rebuilt.
2151 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2153 * configure.in: Define @SIMCONF@ depending on mips target.
2154 * configure: Rebuild.
2155 * Makefile.in (run): Add @SIMCONF@ to control simulator
2157 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2158 * interp.c: Remove some debugging, provide more detailed error
2159 messages, update memory accesses to use LOADDRMASK.
2161 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2163 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2164 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2166 * configure: Rebuild.
2167 * config.in: New file, generated by autoheader.
2168 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2169 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2170 HAVE_ANINT and HAVE_AINT, as appropriate.
2171 * Makefile.in (run): Use @LIBS@ rather than -lm.
2172 (interp.o): Depend upon config.h.
2173 (Makefile): Just rebuild Makefile.
2174 (clean): Remove stamp-h.
2175 (mostlyclean): Make the same as clean, not as distclean.
2176 (config.h, stamp-h): New targets.
2178 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2180 * interp.c (ColdReset): Fix boolean test. Make all simulator
2183 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2185 * interp.c (xfer_direct_word, xfer_direct_long,
2186 swap_direct_word, swap_direct_long, xfer_big_word,
2187 xfer_big_long, xfer_little_word, xfer_little_long,
2188 swap_word,swap_long): Added.
2189 * interp.c (ColdReset): Provide function indirection to
2190 host<->simulated_target transfer routines.
2191 * interp.c (sim_store_register, sim_fetch_register): Updated to
2192 make use of indirected transfer routines.
2194 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2196 * gencode.c (process_instructions): Ensure FP ABS instruction
2198 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2199 system call support.
2201 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2203 * interp.c (sim_do_command): Complain if callback structure not
2206 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2208 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2209 support for Sun hosts.
2210 * Makefile.in (gencode): Ensure the host compiler and libraries
2211 used for cross-hosted build.
2213 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2215 * interp.c, gencode.c: Some more (TODO) tidying.
2217 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2219 * gencode.c, interp.c: Replaced explicit long long references with
2220 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2221 * support.h (SET64LO, SET64HI): Macros added.
2223 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2225 * configure: Regenerate with autoconf 2.7.
2227 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2229 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2230 * support.h: Remove superfluous "1" from #if.
2231 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2233 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2235 * interp.c (StoreFPR): Control UndefinedResult() call on
2236 WARN_RESULT manifest.
2238 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2240 * gencode.c: Tidied instruction decoding, and added FP instruction
2243 * interp.c: Added dineroIII, and BSD profiling support. Also
2244 run-time FP handling.
2246 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2248 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2249 gencode.c, interp.c, support.h: created.